Instruction transmission device, method, chip, computer equipment and storage medium

Abstract

The present disclosure provides an instruction emission device, method, chip, computer equipment and storage medium, wherein the instruction emission device includes: an instruction emission unit and a conflict detection unit; the instruction emission unit is used to send a conflict detection signal to the conflict detection circuit based on the instruction to be emitted in the current processing cycle; receive a conflict detection result signal fed back by the conflict detection unit based on the conflict detection signal; in response to the conflict detection result signal indicating that there is no resource access conflict between the instruction to be emitted and the historical emission instruction, emit the instruction to be emitted; the conflict detection unit is used to detect whether there is a resource access conflict between the instruction to be emitted and the historical emission instruction based on the conflict detection signal in response to receiving the conflict detection signal sent by the instruction emission unit, and feed back the conflict detection result signal to the instruction emission unit.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, and in particular to an instruction transmitting device, method, chip, computer equipment and storage medium. Background Art

[0002] As processors become more powerful, their structures become more complex. In processors, control conflicts are often encountered, for example, there are multiple instructions to be issued that indicate memory access at the same time in the same processing cycle. Currently, in order to solve the problem of control conflicts, it is usually chosen to use a register stack that can read and write multiple ports to build the memory, but this will increase the area of ​​the processor. Summary of the invention

[0003] The embodiments of the present disclosure at least provide an instruction transmitting device, method, chip, computer equipment and storage medium.

[0004] In the first aspect, an embodiment of the present disclosure provides an instruction transmitting device, comprising: an instruction transmitting unit, and a conflict detection unit; the instruction transmitting unit is used to send a conflict detection signal to the conflict detection circuit based on the instruction to be transmitted in the current processing cycle; receive a conflict detection result signal fed back by the conflict detection unit based on the conflict detection signal; in response to the conflict detection result signal indicating that there is no resource access conflict between the instruction to be transmitted and the historically transmitted instruction, transmit the instruction to be transmitted; the conflict detection unit is used to detect whether there is a resource access conflict between the instruction to be transmitted and the historically transmitted instruction based on the conflict detection signal in response to receiving the conflict detection signal sent by the instruction transmitting unit, and feed back the conflict detection result signal to the instruction transmitting unit.

[0005] In this way, the conflict detection unit can be used to determine whether a resource access conflict will occur before the instruction issuing unit issues the instruction to be issued, so that the issuing instruction can be issued when there is no resource access conflict, thereby avoiding the conflict from the source. Since the conflict can be directly avoided, there is no need to use register pairs to build a memory, reducing the area overhead of the processor.

[0006] In an optional embodiment, the instruction issuing unit is also used to: in response to the conflict detection result signal indicating that there is a resource access conflict between the instruction to be issued and the historically issued instruction, use the instruction to be issued as the instruction to be issued for the next processing cycle, and when the next processing cycle arrives, send a conflict detection signal to the conflict detection circuit based on the instruction to be issued for the next processing cycle.

[0007] In this way, for the instructions to be issued that have resource access conflicts, the issuance in the current processing cycle can be paused to avoid conflicts; at the same time, the instructions to be issued corresponding to the next processing cycle are again checked for resource access conflicts to ensure that the instructions to be issued are not lost and can be issued when there is no resource access conflict.

[0008] In an optional embodiment, the conflict detection signal includes: type information of the instruction to be issued; the conflict detection unit includes: a signal conversion circuit, and a conflict detection circuit; wherein the signal conversion circuit, in response to receiving the type information sent by the instruction issuing unit, converts the type information into access action information corresponding to the instruction to be issued, and sends the access action information to the conflict detection circuit; wherein the access action information is used to indicate a resource access cycle corresponding to the instruction to be issued; the conflict detection circuit is used to detect whether there is a resource access conflict between the instruction to be issued and the historically issued instruction based on the access action information and historical access status information in response to receiving the access action information sent by the signal conversion circuit, and feedback the conflict detection result signal to the instruction issuing unit.

[0009] In this way, the signal conversion circuit can determine the access action information corresponding to the current processing cycle according to the type information sent by the instruction emission unit. Since the access action information can express the processing cycle corresponding to the access action, the conflict detection circuit can use the access action information of the current processing cycle and the historical access status information to more accurately determine whether there will be a resource access conflict for the current processing cycle, and accordingly determine a conflict detection result signal that can indicate whether there is a resource access conflict.

[0010] In an optional embodiment, the conflict detection signal also includes: an enable signal; the conflict detection circuit is used to respond to receiving the access action information sent by the signal conversion circuit and the enable signal sent by the instruction issuance unit, based on the access action information and historical access status information, detect whether there is a resource access conflict between the instruction to be issued and the historical issuance instruction, and feedback the conflict detection result signal to the instruction issuance unit.

[0011] In this way, the conflict detection circuit can first determine whether it is necessary to detect resource access conflicts for access action information based on the enable signal. In this way, the conflict detection process can be controlled by the enable signal. For instructions that do not access the memory, since they themselves will not have memory access conflicts with other instructions, the efficiency of instruction transmission can be improved. In addition, in some cases, instructions need to be transmitted quickly, and the problem of memory access conflicts can be ignored. At this time, the conflict detection process can be controlled by whether to send an enable signal, and the instruction transmission process is more flexible.

[0012] In an optional embodiment, the conflict detection circuit includes: a logic processing circuit and a conflict decision circuit; the logic processing circuit is used to determine a conflict indication signal based on the access action information and the historical access status information; and send the conflict indication signal to the conflict decision circuit; the conflict decision circuit is used to determine whether there is a resource access conflict between the instruction to be issued and the historically issued instruction based on the conflict indication signal in response to receiving the conflict indication signal sent by the logic processing circuit, and to feed back the conflict detection result signal to the instruction issuing unit.

[0013] In an optional embodiment, the logic processing circuit includes: an AND gate circuit; the conflict decision circuit includes: a first OR gate circuit; the AND gate circuit is used to perform bitwise AND processing on the access action information and the historical access status information to obtain the conflict indication signal; the first OR gate circuit is used to perform bitwise OR processing on the conflict indication signal to obtain the conflict detection result signal.

[0014] In this way, through digital logic operations, the access action information and historical access status information can be directly analyzed, with small amount of calculation and processing and high accuracy.

[0015] In an optional embodiment, the signal conversion circuit includes: a selector; the selector is used to select a transmission path corresponding to the type information in response to receiving the type information sent by the instruction emission unit, output access action information corresponding to the transmission path, and transmit the access action information to the conflict detection circuit.

[0016] In this way, on the one hand, the structure of the selector is relatively simple, and compared with using the central processing unit to analyze the type information and then access the register to obtain the corresponding access action information, the area occupied is smaller; on the other hand, the selector can complete the conversion from type information to access action information through its own calculation processing logic, and can also better guarantee accuracy.

[0017] In an optional implementation, the instruction transmitting device further includes: an access status register; the access status register is used to store the historical access status information; and the conflict detection circuit is further used to read the historical access status information from the access status register.

[0018] In an optional embodiment, the instruction transmitting device also includes: a historical access status information update circuit; the signal conversion circuit is also used to transmit the access action information to the historical access status information update circuit; the historical access status information update circuit is used to receive the access action information sent by the signal conversion circuit, and read the historical access status information from the access status register; based on the access action information and the historical access status information, generate new historical access status information; and update the new historical access status information to the access status register; wherein the new historical access status information is used to generate a conflict detection result signal for a future processing cycle.

[0019] In this way, the historical access status information update circuit can be updated in different processing cycles according to the access action information and historical access status information of the current processing cycle, and generate historical access status information corresponding to multiple processing cycles before the current processing cycle. In this way, in the subsequent processing cycles, the access conflict detection can be performed on the instruction to be issued corresponding to the current processing cycle directly according to the historical access status information updated in the access status register.

[0020] In an optional embodiment, the historical access status information update circuit includes: a status integration circuit and an update circuit; wherein the status integration circuit is used to receive the access action information sent by the signal conversion circuit, and read the historical access status information from the access status register, integrate the access action information and the historical access status information to obtain fused access status information; send the fused access status information to the update circuit; the update circuit is used to shift the fused access status information in response to receiving the fused access status information sent by the status integration circuit to obtain the new historical access status information, and update the new historical access status information to the access status register.

[0021] In an optional embodiment, the state integration circuit includes: a second OR gate circuit; the update circuit includes: a shift circuit; the second OR gate circuit is used to perform bitwise OR processing on the access action information and the historical access status information to obtain the fused access status information; the shift circuit is used to shift the fused access status information to the right by a bit corresponding to a processing cycle, and supplement a bit corresponding to a processing cycle on the left side of the fused access status information, and set the supplemented bit value on the left side to a preset value.

[0022] In this way, the historical access status information obtained corresponds to the current processing cycle, and the conflict detection circuit can determine whether there is a conflict in the instruction to be issued based on the access action information corresponding to the current processing cycle and the historical access status information corresponding to the current processing cycle in the access status register.

[0023] In the second aspect, the embodiment of the present disclosure also provides an instruction transmitting method, which is applied to an instruction transmitting device; the instruction transmitting device includes: an instruction transmitting unit, and a conflict detection unit; the instruction transmitting method includes: the instruction transmitting unit sends a conflict detection signal to the conflict detection circuit based on the instruction to be transmitted in the current processing cycle; the conflict detection unit responds to receiving the conflict detection signal sent by the instruction transmitting unit, and based on the conflict detection signal, detects whether there is a resource access conflict between the instruction to be transmitted and the historically transmitted instruction, and feeds back the conflict detection result signal to the instruction transmitting unit; the instruction transmitting unit receives the conflict detection result signal fed back by the conflict detection unit; and in response to the conflict detection result signal indicating that there is no resource access conflict between the instruction to be transmitted and the historically transmitted instruction, transmits the instruction to be transmitted.

[0024] In an optional embodiment, the instruction issuing method further includes: the instruction issuing unit responds to the conflict detection result signal indicating that there is a resource access conflict between the instruction to be issued and the historically issued instruction, uses the instruction to be issued as the instruction to be issued for the next processing cycle, and when the next processing cycle arrives, sends a conflict detection signal to the conflict detection circuit based on the instruction to be issued for the next processing cycle.

[0025] In an optional embodiment, the conflict detection signal includes: type information of the instruction to be issued; the conflict detection unit includes: a signal conversion circuit and a conflict detection circuit; the instruction issuance method includes: the signal conversion circuit, in response to receiving the type information sent by the instruction issuance unit, converts the type information into access action information corresponding to the instruction to be issued, and sends the access action information to the conflict detection circuit; wherein the access action information is used to indicate a resource access cycle corresponding to the instruction to be issued; the conflict detection circuit, in response to receiving the access action information sent by the signal conversion circuit, detects whether there is a resource access conflict between the instruction to be issued and the historically issued instruction based on the access action information and historical access status information, and feeds back the conflict detection result signal to the instruction issuance unit.

[0026] In an optional embodiment, the conflict detection signal also includes: an enable signal; the instruction transmission method includes: the conflict detection circuit responds to receiving the access action information sent by the signal conversion circuit and the enable signal sent by the instruction transmission unit, based on the access action information and historical access status information, detecting whether there is a resource access conflict between the instruction to be transmitted and the historically transmitted instruction, and feeding back the conflict detection result signal to the instruction transmission unit.

[0027] In an optional embodiment, the conflict detection circuit includes: a logic processing circuit and a conflict decision circuit; the instruction issuance method includes: the logic processing circuit determines a conflict indication signal based on the access action information and the historical access status information; sends the conflict indication signal to the conflict decision circuit; the conflict decision circuit determines whether there is a resource access conflict between the instruction to be issued and the historically issued instruction based on the conflict indication signal in response to receiving the conflict indication signal sent by the logic processing circuit, and feeds back the conflict detection result signal to the instruction issuance unit.

[0028] In an optional implementation, the logic processing circuit includes: an AND gate circuit; the conflict decision circuit includes: a first OR gate circuit; the instruction transmission method includes: the AND gate circuit performs bitwise AND processing on the access action information and the historical access status information to obtain the conflict indication signal; the first OR gate circuit performs bitwise OR processing on the conflict indication signal to obtain the conflict detection result signal.

[0029] In an optional embodiment, the signal conversion circuit includes: a selector; the instruction transmission method includes: the selector, in response to receiving the type information sent by the instruction transmission unit, selects the transmission path corresponding to the type information, outputs access action information corresponding to the transmission path, and transmits the access action information to the conflict detection circuit.

[0030] In an optional implementation, the instruction transmission method is applied to the instruction transmission device, and the instruction transmission device also includes: an access status register; the instruction transmission method includes: the access status register stores the historical access status information; the conflict detection circuit reads the historical access status information from the access status register.

[0031] In an optional embodiment, the instruction transmitting method is applied to the instruction transmitting device, and the instruction transmitting device also includes: a historical access status information update circuit; the instruction transmitting method includes: the signal conversion circuit transmits the access action information to the historical access status information update circuit; the historical access status information update circuit receives the access action information sent by the signal conversion circuit, and reads the historical access status information from the access status register; based on the access action information and the historical access status information, generates new historical access status information; and updates the new historical access status information to the access status register; wherein, the new historical access status information is used to generate a conflict detection result signal for a future processing cycle.

[0032] In an optional embodiment, the historical access status information update circuit includes: a status integration circuit and an update circuit; the instruction issuance method includes: the status integration circuit receives the access action information sent by the signal conversion circuit, and reads the historical access status information from the access status register, integrates the access action information and the historical access status information to obtain fused access status information; sends the fused access status information to the update circuit; the update circuit shifts the fused access status information in response to receiving the fused access status information sent by the status integration circuit to obtain the new historical access status information, and updates the new historical access status information to the access status register.

[0033] In an optional embodiment, the state integration circuit includes: a second OR gate circuit; the update circuit includes: a shift circuit; the instruction transmission method includes: the second OR gate circuit performs bitwise OR processing on the access action information and the historical access status information to obtain the fused access status information; the shift circuit shifts the fused access status information to the right by a bit corresponding to a processing cycle, and supplements a bit corresponding to a processing cycle on the left side of the fused access status information, and sets the supplemented bit value on the left side to a preset value.

[0034] In a third aspect, an optional implementation of the present disclosure further provides a chip, comprising the instruction transmitting device described in the first aspect above.

[0035] In a fourth aspect, an optional implementation of the present disclosure further provides a computer device, a processor, and a memory, wherein the memory stores machine-readable instructions executable by the processor, and the processor is used to execute the machine-readable instructions stored in the memory, and when the machine-readable instructions are executed by the processor, the machine-readable instructions perform the steps in the above-mentioned second aspect, or any possible implementation of the second aspect.

[0036] In a fifth aspect, an optional implementation of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed, the steps of the above-mentioned second aspect, or any possible implementation of the second aspect are executed.

[0037] For a description of the effects of the above-mentioned instruction transmitting method, chip, computer device, and computer-readable storage medium, please refer to the description of the above-mentioned instruction transmitting device, which will not be repeated here.

[0038] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following is a brief introduction to the drawings required for use in the embodiments. The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used together with the specification to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can also be obtained based on these drawings without creative work.

[0040] Figure 1 A schematic diagram of a command transmitting device provided by an embodiment of the present disclosure is shown;

[0041] Figure 2 A specific schematic diagram of a command transmitting device provided by an embodiment of the present disclosure is shown;

[0042] Figure 3 A specific schematic diagram of a conflict detection unit provided by an embodiment of the present disclosure is shown;

[0043] Figure 4 A specific schematic diagram of a signal conversion circuit provided by an embodiment of the present disclosure is shown;

[0044] Figure 5 A specific schematic diagram of a conflict detection circuit provided by an embodiment of the present disclosure is shown;

[0045] Figure 6 A specific schematic diagram of an access status register provided by an embodiment of the present disclosure is shown;

[0046] Figure 7 A schematic diagram of a historical access status information updating circuit provided by an embodiment of the present disclosure is shown;

[0047] Figure 8 A specific schematic diagram of a historical access status information updating circuit provided by an embodiment of the present disclosure is shown;

[0048] Fig. 9 A specific schematic diagram of a command transmitting device provided by an embodiment of the present disclosure and applied to a specific embodiment is shown;

[0049] Fig.10 A flow chart of an instruction transmitting method provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure is not intended to limit the scope of the present disclosure claimed for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0051] According to research, in the processor, control conflicts often occur because the hardware resources cannot meet the requirements of overlapping execution of instructions. For example, multiple instructions indicate simultaneous access to a memory in the same processing cycle, which will cause conflicts in memory access. At present, in order to resolve such conflicts, it is usually chosen to use a register stack that can read and write from multiple ports to build the memory. In this way, for different instructions that need to access the memory at the same time in the same processing cycle, the memory can be accessed separately through different ports of the register stack, thereby avoiding conflicts in memory access; the memory built by the register stack needs to occupy a larger area, which will increase the area of ​​the processor; but in fact, since the area of ​​the processor is limited when it is actually deployed in an embedded device, the use of a register stack will inevitably increase the area overhead of the processor. Therefore, this method of resolving control conflicts is not suitable for scenarios with limited processor area.

[0052] Based on the above research, the present disclosure provides an instruction emission device, which uses a conflict detection unit to determine whether a resource access conflict will occur before the instruction emission unit emits the instruction to be emitted, so that the instruction to be emitted can be emitted when there is no resource access conflict, thereby avoiding the generation of conflicts from the source. Since the generation of conflicts can be directly avoided, there is no need to use register pairs to build a memory, reducing the area overhead of the processor.

[0053] The defects existing in the above solutions are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the present disclosure for the above problems below should be the contributions made by the inventor to the present disclosure during the disclosure process.

[0054] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0055] To facilitate understanding of this embodiment, a command transmitting device provided by the embodiment of the present disclosure is first described in detail. Figure 1 FIG. 1 is a schematic diagram of a command transmitting device provided by an embodiment of the present disclosure; the command transmitting device comprises: a command transmitting unit 10 and a conflict detecting unit 20; wherein,

[0056] The instruction transmitting unit 10 is used to send a conflict detection signal to the conflict detection circuit based on the instruction to be transmitted in the current processing cycle; receive a conflict detection result signal fed back by the conflict detection unit 20 based on the conflict detection signal; and transmit the instruction to be transmitted in response to the conflict detection result signal indicating that there is no resource access conflict between the instruction to be transmitted and the historical transmitted instruction;

[0057] The conflict detection unit 20 is used to respond to receiving a conflict detection signal sent by the instruction emission unit 10, detect whether there is a resource access conflict between the instruction to be emitted and the historical emission instruction based on the conflict detection signal, and feed back the conflict detection result signal to the instruction emission unit 10.

[0058] The instruction emission device provided by the embodiment of the present disclosure includes an instruction emission unit and a conflict detection unit; since there may be a resource access conflict between the instruction to be emitted and the historical emission instruction, the instruction emission unit can send a conflict detection signal to the conflict detection unit before emitting the instruction to be emitted, so that the conflict detection unit can determine whether there is a resource access conflict between the instruction to be emitted and the historical emission instruction based on the received conflict detection signal, and feedback the conflict detection result signal to the instruction emission unit based on the monitoring result; accordingly, the instruction emission unit can emit the instruction to be emitted in the absence of a resource access conflict. In this way, the conflict detection unit is used to determine whether a resource access conflict will occur before the instruction emission unit emits the instruction to be emitted, so that the emission instruction can be emitted in the absence of a resource access conflict, thereby avoiding the generation of conflicts from the source. Since the generation of conflicts can be directly avoided, there is no need to use register pairs to build a memory, reducing the area overhead of the processor.

[0059] In a specific implementation, the instruction transmitting device can be deployed on different data processing chips. Exemplarily, the data processing chip may include: a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller unit (MCU), and a system on chip (SoC).

[0060] Among them, different data processing chips actually perform different data processing tasks, so the corresponding instructions to be issued are also different. Exemplarily, taking the deployment of the instruction emission device on the GPU as an example, when the GPU processes the image based on the target neural network, the corresponding instructions to be emitted may include, for example, operation instructions for image processing. Here, the target neural network may include, for example, at least one of the following: convolutional neural networks (CNN), recurrent neural networks (RNN), and self-attention neural networks (transformers). For operation instructions, specifically, for example, it may include read and write access to the register where the intermediate data is located, or read the result data from the corresponding register. When the task corresponding to the instruction to be emitted is specifically executed, the register needs to be accessed. In this case, it may include the need to access the same register in a processing cycle, that is, an access conflict occurs.

[0061] In addition, when the GPU processes the image based on the target neural network, the corresponding instructions to be issued may also include control instructions, such as loop instructions (for instructions), jump instructions (jump instructions), and conditional instructions (if else instructions). When executing the tasks corresponding to the instructions to be issued, since it does not involve the specific processing of the data in the register, there is no need to access the register, that is, there will be no need to access the same register in one processing cycle, and no access conflict will occur.

[0062] In a specific implementation, the instruction issuing unit 10 may determine a conflict detection signal to be sent to the conflict detection circuit based on the instruction to be issued. The conflict detection signal is used to request the conflict detection unit 20 to detect resource access conflicts for the instruction to be issued. Specifically, the conflict detection signal includes type information of the instruction to be issued.

[0063] The type information of the instruction to be issued may include, for example, different operation types. Exemplarily, the different operation types may include, for example, addition operation, multiplication operation, convolution operation, and normalization operation. Since the specific operations performed in different processing cycles are different, the instructions to be issued corresponding to different cycles are different, and the corresponding type information is also different.

[0064] See also Figure 2 FIG. 1 is a schematic diagram of a command transmitting device provided by an embodiment of the present disclosure. For the command transmitting unit 10, it may include two output ports O 10-1 , O 10-2 , and an input port I 10When the instruction transmitting unit 10 sends the conflict detection signal to the conflict detection unit 20, for example, the instruction transmitting unit 10 can transmit the conflict detection signal to the conflict detection unit 20 through the output port O 10-1 , and O 10-2 Sending a conflict detection signal, specifically, for example, can be performed through the output port O 10-1 The conflict detection signal including the enable signal is sent to the conflict detection circuit in the conflict detection unit 20, and is output through the output port O 10-2 The conflict detection signal containing the type information is sent to the signal conversion circuit in the conflict detection unit 20. The input port I of the instruction issuing unit 10 10 For example, a conflict detection result signal fed back by the conflict detection unit 20 based on the conflict detection signal may be received; this will be described in detail below and will not be repeated here.

[0065] For the conflict detection unit 20, see Figure 3 FIG. 2 is a specific schematic diagram of a conflict detection unit provided in an embodiment of the present disclosure, wherein the conflict detection unit includes a signal conversion circuit 30 and a conflict detection circuit 40 .

[0066] After the instruction emission unit 10 sends a conflict detection signal to the conflict detection unit 20, the signal conversion circuit 30 in the conflict detection unit 20 is used to respond to receiving the type information sent by the instruction emission unit 10, convert the type information into access action information corresponding to the instruction to be emitted, and send the access action information to the conflict detection circuit 40; wherein, the access action information is used to indicate the resource access cycle corresponding to the instruction to be emitted.

[0067] In a specific implementation, the signal conversion circuit 30 may, for example, include a selector for selecting a transmission path corresponding to the type information in response to receiving the type information sent by the instruction emission unit 10, outputting access action information corresponding to the transmission path, and transmitting the access action information to the conflict detection circuit 40.

[0068] For the signal conversion circuit 30, see Figure 4 FIG. 1 is a schematic diagram of a signal conversion circuit provided by an embodiment of the present disclosure. The signal conversion circuit 30 may have multiple input ports I 30-0 ~I 30-n And two output ports O 30-1 , O 30-2 Among the multiple input ports, a data receiving port I is included for receiving type information sent by the instruction transmitting unit 10. 30-0 , and input ports I corresponding to multiple transmission paths 30-1 ~I 30-n Output port O 30-1Connected to the conflict detection circuit 40, used to send access action information to the conflict detection circuit 40; output port O 30-2 It is connected to the historical access status information update circuit, and the access action information is similarly sent to the historical access status information update circuit. For details, please refer to the description below and will not be described in detail here.

[0069] Among them, multiple transmission paths correspond to access action information under different types of information. Taking the GPU in the above example as an example, when the GPU processes the image based on the target neural network, the instructions to be issued may include type information under different operation types. Because when the target neural network performs specific operations, different operation steps are executed in order according to the processing cycle, when determining the instructions to be issued, the processing cycle when executing the operation steps under the instruction can be determined according to the type information corresponding to the instruction to be issued.

[0070] Exemplarily, the operation corresponding to different processing cycles may include, for example: an operation of performing a multiplication operation in the first processing cycle, an operation of performing an addition operation in the second processing cycle, an operation of performing a normalization operation in the third processing cycle, etc. In this way, since each cycle corresponds to a specific operation, the corresponding processing cycle can be determined for the instruction to be issued according to the operation type determined by the instruction to be issued, and the access action information can be determined according to the determined processing cycle.

[0071] Specifically, the access action information can be represented by data of multiple bits, for example. Exemplarily, the access action information can occupy 5, 6, or 7 bits, for example. Here, the number of bits included in the access action information is determined by the number of processing cycles that the operation needs to wait for at most. For example, for multiple operation operations, the longest processing cycle required to wait is 5, that is, the longest waiting time is until the fifth processing cycle to access the resources corresponding to the operation, then the access action information can be set to 5 bits, for example. Here, for different data processing chips, due to the different computing efficiencies of different data processing chips, the instruction sets used may also be different, so the longest processing cycle required to wait for the operation may also be different. Therefore, the bits occupied by the access action information can be determined according to the actual situation, and no limitation is made here.

[0072] Taking the access action information occupying 5 bits as an example, the 5 bits from right to left can correspond to 5 consecutive processing cycles. For example, the first bit on the far right corresponds to the first processing cycle, and the first bit on the far left corresponds to the fifth processing cycle. When the bits corresponding to each processing cycle are determined, according to the operation steps corresponding to different processing cycles, the following corresponding relationship can be obtained, for example:

[0073] Multiplication operation -00001,

[0074] It indicates the operation steps of performing multiplication operation in the first processing cycle;

[0075] Addition operation - 00010,

[0076] It indicates the operation steps of performing the addition operation in the second processing cycle;

[0077] Normalization operation - 00100,

[0078] represents the operation steps of performing the normalization operation in the third processing cycle;

[0079] …….

[0080] For the multiple input ports I in the signal conversion circuit 30 30-1 ~I 30-n , respectively corresponding to different transmission paths, each transmission communication corresponds to different type information. For example, for input port I 30-1 , the type information of the corresponding transmission path is multiplication operation, and the corresponding access action information is 00001; for input port I 30-1 The type information of the corresponding transmission path is addition operation, and the corresponding access action information is 00010.

[0081] Exemplarily, the instruction to be issued by the instruction issuing unit 10 in the current cycle includes, for example, a1. After the instruction issuing unit 10 sends a1 to the signal conversion circuit 30, the signal conversion circuit 30 selects the input port I according to the type information corresponding to the current instruction to be issued a1, such as multiplication operation. 30-1 The corresponding transmission path and the corresponding access action information 00001 are transmitted through the output port O 30-1 The signal is output to the conflict detection circuit 40. Here, the plurality of input ports in the signal conversion circuit 30 may be respectively connected to registers storing access action information, for example.

[0082] Correspondingly, after the conflict detection circuit 40 receives the access action information sent by the signal conversion circuit 30, it can detect whether there is a resource access conflict between the instruction to be issued and the historically issued instruction based on the access action information and the historical access status information, and feedback the conflict detection result signal to the instruction issuing unit 10.

[0083] As for the conflict detection circuit 40, according to the above description of different instructions to be issued, not all instructions to be issued will generate resource access conflicts, so the conflict detection unit 20 does not need to detect resource access conflicts for all instructions to be issued. In order to enable the conflict detection circuit 40 to efficiently detect instructions to be issued that need to be detected for resource access conflicts, the conflict detection signal sent by the instruction issuing unit 10 to the conflict detection unit 20 may also include an enable signal.

[0084] Exemplarily, if the instruction emission unit 10 determines that a resource access conflict needs to be detected based on the instruction to be emitted, it accordingly sends a conflict detection signal including an enable signal to the conflict detection unit 20, so that the conflict detection circuit 40 can respond to the access action information sent by the signal conversion circuit 30 and the enable signal sent by the instruction emission unit 10, detect whether there is a resource access conflict between the instruction to be emitted and the historically emitted instruction based on the access action information and the historical access status information, and feed back the conflict detection result signal to the instruction emission unit 10.

[0085] For the conflict detection circuit 40, see Figure 5 FIG. 4 is a schematic diagram of a conflict detection circuit provided by an embodiment of the present disclosure. The conflict detection circuit 40 includes a logic processing circuit 50 and a conflict decision circuit 60. Specifically, the logic processing circuit 50 includes an AND gate circuit. Figure 5 The logic processing circuit 50 includes three input ports I 50-0 ~I 50-2 , where the input port I 50-0 Used to receive the conflict detection signal sent by the instruction transmitting unit 10. Specifically, the conflict detection signal includes an enable signal, so the logic processing circuit 50 can start detecting the instruction to be transmitted according to the enable signal in the conflict detection signal. 50-1 The output port O of the signal conversion circuit 30 30-1 connected, and the corresponding receiving output port O 30-1 Access action information sent; input port I 50-2 The logic processing circuit 50 is connected to the access status register in the conflict detection unit 20. For details, please refer to the following description and will not be described in detail here. In addition, the logic processing circuit 50 also includes an output port O 50-0 , used to convert the input port I 50-0 ~I 50-2 The conflict indication signal is output after the input data is processed.

[0086] The output port O of the logic processing circuit 50 is 50-0The input port I of the conflict decision circuit 60 60-0 and transmits the determined conflict indication signal through the input port I of the conflict decision circuit 60. 60-0 The conflict decision circuit 60 includes, for example, a first OR gate circuit. Figure 5 The conflict decision circuit 60 also includes an output port O 60-0 , used to send the conflict detection result signal fed back to the instruction issuing unit 10 according to the conflict indication signal to the instruction issuing unit 10, that is, the output port O in the conflict decision circuit 60. 60-0 and the input port I in the instruction issuing unit 10 10 connect.

[0087] Specifically, when the conflict detection circuit 40 detects whether there is a resource access conflict between the instruction to be issued and the historically issued instruction, the logic processing circuit 50 is used to determine a conflict indication signal based on the access action information and the historical access status information; and send the conflict indication signal to the conflict decision circuit 60; the conflict decision circuit 60 is used to determine whether there is a resource access conflict between the instruction to be issued and the historically issued instruction based on the conflict indication signal in response to receiving the conflict indication signal sent by the logic processing circuit 50, and to feed back the conflict detection result signal to the instruction issuing unit 10.

[0088] In a specific implementation, the logic processing circuit 50 receives the input signal through the input port I 50-0 After receiving the conflict detection signal sent by the instruction transmitting unit 10, if it contains an enable signal, the detection of the instruction to be transmitted will be started accordingly; if it does not contain an enable signal, the instruction to be transmitted will not be detected. In one possible case, the logic processing circuit 50 receives the conflict detection signal sent by the input port I 50-0 After the received conflict detection signal determines to start detecting the instruction to be transmitted, the input port I 50-1 The access action information sent by the receiving signal conversion circuit 30 is received and transmitted by the input port I 50-2 Receive historical access status information from the access status register.

[0089] After the logic processing circuit 50 determines the access action information of the current cycle and the historical access status information, it can perform bitwise AND processing accordingly to obtain the conflict indication signal. Exemplarily, the access action information of the current cycle is, for example, 00100, and the historical access status information is, for example, 00000. After the access action information and the historical access status information are bitwise ANDed, the conflict indication signal can be determined to be 00000 accordingly.

[0090] After receiving the conflict indication signal, the logic processing circuit 50 outputs the conflict indication signal to the output port O. 50-0 Sent to the input port I of the conflict decision circuit 60 60-0 . After the conflict decision circuit 60 receives the conflict indication signal, the conflict indication signal itself is bitwise ORed, and a conflict detection result signal can be obtained accordingly. Taking the conflict indication signal as 00000 as an example, the corresponding conflict detection result signal is 0. Here, the conflict detection result signal is 0, indicating that the instruction to be issued does not conflict with other instructions in the same processing cycle, so it can be indicated that there is no resource access conflict between the instruction to be issued and the historically issued instruction; if the conflict detection result signal is 1, it means that the instruction to be issued conflicts with other instructions in the same processing cycle, so it can be indicated that there is a resource access conflict between the instruction to be issued and the historically issued instruction.

[0091] Corresponding to the different conflict detection signals determined, the instruction issuing unit 10 may issue the instruction to be issued in response to the conflict detection result signal indicating that there is no resource access conflict between the instruction to be issued and the historically issued instruction; or, in response to the conflict detection result signal indicating that there is a resource access conflict between the instruction to be issued and the historically issued instruction, use the instruction to be issued as the instruction to be issued in the next processing cycle, and send a conflict detection signal to the conflict detection circuit 40 based on the instruction to be issued in the next processing cycle when the next processing cycle arrives. The situation in which the instruction issuing unit 10 uses the instruction to be issued as the instruction to be issued in the next processing cycle in response to the conflict detection result signal indicating that there is a resource access conflict between the instruction to be issued and the historically issued instruction is shown in the form of an example in the specific embodiments below, and will not be repeated here.

[0092] In a possible case, the conflict decision circuit 60 can directly use the result obtained after bitwise OR as the conflict detection result signal and output it through the output port O 60-0 Sent to the input port I in the instruction issuing unit 10 10 , that is, the conflict detection result signal received by the input port in the instruction emission unit 10 is a "0" occupying one bit, and the instruction emission unit 10 determines whether the instruction to be emitted has a conflict according to the "0" of the one bit; in another possible case, the conflict decision circuit 60 can determine whether the instruction to be emitted has a conflict after bitwise OR processing the conflict indication signal, and according to the preset logic, for example, send a signal "0" to the instruction emission unit 10 when it is determined that there is no conflict, so that the instruction emission unit 10 can determine that there is no conflict in the instruction to be emitted after receiving the signal "0". The specific details can be determined according to the actual situation, and no further details are given here.

[0093] In another embodiment of the present disclosure, the instruction issuing device further includes an access status register; specifically, the conflict detection unit 20 in the instruction issuing device includes an access status register. Figure 6 , which is a specific schematic diagram of an access status register provided by an embodiment of the present disclosure. The access status register 70 includes an input port I 70 And two output ports O 70-0 , O 70-1 .

[0094] Among them, the input port I 70 Connected to the historical access status information update circuit, and receives the historical access status information sent by the historical access status information update circuit. Output port O 70-0 The input port I of the logic processing circuit 50 in the conflict detection circuit 40 50-2 The output port O is connected and sends the historical access status information to the logic processing circuit 50, so that the conflict detection circuit 40 can determine whether there is an instruction conflict based on the historical access status information stored in the historical processing cycle before the current processing cycle and the access action information corresponding to the current processing cycle. 70-1 It is connected to the historical access status information update circuit, and similarly sends the historical access status information to the historical access status information update circuit. For details, please refer to the description below, which will not be repeated here.

[0095] The access status register 70 stores historical access status information, which may include, for example, access action information corresponding to a previous processing cycle relative to the current processing cycle, stored in the access status register 70 after being processed in the previous processing cycle.

[0096] Specifically, the historical access status information updating circuit processes the access action information in one processing cycle. Figure 7 FIG. 8 is a schematic diagram of a historical access status information update circuit provided by an embodiment of the present disclosure. The historical access status information update circuit 80 is connected to the signal conversion circuit 30 and receives the access action information sent by the signal conversion circuit 30; the historical access status information update circuit 80 is also connected to the access status register 70, reads and processes the historical access status information in the access status register 70, and stores the historical access status information obtained in the current processing cycle in the access status register 70.

[0097] In a specific implementation, the historical access status information update circuit 80 is used to receive the access action information sent by the signal conversion circuit 30, and read the historical access status information from the access status register 70; generate new historical access status information based on the access action information and the historical access status information; and update the new historical access status information to the access status register 70; wherein the new historical access status information is used to generate a conflict detection result signal for a future processing cycle.

[0098] Since the access action information is determined according to the processing cycle, after multiple processing cycles, the specific operation steps can be determined in the processing cycle indicated by the access action information. If the processing cycle corresponding to the operation represented by the historical access information is the same as the processing cycle corresponding to the operation represented by the access action information, there are multiple operation operations synchronized in one processing cycle, that is, there is an access conflict in the processing cycle. The historical access status information update circuit 80 can determine new historical access information based on the access action information of the current cycle and the historical access status information to record the access operation corresponding to the processing cycle that has not been reached, and after determining the new access action information, it can determine whether there is an access conflict based on the historical access status information and the new historical access information.

[0099] Specifically, see Figure 8 FIG. 8 is a schematic diagram of a historical access status information updating circuit provided by an embodiment of the present disclosure. The historical access status information updating circuit 80 includes a status integration circuit 81 and an updating circuit 82. The status integration circuit 81 includes two input ports I 81-0 and I 81-1 , and output port O 81 Among them, the input port I 81-0 The output port O of the signal conversion circuit 30 30-2 Connection, used to receive the access action information of the current cycle determined by the signal conversion circuit 30. Input port I 81-1 and accessing the output port O in the status register 70 70-1 The output port is connected to the input port I of the update circuit 82, and the historical access status information stored in the access status register 70 is read accordingly. 82 The connection is used to send the fused access status information obtained after processing the access action information and the historical access status information to the update circuit 82.

[0100] The update circuit 82 includes an input port I 82, for receiving the fused access information sent by the state integration circuit 81, and performing shift processing on the fused access information to obtain new historical access information, and updating the new historical access state information to the access state register 70. Specifically, the update circuit 82 includes an output port O 82 , output port O 82 The input port I of the access status register 70 70 The updated historical access status information can be connected to the input port I 70 Update the access status register 70.

[0101] In a specific implementation, the state integration circuit 81 includes a second OR gate circuit. Figure 8 In the figure, “≥1” indicates that the updating circuit 82 includes a shift circuit. Figure 8 Specifically, the state integration circuit 81 is used to perform bitwise OR processing on the access action information and the historical access state information to obtain the fused access state information; the update circuit 82 is used to shift the fused access state information to the right by a bit corresponding to a processing cycle, and to supplement a bit corresponding to a processing cycle on the left side of the fused access state information, and set the value of the supplemented bit on the left side to a preset value.

[0102] Exemplarily, when the access action information includes 00100 and the historical access status information includes 00000, the status integration circuit can perform bitwise OR processing on the access action information and the historical access status information to obtain the fused access status information 00100. After sending the fused access information to the update circuit 82, the update circuit 82 shifts the bit corresponding to one processing cycle to the right to obtain 0010, supplements the bit corresponding to one processing cycle on the left, and sets it to a preset value, such as "0", to obtain 00010 as the new historical access status information. Here, due to the shift of the bit corresponding to one processing cycle, the operation originally corresponding to the third processing cycle is changed to the operation corresponding to the second processing cycle relative to the current processing cycle. Through such a shift operation, the operation can be changed in the processing cycle in accordance with the current processing cycle in the continuous updating of the processing cycle. In this way, the historical access status information obtained corresponds to the current processing cycle, and the conflict detection circuit 40 can determine whether there is a conflict in the instruction to be issued according to the access action information corresponding to the current processing cycle and the historical access status information corresponding to the current processing cycle in the access status register 70.

[0103] In another embodiment of the present disclosure, a specific embodiment of using an instruction transmitting device to perform conflict detection on instructions to be transmitted is also provided. Fig. 9FIG. 1 is a schematic diagram of a command transmitting device applied to a specific embodiment provided by the present disclosure. For this specific embodiment, wherein:

[0104] (1): In the first processing cycle t1, the instruction to be issued is a1. The instruction issuing unit 10 determines the conflict detection signal b1 according to the instruction to be issued a1. The conflict detection signal b1 includes type information: normalization operation and enable signal. The instruction issuing unit 10 sends the conflict detection signal to the signal conversion circuit 30 and the logic processing circuit 50.

[0105] After receiving the conflict detection signal sent by the instruction issuing unit 10, the signal conversion circuit 30 selects the corresponding transmission path i3 (here, for the convenience of explanation, the input port i3 described above is replaced by the input port i4) according to the type information contained therein: normalization operation. 30-1 ~I 30-n The signal conversion circuit 30 transmits the access action information 00100 to the state integration circuit 81 and the logic processing circuit 50 .

[0106] When receiving the access action information 00100, the state integration circuit 81 can synchronously read the stored historical access state information from the access state register 70. Since the current processing cycle is the first processing cycle, the historical access state information stored in the access state register 70 is, for example, 00000. The state integration circuit 81 performs bitwise OR processing on the access action information 00100 and the historical access state information 00000 to obtain the fused access state information 00100. The state integration circuit 81 sends the fused access state information 00100 to the update circuit 82.

[0107] After receiving the fused access status information 00100, the update circuit 82 performs a right shift by the bit corresponding to a processing cycle, and fills the bit corresponding to a cycle on the left to obtain the historical access status information 00010 as the new historical access status information.

[0108] The updating circuit 82 sends the historical access status information determined in the current processing cycle t1 to the access status register 70, and sends the historical access status information 00000 to the logic processing circuit 50. The access status register 70 updates the historical access status information 00000 stored therein to 00010.

[0109] After receiving the conflict detection signal b1 sent by the instruction issuing unit 10, the logic processing circuit 50 determines the access action information 00100 sent by the receiving signal conversion circuit 30 and the historical access status information 00000 sent by the access status register 70 according to the enable signal included in the conflict detection signal b1. After receiving the access action information 00100 and the historical access status information 00000, a bitwise AND process is performed to obtain the conflict indication signal 00000, and the conflict indication signal 00000 is sent to the conflict decision circuit 60.

[0110] After the conflict decision circuit 60 receives the conflict indication signal 00000, the conflict decision circuit 60 performs a bitwise OR process on the conflict indication signal to obtain a conflict detection result signal “0”, and feeds the conflict detection result signal back to the instruction issuing unit 10 .

[0111] After receiving the conflict detection result signal fed back by the conflict decision unit, the instruction issuing unit 10 determines that the instruction a1 to be issued corresponding to the current processing cycle t1 does not cause a conflict, and accordingly sends the instruction a1 to be issued.

[0112] (2): In the second processing cycle t2, the instruction to be issued is a2. The instruction issuing unit 10 determines the conflict detection signal b2 according to the instruction to be issued is a2. The conflict detection signal b2 includes type information: addition operation and enable signal. The instruction issuing unit 10 sends the conflict detection signal to the signal conversion circuit 30 and the logic processing circuit 50.

[0113] After receiving the conflict detection signal sent by the instruction issuing unit 10, the signal conversion circuit 30 selects the corresponding transmission path i2 according to the type information contained therein: addition operation, and outputs the access action information 00010 corresponding to the transmission path i2. The signal conversion circuit 30 transmits the access action information 00010 to the state integration circuit 81 and the logic processing circuit 50.

[0114] When receiving the access action information 00010, the state integration circuit 81 can synchronously read the stored historical access state information from the access state register 70, that is, the historical access state information 00010 stored in the first processing cycle t1. The state integration circuit 81 performs bitwise OR processing on the access action information 00010 and the historical access state information 00010 to obtain the fused access state information 00010. The state integration circuit 81 sends the fused access state information 00010 to the update circuit 82.

[0115] After receiving the fused access status information 00010, the update circuit 82 performs a right shift by the bit corresponding to a processing cycle, and fills the bit corresponding to a cycle on the left to obtain the historical access status information 00001 as the new historical access status information.

[0116] The updating circuit 82 sends the historical access status information determined in the current processing cycle t2 to the access status register 70, and sends the historical access status information 00010 to the logic processing circuit 50. The access status register 70 updates the historical access status information 00010 stored therein to 00001.

[0117] After receiving the conflict detection signal b2 sent by the instruction issuing unit 10, the logic processing circuit 50 determines the access action information 00010 sent by the receiving signal conversion circuit 30 and the historical access status information 00010 sent by the access status register 70 according to the enable signal included in the conflict detection signal b2. After receiving the access action information 00010 and the historical access status information 00010, a bitwise AND process is performed to obtain the conflict indication signal 00010, and the conflict indication signal 00010 is sent to the conflict decision circuit 60.

[0118] After the conflict decision circuit 60 receives the conflict indication signal 00010, the conflict decision circuit 60 performs a bitwise OR process on the conflict indication signal to obtain a conflict detection result signal “1”, and feeds the conflict detection result signal back to the instruction issuing unit 10 .

[0119] After receiving the conflict detection result signal fed back by the conflict decision unit, the instruction issuing unit 10 determines that the instruction a2 to be issued corresponding to the current processing cycle t2 has a conflict, and does not send out the instruction a2 to be issued, but uses it as the instruction a3 to be issued corresponding to the next processing cycle.

[0120] (3): In the third processing cycle t3, the instruction to be issued is a3, which is the instruction to be issued a2 corresponding to the second processing cycle. Similarly, according to the above steps, it is determined whether the instruction to be issued a3 will cause a resource access conflict, and whether to issue the instruction to be issued a3 is determined.

[0121] By analogy, it can be determined whether a conflict occurs for the to-be-issued instruction corresponding to each processing cycle.

[0122] In this way, for instructions to be issued that do not have any resource access conflicts, they can be issued directly; for instructions to be issued that have any resource access conflicts, the issuance can be paused in the current processing cycle to avoid conflicts; at the same time, the instructions to be issued corresponding to the next processing cycle are once again checked for resource access conflicts to ensure that the instructions to be issued are not lost and can be issued when there is no resource access conflict.

[0123] Based on the same inventive concept, an instruction transmitting method corresponding to the instruction transmitting device is also provided in the embodiment of the present disclosure. Since the principle of solving the problem by the method in the embodiment of the present disclosure is similar to that of the above-mentioned instruction transmitting device in the embodiment of the present disclosure, the implementation of the method can refer to the implementation of the device, and the repeated parts will not be repeated.

[0124] In another embodiment of the present disclosure, a method for transmitting an instruction is also provided. Fig.10 FIG. 1 is a flowchart of a method for transmitting an instruction provided by an embodiment of the present disclosure. The method for transmitting an instruction is applied to the instruction transmitting device described above. The method includes steps S101 to S103, wherein:

[0125] S101: The instruction issuing unit sends a conflict detection signal to the conflict detection circuit based on the instruction to be issued in the current processing cycle;

[0126] S102: In response to receiving a conflict detection signal sent by the instruction issuing unit, the conflict detection unit detects whether there is a resource access conflict between the instruction to be issued and the historically issued instruction based on the conflict detection signal, and feeds back the conflict detection result signal to the instruction issuing unit;

[0127] S103: the instruction issuing unit receives the conflict detection result signal fed back by the conflict detection unit; in response to the conflict detection result signal indicating that there is no resource access conflict between the instruction to be issued and the historically issued instruction, the instruction to be issued is issued.

[0128] In an optional embodiment, the instruction issuing method further includes: the instruction issuing unit responds to the conflict detection result signal indicating that there is a resource access conflict between the instruction to be issued and the historically issued instruction, uses the instruction to be issued as the instruction to be issued for the next processing cycle, and when the next processing cycle arrives, sends a conflict detection signal to the conflict detection circuit based on the instruction to be issued for the next processing cycle.

[0129] In an optional embodiment, the conflict detection signal includes: type information of the instruction to be issued; the conflict detection unit includes: a signal conversion circuit and a conflict detection circuit; the instruction issuance method includes: the signal conversion circuit, in response to receiving the type information sent by the instruction issuance unit, converts the type information into access action information corresponding to the instruction to be issued, and sends the access action information to the conflict detection circuit; wherein the access action information is used to indicate a resource access cycle corresponding to the instruction to be issued; the conflict detection circuit, in response to receiving the access action information sent by the signal conversion circuit, detects whether there is a resource access conflict between the instruction to be issued and the historically issued instruction based on the access action information and historical access status information, and feeds back the conflict detection result signal to the instruction issuance unit.

[0130] In an optional embodiment, the conflict detection signal also includes: an enable signal; the instruction transmission method includes: the conflict detection circuit responds to receiving the access action information sent by the signal conversion circuit and the enable signal sent by the instruction transmission unit, based on the access action information and historical access status information, detecting whether there is a resource access conflict between the instruction to be transmitted and the historically transmitted instruction, and feeding back the conflict detection result signal to the instruction transmission unit.

[0131] In an optional embodiment, the conflict detection circuit includes: a logic processing circuit and a conflict decision circuit; the instruction issuance method includes: the logic processing circuit determines a conflict indication signal based on the access action information and the historical access status information; sends the conflict indication signal to the conflict decision circuit; the conflict decision circuit determines whether there is a resource access conflict between the instruction to be issued and the historically issued instruction based on the conflict indication signal in response to receiving the conflict indication signal sent by the logic processing circuit, and feeds back the conflict detection result signal to the instruction issuance unit.

[0132] In an optional implementation, the logic processing circuit includes: an AND gate circuit; the conflict decision circuit includes: a first OR gate circuit; the instruction transmission method includes: the AND gate circuit performs bitwise AND processing on the access action information and the historical access status information to obtain the conflict indication signal; the first OR gate circuit performs bitwise OR processing on the conflict indication signal to obtain the conflict detection result signal.

[0133] In an optional embodiment, the signal conversion circuit includes: a selector; the instruction transmission method includes: the selector, in response to receiving the type information sent by the instruction transmission unit, selects the transmission path corresponding to the type information, outputs access action information corresponding to the transmission path, and transmits the access action information to the conflict detection circuit.

[0134] In an optional implementation, the instruction transmission method is applied to the instruction transmission device, and the instruction transmission device also includes: an access status register; the instruction transmission method includes: the access status register stores the historical access status information; the conflict detection circuit reads the historical access status information from the access status register.

[0135] In an optional embodiment, the instruction transmitting method is applied to the instruction transmitting device, and the instruction transmitting device also includes: a historical access status information update circuit; the instruction transmitting method includes: the signal conversion circuit transmits the access action information to the historical access status information update circuit; the historical access status information update circuit receives the access action information sent by the signal conversion circuit, and reads the historical access status information from the access status register; based on the access action information and the historical access status information, generates new historical access status information; and updates the new historical access status information to the access status register; wherein, the new historical access status information is used to generate a conflict detection result signal for a future processing cycle.

[0136] In an optional embodiment, the historical access status information update circuit includes: a status integration circuit and an update circuit; the instruction issuance method includes: the status integration circuit receives the access action information sent by the signal conversion circuit, and reads the historical access status information from the access status register, integrates the access action information and the historical access status information to obtain fused access status information; sends the fused access status information to the update circuit; the update circuit shifts the fused access status information in response to receiving the fused access status information sent by the status integration circuit to obtain the new historical access status information, and updates the new historical access status information to the access status register.

[0137] In an optional embodiment, the state integration circuit includes: a second OR gate circuit; the update circuit includes: a shift circuit; the instruction transmission method includes: the second OR gate circuit performs bitwise OR processing on the access action information and the historical access status information to obtain the fused access status information; the shift circuit shifts the fused access status information to the right by a bit corresponding to a processing cycle, and supplements a bit corresponding to a processing cycle on the left side of the fused access status information, and sets the supplemented bit value on the left side to a preset value.

[0138] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0139] The embodiment of the present disclosure further provides a computer device, including: an instruction memory and an instruction transmitting device provided by the embodiment of the present disclosure.

[0140] An embodiment of the present disclosure further provides a computer-readable storage medium having a computer program stored thereon, wherein the program is executed by an instruction transmitting unit and a conflict detection unit to execute a method provided by any instruction transmitting method embodiment of the present disclosure.

[0141] The present disclosure also provides a computer program product that carries a program code. The program code includes instructions that can be used to execute the steps of the instruction transmission method described in the above method embodiment. For details, please refer to the above method embodiment, which will not be repeated here.

[0142] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is implemented as a computer storage medium. In another optional embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0143] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0144] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0145] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0146] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0147] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present disclosure, which are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present disclosure, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A command transmitting device, characterized in that: include: A command issuing unit, and a conflict detecting unit; The instruction transmitting unit is used to send a conflict detection signal to the conflict detection unit based on the instruction to be transmitted in the current processing cycle; receiving a conflict detection result signal fed back by a conflict detection unit based on the conflict detection signal; In response to the conflict detection result signal indicating that there is no resource access conflict between the to-be-issued instruction and the historically-issued instruction, transmitting the to-be-issued instruction; The conflict detection unit is used to detect whether there is a resource access conflict between the to-be-issued instruction and the historically-issued instruction in response to receiving a conflict detection signal sent by the instruction-issuing unit, based on the conflict detection signal, and to feed back the conflict detection result signal to the instruction-issuing unit; The conflict detection signal includes: type information of the instruction to be transmitted; The conflict detection unit includes: a signal conversion circuit and a conflict detection circuit; The signal conversion circuit, in response to receiving the type information sent by the instruction issuing unit, converts the type information into access action information corresponding to the instruction to be issued, and sends the access action information to the conflict detection circuit; wherein the access action information is used to indicate a resource access cycle corresponding to the instruction to be issued; The conflict detection circuit is used to detect whether there is a resource access conflict between the to-be-issued instruction and the historically-issued instruction in response to receiving the access action information sent by the signal conversion circuit, based on the access action information and the historical access status information, and to feed back the conflict detection result signal to the instruction-issuing unit; The conflict detection circuit includes: a logic processing circuit and a conflict decision circuit; The logic processing circuit is used to determine a conflict indication signal based on the access action information and the historical access status information; and send the conflict indication signal to the conflict decision circuit; The conflict decision circuit is used to determine whether there is a resource access conflict between the to-be-issued instruction and the historically-issued instruction in response to receiving the conflict indication signal sent by the logic processing circuit, based on the conflict indication signal, and to feed back the conflict detection result signal to the instruction-issuing unit; The logic processing circuit includes: an AND gate circuit; the conflict decision circuit includes: a first OR gate circuit; The AND gate circuit is used to perform bitwise AND processing on the access action information and the historical access status information to obtain the conflict indication signal; The first OR gate circuit is used to perform bitwise OR processing on the conflict indication signal to obtain the conflict detection result signal.

2. The instruction transmitting device according to claim 1, characterized in that: The instruction issuing unit is also used for: in response to the conflict detection result signal indicating that there is a resource access conflict between the instruction to be issued and the historically issued instruction, using the instruction to be issued as the instruction to be issued for the next processing cycle, and when the next processing cycle arrives, sending a conflict detection signal to the conflict detection circuit based on the instruction to be issued for the next processing cycle.

3. The instruction transmitting device according to claim 1, characterized in that: The conflict detection signal also includes: an enable signal; The conflict detection circuit is used to respond to the access action information sent by the signal conversion circuit and the enable signal sent by the instruction issuance unit, detect whether there is a resource access conflict between the instruction to be issued and the historical issuance instruction based on the access action information and the historical access status information, and feedback the conflict detection result signal to the instruction issuance unit.

4. The instruction transmitting device according to any one of claims 1 to 3, characterized in that: The signal conversion circuit comprises: a selector; The selector is used to select the transmission path corresponding to the type information in response to receiving the type information sent by the instruction emission unit, output the access action information corresponding to the transmission path, and transmit the access action information to the conflict detection circuit.

5. The instruction transmitting device according to any one of claims 1 to 3, characterized in that: Also includes: Access the status register; The access status register is used to store the historical access status information; The conflict detection circuit is further used to read the historical access status information from the access status register.

6. The instruction transmitting device according to claim 5, characterized in that: Also included: a historical access status information updating circuit; The signal conversion circuit is further used to transmit the access action information to the historical access status information updating circuit; The historical access status information update circuit is used to receive the access action information sent by the signal conversion circuit and read the historical access status information from the access status register; generate new historical access status information based on the access action information and the historical access status information; and update the new historical access status information to the access status register; wherein the new historical access status information is used to generate a conflict detection result signal for a future processing cycle.

7. The instruction transmitting device according to claim 6, characterized in that: The historical access status information updating circuit includes: a status integration circuit and an updating circuit; The state integration circuit is used to receive the access action information sent by the signal conversion circuit, read the historical access state information from the access state register, integrate the access action information and the historical access state information to obtain fused access state information; and send the fused access state information to the update circuit; The update circuit is used for, in response to receiving the fused access state information sent by the state integration circuit, performing shift processing on the fused access state information to obtain the new historical access state information, and updating the new historical access state information to the access state register.

8. The instruction transmitting device according to claim 7, characterized in that: The state integration circuit includes: a second OR gate circuit; the update circuit includes: a shift circuit; The second OR gate circuit is used to perform bitwise OR processing on the access action information and the historical access status information to obtain the fused access status information; The shift circuit is used to shift the fused access state information to the right by a bit corresponding to a processing cycle, and to supplement a bit corresponding to a processing cycle on the left side of the fused access state information, and to set the value of the supplemented bit on the left side to a preset value.

9. A command transmission method, characterized in that: Applied to command transmitting device; The instruction transmitting device comprises: an instruction transmitting unit and a conflict detection unit; the instruction transmitting method comprises: The instruction transmitting unit sends a conflict detection signal to the conflict detection unit based on the instruction to be transmitted in the current processing cycle; The conflict detection unit detects whether there is a resource access conflict between the to-be-issued instruction and the historically-issued instruction based on the conflict detection signal in response to receiving the conflict detection signal sent by the instruction-issuing unit, and feeds back the conflict detection result signal to the instruction-issuing unit; The instruction transmitting unit receives the conflict detection result signal fed back by the conflict detection unit; in response to the conflict detection result signal indicating that there is no resource access conflict between the instruction to be transmitted and the historical transmitted instruction, transmits the instruction to be transmitted; The conflict detection signal includes: type information of the instruction to be transmitted; The conflict detection unit includes: a signal conversion circuit and a conflict detection circuit; The instruction transmission method comprises: the signal conversion circuit, in response to receiving the type information sent by the instruction transmission unit, converts the type information into access action information corresponding to the instruction to be transmitted, and sends the access action information to the conflict detection circuit; wherein the access action information is used to indicate the resource access cycle corresponding to the instruction to be transmitted; In response to receiving the access action information sent by the signal conversion circuit, the conflict detection circuit detects whether there is a resource access conflict between the to-be-issued instruction and the historically-issued instruction based on the access action information and the historical access status information, and feeds back the conflict detection result signal to the instruction-issuing unit; The conflict detection circuit includes: a logic processing circuit and a conflict decision circuit; The instruction transmission method comprises: the logic processing circuit determines a conflict indication signal based on the access action information and the historical access status information; and sends the conflict indication signal to the conflict decision circuit; The conflict decision circuit, in response to receiving the conflict indication signal sent by the logic processing circuit, determines whether there is a resource access conflict between the to-be-issued instruction and the historically-issued instruction based on the conflict indication signal, and feeds back the conflict detection result signal to the instruction-issuing unit; The logic processing circuit includes: an AND gate circuit; the conflict decision circuit includes: a first OR gate circuit; The instruction transmission method comprises: the AND gate circuit performs bitwise AND processing on the access action information and the historical access status information to obtain the conflict indication signal; The first OR gate circuit performs bitwise OR processing on the conflict indication signal to obtain the conflict detection result signal.

10. A chip, characterized in that: include: The instruction transmitting device as claimed in any one of claims 1 to 8.

11. A computer device, characterized in that: include: An instruction memory and an instruction transmitting device as claimed in any one of claims 1 to 8.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program. When the computer program is executed by a computer device, the computer device executes the steps of the instruction transmitting method according to claim 9.

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