Semiconductor package device and method of manufacturing the same

Abstract

This disclosure relates to a semiconductor packaging apparatus and a method for manufacturing the same. The semiconductor packaging apparatus includes: a first redistribution layer; a reinforcing layer disposed on the first redistribution layer; and a first electronic component disposed on the reinforcing layer and electrically connected to the first redistribution layer via a first connecting line. This semiconductor packaging apparatus and method for manufacturing the same can avoid the need for filler material between the first electronic component and the first redistribution layer, thereby preventing structural breakage caused by thermal expansion of the filler material and improving product yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to semiconductor packaging apparatus and manufacturing methods thereof. Background Technology

[0002] FOCoS (Fan Out Chip on Substrate) packaging technology is implemented by using a fan-out composite chip on a typical ball grid array substrate.

[0003] In FOCoS packaging devices, an underfill material is typically placed between the chip and the fan-out layer. During thermal cycling, the underfill material expands due to heat, causing delamination at the interface between the underfill material and the chip, as well as cracking within the underfill material. These cracks can further extend to the fan-out layer, damaging it and affecting product yield.

[0004] Therefore, it is necessary to propose a new technical solution to solve at least one of the above-mentioned technical problems. Summary of the Invention

[0005] This disclosure provides a semiconductor packaging device and a method for manufacturing the same.

[0006] In a first aspect, this disclosure provides a semiconductor packaging apparatus, comprising:

[0007] First wiring layer;

[0008] A reinforcement layer is disposed on the first rewiring layer;

[0009] A first electronic component is disposed on the reinforcing layer and electrically connected to the first redistribution layer via a first connecting line.

[0010] In some alternative implementations, the reinforcing layer is provided with a circuit pattern, which is electrically connected to the first redistribution layer via a second connecting line.

[0011] In some alternative embodiments, a second electronic component is further disposed on the reinforcing layer, the second electronic component being electrically connected to the first redistribution layer via a third connecting line.

[0012] In some alternative implementations, the first electronic component and the second electronic component are electrically connected through the first redistribution layer.

[0013] In some alternative implementations, the first redistribution layer includes fine lines through which the first electronic component and the second electronic component are electrically connected.

[0014] In some alternative implementations, the fine lines are located in the vertical projection area of ​​the reinforcing layer.

[0015] In some alternative embodiments, a second rewiring layer is provided between the reinforcing layer and the first rewiring layer, the second rewiring layer including fine lines, through which the first electronic component and the second electronic component are electrically connected.

[0016] In some alternative implementations, the reinforcement layer is attached to the first rewiring layer.

[0017] In some alternative embodiments, a second wiring layer is disposed between the reinforcing layer and the first wiring layer, the second wiring layer being electrically connected to the first wiring layer, and the reinforcing layer being attached to the second wiring layer.

[0018] In some alternative embodiments, the reinforcing layer has a accommodating space within which the first electronic component is located.

[0019] Secondly, this disclosure provides a method for manufacturing a semiconductor packaging device, including:

[0020] A circuit pattern is formed on the reinforcing layer;

[0021] The first electronic component is disposed on the reinforcing layer;

[0022] The reinforcement layer is disposed on the first rewiring layer;

[0023] The first electronic component and the first redistribution layer are electrically connected via a first connection line, and the circuit pattern and the first redistribution layer are electrically connected via a second connection line.

[0024] In some alternative implementations, forming the circuit pattern on the reinforcing layer includes:

[0025] A circuit pattern is formed on the first surface of the reinforcing layer, and a second redistribution layer is formed on the second surface of the reinforcing layer; and

[0026] The step of placing the reinforcement layer on the first redistribution layer includes:

[0027] The second wiring layer is electrically flip-chip connected to the first wiring layer.

[0028] In the semiconductor packaging apparatus and manufacturing method disclosed herein, by providing a reinforcing layer on the first redistribution layer and providing a first electronic component on the reinforcing layer, it is possible to avoid providing a filler material between the first electronic component and the first redistribution layer, thereby avoiding structural fracture caused by thermal expansion of the filler material, which is beneficial to improving product yield. Attached Figure Description

[0029] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0030] Figures 1A-1C This is a schematic diagram of a semiconductor packaging device in the prior art;

[0031] Figures 2-4 These are first to third schematic diagrams of a semiconductor packaging apparatus according to embodiments of the present invention;

[0032] Figures 5-13 This is a schematic diagram of a method for manufacturing a semiconductor packaging device according to an embodiment of the present invention.

[0033] Symbol explanation:

[0034] 11. Fan-out layer; 12. Left chip; 13. Right chip; 14. Filler material; 15. Capacitor; 16. Reinforcing component; 17. Substrate; 100. First redistribution layer; 200. Second redistribution layer; 210. Fine line; 310. First electronic component; 320. Second electronic component; 410. First connecting line; 420. Second connecting line; 430. Third connecting line; 500. Reinforcing layer; 510. Circuit pattern; 520. Accommodation space; 600. Solder. Detailed Implementation

[0035] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0036] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0037] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0038] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0039] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used in this disclosure to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used in this disclosure may be interpreted accordingly.

[0040] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0041] Figure 1A This is a schematic diagram of a semiconductor packaging device in the prior art. For example... Figure 1A As shown, the semiconductor packaging device includes a fan-out layer 11, a left-side chip 12, and a right-side chip 13. The left-side chip 12 and the right-side chip 13 are disposed on the fan-out layer 11. Filler material 14 is disposed between the left-side chip 12 and the fan-out layer 11, between the right-side chip 13 and the fan-out layer 11, and between the left-side chip 12 and the right-side chip 13. The coefficient of thermal expansion of the filler material 14 is greater than that of the chip (including the left-side chip 12 and the right-side chip 13). When heated, the filler material 14 will undergo greater thermal expansion deformation relative to the chip. This mismatch in deformation between the filler material 14 and the chip can cause fractures within the filler material 14, which can then extend further to the fan-out layer 11, leading to fractures in the fan-out layer 11 (e.g., ...). Figure 1A (As shown in the dashed circle), it affects product yield.

[0042] In order to improve structural strength, Figure 1BIn the semiconductor packaging apparatus shown, reinforcing members 16 are disposed above the left chip 12 and the right chip 13. However, in this semiconductor packaging apparatus, filling material 14 still needs to be disposed between the left chip 12 and the fan-out layer 11, between the right chip 13 and the fan-out layer 11, and between the left chip 12 and the right chip 13, thus failing to fundamentally solve the problem of... Figure 1A Similar structural fracture issues to those found in semiconductor packaging devices.

[0043] This disclosure provides a semiconductor packaging apparatus. Figures 2-4 These are first to third schematic diagrams of a semiconductor packaging apparatus according to embodiments of the present invention.

[0044] Figure 2 This is a first schematic diagram of a semiconductor packaging apparatus according to an embodiment of the present invention. Figure 2 As shown, the semiconductor packaging device includes a first redistribution layer 100, a reinforcement layer 500, a first electronic component 310, and a second electronic component 320. The reinforcement layer 500 is disposed on the first redistribution layer 100. Both the first electronic component 310 and the second electronic component 320 are disposed on the reinforcement layer 500. The first electronic component 310 is electrically connected to the first redistribution layer 100 via a first bonding wire 410. The second electronic component 320 is electrically connected to the first redistribution layer 100 via a third bonding wire 430. The material of the reinforcement layer 500 is, for example, silicon.

[0045] like Figure 2 As shown, a circuit pattern 510 is also provided on the reinforcing layer 500. The circuit pattern 510 is electrically connected to the first redistribution layer 100 via a second connecting line 420. The circuit pattern 510 is, for example, a capacitor structure or an inductor structure.

[0046] like Figure 2 As shown, since the first electronic component 310 and the second electronic component 320 have a large number of input / output (I / O) operations, a thin line 210 is provided in the first rewiring layer 100 to realize the electrical connection between the first electronic component 310 and the second electronic component 320. The electrical signal in the first electronic component 310 can be transmitted to the first rewiring layer 100 through the first connecting line 410, and then transmitted from left to right through the thin line 210 within the first rewiring layer 100, and finally transmitted to the second electronic component 320 through the third connecting line 430, and vice versa. The thin line 210 is located in the vertical projection area of ​​the reinforcing layer 500.

[0047] Figure 3 yes Figure 2 This is a variation of the semiconductor packaging device shown. Figure 2In the semiconductor packaging device shown, the reinforcing layer 500 is directly attached to the first redistribution layer 100, and the two are connected by means of adhesive bonding or similar methods. Figure 3 In the semiconductor packaging device shown, a second wiring layer 200 is disposed between the reinforcing layer 500 and the first wiring layer 100, and the reinforcing layer 500 is attached to the second wiring layer 200. The second wiring layer 200 and the first wiring layer 100 can be connected by solder 600.

[0048] In addition, Figure 2 In the semiconductor packaging device shown, fine lines 210 are disposed in the first wiring layer 100. And... Figure 3 In the semiconductor packaging device shown, fine lines 210 are disposed in the second wiring layer 200. For Figure 3 The semiconductor packaging device shown can manufacture fine lines 210 separately outside the process of the first wiring layer 100, which can avoid the entire first wiring layer 100 being defective due to the failure of the fine lines, thus improving the product yield.

[0049] Figure 4 yes Figure 3 This is a variation of the semiconductor packaging device shown. Figure 3 In the semiconductor packaging device shown, the reinforcing layer 500 has a accommodating space 520, within which the first electronic component 310 and the second electronic component 320 are located. Figure 4 In the semiconductor packaging device shown, the reinforcing layer 500 does not have a accommodating space 520, and the first electronic component 310 and the second electronic component 320 are directly disposed on the upper surface of the reinforcing layer 500.

[0050] In the semiconductor packaging apparatus provided in the embodiments of this disclosure, by providing a reinforcing layer 500 on the first redistribution layer 100 and providing a first electronic component 310 on the reinforcing layer 500, it is possible to avoid providing a filling material 14 between the first electronic component 310 and the first redistribution layer 100, thereby avoiding structural breakage caused by thermal expansion of the filling material 14, which is beneficial to improving product yield.

[0051] In addition, such as Figure 1C As shown, in existing semiconductor packaging devices, capacitor 15 and left-side chip 12 need to transmit signals through the lower substrate 17 and fan-out layer 11, such as... Figure 1C As shown by the dashed lines in the diagram. In the semiconductor packaging device of this embodiment, the capacitor structure (i.e., circuit pattern 510) and the first electronic component 310 can transmit signals through the first wiring, redistribution layer and the second connection line 420 without passing through the substrate 17. Therefore, the signal transmission path can be shortened, which is beneficial to improving the signal transmission efficiency.

[0052] This disclosure also provides a method for manufacturing a semiconductor packaging device.

[0053] Figures 5-9 This is a first embodiment of a method for manufacturing a semiconductor packaging device according to an embodiment of the present invention, specifically including the following steps:

[0054] First step, such as Figure 5 As shown, a second wiring layer 200 is formed on the first side of the reinforcing layer 500, wherein the second wiring layer 200 includes fine lines 210.

[0055] The second step, as Figure 6 As shown, a circuit pattern 510 is formed on the second side of the reinforcing layer 500.

[0056] The third step, as Figure 7 As shown, an accommodating space 520 is formed on the second side of the reinforcing layer 500.

[0057] Step four, as Figure 8 As shown, the first electronic component 310 and the second electronic component 320 are disposed within the accommodating space 520 of the reinforcing layer 500.

[0058] Fifth step, as Figure 9 As shown, the reinforcement layer 500 is placed on the pre-fabricated first rewiring layer 100.

[0059] The sixth step involves electrically connecting the first electronic component 310 and the first redistribution layer 100 via the first connecting line 410, electrically connecting the circuit pattern 510 and the first redistribution layer 100 via the second connecting line 420, and electrically connecting the second electronic component 320 and the first redistribution layer 100 via the third connecting line 430, to obtain the following... Figure 3 The semiconductor packaging device shown.

[0060] Figures 10-13 This is a second embodiment of the method for manufacturing a semiconductor packaging device according to an embodiment of the present invention, specifically including the following steps:

[0061] First step, such as Figure 10 As shown, a circuit pattern 510 is formed on the surface of the reinforcing layer 500.

[0062] The second step, as Figure 11 As shown, an accommodating space 520 is formed on the surface of the reinforcing layer 500.

[0063] The third step, as Figure 12 As shown, the first electronic component 310 and the second electronic component 320 are disposed within the accommodating space 520 of the reinforcing layer 500.

[0064] Step four, as Figure 13As shown, a reinforcement layer 500 is disposed on a pre-fabricated first wiring layer 100, wherein the first wiring layer 100 includes fine lines 210.

[0065] Fifth step: The first electronic component 310 and the first redistribution layer 100 are electrically connected via the first connecting line 410; the circuit pattern 510 and the first redistribution layer 100 are electrically connected via the second connecting line 420; and the second electronic component 320 and the first redistribution layer 100 are electrically connected via the third connecting line 430, to obtain the following... Figure 2 The semiconductor packaging device shown.

[0066] The manufacturing method of the semiconductor packaging device provided in this disclosure can achieve similar technical effects to the semiconductor packaging device described above, and will not be repeated here.

[0067] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed in this disclosure have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated in this disclosure, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor packaging device, comprising: First wiring layer; A reinforcement layer is disposed on the first rewiring layer; A first electronic component is disposed on the reinforcing layer and electrically connected to the first redistribution layer via a first connecting line; The reinforcing layer is further provided with a second electronic component, which is electrically connected to the first redistribution layer via a third connecting line; The first rewiring layer includes fine lines, through which the first electronic component and the second electronic component are electrically connected; The reinforcing layer has a accommodating space, within which the first electronic component and the second electronic component are located.

2. The semiconductor package device of claim 1, wherein, The fine lines are located in the vertical projection area of ​​the reinforcing layer.

3. The semiconductor package device of claim 1, wherein, The reinforcement layer is attached to the first rewiring layer.

4. A semiconductor packaging apparatus, comprising: First wiring layer; A reinforcement layer is disposed on the first rewiring layer; A first electronic component is disposed on the reinforcing layer and electrically connected to the first redistribution layer via a first connecting line; The reinforcing layer is further provided with a second electronic component, which is electrically connected to the first redistribution layer via a third connecting line; A second wiring layer is provided between the reinforcing layer and the first wiring layer. The second wiring layer includes fine lines, and the first electronic component and the second electronic component are electrically connected through the fine lines. The reinforcing layer has a accommodating space, within which the first electronic component and the second electronic component are located.

5. The semiconductor package device of claim 4, wherein, The second wiring layer is electrically connected to the first wiring layer, and the reinforcement layer is attached to the second wiring layer.

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