Display device and mobile terminal device including the same

Abstract

Disclosed are a display device and a mobile terminal device including the display device. The display device includes a display panel, the display panel including a display area having a plurality of display pixels and a sensing area having a plurality of display pixels and a plurality of sensor pixels. In display mode, the display pixels in the display area and the display pixels in the first sensing area emit light by receiving data voltages from an input image. In fingerprint recognition mode, the sensor pixels in the first sensing area generate current based on light reflected from a fingerprint. In the first sensing area, the resolution of the display pixels is lower than the resolution of the sensor pixels.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0095198, filed on Jul. 30, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device having a fingerprint sensor and a mobile terminal device including the display device. Background Art

[0004] According to the material of the light-emitting layer, electroluminescent display devices are roughly divided into inorganic light-emitting display devices and organic light-emitting display devices. Active matrix organic light-emitting display devices include organic light-emitting diodes (hereinafter referred to as "OLEDs"), which emit light themselves and have the advantages of fast response speed, high luminous efficiency, high brightness and wide viewing angle. In an organic light-emitting display device, an OLED is formed in a pixel. Since the organic light-emitting display device has a faster response speed and is excellent in luminous efficiency, brightness and viewing angle, and can also display black grayscale in full black, the organic light-emitting display device is excellent in contrast and color reproducibility.

[0005] Recently, organic light-emitting display devices have become widely used as display devices in mobile devices. Biometric technology is also being used for user authentication in mobile devices. As an example of biometric technology, fingerprint sensors are widely used in smartphones because they provide security and convenience during user authentication. Fingerprint sensors used in smartphones sense the user's fingerprint when unlocking the screen or performing user authentication.

[0006] Due to the fingerprint sensor, there are many limitations on the screen design of smartphones. For example, since the existing button-type fingerprint sensor is set below the screen of the display device, the button-type fingerprint sensor is an obstacle that makes it impossible to expand the screen size and achieve full-screen display. In order to achieve full-screen display, a fingerprint recognition under the screen (FOD) technology has been developed to place the fingerprint sensor under the screen of the display panel and sense the fingerprint on the screen. Since the fingerprint sensor module should be located below the screen to achieve FOD, the thickness of the display device is increased, and the process of assembling the display panel and the fingerprint sensor module is increased, resulting in the problem of reduced yield and increased manufacturing cost. Summary of the Invention

[0007] The present disclosure is intended to address all of the above-mentioned needs and problems.

[0008] The present disclosure relates to a display device and a mobile terminal device including the display device. In the display device, sensor pixels are embedded in a display panel, so that the process of assembling the display panel and a fingerprint sensor module is unnecessary and fingerprint recognition can be performed.

[0009] It should be noted that the objects of the present disclosure are not limited to the above objects, and other objects of the present disclosure will become apparent to those skilled in the art through the following description.

[0010] According to one aspect of the present disclosure, a display device is provided, comprising a display panel including a display area having a plurality of display pixels, and a first sensing area having a plurality of display pixels and a plurality of sensor pixels. In a display mode, the display pixels of the display area and the display pixels of the first sensing area can emit light by receiving a data voltage of an input image. In a fingerprint recognition mode, the sensor pixels in the first sensing area can generate a current based on light reflected from a fingerprint. The resolution of the display pixels in the first sensing area can be lower than the resolution of the sensor pixels in the first sensing area.

[0011] According to another aspect of the present disclosure, a mobile terminal device including the above display device is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0013] Figure 1 is a schematic diagram showing a display device according to an embodiment of the present disclosure;

[0014] Figure 2 is a flowchart illustrating a method for driving a first sensing area in a fingerprint recognition mode according to an embodiment of the present disclosure;

[0015] Figure 3 is a diagram illustrating a fingerprint sensing method on a display screen of a mobile terminal device;

[0016] Figure 4 is a diagram showing an example of a display area according to one embodiment of the present disclosure;

[0017] Figure 5 is a view showing an example of a first sensing area according to one embodiment of the present disclosure;

[0018] Figure 6 is a view showing an example of a first sensing area according to another embodiment of the present disclosure;

[0019] Figure 7is a view showing an example of a second sensing area according to one embodiment of the present disclosure;

[0020] Figure 8A and Figure 8B is a view illustrating a method of registering a fingerprint image using a first sensing area;

[0021] Figure 9 is a block diagram illustrating a display panel and a display panel driver according to an embodiment of the present disclosure;

[0022] Figure 10 is a schematic block diagram showing the configuration of a driver integrated circuit (IC);

[0023] Figure 11 is a circuit diagram showing an example of a pixel circuit;

[0024] Figure 12 is a circuit diagram showing another example of a pixel circuit;

[0025] Figure 13 It shows Figure 11 and Figure 12 A waveform diagram of a driving method for a pixel circuit shown;

[0026] Figure 14 is a detailed cross-sectional view showing a cross-sectional structure of a display panel according to one embodiment of the present disclosure;

[0027] Figure 15 is a diagram showing a cross-sectional structure of an organic photodiode of a sensor pixel and a light emitting element of a display pixel according to one embodiment of the present disclosure;

[0028] Figure 16 is a detailed view showing a display period (active interval) and a vertical blank period of one frame period;

[0029] Figure 17 and Figure 18 is a diagram illustrating a method of driving a display device according to an embodiment of the present disclosure;

[0030] Figure 19 is a circuit diagram showing a pixel circuit and a sensor pixel driving circuit according to a first embodiment of the present disclosure;

[0031] Figure 20 It shows Figure 19 Waveform diagram of the pixel circuit and the driving method of the sensor pixel driving circuit shown;

[0032] Figure 21 is a circuit diagram showing a pixel circuit and a sensor pixel driving circuit according to a second embodiment of the present disclosure;

[0033] Figure 22 It shows Figure 21 Waveform diagram of the pixel circuit and the driving method of the sensor pixel driving circuit shown;

[0034] Figure 23 is a circuit diagram showing a pixel circuit and a photosensor driving circuit according to a third embodiment of the present disclosure;

[0035] Figure 24 It shows Figure 23 Waveform diagram of the driving method of the pixel circuit and the photosensor driving circuit shown;

[0036] Figure 25 is a circuit diagram showing a pixel circuit and a photosensor driving circuit according to a fourth embodiment of the present disclosure;

[0037] Figure 26 It shows Figure 25 Waveform diagram of the driving method of the pixel circuit and the photosensor driving circuit shown;

[0038] Figure 27 is a diagram showing metal layers of a pixel circuit and a photosensor driving circuit;

[0039] Figure 28 is a circuit diagram showing a gamma compensation voltage generator according to one embodiment of the present disclosure; and

[0040] Figure 29 is a view showing data voltages applied to pixels in a display area and data voltages applied to pixels in a sensing area. DETAILED DESCRIPTION

[0041] The advantages and features of the present disclosure and their implementation methods will be more clearly understood through the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in a variety of different forms. On the contrary, the presented embodiments will complete the disclosure of the present disclosure and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is limited only within the scope of the appended claims.

[0042] The shapes, sizes, proportions, angles, quantities, etc. shown in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. In this specification, similar reference numerals generally represent similar elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0043] Terms such as “comprising,” “including,” “having,” and “consisting of” used herein are generally intended to allow the addition of other components unless these terms are used with the term “only.” Any reference to the singular may include the plural unless explicitly stated otherwise.

[0044] Even if not explicitly stated, components are interpreted as including ordinary margins of error.

[0045] When terms such as "on", "above", "below", and "beside" are used to describe the positional relationship between two components, one or more components may be located between the two components unless these terms are used together with the terms "immediately adjacent" or "directly".

[0046] Terms such as “first” and “second” may be used to distinguish components from each other, but the function or structure of a component is not limited by the sequence number or name preceding the component.

[0047] The following embodiments may be combined or combined with each other in part or in whole, and the embodiments may be connected and operated in technically different ways. The embodiments may be performed independently or in association with each other.

[0048] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0049] refer to Figure 1 , the screen of the display panel 100 includes a pixel array on which an input image is reproduced. The pixel array includes a display area DA and first and second sensing areas SA and CA.

[0050] A first group of display pixels R, G, and B (in which pixel data is written) is disposed in the display area DA. A second group of display pixels R, G, and B and a plurality of sensor pixels S are disposed in the first sensing area SA. A third group of display pixels R, G, and B is disposed in the second sensing area CA.

[0051] The display area DA includes display pixels R, G, and B that are arranged at a high pixel density (pixels per inch, PPI) and display input data. The input data may be pixel data including an input image or data of various types of information.

[0052] The first sensing area SA includes display pixels R, G, and B (pixel data is written into the display pixels R, G, and B) and pixels of an image sensor that senses fingerprint patterns (hereinafter referred to as "sensor pixels"). Each sensor pixel S includes a photodiode that converts received light into an electric current. The first sensing area SA displays input data on the display pixels R, G, and B in the display mode, and senses fingerprints using the sensor pixels S in the fingerprint recognition mode. The display pixels R, G, and B and the sensor pixels S of the first sensing area SA share most lines and have similar cross-sectional structures. The display pixels R, G, and B can be arranged to be coplanar with the sensor pixels S. In this case, due to the portion occupied by the sensor pixels S, the PPI of the display pixels in the first sensing area SA can be lower than the PPI of the display pixels in the display area DA. The display pixels R, G, and B and the sensor pixels S of the first sensing area SA can be formed simultaneously with the existing manufacturing process without any additional process.

[0053] The second sensing area CA includes display pixels built into the display panel 100 and one or more optical sensors 30 disposed outside the display panel 100. A light receiving surface of the optical sensor 30 may be disposed below (or on a rear surface of) the display panel 100 in the second sensing area CA to face the second sensing area CA.

[0054] The display pixels of the second sensing area CA are arranged coplanar with the display pixels of the display area DA and the first sensing area SA. In display mode, pixel data is written to the display pixels of the second sensing area SA, so that the display pixels display the input image. The PPI of the display pixels R, G, and B in the first sensing area SA and the second sensing area CA can be the same.

[0055] The optical sensor 30 disposed in the second sensing area CA may include one or more imaging devices such as a camera, an infrared sensor, and an illuminance sensor. To reproduce an input image and increase light transmittance, the second sensing area CA may include low PPI display pixels and a light transmitting portion.

[0056] The PPI of each of the first sensing area SA and the second sensing area CA is lower than the PPI of the display area DA. In order to achieve no difference in image quality between the first sensing area SA and the display area DA, an image quality compensation algorithm that compensates for brightness and color coordinates may be applied to pixel data to be written into display pixels of the first sensing area SA and the second sensing area CA.

[0057] According to the present disclosure, the display pixels R, G, and B are not only provided in the display area DA, but also in the first sensing area SA and the second sensing area CA. Therefore, the display device of the present disclosure can realize full-screen display.

[0058] Each of the display pixels R, G, and B provided in the display area DA and the first and second sensing areas SA and CA includes sub-pixels of different colors to realize the color of the image. The sub-pixels include red sub-pixels (hereinafter referred to as "R sub-pixels"), green sub-pixels (hereinafter referred to as "G sub-pixels"), and blue sub-pixels (hereinafter referred to as "B sub-pixels"). Although not shown in the drawings, each pixel P may also include a white sub-pixel (hereinafter referred to as "W sub-pixel"). Each sub-pixel includes a pixel circuit and a light-emitting element. Figure 1 In FIG, R represents an R sub-pixel, G represents a G sub-pixel, and B represents a B sub-pixel.

[0059] At least one of the display pixels in the first sensing area SA can be driven as a light source in fingerprint recognition mode, which is executed when a fingerprint recognition event occurs. In fingerprint recognition mode, when a user places a fingerprint on the encapsulation glass 20 in the sensing area SA, the light source in the first sensing area SA is turned on. In fingerprint recognition mode, the sensor pixels S in the first sensing area SA are driven to convert light reflected from the user's fingerprint in contact with the encapsulation glass 20 into an electrical signal for transmission to the fingerprint recognition processor. The fingerprint recognition processor amplifies the output signal of the sensor pixel S and converts the output signal into digital data to generate fingerprint pattern data. Figure 1 The host system omitted in the figure compares the fingerprint pattern data from the fingerprint recognition processor with the fingerprint pattern of the pre-registered user and performs fingerprint authentication.

[0060] The fingerprint recognition processor may be integrated with a timing controller for controlling the operation timing of the display panel driver.

[0061] According to the present disclosure, since the fingerprint sensor module is not separately combined with the display panel 100, there is no reduction in yield due to a process of assembling the display panel 100 and the fingerprint sensor module, and manufacturing costs can be reduced.

[0062] The display panel 100 has a width in the X-axis direction, a length in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a circuit layer 12 disposed on a substrate, and a light-emitting element and sensor layer 14 disposed on the circuit layer 12. A polarizer 18 may be disposed on the light-emitting element and sensor layer 14, and an encapsulating glass 20 may be disposed on the polarizer 18.

[0063] The circuit layer 12 may include pixel circuits connected to data lines, gate lines, and power lines, a gate driver for driving the gate lines, and a sensor pixel driving circuit. The circuit layer 12 may include circuit elements such as transistors implemented as thin film transistors (TFTs) and capacitors.

[0064] The light-emitting element and sensor layer 14 may include a light-emitting element driven by a pixel circuit. The light-emitting element may be implemented as an organic light-emitting diode (OLED). The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, an emitting layer EML, an electron transport layer ETL, and an electron injection layer EIL, but the present disclosure is not limited thereto. When a voltage is applied to the anode and cathode of the OLED, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the emitting layer EML to form excitons, thereby emitting visible light from the emitting layer EML. The light-emitting element and sensor layer 14 may also include a color filter disposed on the circuit layer 12 and selectively transmitting red, green, and blue wavelengths.

[0065] The light emitting element and sensor layer 14 includes a photodiode formed on the same layer as the light emitting element.

[0066] The light-emitting element and sensor layer 14 may be covered by a protective film, which may also be covered by an encapsulation layer. The protective film and encapsulation layer may have a structure in which organic and inorganic layers are alternately stacked. The inorganic layers prevent the penetration of moisture and oxygen. The organic layers flatten the surface of the inorganic layers. When the organic and inorganic layers are stacked in multiple layers, the migration path of moisture and oxygen becomes longer than that of a single layer, effectively preventing the penetration of moisture and oxygen that could affect the light-emitting element and sensor layer 14.

[0067] Polarizing plate 18 may be bonded to the encapsulation layer. Polarizing plate 18 improves the outdoor visibility of the display device. Polarizing plate 18 reduces light reflected from the surface of display panel 100 and blocks light reflected from the metal of circuit layer 12, thereby increasing the brightness of the pixels. Polarizing plate 18 may be implemented as a polarizing plate bonded with a linear polarizer and a phase retarder film, or a circular polarizing plate.

[0068] Figure 2 is a flowchart illustrating a driving method of the first sensing area SA in a fingerprint recognition mode according to an embodiment of the present disclosure.

[0069] refer to Figure 2 When a fingerprint sensing event occurs, the first sensing area SA starts operating in the fingerprint recognition mode. The host system is connected to the display device, receives fingerprint pattern image data from the fingerprint recognition processor in an application requiring user authentication, and processes fingerprint authentication.

[0070] like Figure 3As shown, when the fingerprint recognition mode begins, the display device may display a first sensing area SA on the screen to guide the fingerprint sensing position (S01 and S02). In response to the output signal from the touch sensor or pressure sensor, the host system detects a finger placed in the first sensing area SA (S03). In response to a command from the host system, the fingerprint recognition processor drives the light source and sensor pixels S in the first sensing area SA to sense the fingerprint (S04 and S05). In the fingerprint recognition mode, the sensor pixels S perform photoelectric conversion on the light reflected from the user's fingerprint. The fingerprint recognition processor converts the output signal of the sensor pixels S into digital data to generate fingerprint pattern image data, and transmits the fingerprint pattern image data to the host system.

[0071] Figure 4 is a diagram showing an example of pixel arrangement in the display area DA. Figure 5 is a view showing an example of arrangement of pixels, photosensors, and light sources in the first sensing area SA. Figure 6 is a view showing an example of the arrangement of pixels and light transmission parts in the second sensing area CA. Figures 4 to 6 In FIG, the lines connected to the pixels and the lines connected to the sensor pixels are omitted.

[0072] refer to Figure 4 , the display area DA includes display pixels arranged in a matrix form. Each display pixel can be implemented as a real color pixel, wherein the three primary colors R, G and B sub-pixels are formed in one pixel. Alternatively, each display pixel can be formed so that two sub-pixels are formed in one pixel using a sub-pixel rendering algorithm. For example, a first display pixel PIX1 can be formed by an R sub-pixel and a first G sub-pixel, and a second display pixel PIX2 can be formed by a B sub-pixel and a second G sub-pixel. In each of the display pixels PIX1 and PIX2, insufficient color representation can be compensated by the average value of the corresponding color data between adjacent pixels.

[0073] refer to Figure 5 and Figure 6 The first sensing area SA includes display pixel groups PG spaced apart from each other, with sensor pixels S interposed between the display pixel groups PG. The X-axis and Y-axis represent two orthogonal directions. Θx and Θy represent tilt axis directions rotated 45° about the X-axis and Y-axis, respectively.

[0074] The display pixel group PG may include one or two display pixels. For example, one display pixel including R, G, and B sub-pixels may be provided in the display pixel group PG, or two display pixels including two sub-pixels may be included in the display pixel group PG. Figure 5 and Figure 6In the example, the first display pixel PIX1 may include an R sub-pixel and a first G sub-pixel, and the second display pixel PIX2 may be formed of a B sub-pixel and a second G sub-pixel.

[0075] The distance Pd between adjacent display pixel groups PG is substantially the same in the four directions X, Y, θx, and θy. Therefore, the display pixel groups PG in the first sensing area SA are spaced apart by equal distances in all directions. The distance between adjacent display pixel groups PG and sensor pixels S is also the same in all directions.

[0076] The sensor pixels S in the first sensing area SA are spaced apart at equal distances in all directions. The distance Pd between the display pixel groups PG is greater than the distance Ps between the sensor pixels S.

[0077] The distance Ps between adjacent sensor pixels S is substantially the same in the four directions X, Y, Θx and Θy. Each sensor pixel S includes a photodiode.

[0078] In a pixel group PG, the Figure 5 The sub-pixels are arranged in the form of a diamond shape as shown or as Figure 6 The sub-pixels are arranged in the form of a parallelogram shape as shown.

[0079] In the first sensing area SA, the resolution of the sensor pixels is greater than the resolution of the display pixels. Figure 5 and Figure 6 As can be seen from the unit area RES, in the first sensing area SA, the resolution of the display pixels is 1 / 4 of the resolution of the sensor pixels. Due to the higher resolution of the sensor pixels S, the fingerprint pattern can be accurately sensed. In addition, the resolution of the display pixels in the first sensing area SA is 1 / 4 of the resolution of the display area DA.

[0080] refer to Figure 7 The second sensing area CA includes display pixel groups PG spaced apart from each other with light transmission portions AG interposed therebetween. External light is incident on a light receiving surface of the optical sensor 30 disposed below the display panel 100 through the light transmission portions AG.

[0081] The display pixel group PG may include one or two display pixels in the second sensing area CA. For example, one display pixel including R, G, and B sub-pixels may be provided in the display pixel group PG, or two display pixels including two sub-pixels may be included in the display pixel group PG. Figure 5 and Figure 6In the example, the first display pixel PIX1 may include an R subpixel and a first G subpixel, and the second display pixel PIX2 may be formed of a B subpixel and a second G subpixel. The distances between adjacent display pixel groups PG are substantially the same in the four directions X, Y, θx, and θy.

[0082] In each pixel group PG in the second sensing area CA, sub-pixels may be arranged in a rhombus shape or a parallelogram shape.

[0083] The light transmission portion AG can be made of only a transparent medium to reduce optical loss of light incident on the optical sensor 30. The light transmission portion AG can be made of a transparent insulating material without including metal lines or pixels. The distance between adjacent light transmission portions AG is substantially the same in the four directions X, Y, θx, and θy.

[0084] The resolution of the display pixels in the second sensing area CA may be lower than that of the display area DA and may be equal to that of the first sensing area SA. For example, the resolution of the display pixels in the second sensing area CA may be 1 / 4 of that of the display area DA and may be equal to that of the first sensing area SA.

[0085] Figure 8A and Figure 8B is a view illustrating a method of registering a fingerprint image using the first sensing area SA.

[0086] The sensor pixels S in the first sensing area SA perform photoelectric conversion on the light reflected from the fingerprint on the first sensing area SA and transmit the electrical signal to the fingerprint recognition processor. The fingerprint image obtained from the fingerprint recognition processor may be generated as an incomplete image with a discontinuous fingerprint pattern at the location of the display pixel.

[0087] In order to obtain a complete fingerprint image, the host system may display a message on the screen to guide the fingerprint registration process and allow the user to bring his fingerprint into contact with the first sensing area SA while changing the fingerprint angle. Figure 8A As shown, two or more fingerprint images #1 to #n with different angles can be generated. In a state where the angles of multiple fingerprint images with different fingerprint angles are to be matched, the host system can combine the multiple fingerprint images to register the complete image as shown in FIG. Figure 8B During the fingerprint authentication process, the fingerprint image registered in the host system is compared with the fingerprint pattern data of the fingerprint image sensed in the first sensing area SA in real time, thereby performing fingerprint authentication.

[0088] Figure 9 and Figure 10 is a view showing a display device according to an embodiment of the present disclosure.

[0089] refer to Figure 9 and Figure 10 The display device includes a display panel 100 and a display panel driver. In the display panel 100, a pixel array is provided on a screen.

[0090] The pixel array of the display panel 100 includes data lines DL, gate lines GL intersecting the data lines DL, and display pixels P arranged in a matrix defined by the data lines DL and the gate lines GL. The pixel array also includes display elements such as Figure 11 and Figure 12 The power lines shown are VDD line PL1, Vini line PL2 and VSS line PL3. The pixel array includes a display area DA that displays an input image in a display mode, and a first sensing area SA and a second sensing area CA.

[0091] The first sensing area SA senses the user's fingerprint pattern in the fingerprint recognition mode using sensor pixels embedded in the pixel array. Light propagating to the optical sensor 30 disposed under the display panel 100 is emitted to the light receiving surface of the optical sensor 30 through the second sensing area CA.

[0092] like Figure 1 As shown, the pixel array can be divided into a circuit layer 12 and a light emitting element and sensor layer 14. A touch sensor array can be disposed above the light emitting element and sensor layer 14.

[0093] In the display area DA and the first and second sensing areas SA and CA, each subpixel of a display pixel includes a pixel circuit. The pixel circuit may include a driver element that supplies current to the light-emitting element OLED, multiple switching elements for sampling the driver element's threshold voltage and switching the current path of the pixel circuit, and a capacitor for maintaining the gate voltage of the driver element. Each sensor pixel S in the first sensing area SA includes an organic photodiode and a sensor pixel driver circuit for driving the organic photodiode.

[0094] In display mode, the display pixels in the first sensing area SA emit light according to the data voltage of the pixel data to display the input data. In fingerprint recognition mode, the display pixels emit light at high brightness according to the voltage of the light source drive data and are driven as a light source. In fingerprint recognition mode, the light source drive data is set to data unrelated to the pixel data of the input image and is written to the display pixels in the first sensing area SA. Therefore, in fingerprint recognition mode, the display pixels in the first sensing area SA can emit light at the brightness indicated by the grayscale level of the light source drive data.

[0095] like Figure 9 and Figure 10As shown, the pixel circuit CPIX can be arranged below the light emitting element OLED. Similarly, the sensor pixel driving circuit COPD can be arranged below the light emitting element OLED.

[0096] The display panel driver writes pixel data of an input image into display pixels P. The display panel driver includes a data driver 306 that supplies data voltages for pixel data to data lines DL, and a gate driver 120 that sequentially supplies gate pulses to gate lines GL. The data driver 306 may be integrated into the driver IC 300. The display panel driver may also include a touch sensor driver (not shown). The data driver 306 may be integrated into the driver IC 300 along with the timing controller 303.

[0097] The driving IC 300 may include a data receiving and calculating section 308, a timing controller 303, a data driver 306, a gamma compensation voltage generator 305, a power supply 304, and a second memory 302. The driving IC 300 may be connected to the host system 200, the first memory 301, and the display panel 100.

[0098] The driver IC 300 may be bonded to the display panel 100 . The driver IC 300 receives pixel data of an input image and timing signals from the host system 200 , supplies data voltages of the pixel data to display pixels through the data lines DL, and synchronizes the data driver 306 with the gate driver 120 .

[0099] The driver IC 300 is connected to the data lines DL via a data output channel to supply data voltages Vdata1 to Vdata6 representing pixel data DATA to the data lines DL. The driver IC 300 can output gate timing signals for controlling the gate driver 120 via a gate timing signal output channel. The gate timing signals generated by the timing controller 303 may include a gate start pulse VST and a gate shift clock CLK. The gate start pulse VST and the gate shift clock CLK swing between a gate-on voltage VGL and a gate-off voltage VGH. The gate timing signals VST and CLK output from the level shifter 307 are applied to the gate driver 120 to control the shifting operation of the gate driver 120.

[0100] The gate driver 120 may include a shift register formed in the circuit layer 12 of the display panel 100 together with the pixel array. The shift register of the gate driver 120 sequentially supplies gate signals to the gate lines GL under the control of the timing controller 303. The gate signals include scan pulses and EM pulses applied to the pixel circuits, and exposure signals TG applied to the sensor pixel driving circuit. The shift register may include a scan driver that outputs scan pulses and an EM driver that outputs EM pulses. Figure 10In the FPGA, GVST and GCLK are gate timing signals input to the scan driver, and EVST and ECLK are gate timing signals input to the EM driver.

[0101] The data receiving and calculating section 308 includes a receiver for receiving pixel data DATA (which is input in the form of a digital signal) from the host system 200, and a data calculator for processing the pixel data input via the receiver to improve image quality. The data calculator may include a data recovery section for decoding and restoring compressed pixel data, and an optical compensator for adding a predetermined optical compensation value to the pixel data. To compensate for pixel brightness deviations measured based on images captured by a camera during the manufacturing process, an optical compensation value may be derived for each pixel and stored in the form of a lookup table in memories 301 and 302.

[0102] The timing controller 303 provides pixel data of an input image received from the host system 200 to the data driver 306. The timing controller 303 generates gate timing signals for controlling the gate driver 120 and source timing signals for controlling the data driver 306 to control the operation timings of the gate driver 120 and the data driver 306.

[0103] The data driver 306 converts the pixel data DATA (digital data) received from the timing controller 303 into a gamma compensation voltage through a digital-to-analog converter (DAC) and outputs data voltages Vdata1 to Vdata6. The data voltages Vdata1 to Vdata6 output from the data driver 306 are supplied to the data lines DL of the pixel array through output buffers connected to the data channels of the driver IC 300.

[0104] The gamma compensation voltage generator 305 divides the gamma reference voltage from the power supply 304 through a voltage divider circuit to generate gamma compensation voltages for each grayscale level. The gamma compensation voltage is an analog voltage, wherein the voltage is set for each grayscale level of the pixel data. The gamma compensation voltage output from the gamma compensation voltage generator 305 is provided to the data driver 306.

[0105] The power supply 304 uses a direct current (DC)-DC converter to generate the power required to drive the pixel array, gate driver 120, and driver IC 300 of the display panel 100. The DC-DC converter may include a charge pump, a voltage regulator, a buck converter, and a boost converter. The power supply 304 can regulate the DC input voltage from the host system 200 to generate DC power such as a gamma reference voltage, a gate-on voltage VGL, a gate-off voltage VGH, a pixel drive voltage VDD, a low potential voltage VSS, and an initialization voltage Vini. The gamma reference voltage is supplied to the gamma compensation voltage generator 305. The gate-on voltage VGL and the gate-off voltage VGH are supplied to the level shifter 307 and the gate driver 120. Pixel power such as the pixel drive voltage VDD, the low potential voltage VSS, and the initialization voltage Vini is supplied to the pixel P. The pixel drive voltage VDD is set to a voltage higher than the low potential voltage VSS. The initialization voltage Vini is set to a DC voltage lower than the threshold voltage of the light-emitting element OLED to initialize the main node of the pixel circuit and suppress the light-emitting element OLED from emitting light. The initialization voltage Vini may be set to a voltage lower than the pixel driving voltage VDD and less than or equal to the low potential voltage VSS.

[0106] When power is supplied to the driver IC 300, the second memory 302 stores compensation values, resistor setting data, and the like received from the first memory 301. The compensation values can be applied to various algorithms for improving image quality. The compensation values may include optical compensation values. The resistor setting data is pre-set to control the operation of the data driver 306, the timing controller 303, and the gamma compensation voltage generator 305. The first memory 301 may include a flash memory. The second memory 302 may include a static random access memory (SRAM).

[0107] The host system 200 may be implemented as an application processor (AP). The host system 200 may transmit pixel data of an input image to the driver IC 300 via a mobile industry processor interface (MIPI). For example, the host system 200 may be connected to the driver IC 300 via a flexible printed circuit (FPC).

[0108] The present disclosure also includes a fingerprint recognition processor 500. The fingerprint recognition processor 500 is connected to the sensor pixels S in the first sensing area SA. The fingerprint recognition processor 500 amplifies the output voltage of the sensor pixels S and converts the output voltage into digital data using an analog-to-digital converter (ADC) to generate fingerprint pattern image data. The host system 200 receives the fingerprint pattern data from the fingerprint recognition processor 500 in the fingerprint recognition mode and processes the fingerprint authentication based on the result of comparing the fingerprint pattern data with the registered fingerprint image.

[0109] The display panel 100 can be implemented as a flexible panel suitable for a flexible display. The screen size of the flexible display can be changed by winding, folding, and bending the flexible display panel, and the flexible display can be easily manufactured in various designs. The flexible display can be implemented as a roll-up display, a foldable display, a bendable display, a slidable display, etc. The flexible panel can be made of a "plastic OLED panel". The plastic OLED panel may include a backplane and a pixel array on an organic film bonded to the backplane. The touch sensor array can be formed on the pixel array.

[0110] The backplane may be a polyethylene terephthalate (PET) substrate. The pixel array and the touch sensor array may be formed on an organic film substrate. To prevent the pixel array from being exposed to moisture, the backplane may prevent moisture from penetrating into the organic film. The organic film substrate may be a polyimide (PI) film substrate. A multilayer buffer film may be formed on the organic film substrate from an insulating material (not shown). The circuit layer 12, the light-emitting element, and the sensor layer 14 may be stacked on the organic film substrate.

[0111] In the display device of the present disclosure, the pixel circuit CPIX, the sensor pixel driving circuit COPD, and the gate driver 120 provided in the circuit layer 12 may include a plurality of transistors. The transistors may be implemented as oxide TFTs including oxide semiconductors, low-temperature polysilicon TFTs including low-temperature polysilicon (LTPS), or the like. Each transistor may be implemented as a p-channel TFT or an n-channel TFT. In this embodiment, the transistors of the pixel circuit are mainly described as examples implemented as p-channel TFTs, but the present disclosure is not limited thereto.

[0112] A transistor is a three-electrode device consisting of a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In a transistor, carriers begin to flow from the source. The drain is the electrode through which carriers are discharged from the transistor. In a transistor, carriers flow from the source to the drain. In an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage to allow electrons to flow from the source to the drain. In an n-channel transistor, current flows from the drain to the source. In a p-channel transistor (p-type metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage to allow holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, the present disclosure is not limited to the source and drain of a transistor. In the following description, the source and the drain of the transistor will be referred to as a first electrode and a second electrode, respectively.

[0113] The gate pulse swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor turns on in response to the gate-on voltage, and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage can be a gate high voltage VGH, and the gate-off voltage can be a gate low voltage VGL. In the case of a p-channel transistor, the gate-on voltage can be a gate low voltage VGL, and the gate-off voltage can be a gate high voltage VGH.

[0114] The driver elements of the pixel circuit can be implemented as transistors. The driver elements should have uniform electrical characteristics across all pixels. However, due to processing variations and component characteristic variations, there may be differences between pixels, and the electrical characteristics may change over time as the display is driven. To compensate for variations in the driver element's electrical characteristics, the display device may include internal and external compensation circuits. The internal compensation circuit is added to the pixel circuit of each subpixel to sample the driver element's threshold voltage Vth and / or mobility μ, which vary depending on the driver element's electrical characteristics, and compensate for these variations in real time. The external compensation circuit transmits the driver element's threshold voltage Vth and / or mobility μ, sensed via a sensing line connected to the subpixel, to an external compensator. The compensator in the external compensation circuit compensates for variations in the driver element's electrical characteristics by reflecting the sensing results and modulating the pixel data of the input image. The external compensation circuit senses the pixel voltage that varies depending on the driver element's electrical characteristics and, based on the sensed voltage, modulates the input image data in the external circuit, thereby compensating for variations in the driver element's electrical characteristics between pixels.

[0115] Figure 11 and Figure 12 is a circuit diagram illustrating an example of a pixel circuit to which an internal compensation circuit is applied. Figure 13 It shows Figure 11 and Figure 12 2 is a waveform diagram of the driving method of the pixel circuit shown. Figure 11 and Figure 12 The pixel circuit shown can be similarly applied to display pixels in the display area DA and the first sensing area SA. Figure 11 and Figure 12 The illustrated pixel circuit is an example of a pixel circuit applicable to the present disclosure, and the present disclosure is not limited thereto.

[0116] refer to Figures 11 to 13 The pixel circuit includes a light emitting element OLED, a driving element DT for supplying current to the light emitting element OLED, and a switching circuit for switching voltages applied to the light emitting element OLED and the driving element DT.

[0117] The switching circuit is connected to the power lines PL1, PL2 and PL3 (the pixel driving voltage VDD, the low potential voltage VSS and the initialization voltage Vini are applied to the power lines PL1, PL2 and PL3), the data line DL and the gate lines GL1, GL2 and GL3, and switches the voltage applied to the light emitting element OLED and the driving element DT in response to the scan pulses SCAN(N-1) and SCAN(N) and the EM pulse EM(N).

[0118] In addition, the switching circuit samples the threshold voltage Vth of the driving element DT using a plurality of switching elements M1 to M6, stores the sampled threshold voltage Vth in a capacitor Cst1, and includes an internal compensation circuit to compensate the gate voltage of the driving element DT using the voltage of the threshold voltage Vth of the driving element DT. Each of the driving element DT and the switching elements M1 to M6 can be implemented as a p-channel TFT.

[0119] like Figure 13 As shown, the driving period of the pixel circuit can be divided into an initialization period Tini, a sampling period Tsam, a data writing period Twr and a light emitting period Tem.

[0120] During the sampling period Tsam, the Nth scan pulse SCAN(N) is generated as the gate-on voltage VGL and then applied to the first gate line GL1. During the initialization period Tini before the sampling period Tsam, the (N-1)th scan pulse SCAN(N-1) is generated as the gate-on voltage VGL and then applied to the second gate line GL2. During the initialization period Tini and the sampling period Tsam, the EM pulse EM(N) is generated as the gate-off voltage VGH and then applied to the third gate line GL3. During the data write period Twr, the EM pulse EM(N) may be generated as the gate-off voltage VGH.

[0121] During the initialization period Tini, the (N-1)th scan pulse SCAN(N-1) is generated as the gate-on voltage VGL, and the voltage of each of the Nth scan pulse SCAN(N) and the EM pulse EM(N) is the gate-off voltage VGH. During the sampling period Tsam, the Nth scan pulse SCAN(N) is generated as a pulse of the gate-on voltage VGL, and the voltage of each of the (N-1)th scan pulse SCAN(N-1) and the EM pulse EM(N) is the gate-off voltage VGH. During the data write period Twr, the voltage of each of the (N-1)th scan pulse SCAN(N-1), the Nth scan pulse SCAN(N), and the EM pulse EM(N) is the gate-off voltage VGH. During at least a portion of the light emission period Tem, the EM pulse EM(N) is generated as the gate-on voltage VGL, and the voltage of each of the (N-1)th scan pulse SCAN(N-1) and the Nth scan pulse SCAN(N) is the gate-off voltage VGH.

[0122] During the initialization period Tini, the gate-on voltage VGL of the (N-1)th scan pulse SCAN(N-1) turns on the fifth switching element M5, thereby initializing the pixel circuit. During the sampling period Tsam, the gate-on voltage VGL of the Nth scan pulse SCAN(N) turns on the first switching element M1 and the second switching element M2, so that the data voltage Vdata compensated by the threshold voltage Vth of the driving element DT is stored in the capacitor Cst1. Simultaneously, during the sampling period Tsam, the sixth switching element M6 is turned on to reduce the voltage of the fourth node n4 to the reference voltage Vref, thereby suppressing the light emitting element OLED from emitting light. During the data write period Twr, the first to sixth switching elements M1 to M6 remain in the off state.

[0123] During the light-emission period Tem, the third switching element M3 and the fourth switching element M4 are turned on, causing the light-emitting element OLED to emit light. During the light-emission period Tem, to accurately present low grayscale brightness, the voltage level of the EM pulse EM(N) can be inverted between the gate-on voltage VGL and the gate-off voltage VGH at a predetermined duty cycle. In this case, during the light-emission period Tem, the third switching element M3 and the fourth switching element M4 can be repeatedly turned on and off according to the duty cycle of the EM pulse EM(N).

[0124] The light emitting element OLED may be implemented as an organic light emitting diode or an inorganic light emitting diode. Hereinafter, an example in which the light emitting element OLED is implemented as an organic light emitting diode will be described.

[0125] The anode of the light-emitting element OLED is connected to a fourth node n4 between the fourth switching element M4 and the sixth switching element M6. The fourth node n4 is connected to the anode of the light-emitting element OLED, the second electrode of the fourth switching element M4, and the second electrode of the sixth switching element M6. The cathode of the light-emitting element OLED is connected to the VSS line PL3 (the low potential voltage VSS is applied to the VSS line PL3). The light-emitting element OLED emits light by a current Ids that flows in accordance with the gate-source voltage Vgs of the driving element DT. The current path of the light-emitting element OLED is switched by the third switching element M3 and the fourth switching element M4.

[0126] Capacitor Cst1 is connected between VDD line PL1 and first node n1. Capacitor Cst is charged by a data voltage Vdata compensated by a threshold voltage Vth of a driving element DT. Since the data voltage Vdata in each subpixel is compensated by the threshold voltage Vth of the driving element DT, characteristic variations of the driving element DT in each subpixel are compensated.

[0127] The first switching element M1 is turned on in response to the gate-on voltage VGL of the Nth scan pulse SCAN(N) to connect the second node n2 to the third node n3. The second node n2 is connected to the gate of the driving element DT, the first electrode of the capacitor Cst, and the first electrode of the first switching element M1. The third node n3 is connected to the second electrode of the driving element DT, the second electrode of the first switching element M1, and the first electrode of the fourth switching element M4. The gate of the first switching element M1 is connected to the first gate line GL1 to receive the Nth scan pulse SCAN(N). The first electrode of the first switching element M1 is connected to the second node n2, and the second electrode of the first switching element M1 is connected to the third node n3.

[0128] Since the first switching element M1 is only Figure 11 Since the first switching element M1 is turned on during a very short horizontal period 1H (wherein the Nth scan pulse SCAN(N) is generated as the gate-on voltage VGL within one frame period), and thus remains in an off state during approximately one frame period, an off current may exist in the off state of the first switching element M1. In order to suppress the off current of the first switching element M1, as shown in FIG. Figure 12 As shown, the first switching element M1 may be implemented as a transistor having a double-gate structure, in which two transistors M1a and M1b are connected in series.

[0129] The second switching element M2 is turned on in response to the gate-on voltage VGL of the Nth scan pulse SCAN(N) to supply the data voltage Vdata to the first node n1. The gate of the second switching element M2 is connected to the first gate line GL1 to receive the Nth scan pulse SCAN(N). A first electrode of the second switching element M2 is connected to the first node n1. A second electrode of the second switching element M2 is connected to the data line DL (to which the data voltage Vdata is applied). The first node n1 is connected to the first electrode of the second switching element M2, the second electrode of the third switching element M3, and the first electrode of the driving element DT.

[0130] The third switching element M3 is turned on in response to the gate-on voltage VGL of the EM pulse EM(N) to connect the VDD line PL1 to the first node n1. The gate of the third switching element M3 is connected to the third gate line GL3 to receive the EM pulse EM(N). A first electrode of the third switching element M3 is connected to the VDD line PL1. A second electrode of the third switching element M3 is connected to the first node n1.

[0131] The fourth switching element M4 is turned on in response to the gate-on voltage VGL of the EM pulse EM(N) to connect the third node n3 to the anode of the light-emitting element OLED. The gate of the fourth switching element M4 is connected to the third gate line GL3 to receive the EM pulse EM(N). A first electrode of the fourth switching element M4 is connected to the third node n3, and a second electrode of the fourth switching element M4 is connected to a fourth node n4.

[0132] The fifth switching element M5 is turned on in response to the gate-on voltage VGL of the (N-1)th scan pulse SCAN(N-1) to connect the second node n2 to the Vini line PL2. The gate of the fifth switching element M5 is connected to the second gate line GL2 to receive the (N-1)th scan pulse SCAN(N-1). The first electrode of the fifth switching element M5 is connected to the second node n2, and the second electrode of the fifth switching element M5 is connected to the Vini line PL2. In order to suppress the off-current of the fifth switching element M5, as shown in FIG. Figure 12 As shown, the fifth switching element M5 may be implemented as a transistor having a dual-gate structure in which two transistors M5a and M5b are connected in series.

[0133] The sixth switching element M6 is turned on in response to the gate-on voltage VGL of the Nth scan pulse SCAN(N) to connect the Vini line PL2 to the fourth node n4. The gate of the sixth switching element M6 is connected to the first gate line GL1 to receive the Nth scan pulse SCAN(N). A first electrode of the sixth switching element M6 is connected to the Vini line PL2, and a second electrode of the sixth switching element M6 is connected to the fourth node n4.

[0134] At the same time, the gates of the fifth switching element M5 and the sixth switching element M6 may be commonly connected to the second gate line GL2 (the (N-1)th scan pulse SCAN(N-1) is applied to the second gate line GL2). In this case, the fifth switching element M5 and the sixth switching element M6 may be simultaneously turned on in response to the (N-1)th scan pulse SCAN(N-1).

[0135] The driving element DT controls the current flowing in the light emitting element OLED according to the gate-source voltage Vgs, thereby driving the light emitting element OLED. The driving element DT includes a gate connected to the second node n2, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

[0136] During the initialization period Tini, the (N-1)th scan pulse SCAN(N-1) is generated at the gate-on voltage VGL. During the initialization period Tini, each of the Nth scan pulse SCAN(N) and the EM pulse EM(N) maintains the gate-off voltage VGH. Therefore, during the initialization period Tini, the fifth switching element M5 is turned on, so that the second node n2 and the fourth node n4 are initialized at the initialization voltage Vini. A holding period Th may be provided between the initialization period Tini and the sampling period Tsam. During the holding period Th, each of the scan pulses SCAN(N-1) and SCAN(N) and the EM pulse EM(N) is at the gate-off voltage VGH.

[0137] During the sampling period Tsam, the Nth scan pulse SCAN(N) is generated as the gate-on voltage VGL. The pulse of the Nth scan pulse SCAN(N) is synchronized with the data voltage Vdata of the Nth pixel row. During the sampling period Tsam, each of the (N-1)th scan pulse SCAN(N-1) and the EM pulse EM(N) maintains the gate-off voltage VGH. Therefore, during the sampling period Tsam, the first switching element M1 and the second switching element M2 are turned on.

[0138] During the sampling period Tsam, the gate voltage DTG of the driving element DT increases due to the current flowing through the first switching element M1 and the second switching element M2. When the driving element DT is turned off, the gate voltage DTG becomes Vdata - |Vth|. In this case, the voltage of the first node n1 also becomes Vdata - |Vth|. During the sampling period Tsam, the gate-source voltage Vgs of the driving element DT is |Vgs| = Vdata - (Vdata - |Vth|) = |Vth|.

[0139] During the data writing period Twr, the Nth scan pulse SCAN(N) is inverted to the gate-off voltage VGH. During the data writing period Twr, each of the (N-1)th scan pulse SCAN(N-1) and the EM pulse EM(N) maintains the gate-off voltage VGH. Therefore, during the data writing period Twr, all switching elements M1 to M6 remain in the off state.

[0140] During the light emission period Tem, the EM pulse EM(N) may be generated as the gate-off voltage VGH. During the light emission period Tem, the voltage of the EM pulse EM(N) may be inverted at a predetermined duty cycle. Therefore, the EM pulse EM(N) may be generated as the gate-on voltage VGL during at least a portion of the light emission period Tem.

[0141] When the EM pulse EM(N) is the gate-on voltage VGL, current flows between VDD and the light-emitting element OLED, allowing the light-emitting element OLED to emit light. During the light-emitting period Tem, the (N-1)th scan pulse SCAN(N-1) and the Nth scan pulse SCAN(N) maintain the gate-off voltage VGH. During the light-emitting period Tem, the third switching element M3 and the fourth switching element M4 are turned on according to the gate-on voltage VGL of the EM pulse EM(N). When the EM pulse EM(N) is the gate-on voltage VGL, the third switching element M3 and the fourth switching element M4 are turned on, allowing current to flow in the light-emitting element OLED. In this case, the gate-source voltage Vgs of the driving element DT becomes |Vgs|=VDD-(Vdata-|Vth|), and the current flowing in the light-emitting element OLED is K(VDD-Vdata). 2 K is a constant determined by the charge mobility, parasitic capacitance, and channel capacity of the driving element DT.

[0142] Figure 14 It should be noted that the cross-sectional structure of the display panel 100 is not limited to Figure 14 .

[0143] refer to Figure 14 In the pixel circuit, the circuit layer 12, the light emitting element and sensor layer 14, and the encapsulation layer can be stacked on a substrate GLS. The substrate GLS can be a glass substrate or an organic film substrate.

[0144] A first buffer layer BUF1 may be formed on the substrate GLS. A first metal layer may be formed on the first buffer layer BUF1, and a second buffer layer BUF2 may be formed on the first metal layer. The first metal layer is patterned using a photolithography process. The first metal layer may include a light shielding pattern BSM. The light shielding pattern BSM blocks external light to prevent it from irradiating the active layer of the TFT. Each of the first and second buffer layers BUF1 and BUF2 may be made of an inorganic insulating material and may be formed of one or more insulating layers. The first buffer layer BUF1 may be implemented as a multilayer buffer layer comprising a stack of oxide and nitride layers.

[0145] The active layer ACT can be formed of a semiconductor material (e.g., amorphous silicon a-Si) deposited on the second buffer layer BUF2. In order to improve electron mobility, amorphous silicon a-Si can be crystallized by an excimer laser annealing (ELA) process to be converted into polycrystalline silicon. The active layer ACT can be patterned by a photolithography process. The active layer ACT includes an active pattern for each of the transistors in the pixel circuit, the transistors in the gate driver, and the transistors in the sensor pixel driving circuit. A portion of the active layer ACT can be metallized by ion doping. The metallized portion can be used as a jumper pattern for connecting the metal layer at some nodes of the pixel circuit to connect the components of the pixel circuit.

[0146] A gate insulating layer GI may be formed on the active layer ACT. The gate insulating layer GI may be made of an inorganic insulating material. A second metal layer may be formed on the gate insulating layer GI. The second metal layer may be patterned using a photolithography process. The second metal layer may include a gate line, a gate pattern GATE of the transistor, a lower electrode of the capacitor Cst1, and a jumper pattern connecting the patterns of the first metal layer and the third metal layer.

[0147] The first interlayer insulating layer ILD1 may cover the second metal layer. A third metal layer may be formed on the first interlayer insulating layer ILD1, and the second interlayer insulating layer ILD2 may cover the third metal layer. The third metal layer may be patterned using a photolithography process. The third metal layer may include a metal pattern TM such as an upper electrode of the capacitor Cst1 and a power line. The first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may include an inorganic insulating material.

[0148] A fourth metal layer may be formed on the second interlayer insulating layer ILD2 , and the inorganic insulating layer PAS1 and the first planarization layer PLN1 may be stacked on the fourth metal layer. A fifth metal layer may be formed on the first planarization layer PLN1 .

[0149] Some metal patterns of the fourth metal layer may be connected to the third metal layer through contact holes passing through the first planarization layer PLN1 and the inorganic insulating layer PAS1. The first planarization layer PLN1 and the second planarization layer PLN2 may be made of an organic insulating material that planarizes a surface.

[0150] The fourth metal layer may include a first electrode and a second electrode of the transistor connected to the active pattern of the transistor through a contact hole passing through the second interlayer insulating layer ILD2. One or more of the data line DL and the power lines PL1, PL2, and PL3 may be implemented as a pattern SD1 of the fourth metal layer or a pattern SD2 of the fifth metal layer.

[0151] The anode AND of the light-emitting element OLED can be formed on the second planarization layer PLN2. The anode AND can be connected to the electrode of the transistor used as a switching element or a driving element through a contact hole passing through the second planarization layer PLN2. The anode AND can be made of a transparent or semi-transparent electrode material.

[0152] The pixel defining layer BNK may cover the anode AND of the light-emitting element OLED. The pixel defining layer BNK is formed into a pattern that defines a light-emitting area (or opening area) through which light passes from each pixel to the outside. A spacer SPC may be formed on the pixel defining layer BNK. The pixel defining layer BNK and the spacer SPC may be integrated using the same organic insulating material. The spacer SPC fixes the gap between the fine metal mask (FMM) and the anode AND, thereby preventing the FMM from contacting the anode AND during the deposition process of the organic compound EL.

[0153] An organic compound EL is formed in the light-emitting region of each pixel defined by the pixel defining layer BNK. A cathode CAT of the light-emitting element OLED is formed on the entire surface of the display panel 100 to cover the pixel defining layer BNK, the spacer SPC, and the organic compound EL. The cathode CAT can be connected to a VSS line PL3 formed by any one of the metal layers below the cathode CAT. A cover layer CPL can cover the cathode CAT. The cover layer CPL is formed of an inorganic insulating material, and the cover layer CPL prevents air penetration and degassing of the organic insulating material applied to the cover layer CPL, thereby protecting the cathode CAT. An inorganic insulating layer PAS2 can cover the cover layer CPL, and a planarization layer PCL can be formed on the inorganic insulating layer PAS2. The planarization layer PCL can include an organic insulating material. The inorganic insulating layer PAS3 of the encapsulation layer can be formed on the planarization layer PCL.

[0154] The photodiode of the sensor pixel S can be implemented as an organic photodiode OPD. Figure 15As shown, the anode AND of the organic photodiode OPD can be formed to be coplanar with the anode AND of the light-emitting element OLED. The anode AND of the organic photodiode OPD and the anode AND of the light-emitting element OLED can be formed by separate patterns. The organic photodiode OPD and the light-emitting element OLED can be connected to the cathode CAT, which is a common electrode. Therefore, the cathode can be shared in the organic photodiode OPD and the light-emitting element OLED.

[0155] The circuit layer of the first sensing area SA can be implemented in a structure similar to the pixel circuit, and the circuit layer of the first sensing area SA can share lines connected to the pixel circuit. Therefore, at least a portion of the sensor pixel driving circuit can be implemented in a structure that shares the pixel circuit.

[0156] Figure 15 is a view showing a cross-sectional structure of an organic photodiode OPD of a sensor pixel S and a light emitting element OLED of a display pixel according to one embodiment of the present disclosure.

[0157] refer to Figure 15 , the organic photodiode OPD can be implemented in a structure substantially the same as that of the light emitting element OLED.

[0158] The light-emitting element OLED includes an anode AND, a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, an electron injection layer EIL, and a cathode CAT stacked on the pixel circuit CPIX. The hole injection layer HIL is in contact with the anode AND of the light-emitting element OLED, and the electron injection layer EIL is in contact with the cathode CAT.

[0159] The organic photodiode OPD includes an anode AND, a hole injection layer HIL, a hole transport layer HTL, an active layer ACT-OPD, an electron transport layer ETL, an electron injection layer EIL, and a cathode CAT stacked on a sensor pixel driving circuit COPD. The active layer ACT-OPD of the organic photodiode OPD contains an organic semiconductor material.

[0160] The low potential voltage VSS and the pixel drive voltage VDD are commonly applied to the pixel circuit CPIX and the sensor pixel drive circuit COPD. The cathode CAT of the light-emitting element OLED and the cathode CAT of the organic photodiode OPD share the same metal electrode and are commonly connected to the VSS line PL3. The anode AND of the light-emitting element OLED and the anode AND of the organic photodiode OPD can be divided into metal patterns formed on the same layer. The anode AND of the light-emitting element OLED and the anode AND of the organic photodiode OPD are electrically separated.

[0161] An organic semiconductor material that can be coated by a solution process, for example, one or more of P3HT:PC61BM, squaraine:PC61BM, C60, PBDTTT-C:PC71BM, PDPP3T:PC71BM, PCDTBT:PC61BM, PVK:PC71BM, PCDTBT:PC71BM, ZnO:F8T2, PBDT-TFTTE:PC71BM, P3HT:PC61BM, TAPC:C60, P3HT:PC60BM, PFBT2OBT:PC71BM, PIDT-TPD:PC61BM, P3HT:PC71BM, PV-D4650:PC61BM, P3HT:O-IDTBR and 2,9-dimethylquinacridone (2,9-DMQA) can be used as the active layer ACT-OPD of the organic photodiode OPD, but the present disclosure is not limited thereto. Since organic semiconductor materials can be processed in a solution process at a relatively low temperature compared to inorganic semiconductor materials formed in a high-temperature deposition process, manufacturing costs can be reduced, and organic semiconductor materials can be applied to flexible displays.

[0162] from Figure 15 It can be seen that the organic photodiode OPD has a cross-sectional structure that is substantially the same as that of the light-emitting element OLED, and most layers can be formed from the same materials as the light-emitting element OLED. The organic photodiode OPD and the light-emitting element OLED can be shared and can share power lines and gate lines. Therefore, since the light-emitting element OLED and the organic photodiode OPD can be formed using the same manufacturing process and have the same cross-sectional structure, most circuit components are shared, thereby simplifying the structure of the display panel 100.

[0163] Figure 16 is a detailed view showing the display period and vertical blank period of one frame period. Figure 16 In the display, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE are timing signals synchronized with the input image signal. The timing signals synchronized with the input image signal can be generated by the host system and input to the timing controller of the display device. In mobile devices, the above timing signals can be generated in a further simplified format.

[0164] refer to Figure 16One frame is divided into a display period AT during which pixel data of an input image is input from the host system 200, and a vertical blank period VB during which no pixel data exists. During the display period AT, one frame of pixel data to be written into all pixels P on the screen AA of the display panel 100 is received by the driver IC 300 and written into the pixels P.

[0165] The vertical blank period VB is a blank period during which the driver IC 300 does not receive pixel data between the display period AT of the (N-1)th frame (N is a natural number) and the display period AT of the Nth frame. The vertical blank period VB includes a vertical synchronization time VS, a vertical front porch FP, and a vertical back porch BP.

[0166] The vertical synchronization signal Vsync defines one frame period. The horizontal synchronization signal Hsync defines one horizontal period (1H). The data enable signal DE defines a valid data period containing pixel data to be displayed on screen AA. The pulses of the data enable signal DE are synchronized with the pixel data to be written to the pixels P of the display panel 100. One pulse cycle of the data enable signal DE corresponds to one horizontal period (1H).

[0167] Figure 17 and Figure 18 is a view illustrating a driving method of a display device according to an embodiment of the present disclosure.

[0168] refer to Figure 17 and Figure 18 , the display device of the present disclosure can count the timing signal synchronized with the input image to determine the pixel position to be written into the current input pixel data.

[0169] The display device sequentially scans display pixels in units of pixel rows of the display panel 100 and writes pixel data into the display pixels.

[0170] The first sensing area SA may be provided in a portion of the display area DA. When viewed from a scanning shift direction of the display pixels, the display pixels and the sensor pixels may be simultaneously driven in the display area DA overlapping the first sensing area SA.

[0171] The display pixels of the display area DA are scanned before reaching the first sensing area SA. After exposing the sensor pixels for a predetermined time, the sensor pixels may output photoelectric conversion signals (sensor data) and then may be initialized.

[0172] Before reaching the first sensing area SA, only the display pixels are scanned. This period includes an exposure time te for exposing the sensor pixels. Therefore, during the exposure time te, the display pixels can be scanned and, at the same time, the sensor pixels can be exposed (S1).

[0173] During the scanning process of sequentially shifting the display pixels for each row (the pixel row containing the sensor pixels of the first sensing area SA), for example, when scanning the pixel row to which the i-th scan pulse SCAN(i) (i is a positive integer greater than 2) is applied, the display pixels are scanned, and simultaneously, the output signals of the sensor pixels S, i.e., sensor data, are read through the RX line RXL. The sensor pixel driving circuit COPD drives the sensor pixels S in a source-follower manner and outputs the sensor data to the RX line RXL. Therefore, after the exposure time te, during the sensor pixel output and initialization time Tro, the display pixels R, G, and B are scanned in the pixel row contained in the first sensing area SA, and simultaneously, the sensor data is output from the sensor pixels S (S2 and S3).

[0174] In the pixel row included in the first sensing area SA, the sensor pixels S may be initialized with the initialization voltage Vini. When the sensor pixels S are initialized, pixel data is written into display pixels sharing a gate line with the sensor pixels S. After the sensor data of one pixel row is sequentially output at a time according to sequentially shifted scan pulses, the sensor pixels S of the pixel row including the sensor pixels S of the first sensing area SA are initialized, and the display pixels of one pixel row are sequentially scanned at a time (S4).

[0175] Figure 19 is a circuit diagram showing a pixel circuit and a sensor pixel driving circuit according to a first embodiment of the present disclosure. Figure 20 It shows Figure 19 The waveform diagram of the driving method of the pixel circuit CPIX and the sensor pixel driving circuit COPD shown in FIG. Figures 11 to 13 The pixel circuit CPIX has been described, so its detailed description will be omitted here. Figure 20 , “DATA” is the pixel data to be written to the display pixels R, G and B in synchronization with the scan pulses SCAN1 to SCAN(i+2), “RX” is the sensor data to be output from the sensor pixel S in synchronization with the scan pulses SCANi to SCAN(i+2), “Fn” is the n-th frame period (n is a positive integer), and “F(n+1)” is the (n+1)-th frame period.

[0176] In the pixel rows including the sensor pixels S, the sensor data RX is outputted starting from the pixel row to which the pixel data is written in response to the i-th scan pulse SCANi. Therefore, the output and initialization time Tro of the sensor pixels S can be set to the time from the i-th scan pulse SCANi to the scan pulse applied to the last pixel row of the first sensing area SA. Figure 19 In the example, the (N-1)th scanning pulse SCAN(N-1) can be Figure 20Any one of the i-th scan pulse SCANi to the (i+2)-th scan pulse SCAN(i+2) shown.

[0177] refer to Figure 19 The pixel circuit CPIX and the sensor pixel driving circuit COPD share the power lines PL1, PL2, and PL3. Therefore, power such as VDD, Vini, and VSS is commonly applied to the pixel circuit CPIX and the sensor pixel driving circuit COPD.

[0178] The sensor pixel driving circuit COPD drives the organic photodiode OPD and outputs sensor data RX (which is a photoelectric conversion signal generated by the organic photodiode OPD). The sensor data RX can be transmitted from the organic photodiode OPD to the fingerprint recognition processor 500 through the RX line RXL.

[0179] The sensor pixel drive circuit COPD is connected to the VDD line PL1, the Vini line PL2, the VSS line PL3, the gate lines GL1, GL2, GL3, and GL4, and the RX line RXL. The gate lines GL1 to GL4 may be formed as parallel lines intersecting the RX line RXL and the data line DL. The RX line RXL may be formed as a line parallel to the data line DL and the VDD line PL1.

[0180] In response to the (N-1)th scan pulse SCAN(N-1), the sensor pixel driving circuit COPD outputs sensor data RX and is then initialized according to the N-th scan pulse SCAN(N). The (N-1)th scan pulse SCAN(N-1) is an example of a scan pulse generated before the N-th scan pulse SCAN(N). Since the (N-1)th scan pulse SCAN(N-1) can be replaced by another scan pulse (for example, the (N-2)th scan pulse SCAN(N-2)), it should be noted that the scan pulse is not limited to the (N-1)th scan pulse SCAN(N-1).

[0181] The sensor pixel driving circuit COPD includes an organic photodiode OPD, a capacitor Cst2 and a switching circuit. In response to scan pulses SCAN(N-1) and SCAN(N) and an exposure signal TG, the switching circuit switches a current path between the organic photodiode OPD and the RX line RXL.

[0182] The switching circuit is connected to the organic photodiode OPD, the capacitor Cst2, the first power line PL1, the second power line PL2, the third power line PL3, the RX line RXL, and the gate lines GL1, GL2, GL3, and GL4. The switching circuit includes first to fourth S-switching elements M1S to M4S. Each of the first to fourth S-switching elements M1S to M4S can be implemented as a p-channel TFT.

[0183] The organic photodiode OPD includes an anode connected to the third S-switch element M3SP, a cathode (a low potential voltage VSS is applied to the cathode), and an active layer formed between the anode and the cathode. The cathode is connected to the third power line PL3. The active layer ACT-OPD of the organic photodiode OPD comprises an organic semiconductor material. When a reverse bias voltage is applied, the organic photodiode OPD generates a current based on the received light. The charge generated by the current changes the voltage of the fifth node n5 connected to the gate of the second S-switch element M2S. The capacitor Cst2 is charged by the voltage difference between the voltage of the fifth node n5 and the pixel drive voltage VDD.

[0184] It should be noted that the anode of the organic photodiode OPD and the anode of the light emitting element OLED are provided on the same layer in the cross-sectional structure of the display panel 100 and share a common cathode. Due to the above structure, the anode of the photodiode OPD is connected to the first electrode of the third S switch element M3SP.

[0185] Capacitor Cst2 is connected between the fifth node n5 and the VDD line PL1. When the third S-switching element M3SP is turned on, capacitor Cst2 maintains the voltage of the fifth node n5, which is charged with charge from the organic photodiode OPD. The exposure time te of the sensor pixel S is determined by the pulse width of the exposure signal TG applied to the gate of the third S-switching element M3SP. As the pulse width of the exposure signal TG, which is generated as the gate-on voltage VGL, increases, the exposure time te becomes longer, thereby increasing the amount of charge flowing to the fifth node n5.

[0186] The first S-switching element M1S is turned on in response to the gate-on voltage VGL of the (N-1)th scan pulse SCAN(N-1) to connect the sixth node n6 to the RX line RXL. The sixth node n6 is connected to the second electrode of the first S-switching element M1S and the first electrode of the second S-switching element M2S. The gate of the first S-switching element M1S is connected to the second gate line GL2 (the (N-1)th scan pulse SCAN(N-1) is applied to the second gate line GL2). The first electrode of the first S-switching element M1S is connected to the second node n2, and the second electrode of the first S-switching element M1S is connected to the RX line RXL. When the first S-switching element M1S is turned on, sensor data RX is output through the RX line RXL.

[0187] The second S-switch element M2S regulates the amount of current flowing between the VDD line PL1 and the sixth node n6 through the RX line RXL according to a gate voltage (i.e., the voltage of the fifth node n5). The second S-switch element M2S includes a gate connected to the fifth node n5, a first electrode connected to the sixth node n6, and a second electrode connected to the VDD line PL1. The fifth node n5 is connected to the second electrode of the third S-switch element M3SP, the capacitor Cst2, and the gate of the second S-switch element M2S.

[0188] The third S-switch element M3SP is turned on in response to the gate-on voltage VGL of the exposure signal TG, connecting the anode of the organic photodiode OPD to the fifth node n5. When the third S-switch element M3SP is in the on state, charge flows from the organic photodiode OPD to the fifth node n5. The third S-switch element M3SP includes a gate connected to the fourth gate line GL4 (to which the exposure signal TG is applied), a first electrode connected to the anode of the organic photodiode OPD, and a second electrode connected to the fifth node n5. During the exposure time te, the exposure signal TG is generated as the gate-on voltage VGL. During the output and initialization time Tro of the sensor pixel S, the exposure signal TG is generated as the gate-off voltage VGH. Therefore, during the exposure time te, the third S-switch element M3SP is in the on state, and during the output and initialization time Tro of the sensor pixel S, the third S-switch element M3SP is in the off state.

[0189] The fourth S switching element M4S is turned on in response to the gate-on voltage VGL of the Nth scan pulse SCAN(N) to initialize the fifth node n5 with the initialization voltage Vini. The fourth S switching element M4S includes a gate connected to the first gate line GL1 (to which the Nth scan pulse SCAN(N) is applied), a first electrode connected to the Vini line PL2 (to which the initialization voltage Vini is applied), and a second electrode connected to the fifth node n5.

[0190] The initialization voltage Vini charges the main node of the pixel circuit CPIX and also initializes the main node of the sensor pixel driving circuit COPD. The initialization voltage Vini may be set to a voltage lower than or equal to the low potential voltage VSS.

[0191] refer to Figure 20During the display period AT, the display pixels R, G, and B are sequentially scanned row by row. From the perspective of driving the sensor pixels, one frame of the display device can be divided into an exposure time te, the output of the sensor pixels S, and an initialization time Tro. The exposure time te can be set within the display period AT, or can be further set to a time that includes at least a portion of the display period AT and a vertical blanking period VB. The sensor data output time Tro can be set to a time within the display period AT (during the display period AT, the scan signal can be applied to the sensor pixels S in the first sensing area SA).

[0192] During the display period AT in which the timing controller 303 receives pixel data, scan pulses SCAN1 to SCAN(i+2) and an EM pulse, which are omitted in the drawing, are generated and sequentially shifted.

[0193] During the exposure time te, the first to third scan pulses SCAN1 to SCAN3 may be applied to the display pixels R, G, and B of the pixel row where the sensor pixel S does not exist. During the exposure time te, in the pixel row where the sensor pixel S does not exist, pixel data may be written into the display pixels R, G, and B, and the organic photodiodes OPDs of the sensor pixels S may be exposed to light to generate current.

[0194] During the output and initialization time Tro of the sensor pixels S, the i-th to (i+2)-th scan pulses SCANi to SCAN(i+2) may be applied to the display pixels R, G, and B in the first sensing area SA and the sensor pixels S. During the output and initialization time Tro of the sensor pixels S, pixel data is written to the display pixels R, G, and B, sensor data RX is output from the sensor pixels S, and then the sensor pixels S are initialized.

[0195] Figure 21 is a circuit diagram showing a pixel circuit and a sensor pixel driving circuit according to a second embodiment of the present disclosure. Figure 22 It shows Figure 21 The waveform diagram of the pixel circuit and the driving method of the sensor pixel driving circuit shown in FIG. Figure 21 and Figure 22 Components that are substantially the same as those of the above-described embodiment are given the same reference numerals, and detailed descriptions thereof will be omitted here.

[0196] refer to Figure 21 and Figure 22To reduce the off-state current, the third S-switch element M3SN of the sensor pixel driver circuit COPD can be implemented as an n-channel oxide TFT. In an n-channel oxide TFT, the gate-on voltage is VGH. During the exposure time te, the pulse of the exposure signal TG is generated as a pulse of the gate-on voltage VGH. During the output of the sensor pixel S and the initialization time Tro, the exposure signal TG is generated as a gate-off voltage VGL. Therefore, during the exposure time te, the third S-switch element M3SN is in the on state, and during the output of the sensor pixel S and the initialization time Tro, the third S-switch element M3SN is in the off state.

[0197] Figure 23 is a circuit diagram showing a pixel circuit and a sensor pixel driving circuit according to a third embodiment of the present disclosure. Figure 24 It shows Figure 23 The pixel circuit and the sensor pixel driving circuit shown in the waveform diagram of the driving method. Figures 11 to 13 The pixel circuit has been described, and therefore, a detailed description thereof will be omitted here.

[0198] refer to Figure 23 , power such as VDD and VSS is applied to the pixel circuit CPIX and the sensor pixel driving circuit COPD.

[0199] The sensor pixel driving circuit COPD drives the organic photodiode OPD and outputs sensor data RX obtained from the photoelectric conversion signal through the organic photodiode OPD. The sensor data RX can be transmitted to the fingerprint recognition processor 500 through the RX line RXL.

[0200] The sensor pixel drive circuit COPD is connected to the VDD line PL1, the VSS line PL3, the second and fourth gate lines GL2 and GL4, and the RX line RXL. The second and fourth gate lines GL2 and GL4 can be formed as parallel lines that intersect the RX line RXL and the data line DL on the pixel array. The RX line RXL can be formed as a line parallel to the data line DL and the VDD line PL1.

[0201] The sensor pixel driving circuit COPD includes an organic photodiode OPD, a capacitor Cst2, and a switching circuit connected to the second gate line GL2 and the fourth gate line GL4, and is configured to switch a current path between the organic photodiode OPD and the RX line RXL in response to a scan pulse SCAN(N-1) and an exposure signal TG.

[0202] The switching circuit is connected to the organic photodiode OPD, the capacitor Cst2, the VDD line PL1, the VSS line PL3, the RX line RXL, the second gate line GL2, and the fourth gate line GL4. The switching circuit includes first to third S-switching elements M1S to M3SP. Each of the first to third S-switching elements M1S to M3SP can be implemented as a p-channel TFT.

[0203] The organic photodiode OPD includes an anode connected to the third S-switch element M3SP, a cathode (a low potential voltage VSS is applied to the cathode), and an active layer formed between the anode and the cathode. The active layer ACT-OPD of the organic photodiode OPD includes an organic semiconductor material. When a reverse bias voltage is applied, the organic photodiode OPD generates a current based on the light it receives.

[0204] It should be noted that the anode of the organic photodiode OPD and the anode of the light emitting element OLED are provided on the same layer in the cross-sectional structure of the display panel 100 and share a common cathode. Due to the above structure, the anode of the organic photodiode OPD is connected to the first electrode of the third S-switch element M3SP.

[0205] Capacitor Cst2 is connected between VDD line PL1 and the gate of second S-switching element M2S, which is connected to fifth node n5. When third S-switching element M3SP is turned on, capacitor Cst2 is charged with charge from organic photodiode OPD to store the voltage of photoelectric conversion signal RX. The exposure time of photosensor S is determined by the pulse width of exposure signal TG applied to the gate of third S-switching element M3SP. As the pulse width of exposure signal TG increases, the amount of charge charged to capacitor Cst2 by photosensor S may increase.

[0206] The first S-switching element M1S is turned on in response to the gate-on voltage VGL of the (N-1)th scan pulse SCAN(N-1) to connect the fourth node n4 to the Vini line PL2. The sixth node n6 is connected to the second electrode of the first S-switching element M1S and the first electrode of the second S-switching element M2S. The gate of the first S-switching element M1S is connected to the second gate line GL2 to receive the (N-1)th scan pulse SCAN(N-1). The first electrode of the first S-switching element M1S is connected to the second node n2, and the second electrode of the first S-switching element M1S is connected to the sixth node n6.

[0207] The second S-switch element M2S regulates the amount of current flowing between the VDD line PL1 and the sixth node n6 through the RX line RXL according to a gate voltage (i.e., the voltage of the fifth node n5). The second S-switch element M2S includes a gate connected to the fifth node n5, a first electrode connected to the sixth node n6, and a second electrode connected to the VDD line PL1. The fifth node n5 is connected to the second electrode of the third S-switch element M3SP, the capacitor Cst2, and the gate of the second S-switch element M2S.

[0208] The third S-switching element M3SP is turned on in response to the gate-on voltage VGL of the exposure signal TG to connect the anode of the organic photodiode OPD to the fifth node n5. When the third S-switching element M3SP is in the on state, the capacitor Cst2 is charged with the charge from the organic photodiode OPD. The third S-switching element M3SP includes a gate connected to the fourth gate line GL4 (to which the exposure signal TG is applied), a first electrode connected to the anode of the organic photodiode OPD, and a second electrode connected to the fifth node n5.

[0209] like Figure 24 As shown, the sensor pixel driving circuit COPD is initialized during the vertical blank period VB.

[0210] refer to Figure 24 The vertical blank period VB includes the reset time to and the exposure time te of the sensor pixel driving circuit COPD. During the display period AT in which the timing controller 303 receives pixel data, the scanning pulses SCAN(N-1) and SCAN(N) and the EM pulse are generated, and then the scanning pulses SCAN(N-1) and SCAN(N) and the EM pulse are shifted sequentially.

[0211] In order to reset the sensor pixel driving circuit COPD, the voltage levels of the exposure signal TG, the low potential voltage VSS, and the pixel driving voltage VDD are changed during the vertical blank period VB. During the reset time to, the organic photodiode OPD and the third S-switch element M3SP are turned on, and the voltage of the fifth node n5 is set to the low potential voltage (VSS=V 1-α ).

[0212] Because the pixel circuit CPIX and the sensor pixel driver circuit COPD share power lines PL1 and PL3, low-potential voltage VSS and pixel drive voltage VDD are applied. In pixel circuit CPIX, when the voltage applied to the light-emitting element OLED changes, the current changes, causing the brightness to change. Therefore, during the reset time to of the sensor pixel driver circuit COPD, to prevent the brightness of the pixel circuit CPIX from changing, the voltage levels of low-potential voltage VSS and pixel drive voltage VDD change, while the voltage across the light-emitting element OLED should not change. In other words, the variation widths of low-potential voltage VSS and pixel drive voltage VDD are set to be the same.

[0213] During the reset time to and the exposure time te, the exposure signal TG is generated as a pulse of the gate-on voltage VGL. During the rest of the time, the exposure signal TG maintains the gate-off voltage VGH. Therefore, the third S-switching element M3SP is turned on during the reset time to and the exposure time te. During the reset time to, the capacitor Cst2 is discharged. Then, during the exposure time te, the capacitor Cst2 is charged with the charge from the organic photodiode OPD to store the charge of the photoelectric conversion signal RX.

[0214] During the reset time to, the low potential voltage VSS decreases to a predetermined voltage V 1-α During the other time periods, the low potential voltage VSS maintains the voltage V1. During the reset time to, the cathode voltage of the organic photodiode OPD decreases to V 1-α , so that a forward bias is applied to the organic photodiode OPD. Therefore, during the reset time to, the organic photodiode OPD and the third S-switching element M3SP are turned on, so that the voltage of the fifth node n5 is set to V 1-α The second S switch element M2S is turned on during the reset time to. 1-α It can be set to a voltage lower than V1 and higher than the gate-on voltage VGL.

[0215] During the reset time to, in order to prevent the current flowing in the light emitting element OLED from changing, the voltage across the light emitting element OLED should not change. For this reason, during the reset time to, the pixel driving voltage VDD is reduced by the voltage of the change amount α of the low potential voltage VSS. During the reset time to, the pixel driving voltage VDD is reduced to V 2-α During the other time periods, the pixel driving voltage VDD maintains the voltage V2. The voltage levels of the pixel driving voltage VDD and the low potential voltage VSS can be simultaneously reduced or increased. V2 can be set to a voltage higher than V1 and lower than the gate cutoff voltage VGH.

[0216] During the exposure time te, the low potential voltage VSS rises to V1. During the exposure time te, the third S switch element M3SP is kept in the on state according to the gate turn-on voltage VGL. In this case, since the cathode voltage of the organic photodiode OPD rises to V1 and the anode voltage thereof becomes V 1-α , so the organic photodiode OPD is reverse biased. During the exposure time te, since the gate voltage of the second S switch element M2S is V 1-α , so the second S-switch element M2S remains in the on state.

[0217] During the exposure time te, when the active layer ACT-OPD of the organic photodiode OPD is irradiated with light, photocurrent is generated, the voltage of the capacitor Cst2 changes in proportion to the amount of received light, and thus, sensor data RX is stored in the capacitor Cst2.

[0218] The exposure time te is determined based on the pulse width of the exposure signal TG. The exposure time te may be set during the vertical blank period VB before pixel data is written to the display pixel, but the present disclosure is not limited thereto. The exposure time te may be extended before the first scan pulse SCNA1 is generated as the gate-on voltage VGL based on the pulse width of the exposure signal TG. In another embodiment, the exposure time te may be extended to the display period AT based on the position of the first sensing area SA, thereby overlapping with one or more scan pulses.

[0219] During the display period AT, display pixels are sequentially scanned, pixel data is written to the display pixels, and sensing data obtained from the photosensors, i.e., sensor data RX, is read. During the display period AT, scan pulses SCAN1 to SCAN(N) synchronized with the data voltage Vdata of the pixel data are sequentially applied to gate lines GL1 and GL2. During the display period AT, the first S-switch element M1S of the sensor pixel drive circuit COPD is turned on by the gate-on voltage VGL of the (N-1)th scan pulse SCAN(N-1), connecting the sixth node n6 to the RX line RXL. In this case, the current flowing through the channel of the second S-switch element M2S, to which the gate-source voltage of the photoelectric conversion signal has been set, flows through the first S-switch element M1S to the RX line RXL.

[0220] To prevent the data voltage Vdata from affecting the sensor data RX, in the pixel circuit CPIX and the sensor pixel driving circuit COPD that share the gate lines GL2 and GL4, the scan pulse for controlling the second switching element M2 of the pixel circuit CPIX can be separated from the scan pulse for controlling the first S-switching element M1S of the sensor pixel driving circuit COPD. For example, the gate of the second switching element M2 can be connected to the first gate line GL1 (to which the Nth scan pulse SCAN(N) is applied), and the gate of the first S-switching element M1S can be connected to the second gate line GL2 (to which the N-1th scan pulse SCAN(N-1) is applied). The scan pulse for controlling the first S-switching element M1S is not limited to the (N-1)th scan pulse SCAN(N-1).

[0221] Figure 25 is a circuit diagram showing a pixel circuit and a sensor pixel driving circuit according to a fourth embodiment of the present disclosure. Figure 26 It shows Figure 25 The pixel circuit and the sensor pixel driving circuit shown are waveform diagrams of the driving method. Figure 25 and Figure 26 Components that are substantially the same as those of the above-described embodiment are given the same reference numerals, and detailed descriptions thereof will be omitted here.

[0222] refer to Figure 25 and Figure 26 To reduce the off-state current, the third S-switch element M3SN of the sensor pixel driver circuit COPD can be implemented as an n-channel TFT. In an n-channel TFT, the gate-on voltage is VGH. Therefore, during the initialization time to and the exposure time te, the pulses of the exposure signal TG are generated as pulses of the gate-on voltage VGH.

[0223] Figure 27 1 is a diagram showing the metal layers of the pixel circuit CPIX and the sensor pixel driving circuit COPD. Figure 27 In the embodiment, the first metal layer including the light shielding pattern BSM is omitted. It should be noted that the cross-sectional structure of the pixel circuit CPIX and the sensor pixel driving circuit COPD is not limited to Figure 27 .exist Figure 27 In the embodiment, GI, ILD1, ILD2, PAS, PLN1 and PLN2 are insulating layers for insulating between the semiconductor layer ACT and the first metal layer and between the plurality of metal layers. Figure 14 shown.

[0224] refer to Figure 27The active layer ACT includes a semiconductor pattern ACTC and a semiconductor pattern ACTM that are metallized by ion doping. The semiconductor pattern ACTC includes a semiconductor active pattern of TFTs in the pixel circuit CPIX and the sensor pixel driving circuit COPD.

[0225] The second metal layer M02 may include a gate line (scan pulses and EM pulses are applied to the gate line). The third metal layer M03 may include a Vini line PL2 (Vini is applied to the Vini line PL2) and a gate line (exposure signal TG is applied to the gate line). The fourth metal layer M04 may be patterned as a data line (data voltage Vdata is applied to the data line). The fifth metal layer M05 may include an RX line RXL (sensor data RX is output through the RX line RXL). The VDD line PL1 may be formed on at least one of the fourth metal layer M04 and the fifth metal layer M05. A metal pattern applying the same signal or the same power supply voltage may be connected to the metallized semiconductor pattern ACTC or a metal jumper pattern omitted in the drawings through a contact hole.

[0226] The capacitor Cst1 of the pixel circuit may be formed between the patterns of the second metal layer M02 and the third metal layer M03 overlapping each other. The capacitor Cst2 of the sensor pixel driving circuit COPD may be formed between the metallized semiconductor pattern ACTM and the third metal layer M03 overlapping each other.

[0227] The gate line (to which the exposure signal TG is applied) may be formed as any one of the metal patterns in the second to fourth metal layers M02, M03, and M04, but the present disclosure is not limited thereto. The RX line RXL may be formed as any one of the metal patterns in the fourth metal layer M04 and the fifth metal layer M05, but the present disclosure is not limited thereto.

[0228] Figure 28 is a circuit diagram illustrating a gamma compensation voltage generator 305 according to one embodiment of the present disclosure.

[0229] refer to Figure 28 The gamma compensation voltage generator 305 receives a high potential input reference voltage VRH and a low potential input reference voltage VRL from the power supply 304, outputs a gamma compensation voltage (or display drive voltage) for each grayscale level used for display driving, and outputs a light source drive voltage. When the driving element DT of the pixel circuit CPIX is driven as a p-channel TFT, the amount of current increases as the gate voltage decreases. Therefore, as the gamma compensation voltage output from the gamma compensation voltage generator 305 decreases, the pixel sensing the light source and the light-emitting device OLED can emit light at high brightness.

[0230] The gamma compensation voltage generator 305 includes an input voltage selector, a grayscale voltage generator 700 for generating a gamma compensation voltage for display driving, and a light source driving voltage generator 600 .

[0231] The gamma compensation voltage generator 305 includes a plurality of voltage divider circuits and a plurality of multiplexers. The voltage divider circuit divides the voltage between the high potential voltage and the low potential voltage using resistors connected in series, and outputs voltages with different voltage levels. Each multiplexer selects a voltage indicated by a resistor setting value from the voltage divided by the voltage divider circuit. The timing controller 303 can input a resistor setting value in the display mode and the fingerprint recognition mode to control the terminals of the multiplexer and control the voltage level of the output voltage V0 to V256 of the gamma compensation voltage generator 305 for each mode. The resistor setting value can be defined and updated by the resistor setting data stored in the second memory 302.

[0232] The input voltage selector includes a voltage divider circuit RS01, a multiplexer MUX01 for selecting the highest grayscale voltage V255 based on the set value of the first resistor, a multiplexer MUX02 for selecting a lower gamma compensation voltage based on the set value of the second resistor, and a multiplexer MUX03 for outputting the lowest gamma compensation voltage V0 based on the set value of the third resistor. The voltage V255 output from the multiplexer MUX01 is supplied to the voltage divider circuits of the grayscale voltage generator 700 and the light source driving voltage generator 600. The voltage output from the multiplexer MUX01 is also supplied to the voltage divider circuit of the grayscale voltage generator 700.

[0233] The light source driving voltage generator 600 includes a tenth voltage divider circuit RS10 connected between the VRL node and the V255 node, and multiplexers MUX10 and MUX20. The voltage divider circuit RS10 divides the voltage between the low potential input reference voltage VRL and the maximum grayscale voltage V255. The output voltage of the voltage divider circuit RS10 has a voltage level higher than the maximum grayscale voltage V255. The multiplexer MUX10 selects any one of the voltages divided by the voltage divider circuit RS10 based on the set value of the fourth resistor and outputs a light source driving voltage (display brightness value (DBV) linkage voltage) that varies according to the display brightness value (DBV). The DBV is brightness setting data used to change the brightness based on the output signal of the illuminance sensor of the host system 200 or the brightness input value of the user. The resistor setting value controlling each multiplexer can vary according to the DBV. The output voltage of the multiplexer MUX10 can be selected from a grayscale voltage range higher than the maximum grayscale voltage V255.

[0234] In fingerprint recognition mode, since the display pixels in the first sensing area SA are driven as light sources, the display pixels can emit light at a higher brightness than that in the display area DA. In this case, the data voltage applied to the display pixels in the first sensing area SA in fingerprint recognition mode can be applied as a light source driving voltage V256 having a grayscale higher than the highest grayscale voltage V255 in the display mode.

[0235] Under the control of the host system 200, multiplexer MUX20 selects either a separate reference voltage (non-DBV linkage voltage) independent of the DBV setting or the DBV linkage voltage output from multiplexer MUX10, and outputs a light source driving voltage V256. The non-DBV linkage voltage is a grayscale voltage higher than the maximum grayscale voltage V255. In fingerprint recognition mode, the host system 200 can use the enable signal EN to control the output voltage of multiplexer MUX20. Therefore, the DBV linkage voltage or the DBV non-linked voltage output from multiplexer MUX20 is a light source driving voltage V256 higher than the maximum grayscale voltage V255.

[0236] The grayscale voltage generator 700 includes a plurality of voltage dividing circuits RS11 to RS17 and a plurality of multiplexers MUX11 to MUX18 .

[0237] The first-first voltage divider circuit RS11 divides the voltage between the output voltage of the first multiplexer MUX01 and the output voltage of the second multiplexer MUX02. The first-first multiplexer MUX11 selects any one of the voltages divided by the voltage divider circuit RS11 according to the resistor setting value. The output voltage of the first-first multiplexer MUX11 can be output through a buffer and can be a voltage V191 of 191 grayscale levels. The first-second voltage divider circuit RS12 divides the voltage between the output voltage of the first-first multiplexer MUX11 and the output voltage of the second multiplexer MUX02. The first-second multiplexer MUX12 selects any one of the voltages divided by the voltage divider circuit RS12 according to the resistor setting value. The output voltage of the first-second multiplexer MUX12 can be output through a buffer and can be a voltage V127 of 127 grayscale levels.

[0238] The first-third voltage divider circuit RS13 divides the voltage between the output voltage of the first-second multiplexer MUX12 and the output voltage of the second multiplexer MUX02. The first-third multiplexer MUX13 selects any one of the voltages divided by the voltage divider circuit RS13 according to the resistor setting value. The output voltage of the first-third multiplexer MUX13 can be output through a buffer and can be a voltage V63 of 63 gray levels. The first-fourth voltage divider circuit RS14 divides the voltage between the output voltage of the first-third multiplexer MUX13 and the output voltage of the second multiplexer MUX02. The first-fourth multiplexer MUX14 selects any one of the voltages divided by the voltage divider circuit RS14 according to the resistor setting value. The output voltage of the first-fourth multiplexer MUX14 can be output through a buffer and can be a voltage V31 of 31 gray levels.

[0239] The first to fifth voltage divider circuit RS15 divides the voltage between the output voltage of the first to fourth multiplexers MUX14 and the output voltage of the second multiplexer MUX02. The first to fifth multiplexers MUX15 select any one of the voltages divided by the voltage divider circuit RS15 according to the resistor setting value. The output voltage of the first to fifth multiplexers MUX15 can be output through a buffer and can be a voltage V15 of 15 gray levels. The first to sixth voltage divider circuit RS16 divides the voltage between the output voltage of the first to fifth multiplexers MUX15 and the output voltage of the second multiplexer MUX02. The first to sixth multiplexers MUX16 select any one of the voltages divided by the voltage divider circuit RS16 according to the resistor setting value. The output voltage of the first to sixth multiplexers MUX16 can be output through a buffer and can be a voltage V7 of 7 gray levels.

[0240] The first to seventh voltage divider circuit RS17 divides the voltage between the output voltage of the first to sixth multiplexers MUX16 and the output voltage of the second multiplexer MUX02. The first to seventh multiplexers MUX17 select any one of the voltages divided by the voltage divider circuit RS17 according to the resistor setting value. The output voltage of the first to seventh multiplexers MUX17 can be output through a buffer and can be a voltage V4 of gray level 4. The first to eighth multiplexers MUX18 select any one of the voltages divided by the voltage divider circuit RS18 according to the resistor setting value. The output voltage of the first to eighth multiplexers MUX18 can be output through a buffer and can be a voltage V1 of gray level 1.

[0241] Grayscale voltage generator 700 further includes a plurality of voltage divider circuits RS21 to RS28. A second-first voltage divider circuit R21 divides the voltage between the highest gamma compensation voltage V255 and the voltage V191 of grayscale 191 to output a gamma compensation voltage between the highest grayscale and grayscale 191. A second-second voltage divider circuit R22 divides the voltage between the voltage V191 of grayscale 191 and the voltage V127 of grayscale 127 to output a gamma compensation voltage between grayscale 191 and grayscale 127. A second-third voltage divider circuit R23 divides the voltage between the voltage V127 of grayscale 127 and the voltage V63 of grayscale 63 to output a gamma compensation voltage between grayscale 127 and grayscale 63. The second-fourth voltage divider circuit R24 divides the voltage between the voltage V63 of gray level 63 and the voltage V31 of gray level 31 to output a gamma compensation voltage between gray level 63 and gray level 31. The second-fifth voltage divider circuit R25 divides the voltage between the voltage V31 of gray level 31 and the voltage V15 of gray level 15 to output a gamma compensation voltage between gray level 31 and gray level 15. The second-sixth voltage divider circuit R26 divides the voltage between the voltage V15 of gray level 15 and the voltage V7 of gray level 7 to output a gamma compensation voltage between gray level 15 and gray level 7. The second-seventh voltage divider circuit R27 divides the voltage between the voltage V7 of gray level 7 and the voltage V4 of gray level 4 to output a gamma compensation voltage between gray level 7 and gray level 4. The second to eighth voltage dividing circuit R28 divides the voltage between the voltage V4 of the 4th gray level and the voltage V1 of the 1st gray level to output a gamma compensation voltage between the 4th gray level and the 1st gray level.

[0242] In order to output the optimal gamma compensation voltage for each color sub-pixel, the gamma compensation voltage generator 305 may include an R gamma compensation voltage generator, a G gamma compensation voltage generator, and a B gamma compensation voltage generator. In this case, the resistor setting value may be set to different voltages in the R gamma compensation voltage generator, the G gamma compensation voltage generator, and the B gamma compensation voltage generator. The gamma compensation voltage output from the R gamma compensation voltage generator is the data voltage for the grayscale to be supplied to the R sub-pixel. The gamma compensation voltage output from the G gamma compensation voltage generator is the data voltage for the grayscale to be supplied to the G sub-pixel. The gamma compensation voltage output from the B gamma compensation voltage generator is the data voltage for the grayscale to be supplied to the B sub-pixel.

[0243] Grayscale gamma compensation voltages V0 to V255 and a light source driving voltage V256 are input to the DAC of the data driver 306. The DAC of the data driver 306 converts the pixel data received from the timing controller 303 into different gamma compensation voltages for each grayscale level to generate data voltages Vdata for display driving. In fingerprint recognition mode, the data driver 306 converts the light source driving data received from the timing controller 303 into the light source driving voltage V256 and supplies the light source driving voltage V256 to the display pixels in the first sensing area SA that serve as the light source through the data lines.

[0244] Since the PPI of each of the first sensing area SA and the second sensing area CA is lower than that of the display area DA, when the display pixels in the display area DA and the display pixels in the first sensing area SA are driven with the same data voltage at the same grayscale level, the brightness of the first sensing area SA and the second sensing area CA may be reduced. According to the present disclosure, the resistor setting value of the gamma compensation voltage generator 305 is changed in the fingerprint sensing mode. Therefore, in the fingerprint sensing mode, the dynamic range of the data voltage applied to the display pixels of the first sensing area SA is expanded, so that the brightness of the pixels in the first sensing area SA and the second sensing area CA can be increased.

[0245] Figure 29 is a view showing data voltages applied to display pixels R, G, and B in the display area DA and data voltages applied to pixels in the sensing area. Figure 29 In FIG. 7 , “PGMA range” represents the output voltage range of the grayscale voltage generator 700 .

[0246] refer to Figure 29 , the data voltages of the pixel data output from the data driver 306 can be set differently in the display area DA and the first and second sensing areas SA and CA. Since the PPI of the display pixels in each of the first and second sensing areas SA and CA is low, the dynamic range of the data voltages applied to the display pixels in the first and second sensing areas SA and CA can be greater than the dynamic range of the data voltage Vdata applied to the display pixels in the display area DA. Therefore, when the voltage V255 of the 255 grayscale level can be applied to the driving elements DT in the first and second sensing areas SA and CA, the voltage (anode voltage) applied to the anode of the light-emitting element OLED by the driving elements DT in the first and second sensing areas SA and CA can become greater than the anode voltage in the display area DA, thereby compensating for the reduction in brightness of the first and second sensing areas SA and CA.

[0247] According to the present disclosure, fingerprint sensing sensor pixels are embedded in the display panel along with the pixels. According to the present disclosure, the pixel driver circuit and the sensor pixel driver circuit share at least one of the power and signal lines, and the electrodes of the light-emitting element and the photodiode are arranged on the same layer, simplifying the display panel structure.

[0248] According to the present disclosure, the resolution of sensor pixels is set to be higher than the resolution of display pixels in a sensing area for fingerprint sensing, so that the accuracy of fingerprint sensing can be improved.

[0249] According to the present disclosure, a data voltage applied to the sensing area is greater than a data voltage applied to the display area, so that a brightness reduction in the sensing area can be compensated.

[0250] The effects that can be achieved by the present disclosure are not limited to the above-mentioned effects. That is, those skilled in the art to which the present disclosure belongs can clearly understand other purposes not mentioned through the following description.

[0251] It is obvious to those skilled in the art that various modifications can be made to the above exemplary embodiments of the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is intended to cover all such modifications as long as they are within the scope of the appended claims and their equivalents.

[0252] The objects to be achieved by the present disclosure, means for achieving the objects, and effects of the present disclosure described above do not specifically describe the essential features of the claims, and therefore, the scope of the claims is not limited to the disclosure of the present disclosure.

[0253] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and the present disclosure can be implemented in many different forms without departing from the technical concepts of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are only for illustrative purposes and are not intended to limit the technical concepts of the present disclosure. The scope of the technical concepts of the present disclosure is not limited thereto. Therefore, it should be understood that the embodiments described above are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the following claims, and all technical concepts within their equivalent scope should be interpreted as belonging to the scope of the present disclosure.

Claims

1. A display device, comprising: A display panel including a display area provided with a plurality of display pixels and a first sensing area provided with a plurality of display pixels and a plurality of sensor pixels, Wherein, in the display mode, the display pixels in the display area and the display pixels in the first sensing area emit light by receiving data voltages of an input image, In the fingerprint recognition mode, the sensor pixels in the first sensing area generate current according to light reflected from the fingerprint, and a resolution of the display pixels in the first sensing area is lower than a resolution of the sensor pixels in the first sensing area, wherein the plurality of display pixels are arranged to be coplanar with the plurality of sensor pixels; The first sensing area includes a plurality of pixel groups, each of the plurality of pixel groups includes one or two display pixels, and Adjacent pixel groups in the first sensing area are spaced apart from each other, and the sensor pixels are interposed between the adjacent pixel groups.

2. The display device according to claim 1, wherein A resolution of the display pixels in the first sensing area is ¼ of a resolution of the sensor pixels in the first sensing area.

3. The display device according to claim 1, wherein The distances between the adjacent pixel groups in the first sensing area are the same in the width direction and the length direction of the display panel; The distance between adjacent sensor pixels in the first sensing area is the same in the width direction and the length direction of the display panel; and A distance between the adjacent pixel groups in the first sensing area is greater than a distance between the adjacent sensor pixels in the first sensing area.

4. The display device according to claim 1, wherein The display panel further includes a second sensing area in which a plurality of light transmission parts and a plurality of display pixels are provided; and A resolution of the display pixels in the second sensing area is lower than a resolution of the sensor pixels in the first sensing area.

5. The display device according to claim 4, wherein A resolution of the display pixels in the second sensing area is ¼ of a resolution of the sensor pixels in the first sensing area. The display device according to claim 5 , wherein: The second sensing area includes a plurality of pixel groups, each of the plurality of pixel groups includes one or two display pixels; and Adjacent pixel groups in the second sensing area are spaced apart from each other, and the light transmitting portion is interposed between the adjacent pixel groups. 7 . The display device of claim 4 , further comprising an optical sensor disposed below the display panel and having a light receiving surface facing the second sensing area.

8. The display device according to claim 6, wherein: Each of the display pixels includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

9. The display device according to claim 6, wherein: Each of the plurality of pixel groups includes a first pixel and a second pixel; The first pixel includes a red sub-pixel and a first green sub-pixel; and The second pixel includes a blue sub-pixel and a second green sub-pixel.

10. The display device according to claim 9, wherein Each of the plurality of pixel groups includes pixels in which sub-pixels are arranged in a rhombus shape or a parallelogram shape.

11. The display device according to claim 1, wherein The light emitting element of each of the plurality of display pixels comprises an organic light emitting diode, i.e., an OLED; Each of the plurality of sensor pixels comprises an organic photodiode; The anode of the OLED is arranged to be coplanar with the anode of the organic photodiode; The cathode of the OLED is arranged to be coplanar with the cathode of the organic photodiode; and A pixel driving circuit configured to drive the OLED and a photosensor driving circuit configured to drive the organic photodiode share one or more lines.

12. The display device according to claim 6 , further comprising a data driver configured to output a data voltage of pixel data to be written into the display pixel, in, A dynamic range of a data voltage applied to the first sensing area and the second sensing area is greater than a dynamic range of a data voltage applied to the display area.

13. The display device according to claim 12, wherein: In the fingerprint recognition mode, the data driver outputs a light source driving voltage higher than the data voltage of the pixel data; and The light source driving voltage is applied to the display pixels in the first sensing area.

14. A mobile terminal device, comprising: A display panel including a display area provided with a plurality of display pixels and a first sensing area provided with a plurality of display pixels and a plurality of sensor pixels; as well as a fingerprint recognition processor configured to generate fingerprint pattern data from a signal photoelectrically converted by the sensor pixels, Wherein, in the display mode, the display pixels of the display area and the display pixels of the first sensing area emit light by receiving the data voltage of the input image, and a resolution of the display pixels in the first sensing area is lower than a resolution of the sensor pixels in the first sensing area, wherein the plurality of display pixels are arranged to be coplanar with the plurality of sensor pixels; The first sensing area includes a plurality of pixel groups, each of the plurality of pixel groups includes one or two display pixels, and Adjacent pixel groups in the first sensing area are spaced apart from each other, and the sensor pixels are interposed between the adjacent pixel groups.

15. The mobile terminal device according to claim 14, wherein: A resolution of the display pixels in the first sensing area is ¼ of a resolution of the sensor pixels in the first sensing area.

16. The mobile terminal device according to claim 14, wherein: The distances between the adjacent pixel groups in the first sensing area are the same in the width direction and the length direction of the display panel; The distance between adjacent sensor pixels in the first sensing area is the same in the width direction and the length direction of the display panel; and A distance between the adjacent pixel groups in the first sensing area is greater than a distance between the adjacent sensor pixels in the first sensing area.

17. The mobile terminal device according to claim 15, wherein: The display panel further includes a second sensing area provided with a plurality of light transmission parts and a plurality of display pixels; and A resolution of the display pixels in the second sensing area is lower than a resolution of the sensor pixels in the first sensing area.

18. The mobile terminal device according to claim 17, wherein: A resolution of the display pixels in the second sensing area is ¼ of a resolution of the sensor pixels in the first sensing area.

19. The mobile terminal device according to claim 18, wherein: The second sensing area includes a plurality of pixel groups, each of the plurality of pixel groups includes one or two display pixels; and Adjacent pixel groups in the second sensing area are spaced apart from each other, and the light transmitting portion is interposed between the adjacent pixel groups. 20 . The mobile terminal device of claim 19 , further comprising an optical sensor disposed below the display panel and having a light receiving surface facing the second sensing area.

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