Data storage method, device and data storage equipment

Abstract

The present application provides a data storage method, device and data storage equipment. The data storage method includes: receiving data to be stored sent by an external device; determining whether a transmission anomaly occurs during the transmission of the data to be stored; if a transmission anomaly occurs during the transmission of the data to be stored, determining whether the link transmission and state machine are in a normal state; if no transmission anomaly occurs during the transmission of the data to be stored, or a transmission anomaly occurs during the transmission of the data to be stored and the link transmission and state machine are in a normal state, storing the data to be stored. After determining that the data to be stored is not junk data, the present application stores the data to be stored, thereby reducing the occupation of the effective storage space by junk data and avoiding damage to the storage device caused by the subsequent removal of junk data.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data storage method, apparatus and data storage device. Background Art

[0002] When the operating system transmits data to the solid state drive (SSD), if the line is stuck, garbage data will be sent to the SSD. However, the SSD cannot perceive the reliability of the data and will flush the garbage data to the flash memory for storage. Therefore, when the operating system reads the data stored in the flash memory, the SSD will feed back the garbage data generated when the line is stuck to the operating system.

[0003] Existing technologies usually focus on identifying and recycling junk data stored in SSDs and clearing invalid data. This operation requires transferring valid data stored in the SSD to other free blocks in the flash memory before erasing the dirty blocks. However, the number of times each block in the flash memory particle can be erased is limited. Excessive erasures will cause bad blocks, shortening the service life of the SSD.

[0004] Therefore, the prior art adopts a recycling method for junk data, which will cause wear on the flash memory particles in the SSD and shorten the service life of the SSD. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a data storage method, device and data storage device, and the specific scheme is as follows:

[0006] In a first aspect, an embodiment of the present application provides a data storage method, which is applied to a data storage device, and the method includes:

[0007] Receiving data to be stored sent by an external device;

[0008] Determining whether a transmission anomaly occurs during the transmission of the data to be stored;

[0009] If a transmission anomaly occurs during the transmission of the data to be stored, determining whether the link transmission and the state machine are in a normal state;

[0010] If no transmission abnormality occurs during the transmission of the data to be stored, or if a transmission abnormality occurs during the transmission of the data to be stored and the link transmission and state machine are in a normal state, the data to be stored is stored.

[0011] According to a specific implementation method disclosed in the present application, if a transmission abnormality occurs during the transmission of the transaction layer data packet, after the step of determining whether the link transmission and the state machine are in a normal state, the method further includes:

[0012] If the link transmission and state machine is in an abnormal state, determining whether the abnormal state of the link transmission and state machine is caused by a preset interruption event;

[0013] If the abnormal state of the link transmission and the state machine is caused by a preset interruption event, the data to be stored is stored.

[0014] According to a specific implementation method disclosed in the present application, the data storage device includes a first register, and the step of determining whether a transmission abnormality occurs during the transmission of the data to be stored includes:

[0015] Determine whether a value of any first-category bit in the first register is a first preset value, wherein each first-category bit in the first register is used to indicate whether a transmission abnormality occurs in the data to be stored;

[0016] If the value of any of the first-category bits is the first preset value, it is determined that a transmission anomaly occurs during the transmission of the data to be stored;

[0017] If the values ​​of all the first-category bits are not the first preset values, it is determined that no transmission abnormality occurs during the transmission of the data to be stored.

[0018] According to a specific implementation manner disclosed in the present application, the type of transmission exception includes any one of a timeout error, a completion abort error, a configuration retry error, and an illegal request error.

[0019] According to a specific implementation method disclosed in the present application, the data storage device includes a second register, and the step of determining whether the link transmission and the state machine are in a normal state includes:

[0020] Determine whether the value of any second-category bit in the second register is a second preset value, wherein each second-category bit in the second register is used to indicate whether the current state of the link transmission and state machine is normal, and if the current state is abnormal, the corresponding second-category bit is set to the second preset value;

[0021] If the value of any of the second-category bits is the second preset value, it is determined that the link transmission and state machine is in an abnormal state;

[0022] If all the second-category bits are not the second preset value, it is determined that the link transmission and state machine are in a normal state.

[0023] According to a specific implementation mode disclosed in the present application, the data storage device includes a third register, and the step of determining whether the abnormal state of the link transmission and state machine is caused by a preset interruption event includes:

[0024] Determine whether any third-category bit in the third register is a third preset value, wherein each of the third-category bits in the third register is respectively used to characterize the type of interrupt event that causes the third register to be reset, and if any type of the interrupt event exists, the value of the corresponding third-category bit is set to the third preset value;

[0025] If the value of any of the third-category bits is the third preset value, it is determined that the abnormal state of the link transmission and state machine is not caused by a preset interruption event;

[0026] If the values ​​of all the third-category bits are not the third preset values, it is determined that the abnormal state of the link transmission and the state machine is caused by a preset interruption event.

[0027] In a second aspect, an embodiment of the present application provides a data storage device, the device comprising:

[0028] A receiving module, used for receiving data to be stored sent by an external device;

[0029] A first judgment module is used to judge whether a transmission anomaly occurs during the transmission of the data to be stored;

[0030] A second judgment module is used to judge whether the link transmission and the state machine are in a normal state if a transmission abnormality occurs during the transmission of the data to be stored;

[0031] The storage module is used to store the data to be stored if no transmission anomaly occurs during the transmission of the data to be stored, or if a transmission anomaly occurs during the transmission of the data to be stored and the link transmission and state machine are in a normal state.

[0032] According to a specific embodiment disclosed in the present application, the data storage device further includes:

[0033] A third judgment module is used to judge whether the abnormal state of the link transmission and state machine is caused by a preset interruption event if the link transmission and state machine is in an abnormal state;

[0034] The storage module is further used to store the data to be stored if the abnormal state of the link transmission and the state machine is caused by a preset interruption event.

[0035] In a third aspect, an embodiment of the present application provides a data storage device, the data storage device comprising a processor and a memory, the memory storing a computer program, and the computer program, when executed on the processor, implements the data storage method described in any one of the embodiments of the first aspect.

[0036] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed on a processor, the data storage method described in any one of the embodiments in the first aspect is implemented.

[0037] Compared with the prior art, this application has the following beneficial effects:

[0038] The present application provides a data storage method, device and data storage equipment. The data storage method includes: receiving data to be stored sent by an external device; determining whether a transmission anomaly occurs during the transmission of the data to be stored; if a transmission anomaly occurs during the transmission of the data to be stored, determining whether the link transmission and state machine are in a normal state; if no transmission anomaly occurs during the transmission of the data to be stored, or a transmission anomaly occurs during the transmission of the data to be stored and the link transmission and state machine are in a normal state, storing the data to be stored. After receiving the data to be stored sent by an external device, the present application determines that the data to be stored is not junk data based on whether a transmission anomaly occurs during the transmission of the data to be stored, and / or the state of the link transmission and state machine, and stores the data to be stored, thereby reducing the occupation of effective storage space by junk data and avoiding damage to the storage device caused by the subsequent removal of junk data. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solution of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be regarded as limiting the scope of protection of the present invention. In each of the drawings, similar components are numbered similarly.

[0040] Figure 1 A schematic diagram of a data storage method provided in an embodiment of the present application;

[0041] Figure 2 A bit annotation diagram of a first register involved in a data storage method provided in an embodiment of the present application;

[0042] Figure 3 A bit annotation diagram of a second register involved in a data storage method provided in an embodiment of the present application;

[0043] Figure 4 A bit annotation diagram of a third register involved in a data storage method provided in an embodiment of the present application;

[0044] Figure 5 A module block diagram of a data storage device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0046] The components of the embodiments of the present invention generally described and shown in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0047] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present invention, are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or adding the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0048] Furthermore, the terms “first”, “second”, “third”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0049] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present invention belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present invention.

[0050] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0051] See also Figure 1 , Figure 1 A flowchart of a data storage method provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, applied to a storage device, the method mainly includes:

[0052] Step S101, receiving data to be stored sent by an external device.

[0053] After the host is powered on, the storage device represented by SSD starts running and starts to receive the data to be stored transmitted by the external device or the operating system. In specific implementation, the data to be stored can be sent according to the bus and standard (Peripheral Component Interface Express, referred to as PCIE) or non-volatile memory standard (Non-Volatile Memory Express, referred to as NVME) and other protocol standards to reach the front-end receiving end of the firmware.

[0054] Step S102, determining whether a transmission anomaly occurs during the transmission of a transaction layer data packet corresponding to the data to be stored.

[0055] Storage devices such as SSDs usually use flash memory particles for storage. The storage rules of flash memory particles are as follows:

[0056] 1. Flash memory particles do not support overwriting, that is, write operations can only be performed in blank or erased cells. When changing the storage data in the flash memory particles, you need to copy the entire page to the cache to modify the corresponding page, then move the changed data to the new page for storage, and mark the page at the original location as an invalid page;

[0057] 2. Flash memory particles are written in "pages" and erased in "blocks". A block consists of multiple pages. Before erasing a block, you need to relocate the valid pages inside.

[0058] 3. Each block has a limit on the number of times it can be erased. Excessive erasures will cause the block to become a bad block, shortening the life of the flash memory particles.

[0059] If a transmission anomaly or other abnormal situation occurs during data transmission, the received data to be stored is likely to have changed and is not the data originally required to be transmitted or stored, that is, junk data. At this time, the data to be stored can no longer be directly stored in the storage device, otherwise, when the junk data is cleared later, it will cause wear and tear on the storage device and shorten the service life of the storage device. This embodiment provides a solution that can pre-screen possible junk data before storage.

[0060] The architecture of PCIE devices can be divided into three levels: transaction layer (TL), data link layer (DLL) and physical layer (PL). Each level can be divided into two parts, namely, the part for processing sending and the part for processing receiving. Data is transmitted between PCIE in the form of data packets, among which the transaction layer data packet (TLP) is related to the part for processing sending in the transaction layer. TLP mainly consists of three parts: Header, Data and ECRC (End-To-End CRC). Header includes relevant information of the sender, target address, TLP type and data length, etc. Data is used to store valid data to be stored. ECRC is used to generate a CRC based on Header and Data, and the receiving end then regenerates Header, Data and CRC based on the received TLP. Compare the two CRCs. If they are the same, it means that the data has a transmission exception during the transmission process, otherwise no transmission exception has occurred. Therefore, after receiving the data to be stored, it can be judged whether the data to be stored has a transmission exception during the transmission process according to the TLP corresponding to the data to be stored.

[0061] The data storage device includes a first register, and the step of determining whether a transmission abnormality occurs during the transmission of the data to be stored includes:

[0062] Determine whether a value of any first-category bit in the first register is a first preset value, wherein each first-category bit in the first register is used to indicate whether there is a transmission anomaly in the data to be stored;

[0063] If the value of any of the first-category bits is the first preset value, it is determined that a transmission anomaly occurs during the transmission of the data to be stored;

[0064] If the values ​​of all the first-category bits are not the first preset values, it is determined that no transmission abnormality occurs during the transmission of the data to be stored.

[0065] The SSD main control chip includes a central processing unit, and the central processing unit is usually composed of an arithmetic unit, a controller and multiple registers, that is, the data storage device includes multiple registers, which can directly determine whether the transaction processing layer data packet is junk data.

[0066] In specific implementation, you can select the first register that meets the requirements according to the register manual comments, such as PCIe_Local_Intr_Enable_Register2 (0x50002D10). Figure 2 , Figure 2 A bit annotation diagram of a first register involved in a data storage method provided in an embodiment of the present application. It should be noted that a register generally consists of 32 bits, and after a single register is split, it can be divided into multiple domains, namely Figure 3 The fields shown in the table often represent a certain independent function. "axi_bridge" is a link bridge, which is used to process the read or write TLP generated by PCIE. The first type of bit can select BIT3-BIT6 in PCIe_Local_Intr_Enable_Register2 (0x50002D10). Combined with the annotations, it can be seen that BIT3 means: when the TLP is detected as ur type, the interrupt is set to the first preset value, where ur refers to unsupported request, that is, the link bridge illegal request error. Generally, the first preset value is 1. Of course, the first preset value can also be customized according to actual usage requirements, and no specific restrictions are made here. BIT4 means: when the TLP is detected as crs type, the interrupt is set to the first preset value, where crs refers to configuration retrystatus, that is, the link bridge configuration retry error. BIT5 means: when the TLP is detected as ca type, the interrupt is set to the first preset value, where ca refers to completer abort, that is, the link bridge completes the abort error. BIT6 indicates: when a TLP timeout is detected, the interrupt is set to the first preset value, i.e., a link bridge timeout error.

[0067] If the values ​​of all the first-category bits are not the first preset values, it is determined that no transmission anomaly occurs during the transmission of the data to be stored, that is, no transmission anomaly occurs that may cause changes in the data to be stored. At this time, the data to be stored can be directly stored in the storage device.

[0068] If the value of any of the first-category bits is a first preset value, it can be determined that a transmission anomaly occurs during the transmission of the data to be stored.

[0069] Step S103: If a transmission abnormality occurs during the transmission of the data to be stored, it is determined whether the link transmission and the state machine are in a normal state.

[0070] The above steps limit it to that if the value of any first-category bit in the first register is the first preset value, it is determined that the data to be stored has a transmission anomaly during the transmission process. However, this does not mean that the data to be stored received at this time is junk data, and it is necessary to further confirm the cause of the anomaly in the first register, that is, whether the upper layer actively sends junk data. For example, the reason why the first-category bit position in the first register is 1 may also be due to poor contact, unstable voltage, or a software bug causing the anomaly.

[0071] That is to say, if the data to be stored has a transmission abnormality during the transmission process, the link transmission and the state machine can continue to be judged according to the second register whether they are in a normal state. The step of judging whether the link transmission and the state machine are in a normal state can specifically include:

[0072] Determine whether the value of any second-category bit in the second register is a second preset value, wherein each second-category bit in the second register is used to indicate whether the current state of the link transmission and state machine is normal, and if the current state is abnormal, the corresponding second-category bit is set to the second preset value;

[0073] If the value of any of the second-category bits is the second preset value, it is determined that the link transmission and state machine is in an abnormal state;

[0074] If all the second-category bits are not the second preset value, it is determined that the link transmission and state machine are in a normal state.

[0075] It should be noted that the second preset value here and the third preset value in the following text are similar to the first preset value mentioned above, and can be set to 1, or the second preset value or the third preset value can be customized according to actual usage requirements.

[0076] In specific implementation, cxpl_debug_info0 (0x50002c04) can be selected as the second register, and the corresponding BIT0-BIT5 can be selected as the second type of bits. Figure 3 , Figure 3 A bit annotation diagram of a second register involved in a data storage method provided in an embodiment of the present application. LTSSM refers to Link Training and Status state Machine, i.e., link transmission and state machine. BIT0-BIT5 are used to characterize the current state of the link transmission and state machine. If the current state is abnormal, the corresponding second type of bit is set to a second preset value. If it is determined that the link transmission and state machine is in a normal state, the data to be stored can be stored.

[0077] If a transmission abnormality occurs during the transmission of the data to be stored, after the step of determining whether the link transmission and the state machine are in a normal state, the method further includes:

[0078] If the link transmission and state machine is in an abnormal state, determining whether the abnormal state of the link transmission and state machine is caused by a preset interruption event;

[0079] If the abnormal state of the link transmission and the state machine is caused by a preset interruption event, the data to be stored is stored.

[0080] In specific operations, it can be determined that the working state of the second register of the LTSSM is usually affected by other registers, and the register that affects the working state of the second register can be defined as a third register. If the third register is reset, the second register will be abnormal, but the abnormal state of the second register is not necessarily caused by the third register. Therefore, it is necessary to further confirm whether the second type of bit in the second register is set to the second preset value due to the reset of the third register. The reasons for resetting the third register include a variety of interruption events. The steps for determining whether the abnormal state of the link transmission and state machine is caused by a preset interruption event include:

[0081] Determine whether any third-category bit in the third register is a third preset value, wherein each of the third-category bits in the third register is respectively used to characterize the type of interrupt event that causes the third register to be reset, and if any type of the interrupt event exists, the value of the corresponding third-category bit is set to the third preset value;

[0082] If the value of any of the third-category bits is the third preset value, it is determined that the abnormal state of the link transmission and state machine is not caused by a preset interruption event;

[0083] If the values ​​of all the third-category bits are not the third preset values, it is determined that the abnormal state of the link transmission and the state machine is caused by a preset interruption event.

[0084] See also Figure 4 , Figure 4 The bit annotation diagram of the third register involved in a data storage method provided in an embodiment of the present application. In specific implementation, the third register can select PCIe_Local_Intr_Register0 (0x5000_2D00), in which all bits BIT0-BIT31 are defined as the third type of bits. Figure 5From the annotations of each bit, it can be seen that if a preset interrupt event occurs, the corresponding bit will be set to the third preset value. For example, Bit2 is used to detect the LTSSM_DISABLE pulse interrupt event, Bit3 is set to 1 when core_rst_n changes to the active state, and the hot reset state is cleared, Bit4 indicates that a hot reset interrupt occurs when LTSSM jumps from S_RCVRY_IDLE to S_HOT_RESET_ENTRY, Bit5 is used when both the application layer and the logic control layer have completed the reset, a register interrupt will occur, and this bit is set to 1, Bit6 is used when flr is initiated by software, a register interrupt will occur, and this bit is set to 1. For a detailed description of other bits, please refer to Figure 5 , I will not go into details here.

[0085] If the abnormal state of the link transmission and the state machine is caused by a preset interruption event, it indicates that the corresponding data to be stored is normal data. This is because the abnormal state without direct correlation mentioned above causes the data to be stored to be "misidentified" as junk data. Therefore, the data to be stored can be stored.

[0086] Step S104: if no transmission anomaly occurs during the transmission of the data to be stored, or if a transmission anomaly occurs during the transmission of the data to be stored and the link transmission and state machine are in a normal state, the data to be stored is stored.

[0087] In summary, the following three situations can determine that the data to be stored is not garbage data and can be stored in the storage space:

[0088] 1. Determine based on the first register that no transmission abnormality occurs during the transmission of the TLP or the data to be stored;

[0089] 2. Determine based on the first register that a transmission abnormality occurs during the transmission of the TLP or the data to be stored, but determine based on the second register that the LTSSM is in a normal state;

[0090] 3. Based on the first register, it is determined that a transmission abnormality occurs in the transmission process of the TLP or the data to be stored, and based on the second register, it is determined that the LTSSM is in an abnormal state, but based on the third register, it is determined that the LTSSM is in an abnormal state due to other interrupt events.

[0091] The data storage method provided by the present application, after receiving the data to be stored sent by the external device, determines whether the data to be stored is reliable based on the value of the relevant register, thereby avoiding storing junk data in the storage device, resulting in the need to subsequently clean up the stored junk data, shortening the service life of the storage device, and also reducing the ineffective occupation of storage space by junk data.

[0092] Corresponding to the above method embodiment, see Figure 5 The present invention further provides a data storage device 500, the data storage device 500 comprising:

[0093] The receiving module 501 is used to receive the data to be stored sent by the external device;

[0094] The first judgment module 502 is used to judge whether a transmission anomaly occurs during the transmission of the data to be stored;

[0095] The second judgment module 503 is used to judge whether the link transmission and the state machine are in a normal state if a transmission abnormality occurs during the transmission of the data to be stored;

[0096] The storage module 504 is used to store the data to be stored if no transmission anomaly occurs during the transmission of the data to be stored, or if a transmission anomaly occurs during the transmission of the data to be stored and the link transmission and state machine are in a normal state.

[0097] In a specific implementation, the data storage device 500 further includes:

[0098] The third judgment module 505 is used to judge whether the abnormal state of the link transmission and state machine is caused by a preset interruption event if the link transmission and state machine is in an abnormal state;

[0099] The storage module 504 is further configured to store the data to be stored if the abnormal state of the link transmission and the state machine is caused by a preset interruption event.

[0100] The data storage device, data storage equipment and computer-readable storage medium provided by the present application, after receiving the data to be stored sent by an external device, determine whether the data to be stored is reliable based on the value of the relevant register, thereby avoiding storing junk data in the storage device, resulting in the need to subsequently clean up the stored junk data, shortening the service life of the storage device, and also reducing the ineffective occupation of storage space by junk data.

[0101] The specific implementation process of the data storage device, data storage equipment and computer-readable storage medium provided in the present application can refer to the specific implementation process of the data storage method provided in the above embodiments, which will not be described in detail here.

[0102] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or the flow chart, and the combination of boxes in the structure diagram and / or the flow chart, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0103] In addition, the functional modules or units in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0104] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0105] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A data storage method, It is characterized in that Applied to a data storage device, the method comprises: Receiving data to be stored sent by an external device; Determining whether a transmission anomaly occurs during the transmission of the data to be stored; If a transmission anomaly occurs during the transmission of the data to be stored, determining whether the link transmission and the state machine are in a normal state; If no transmission anomaly occurs during the transmission of the data to be stored, or if a transmission anomaly occurs during the transmission of the data to be stored and the link transmission and state machine are in a normal state, the data to be stored is stored; If the link transmission and state machine is in an abnormal state, determining whether the abnormal state of the link transmission and state machine is caused by a preset interruption event; If the abnormal state of the link transmission and the state machine is caused by a preset interruption event, the data to be stored is stored.

2. The method according to claim 1, It is characterized in that The data storage device includes a first register, and the step of determining whether a transmission abnormality occurs during the transmission of the data to be stored includes: Determine whether a value of any first-category bit in the first register is a first preset value, wherein each first-category bit in the first register is used to indicate whether a transmission abnormality occurs in the data to be stored; If the value of any of the first-category bits is the first preset value, it is determined that a transmission anomaly occurs during the transmission of the data to be stored; If the values ​​of all the first-category bits are not the first preset values, it is determined that no transmission abnormality occurs during the transmission of the data to be stored.

3. The method according to claim 2, It is characterized in that The type of the transmission exception includes any one of a timeout error, a completion abort error, a configuration retry error, and an illegal request error.

4. The method according to claim 1, It is characterized in that The data storage device includes a second register, and the step of determining whether the link transmission and the state machine are in a normal state includes: Determine whether the value of any second-category bit in the second register is a second preset value, wherein each second-category bit in the second register is used to indicate whether the current state of the link transmission and state machine is normal, and if the current state is abnormal, the corresponding second-category bit is set to the second preset value; If the value of any of the second-category bits is the second preset value, it is determined that the link transmission and state machine is in an abnormal state; If all the second-category bits are not the second preset value, it is determined that the link transmission and state machine are in a normal state.

5. The method according to claim 1, It is characterized in that The data storage device includes a third register, and the step of determining whether the abnormal state of the link transmission and state machine is caused by a preset interruption event includes: Determine whether any third-category bit in the third register is a third preset value, wherein each of the third-category bits in the third register is respectively used to characterize the type of interrupt event that causes the third register to be reset, and if any type of the interrupt event exists, the value of the corresponding third-category bit is set to the third preset value; If the value of any of the third-category bits is the third preset value, it is determined that the abnormal state of the link transmission and state machine is not caused by a preset interruption event; If the values ​​of all the third-category bits are not the third preset values, it is determined that the abnormal state of the link transmission and the state machine is caused by a preset interruption event.

6. A data storage device, It is characterized in that The device comprises: A receiving module, used for receiving data to be stored sent by an external device; A first judgment module is used to judge whether a transmission anomaly occurs during the transmission of the data to be stored; A second judgment module is used to judge whether the link transmission and the state machine are in a normal state if a transmission abnormality occurs during the transmission of the data to be stored; A storage module, used for storing the data to be stored if no transmission anomaly occurs during the transmission of the data to be stored, or if a transmission anomaly occurs during the transmission of the transaction layer data packet and the link transmission and state machine are in a normal state; A third judgment module is used to judge whether the abnormal state of the link transmission and state machine is caused by a preset interruption event if the link transmission and state machine is in an abnormal state; The storage module is further used to store the data to be stored if the abnormal state of the link transmission and the state machine is caused by a preset interruption event.

7. A data storage device, It is characterized in that The data storage device comprises a processor and a memory, wherein the memory stores a computer program, and the computer program implements the data storage method according to any one of claims 1 to 4 when executed on the processor.

8. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed on a processor, the computer program implements the data storage method according to any one of claims 1 to 4.

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