Instruction processing method, apparatus, device, and storage medium

Abstract

The application provides an instruction processing method and device, equipment and a storage medium. The method comprises the following steps: obtaining an instruction to be processed, the instruction to be processed comprising an operation code and an identifier of at least one source operand register, the operation code being used to indicate the type of the instruction to be processed; when it is determined that the instruction to be processed is an exclusive or operation instruction, obtaining operand information from an operand information area of the at least one source operand register; according to the operand information, obtaining a plurality of source operands corresponding to the exclusive or operation instruction from an operand storage area of the at least one source operand register; and performing an exclusive or operation operation corresponding to the exclusive or operation instruction on the plurality of source operands to obtain an instruction operation result. The technical solution can effectively utilize the vector register storage space, reduce the execution time of the plurality of operands in the vector computer when performing the exclusive or operation, and improve the exclusive or operation efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to an instruction processing method and device, equipment and a storage medium. BACKGROUND

[0002] A vector instruction is an instruction used to complete a vector operation in a computer, and modern computers can implement some functions based on the vector instruction. The processing of the vector instruction can include an exclusive-OR operation between operands, and the exclusive-OR operation between two operands and the exclusive-OR operation between multiple operands are common in various application scenarios in a vector computer.

[0003] In the prior art, the vector instruction operation focuses on the parallelism of vectors, and the operands to be processed are filled into different positions of vector registers, and then an exclusive-OR operation is performed between the vector registers, so that the corresponding operation task is completed based on the vector instruction.

[0004] However, the existing vector instruction operation can only perform an exclusive-OR operation between two vector registers each time, and when a large number of vector registers are used, there is a problem that the vector register space cannot be effectively utilized, and the operation efficiency is low. SUMMARY

[0005] The present application provides an instruction processing method, device, equipment and storage medium to overcome the problem that the vector register space cannot be effectively utilized and the operation efficiency is low in the existing exclusive-OR operation process.

[0006] In a first aspect, an embodiment of the present application provides an instruction processing method, comprising:

[0007] obtaining a to-be-processed instruction, wherein the to-be-processed instruction comprises an operation code and an identifier of at least one source operand register, and the operation code is used to indicate the type of the to-be-processed instruction;

[0008] when it is determined that the to-be-processed instruction is an exclusive-OR operation instruction, obtaining operand information from an operand information area of the at least one source operand register;

[0009] obtaining a plurality of source operands corresponding to the exclusive-OR operation instruction from an operand storage area of the at least one source operand register according to the operand information;

[0010] performing an exclusive-OR operation corresponding to the exclusive-OR operation instruction on the plurality of source operands to obtain an instruction operation result.

[0011] In a possible design of the first aspect, the obtaining of the plurality of source operands corresponding to the exclusive-OR operation instruction from the operand storage area of the at least one source operand register according to the operand information comprises:

[0012] According to the operand information, determine the operand type and the number of operands corresponding to the XOR operation instruction, the operand type is used to represent the operand bit width of XOR operation;

[0013] According to the operand type and the operation unit bit width in the computer, determine the number of operation units included in each operand;

[0014] According to the number of operation units included in each operand, sequentially obtain a plurality of source operands of the number of operands from the operand storage area of the at least one source operand register.

[0015] Optionally, before the obtaining the instruction to be processed, the method further comprises:

[0016] Obtain the vector register length in the computer and the operation unit bit width;

[0017] According to the vector register length, the operation unit bit width and the length of the operand type, determine the maximum length of the operand information area;

[0018] According to the length of the operand information area and the vector register length, determine the operand storage area in the at least one source operand register;

[0019] Sequentially store the obtained vector source operand to the operand storage area of the at least one source operand register.

[0020] Optionally, according to the vector register length, the operation unit bit width and the length of the operand type, determining the maximum length of the operand information area, comprises:

[0021] According to the vector register length and the operation unit bit width, determine the width of the operation unit identifier and the number of operation units;

[0022] According to the width of the operation unit identifier and the number of operation units, determine the length occupied by the operation unit identifier;

[0023] According to the length occupied by the operation unit identifier and the length of the operand type, determine the maximum length of the operand information area.

[0024] Optionally, the method further comprises:

[0025] Obtain the bit width of the vector computer;

[0026] According to the bit width of the vector computer and the operation unit bit width, split the operand storage area in the at least one source operand register into at least two operation units;

[0027] The at least two operation units are numbered in sequence to obtain an identifier of each operation unit.

[0028] In a possible design of the first aspect, the to-be-processed instruction further includes an identifier of a destination operand register.

[0029] Correspondingly, the method further includes:

[0030] storing the instruction operation result into the destination operand register.

[0031] In a second aspect, an embodiment of the present application provides an instruction processing apparatus, including:

[0032] an instruction fetching unit, configured to obtain a to-be-processed instruction, the to-be-processed instruction including an operation code and an identifier of at least one source operand register, the operation code being used to indicate a type of the to-be-processed instruction;

[0033] an execution unit, configured to, when it is determined that the to-be-processed instruction is an exclusive OR operation instruction, obtain, from an operand information area of the at least one source operand register, operand information;

[0034] a data fetching unit, configured to, according to the operand information, obtain, from an operand storage area of the at least one source operand register, a plurality of source operands corresponding to the exclusive OR operation instruction;

[0035] an operation unit, configured to perform an exclusive OR operation operation corresponding to the exclusive OR operation instruction on the plurality of source operands to obtain an instruction operation result.

[0036] In a possible design of the second aspect, the data fetching unit is specifically configured to perform the following operation:

[0037] determine, according to the operand information, an operand type and an operand number corresponding to the exclusive OR operation instruction, the operand type being used to represent an operand bit width of the exclusive OR operation;

[0038] determine, according to the operand type and an operation unit bit width in a computer, a number of operation units included in each operand;

[0039] according to the number of operation units included in each operand, sequentially obtain, from the operand storage area of the at least one source operand register, the plurality of source operands of the operand number.

[0040] Optionally, the execution unit is further configured to perform the following operation:

[0041] obtain a vector register length in the computer and the operation unit bit width;

[0042] determine a maximum length of the operand information area according to the vector register length, the operation unit bit width and a length of the operand type;

[0043] determine an operand storage area in the at least one source operand register according to the length of the operand information area and the vector register length;

[0044] store the obtained vector source operand to the operand storage area of the at least one source operand register in sequence.

[0045] Optionally, the execution unit is configured to determine the maximum length of the operand information area according to the vector register length, the operation unit bit width and a length of the operand type, specifically:

[0046] The execution unit is specifically configured to:

[0047] determine a width of an operation unit identifier and a number of operation units according to the vector register length and the operation unit bit width;

[0048] determine a length occupied by the operation unit identifier according to the width of the operation unit identifier and the number of operation units;

[0049] determine the maximum length of the operand information area according to the length occupied by the operation unit identifier and the length of the operand type.

[0050] Optionally, the execution unit is further configured to perform the following operation:

[0051] obtain a bit width of the vector computer;

[0052] split the operand storage area in the at least one source operand register into at least two operation units according to the bit width of the vector computer and the operation unit bit width;

[0053] number the at least two operation units in sequence to obtain an identifier of each operation unit.

[0054] In a possible design of the second aspect, the to-be-processed instruction further includes an identifier of a destination operand register;

[0055] Correspondingly, the operation unit is further configured to store the instruction operation result to the destination operand register.

[0056] In a third aspect, an embodiment of the present application provides a computer device, including a memory and a processor;

[0057] The memory is configured to store computer instructions executable on the processor.

[0058] The processor is configured to execute the computer instructions to implement the instruction processing method according to the first aspect.

[0059] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, wherein computer execution instructions are stored in the computer readable storage medium, and the computer execution instructions are used to implement the instruction processing method according to the first aspect when executed by a processor.

[0060] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising a computer program, which is used to implement the instruction processing method according to the first aspect when executed by a processor.

[0061] The instruction processing method, device, equipment and storage medium provided by the embodiments of the present application can effectively utilize the vector register storage space, reduce the execution time of the plurality of operands in the vector computer when performing the exclusive or operation, and improve the exclusive or operation efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0062] Figure 1 An application scenario diagram of the instruction processing method provided by the embodiments of the present application is shown.

[0063] Figure 2 A flowchart of the instruction processing method provided by the embodiments of the present application is shown.

[0064] Figure 3 A position distribution diagram of the operand information area is shown.

[0065] Figure 4 A processing process diagram of the exclusive or operation instruction in the instruction processing method provided by the embodiments of the present application is shown.

[0066] Figure 5 A flowchart of the instruction processing method provided by the embodiments of the present application is shown.

[0067] Figure 6 A structure diagram of the instruction processing device provided by the embodiments of the present application is shown.

[0068] Figure 7 A structure diagram of the computer equipment provided by the embodiments of the present application is shown. DETAILED DESCRIPTION

[0069] In order to make the purposes, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0070] A vector instruction is an instruction used to complete a vector operation in a computer. An instruction is a command indicating a processor to perform a certain operation. By processing each instruction, an expected function can be achieved. An exclusive-OR operation is an important mathematical operation. Not only the exclusive-OR operation of two operands, but also the exclusive-OR operation of multiple operands plays a role in various application scenarios. For example:

[0071] a) The exclusive-OR operation of multiple operands is quite widely used in block encryption algorithms, such as the advanced encryption standard (AES) algorithm or the Serpent algorithm. In various implementations of block encryption algorithms, such as the cipher block chaining (CBC) mode, the cipher feedback (CFB) mode, and the Counter (CTR) mode, there are also a large number of exclusive-OR operations of multiple operands.

[0072] b) The exclusive-OR operation of multiple operands is also used in algorithms for generating random numbers by hardware.

[0073] c) The exclusive-OR operation of multiple operands is used for parity checking in disk management programs, such as the exclusive-OR operation used in a redundant array of independent disks (RAID3) system to determine whether the value in a disk is incorrect.

[0074] d) An important data structure in computer science: the exclusive-OR linked list, which uses the exclusive-OR operation of two operands to create a linked list and uses the exclusive-OR operation of three operands to perform insertion or deletion operations.

[0075] e) In computer graphics, the exclusive-OR operation of multiple operands is often used as a fast rendering method to replace alpha rendering.

[0076] Based on the background art, in today's widely used vector computers, people take full advantage of the parallelism of vector operations, but ignore the expansion of storage space brought by vector registers, which makes the XOR operation with variable operands can be completed under the condition of using only a small amount of vector registers. Therefore, in some algorithms, although the program behavior has obvious parallelism, the way of selecting operands does not have regularity, and when using vector instructions to perform XOR operation, the space of vector registers cannot be effectively utilized, and there is a problem of low operation efficiency.

[0077] For example, the existing vector instruction focuses on the parallelism of vectors, fills many operands into different positions of the vector register, and performs the same operation on them. For example, the operation between the following operands:

[0078]

[0079] In order to effectively utilize the parallelism of vectors, the operation process between operands can be replaced by the following vector operation:

[0080]

[0081]

[0082] After the above replacement operation, the number of instructions is greatly reduced to a certain extent. However, the above bit operation can only be performed between vector registers, and therefore the operation based on vector parallelism cannot effectively utilize the space of vector registers, for example, for the following operation:

[0083] {

[0084] a1=b1^c1^d1^e1^f1^g1^h1

[0085] }

[0086] Therefore, this operation itself has no parallelism, and therefore the prior art cannot reduce the execution time of this operation in a vector computer, and cannot quickly complete the corresponding operation task, and there is a problem of low operation efficiency.

[0087] In view of the above technical problems, the technical scheme of the present application has the following process: the transmitting unit of the processor inputs the source operands to the operation unit, and also sends control information (operand information) for selecting operands during execution to the operation unit, so that the operation unit selects a plurality of source operands for performing XOR operation according to the control information after receiving the source operands and the control information, and then completes the execution process. The technical scheme can effectively utilize the storage space of vector registers, reduce the execution time of XOR operation of multiple operands in a vector computer, and improve the efficiency of XOR operation.

[0088] It can be understood that the technical solution of the embodiment of the present application can effectively utilize the storage space brought by the vector register, and can process a plurality of 64-bit, 32-bit or 16-bit XOR operations (for example, a 128-bit vector register: up to 3 64-bit numbers, 7 32-bit numbers or 15 16-bit numbers; a 256-bit vector register: up to 7 64-bit numbers, 15 32-bit numbers or 31 16-bit numbers; a 512-bit vector register: up to 15 64-bit numbers, 31 32-bit numbers or 63 16-bit numbers). The embodiment of the present application does not limit the size of the vector register used, nor the number of bits processed, which can be determined according to actual needs, and will not be described here.

[0089] Based on the above construction process, the embodiment of the present application provides an instruction processing method, which comprises the following steps: obtaining a to-be-processed instruction, the to-be-processed instruction comprising: an operation code and an identifier of at least one source operand register, the operation code being used to indicate the type of the to-be-processed instruction; when it is determined that the to-be-processed instruction is an XOR operation instruction, obtaining operand information from an operand information area of the at least one source operand register; according to the operand information, obtaining a plurality of source operands corresponding to the XOR operation instruction from an operand storage area of the at least one source operand register; and performing an XOR operation corresponding to the XOR operation instruction on the plurality of source operands to obtain an instruction operation result.

[0090] Exemplarily, Figure 1 An application scenario of the instruction processing method provided by the embodiment of the present application is shown in the figure. Figure 1 As shown in the figure, the application scenario can comprise a processor and a memory. When the processor is a sequential execution architecture, the processor can comprise a fetch unit, a decoding unit, a physical register stack, an execution unit (including an operation unit) and a memory access unit. The memory access unit can be connected with the memory.

[0091] Specifically, when the processor normally executes a to-be-processed instruction, the processor first obtains the to-be-processed instruction by using the fetch unit, decodes the to-be-processed instruction by using the decoding unit, and then executes the operation corresponding to the processing instruction by using the execution unit. Exemplarily, the operation unit in the execution unit is used to participate in the operation, the physical register stack is used to save the data participating in the operation or save the state of the processor, and the memory access operation is realized between the memory access unit and the memory.

[0092] It can be understood that when the processor is a out-of-order execution architecture, the processor can further comprise a renaming unit, a launch unit, a reordering queue and the like. That is, the above-mentioned renaming unit, launch unit and reordering queue are not required for a non-out-of-order execution processor.

[0093] The renaming unit is used to solve the problem of reverse dependence and perform renaming when out-of-order execution. The renaming process corresponds the register number (referred to as a "logical register") recorded in the program to a physical register number. The logical register of the result of each instruction must be allocated to an idle physical register. The emission unit can emit multiple instructions to the execution unit in one cycle. The reorder queue is used to adjust the order of the instructions to be executed by the processor to achieve the purpose of out-of-order execution. The memory unit can write the result of the search instruction to the corresponding memory.

[0094] It should be noted that the accompanying Figure 1 The application embodiments provided in the application embodiments are only a schematic diagram of an application scenario, and the application embodiments do not limit Figure 1 the components included in the application embodiments, nor limit the positional relationship between the components in the application embodiments. For example, the application scenario can further include other components based on the functions that the processor can implement, and the stack maintenance module that can process the exception path, and the application embodiments do not limit the same. Figure 1

[0095] In the following, the technical solutions of the application are described in detail through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described in detail in some embodiments.

[0096] Figure 2 A flowchart of an instruction processing method embodiment provided by the application embodiments is shown. The method is explained and described by taking the processor as the execution subject. As shown in Figure 2 the instruction processing method can include the following steps:

[0097] S201, obtaining a to-be-processed instruction, the to-be-processed instruction including an operation code and an identifier of at least one source operand register, the operation code being used to indicate the type of the to-be-processed instruction.

[0098] In the embodiments of the application, the to-be-processed instruction in the computer can be stored in the memory in advance, so that when the processor receives the instruction processing indication of the user, the to-be-processed instruction is first taken out from the memory by the instruction fetch unit (i.e., the program counter (PC)), and then the decoding unit is used to decode the to-be-processed instruction to determine the content included in the to-be-processed instruction, such as the operation code and the identifier of the at least one source operand register.

[0099] ​In actual application, the processor can execute different types of instructions, such as exclusive or operation instruction, bit operation instruction and different logical operations. Thus, by including the operation code in the to-be-processed instruction, the type of the to-be-processed instruction can be indicated, so that the processor can implement specific functions when executing the to-be-processed instruction.

[0100] Optionally, in order to determine the source operand register to be operated, the to-be-processed instruction also needs to include the identification of at least one source operand register, so that the source operand can be taken from the at least one source operand register for corresponding operation before the operation corresponding to the to-be-processed instruction is executed. Exemplarily, the identification of the source operand register can also be referred to as the source operand register number, which is used to uniquely identify a source operand register.

[0101] S202, when it is determined that the to-be-processed instruction is an exclusive or operation instruction, obtaining the operand information from the operand information area of the at least one source operand register.

[0102] Optionally, the processor can determine the type of the to-be-processed instruction according to the operation code obtained after decoding the to-be-processed instruction. In this step, in order to solve the problem of low operation efficiency when the vector computer executes the exclusive or operation of multiple operands and cannot effectively utilize the register space, the operand information area is configured in the at least one source operand register to be operated in each to-be-processed instruction, and the operand information required for this operation is stored in the operand information area.

[0103] Exemplarily, the operand information area can also be referred to as the control information domain, which is a position for storing the control information of this operation. The control information is the operand information described in this step, which can include the number of operands to be operated and the like. The embodiments of the present application do not limit the specific content of the operand information, which can be determined according to actual needs, and thus will not be described here.

[0104] In the embodiments of the present application, when the number of operands used in this operation is small, for example, there is only one source operand stored in the remaining space of the source operand register after the operand information area, and the to-be-processed instruction only includes this one source operand register. In actual application, the operands of each operation are usually stored in two or more source operand registers, which are not limited by the embodiments of the present application.

[0105] Optionally, in a possible design of the present application, when the vector source operands participating in this exclusive or operation instruction are stored in two source operand registers, for example, the first part of the vector source operands is stored in the first source operand register and the second part of the vector source operands is stored in the second source operand register, refer to the following Figure 3 Figure 3 ​This is a schematic diagram showing the location distribution of the operand information area. For example... Figure 3 As shown, the processor's data fetching direction (i.e., the direction of operand fetching) starts from the top of the source operand register.

[0106] Optionally, when the vector source operands involved in this XOR operation are stored in a single source operand register, the operation information area is located at the very end of that source operand register. When the vector source operands involved in this XOR operation are stored in multiple source operand registers, the operation information area is located at the very end of the last source operand register in the sequence.

[0107] For example, such as Figure 3 As shown, assuming the instruction to be processed includes a first source operand register and a second source operand register, the operand information area can be located at the very end of the second source operand register.

[0108] Optionally, in embodiments of this application, the size of the operand information area is not fixed, and it varies with the length of the vector register in the vector computer, the bit width of the operation unit in the computer, and the length of the operand type. The operand information area stores operand information, such as the number of operands involved in the current operation and the operand type.

[0109] S203. Based on the operand information, obtain multiple source operands corresponding to the XOR operation instruction from the operand storage area of ​​at least one source operand register.

[0110] In this step, before the processor executes the XOR operation instruction, it can determine the operand type and number of operands for this operation based on the operand information obtained from the operand information area. Then, it reads multiple source operands corresponding to the XOR operation instruction from the operand storage area of ​​at least one source operand register, according to the operand type and number of operands.

[0111] For example, in an embodiment of this application, S203 can be implemented through the following steps:

[0112] A1. Based on the operand information, determine the operand type and number of operands corresponding to the XOR operation instruction. The operand type is used to represent the operand bit width of the XOR operation.

[0113] Optionally, in the embodiments of this application, the operand storage area of ​​the source operand register stores data using the operand unit bit width as the basic length. For example, the operand unit bit width can be 8 bits or 16 bits, etc., which will not be elaborated here. Correspondingly, the operand bit width of the XOR operation instruction can be different operand types such as 16 bits, 32 bits, 64 bits, etc. Therefore, in order to facilitate the subsequent retrieval of operands from at least one source operand register, the processor first determines the operand type corresponding to the XOR operation instruction and the number of operands to be used based on the operand information stored in the operand information area.

[0114] A2. Determine the number of operation units included in each operand based on the operand type and the bit width of the operation unit in the computer.

[0115] Optionally, the bit width of the operation unit in the computer is determined by the instruction encoding. Therefore, when the bit width of the operation unit is determined, the number of operation units included in each operand can be determined based on the bit width of the operand in the XOR operation represented by the operand type.

[0116] For example, assuming the operation unit width in a computer is 16 bits, the way multiple source operands are read depends on the operand type: if the operand type is 16 bits wide, each operand includes 1 operation unit; if the operand type is 32 bits wide, each operand includes 2 operation units; and if the operand type is 64 bits wide, each operand includes 4 operation units.

[0117] A3. Based on the number of operation units included in each operand, obtain multiple source operands of the same number of operands sequentially from the operand storage area of ​​at least one source operand register.

[0118] Optionally, in this embodiment of the application, multiple source operands are read sequentially from the operand storage area according to the number of operands.

[0119] For example, Figure 4 This is a schematic diagram illustrating the processing of the XOR operation instruction in the instruction processing method provided in the embodiments of this application. Figure 4 by Figure 3 The two source operand registers shown are explained below. Figure 4 As shown, the first source operand register stores the first part of the vector source operand, and the second operand register stores the second part of the vector source operand. When the operation unit bit width is used as the basic length, for example, the first part of the vector source operand can be split into 'a' operands, namely O1, O2, O3, ..., O aThe second part of the vector source operand is split into multiple operands. Optionally, the multiple source operands obtained from the splitting of the second part of the vector source operand can be numbered from a+1, sequentially as O... a+1 O a+2 O a+3 And so on. Where a is an integer greater than or equal to 1.

[0120] It is understood that the embodiments of this application do not limit the number of operands obtained by splitting the second part of the vector source operand. The number of operands can be determined according to the length of the vector source operand and the bit width of the operation unit, which will not be elaborated here.

[0121] Reference Figure 4 As shown, the second source operand register has an operand information area, which stores operand information, such as operand type and number of operands N. Therefore, in the embodiments of this application, after the arithmetic unit in the execution unit determines the number of operation units included in each operand according to the operand type and operation unit bit width, it can sequentially read the source operands corresponding to the number of operands from the above-mentioned at least one source operand register.

[0122] For example, if the operation unit width in a computer is 16 bits, and the operand type is 16 bits wide with N operands, then O1, O2, O3, ..., O... are selected sequentially. N As multiple source operands; if the operand type represents a 32-bit width, then based on the number of operands, {O1, O2} is selected as the first source operand, {O3, O4} as the second source operand, and so on, until {O... 2N-1 O 2N} represents the Nth source operand; if the operand type represents a 64-bit width, then {O1, O2, O3, O4} is chosen as the first source operand, {O5, O6, O7, O8} as the second source operand, and so on, until {O... 4N-3 O 4N-2 O 4N-1 O 4N} represents the Nth source operand.

[0123] S204. Perform the XOR operation corresponding to the XOR operation instruction on multiple source operands to obtain the instruction operation result.

[0124] Optional, refer to Figure 4 As shown, the arithmetic unit in the processor selects N source operands based on the operand type and performs an XOR operation on the N operands to obtain the instruction operation result.

[0125] Further, in the embodiments of the present application, the to-be-processed instruction can further include an identifier of the destination operand register. Correspondingly, the instruction processing method provided by the embodiments of the present application can further include the following steps:

[0126] S205, storing the instruction operation result into the destination operand register.

[0127] In this step, the to-be-processed instruction can carry an identifier of at least one source operand register used to store the vector source operand, or can carry an identifier of the destination operand register. Thus, after the processor performs the XOR operation on the obtained multiple source operands to obtain the instruction operation result, the instruction operation result can be stored into the destination operand register corresponding to the identifier of the destination operand register, so as to be used subsequently.

[0128] The instruction processing method provided by the embodiments of the present application includes the following steps: obtaining a to-be-processed instruction, the to-be-processed instruction including an operation code and an identifier of at least one source operand register, the operation code being used to indicate the type of the to-be-processed instruction; when it is determined that the to-be-processed instruction is an XOR operation instruction, obtaining operation number information from an operation number information area of the at least one source operand register, obtaining multiple source operands corresponding to the XOR operation instruction from an operation number storage area of the at least one source operand register according to the operation number information, and performing an XOR operation corresponding to the XOR operation instruction on the multiple source operands to obtain an instruction operation result. This technical solution can effectively utilize the vector register storage space, reduce the execution time of the multiple operands in the vector computer when performing the XOR operation, and improve the XOR operation efficiency.

[0129] Optionally, based on the above-mentioned embodiments, Figure 5 A flowchart of an embodiment of the instruction processing method provided by the embodiments of the present application is shown in FIG. 2. As shown in FIG. 2, in the embodiments of the present application, before S201, the method can further include the following steps: Figure 5

[0130] S501, obtaining the length of the vector register in the computer and the operation unit bit width.

[0131] In actual application, the processor of the computer device is usually provided with multiple groups of vector registers, each group of vector registers can be configured as a source operation register of an instruction, that is, each group of vector registers can be used to store an instruction run by the processor. Generally, the length of the vector register in the processor is fixed, and for a certain operation instruction, the operation unit bit width is determined by the instruction code. Thus, in this step, before obtaining the to-be-processed instruction, the processor can first obtain the length of the vector register in the computer and the operation unit bit width, so as to calculate the length of the operation number information area used to store the operation number information.

[0132] ​S502, determining the maximum length of the operand information area according to the vector register length, the operation unit bit width and the length of the operand type.

[0133] In the embodiment, the maximum length of the operand information area is generally determined according to the vector register length, the operation unit bit width and the length of the operand type, and the actual length of the operand information area is determined by the operation number bit width of the XOR operation indicated by the operand type in the actual application.

[0134] For example, the specific implementation of the step can include the following steps:

[0135] B1, determining the width of the operation unit identifier and the number of operation units according to the vector register length and the operation unit bit width.

[0136] Optionally, in the embodiment of the present application, the width of the operation unit identifier can be obtained by (log2 (vector register length / operation unit bit width)+1), and the number of operation units can be obtained by (vector register length / operation unit bit width).

[0137] B2, determining the length occupied by the operation unit identifier according to the width of the operation unit identifier and the number of operation units.

[0138] In this step, when the width of the operation unit identifier and the number of operation units are known, the length occupied by all operation unit identifiers is obtained by multiplying the two. That is, in the actual application, when the operation number bit width is the same as the operation unit bit width, the length occupied by the operation unit identifier is the length occupied by the operation number; when the operation number bit width is greater than the operation unit bit width, the length occupied by the operation unit identifier is greater than the length occupied by the operation number.

[0139] For example, when the operation unit bit width is 16 bits and the operation number bit width is 16 bits, the length occupied by the operation unit identifier is the length occupied by the operation number; when the operation unit bit width is 16 bits and the operation number bit width is 32 bits or 64 bits, the length occupied by the operation unit identifier is greater than the length occupied by the operation number.

[0140] B3, determining the maximum length of the operand information area according to the length occupied by the operation unit identifier and the length of the operand type.

[0141] For example, the actual length of the operand information area is determined by the length occupied by the operation number and the length of the operand type. Since the maximum length occupied by the operation number is the length occupied by the operation unit identifier, the maximum length of the operand information area is the sum of the length occupied by the operation unit identifier and the length of the operand type.

[0142] In another possible design of the embodiment of the present application, the size of the operand information area can also be pre-configured, for example, refer to the above Figure 3 and Figure 4 As shown in the above two figures, an 18-bit wide operand information area is configured at the tail end of the fetch direction of the second source operand register, wherein the 2 bits of the operand type length are used to indicate that the operand bit width of the XOR operation is 16 bits, 32 bits or 64 bits. The remaining 16 bits (denoted as N in the above figure) of the operand information area are used to record the number of operands of the XOR operation to be performed in this XOR operation. Figure 4

[0143] S503, determine the operand storage area in the at least one source operand register according to the length of the operand information area and the vector register length.

[0144] In this step, after the operand information area in the at least one source operand register is determined, the information such as the operand type and the number of operands can be stored in the space of the operand information area, and the storage space in the at least one source operand register except the storage space occupied by the operand information area is used as the operand storage area. For example, as shown in the above figure, when the number of source operand registers is two, the operand information area is located in the second source operand register, and the operand storage area is the storage space of the first source operand register and the storage space in the second source operand register except the operand information area. Figure 4

[0145] S504, store the obtained vector source operands into the operand storage area of the at least one source operand register in sequence.

[0146] Optionally, after the operand storage area of the at least one source operand register is determined, in order to subsequently obtain the source operands participating in the XOR operation from the source operand register, the obtained vector source operands need to be stored into the at least one source operand register in sequence. For example, when the number of source operand registers is two, the vector source operands are first stored into the first source operand register in sequence, and then stored into the operand storage area of the second source operand register.

[0147] Further, in the embodiment of the present application, refer to the above figure, the instruction processing method can further include the following steps: Figure 5

[0148] S505, obtain the bit width of the vector computer.

[0149] For example, the vector computer is a computer equipped with a special vector instruction to improve the vector processing speed. The bit width of the vector computer can be understood as the vector size specified by the processor.​​​

[0150] S506, according to the bit width of the vector computer and the operation unit bit width, the operation number storage area in the at least one source operation number register is split into at least two operation units.

[0151] Optionally, the operation unit bit width is determined by the instruction code, and after the bit width of the vector computer and the operation unit bit width are obtained, the number of operation units can be calculated by dividing the bit width of the vector computer by the operation unit bit width, for example, for a vector computer with a bit width of 256 bits and an operation unit bit width of 16 bits, the source operation number register without the operation number information area can be divided into 256÷16=16 operation units. Similarly, the operation number storage area in the at least one source operation number register can be split into operation units.

[0152] S507, sequentially numbering the at least two operation units to obtain the identification of each operation unit.

[0153] In the embodiments of the present application, the operation number information in the operation number information area is usually stored in the form of operation number, but the way of taking the source operation number from the source operation number register is determined based on the operation number type and the number of operation units included in each operation number, so in the actual operation process, after the operation number storage area in the at least one source operation number register is split into at least two operation units, it still needs to be sequentially numbered and the identification of each operation unit is determined.

[0154] The instruction processing method provided in the embodiments of the present application obtains the vector register length and the operation unit bit width in the computer, determines the maximum length of the operation number information area according to the vector register length, the operation unit bit width and the length of the operation number type, determines the operation number storage area in the at least one source operation number register according to the length of the operation number information area and the vector register length, and sequentially stores the obtained vector source operation number into the operation number storage area of the at least one source operation number register. In this technical solution, the operation number information area of the at least one source operation number register is determined, and the obtained vector source operation number is stored into the operation number storage area of each source operation number, which provides an implementation condition for subsequent reading when used.

[0155] It can be understood that based on the technical solution of the present application, the vector operation can be flexibly constructed, for example, the program of the highly efficient multi-operation number exclusive or operation can be constructed, which is not described here.

[0156] The following is an embodiment of the device of the present application, which can be used to execute the method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

[0157] Figure 6A structural schematic diagram of an instruction processing apparatus embodiment provided by the present application is shown. The apparatus can be integrated in a processor or implemented by a processor. As shown in the figure, the instruction processing apparatus can include: Figure 6

[0158] An instruction fetching unit 601 is configured to fetch a to-be-processed instruction, the to-be-processed instruction including an operation code and an identification of at least one source operand register, the operation code being used to indicate a type of the to-be-processed instruction.

[0159] An execution unit 602 is configured to, when determining that the to-be-processed instruction is an exclusive OR operation instruction, acquire, from an operand information area of the at least one source operand register, operand information.

[0160] An operand fetching unit 603 is configured to acquire, according to the operand information, a plurality of source operands corresponding to the exclusive OR operation instruction from an operand storage area of the at least one source operand register.

[0161] An operation unit 604 is configured to perform an exclusive OR operation corresponding to the exclusive OR operation instruction on the plurality of source operands to obtain an instruction operation result.

[0162] In a possible design of the embodiment of the present application, the operand fetching unit 603 is specifically configured to perform the following operation:

[0163] According to the operand information, determine an operand type and an operand number corresponding to the exclusive OR operation instruction, the operand type being used to represent an operand bit width of the exclusive OR operation.

[0164] According to the operand type and an operation unit bit width in a computer, determine a number of operation units included in each operand.

[0165] According to the number of operation units included in each operand, sequentially acquire, from the operand storage area of the at least one source operand register, the plurality of source operands of the operand number.

[0166] Optionally, the execution unit 602 is further configured to perform the following operation:

[0167] Acquire a vector register length in the computer and the operation unit bit width.

[0168] According to the vector register length, the operation unit bit width and a length of the operand type, determine a maximum length of the operand information area.

[0169] According to the length of the operand information area and the vector register length, determine the operand storage area in the at least one source operand register.

[0170] ​store the obtained vector source operand to the operand storage area of the at least one source operand register in sequence.

[0171] Optionally, the execution unit 602 is configured to determine the maximum length of the operand information area according to the vector register length, the operation unit bit width and the length of the operand type, specifically:

[0172] The execution unit 602 is specifically configured to:

[0173] determine the width of the operation unit identifier and the number of operation units according to the vector register length and the operation unit bit width;

[0174] determine the length occupied by the operation unit identifier according to the width of the operation unit identifier and the number of operation units;

[0175] determine the maximum length of the operand information area according to the length occupied by the operation unit identifier and the length of the operand type.

[0176] Optionally, the execution unit 602 is further configured to perform the following operations:

[0177] obtain the bit width of the vector computer;

[0178] split the operand storage area in the at least one source operand register into at least two operation units according to the bit width of the vector computer and the operation unit bit width;

[0179] number the at least two operation units in sequence to obtain the identifier of each operation unit.

[0180] In a possible design of the embodiment of the application, the to-be-processed instruction further includes: an identifier of a destination operand register.

[0181] Correspondingly, the operation unit 604 is further configured to store the instruction operation result to the destination operand register.

[0182] The apparatus provided in the embodiments of the application can be used to execute the technical solutions of the above-mentioned method embodiments, and the implementation principles and technical effects are similar, which will not be described herein.

[0183] It should be noted that the division of the units of the above apparatus is only a logical function division, and all or part of them can be integrated into a physical entity or physically separated when actually implemented. These units can all be implemented in the form of software called by a processing element, or all in the form of hardware, or part of the units are implemented in the form of software called by a processing element and part of the units are implemented in the form of hardware. In addition, all or part of these units can be integrated together or independently implemented. The processing element described herein can be an integrated circuit having a signal processing capability. In the implementation process, the steps of the above method or the above units can be completed by the integrated logic circuit of hardware in the processing element or the instructions in the form of software.

[0184] For example, the above units can be one or more integrated circuits configured to implement the above method, such as one or more application specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs), etc. For another example, when a certain unit above is implemented in the form of a processing element scheduling program code, the processing element can be a general purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these units can be integrated together to implement in the form of a system on a chip (SOC).

[0185] In the above embodiments, all or part can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable apparatus. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another, for example, the computer instructions can be transferred from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that includes one or more available media sets. The available media can be magnetic media (for example, floppy disk, hard disk, magnetic tape), optical media (for example, DVD), or semiconductor media (for example, solid state disk (SSD)) and the like.

[0186] Figure 7 The structural schematic diagram of the computer device embodiment provided by the embodiments of the present application is shown in FIG. 7. As shown in the figure, the computer device can include a processor 701, a memory 702, a communication interface 703 and a system bus 704, the memory 702 and the communication interface 703 are connected with the processor 701 through the system bus 704 and complete the communication between each other, the memory 702 is used to store the computer program that can run on the processor 701, the communication interface 703 is used to communicate with other devices, and the processor 701 implements the technical solutions described in the above method embodiments when executing the computer program. Figure 7

[0187] In the above Figure 7 , the processor 701 described above can be a general-purpose processor, including a central processing unit CPU, a network processor NP and the like; can also be a digital signal processor DSP, an application-specific integrated circuit ASIC, a field programmable gate array FPGA or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component.

[0188] ​The memory 702 can include random access memory (RAM) and can also include read-only memory (ROM). The memory 702 can also include non-volatile memory, such as at least one disk memory.

[0189] The communication interface 703 is configured to realize communication between the database access apparatus and other devices (for example, a client, a read-write library, and a read-only library).

[0190] The system bus 704 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The system bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or only one type of bus.

[0191] Optionally, the embodiment of the present application further provides a computer readable storage medium, and the computer readable storage medium stores computer execution instructions. When the computer execution instructions are executed by a processor, the computer execution instructions are used to implement the technical solutions in the above method embodiments.

[0192] Optionally, the embodiment of the present application further provides a chip for running instructions, and the chip is used to execute the technical solutions in the above method embodiments.

[0193] According to the embodiment of the present application, the present application further provides a computer program product, which comprises a computer program. When the computer program is executed by a processor, the computer program is used to implement the technical solutions in the above method embodiments.

[0194] In the present application, "at least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, wherein A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it; in the formula, the character " / ", represents the "division" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single item or multiple items.

[0195] It can be understood that various numerical numbers involved in the embodiments of the present application are only distinguished for convenience of description, and are not used to limit the scope of the embodiments of the present application. In the embodiments of the present application, the size of the serial number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0196] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An instruction processing method, characterized in that, include: Obtain a pending instruction, the pending instruction including: an opcode and an identifier of at least one source operand register, the opcode being used to indicate the type of the pending instruction; When it is determined that the instruction to be processed is an XOR operation instruction, operand information is obtained from the operand information area of ​​the at least one source operand register; Based on the operand information, multiple source operands corresponding to the XOR operation instruction are obtained from the operand storage area of ​​the at least one source operand register; Perform the XOR operation corresponding to the XOR operation instruction on the plurality of source operands to obtain the instruction operation result; The maximum length of the operand information area is determined based on the length of the vector register in the computer, the bit width of the operation unit in the computer, and the length of the operand type corresponding to the XOR operation instruction; the operand storage area in the at least one source operand register is determined according to the length of the operand information area and the length of the vector register; the operand storage area of ​​the at least one source operand register is used to sequentially store the acquired vector source operands.

2. The method according to claim 1, characterized in that, The step of obtaining multiple source operands corresponding to the XOR operation instruction from the operand storage area of ​​the at least one source operand register based on the operand information includes: Based on the operand information, determine the operand type and number of operands corresponding to the XOR operation instruction, wherein the operand type is used to represent the operand bit width of the XOR operation; The number of operation units included in each operand is determined based on the operand type and the operation unit bit width; Based on the number of operation units included in each operand, multiple source operands of the number of operands are sequentially obtained from the operand storage area of ​​the at least one source operand register.

3. The method according to claim 1, characterized in that, Determining the maximum length of the operand information area includes: The width of the operation unit identifier and the number of operation units are determined based on the length of the vector register and the bit width of the operation unit; The length occupied by the operation unit identifier is determined based on the width of the operation unit identifier and the number of operation units; The maximum length of the operand information area is determined based on the length occupied by the operation unit identifier and the length of the operand type.

4. The method according to claim 1, characterized in that, The method further includes: Obtain the bit width of the vector computer; Based on the bit width of the vector computer and the bit width of the operation unit, the operand storage area in the at least one source operand register is split into at least two operation units; The at least two operation units are numbered sequentially to obtain the identifier of each operation unit.

5. The method according to any one of claims 1-4, characterized in that, The instruction to be processed also includes: the identifier of the destination operand register; Accordingly, the method further includes: The result of the instruction operation is stored in the destination operand register.

6. An instruction processing device, characterized in that, include: The instruction fetch unit is used to fetch an instruction to be processed, the instruction to be processed including: an opcode and an identifier of at least one source operand register, the opcode being used to indicate the type of the instruction to be processed; An execution unit is configured to, when determining that the instruction to be processed is an XOR operation instruction, obtain operand information from the operand information area of ​​the at least one source operand register; The data retrieval unit is used to retrieve multiple source operands corresponding to the XOR operation instruction from the operand storage area of ​​the at least one source operand register according to the operand information. The arithmetic unit is used to perform the XOR operation corresponding to the XOR operation instruction on the plurality of source operands to obtain the instruction operation result; The maximum length of the operand information area is determined based on the length of the vector register in the computer, the bit width of the operation unit in the computer, and the length of the operand type corresponding to the XOR operation instruction; the operand storage area in the at least one source operand register is determined according to the length of the operand information area and the length of the vector register; the operand storage area of ​​the at least one source operand register is used to sequentially store the acquired vector source operands.

7. The apparatus according to claim 6, characterized in that, The data retrieval unit is specifically used to perform the following operations: Based on the operand information, determine the operand type and number of operands corresponding to the XOR operation instruction, wherein the operand type is used to represent the operand bit width of the XOR operation; The number of operation units included in each operand is determined based on the operand type and the operation unit bit width; Based on the number of operation units included in each operand, multiple source operands of the number of operands are sequentially obtained from the operand storage area of ​​the at least one source operand register.

8. The apparatus according to claim 6, characterized in that, The execution unit is specifically used for: The width of the operation unit identifier and the number of operation units are determined based on the length of the vector register and the bit width of the operation unit; The length occupied by the operation unit identifier is determined based on the width of the operation unit identifier and the number of operation units; The maximum length of the operand information area is determined based on the length occupied by the operation unit identifier and the length of the operand type.

9. The apparatus according to claim 6, characterized in that, The execution unit is also used to perform the following operations: Obtain the bit width of the vector computer; Based on the bit width of the vector computer and the bit width of the operation unit, the operand storage area in the at least one source operand register is split into at least two operation units; The at least two operation units are numbered sequentially to obtain the identifier of each operation unit.

10. The apparatus according to any one of claims 6-9, characterized in that, The instruction to be processed also includes: the identifier of the destination operand register; Correspondingly, the arithmetic unit is also used to store the result of the instruction operation into the destination operand register.

11. A computer device, characterized in that, include: Memory and processor; Memory for storing computer instructions that can be executed on the processor; The processor is configured to execute the computer instructions to implement the instruction processing method as described in any one of claims 1-5.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the instruction processing method as described in any one of claims 1-5.

13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the instruction processing method according to any one of claims 1-5.

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