A circuit yield analysis method based on multilayer perceptron neural network

Abstract

The present invention discloses a circuit yield analysis method based on a multilayer perceptron neural network, comprising the following steps: 1. uniform distribution sampling: for each process variation parameter of a circuit device, a total amount sample is obtained by adopting a uniform distribution sampling method; 2. Monte Carlo simulation: a circuit simulation is performed on the total amount sample by adopting a Monte Carlo simulation method to obtain a circuit failure sample; 3. importance sampling: the mean value of each parameter of the circuit failure sample is statistically calculated, and the mean value is used as the center point of the circuit failure area, and Gaussian distribution sampling is performed in the circuit failure area with the mean value as the origin to obtain an important sample; 4. multilayer perceptron neural network screening: the important sample is input into a pre-trained multilayer perceptron neural network for screening to obtain a sampling point of circuit failure; 5. circuit yield calculation: the circuit yield is calculated by adopting an importance sampling formula. The present invention can provide fast and accurate yield verification analysis, shortening the project cycle while improving product reliability.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit yield analysis, and in particular relates to a circuit yield analysis method based on a multi-layer perceptron neural network. Background Art

[0002] On the one hand, due to the continuous upgrades and iterations of chip processing technology, chip manufacturing processes continue to shrink. For CMOS processes below 100nm, random variations in process parameters lead to increasingly severe fluctuations in MOS transistor threshold voltages, threatening the stability of SRAM (static random access memory) and causing a decline in SRAM yield. As CMOS process technology advances to 40nm, this impact will become even more severe, accompanied by the increasing impact of process drift and small size effects, which will lead to a significant increase in the uncertainty of IC design results. Therefore, it is crucial to correctly establish and apply comprehensive statistical models during the IC design stage to conduct rapid and accurate IC design yield analysis to effectively prevent the impact on circuit performance and yield.

[0003] On the other hand, in the field of integrated circuit production and manufacturing, the yield rate has improved a company's competitiveness to a certain extent. The higher the yield rate, the higher the company's output at the same cost, and the higher the profit.

[0004] In the prior art, methods for performing circuit yield analysis include Monte Carlo simulation, importance sampling simulation, and the like.

[0005] The Monte Carlo simulation method can evaluate the fluctuation of the overall characteristics by performing multiple simulations and reflecting the fluctuations of various circuit elements in the simulation. However, as the integration density of SRAM increases, the requirements for the simulation accuracy of the failure rate of a single SRAM storage unit are getting higher and higher. The traditional Monte Carlo analysis method has become increasingly impractical because of the large number of simulations required and the long simulation time. For example, in order to obtain a 6-sigma accuracy within a 95% confidence interval for a traditional Monte Carlo simulation of an SRAM critical path, 10 12 Sampling times. Using spice to simulate, 2×10 14 The sampling process takes about 7 days, so 10 12 Traditional Monte Carlo simulation is impractical in today's world where design cycles are key.

[0006] To address this issue, some scholars have proposed the importance sampling method. This algorithm constructs an importance density function (also known as a bias function) to form a corresponding weight function. This weight function is then used to adjust the sampling points, thereby ensuring an unbiased estimate of the failure rate. The importance sampling method reduces the number of simulations and simulation time by selecting a reasonable importance density function. However, if the importance density function is not properly selected, the simulation efficiency and accuracy of the importance sampling method can even fall below those of traditional Monte Carlo simulation methods.

[0007] Establishing comprehensive statistical models, correctly applying them during the IC design phase, and enabling rapid and accurate yield analysis to effectively prevent impacts on circuit performance and yield remain key challenges. As process complexity increases, the greatest challenge in performing statistical analysis of circuits lies in the conflict between speed and accuracy. The pursuit of high accuracy necessitates thorough variability analysis, which necessitates extremely high simulation verification cycles and, consequently, extremely large sampling, inevitably hindering chip design efficiency. Focusing on performance can only compromise circuit analysis accuracy. Monte Carlo can barely cover the required sampling, but the runtime is prohibitively long. Circuits with large repetitive structures, such as SRAM, often require the more sophisticated Six Sigma verification, requiring millions, tens of millions, or even hundreds of millions of simulations, significantly exceeding the capabilities of Monte Carlo. In these circumstances, circuit designers are forced to abandon Monte Carlo. Some opt for maximizing the margin to encompass all process variation, but this can lead to skyrocketing chip costs due to overdesign. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to address the deficiencies in the above-mentioned prior art and provide a circuit yield analysis method based on a multi-layer perceptron neural network, which can provide fast and accurate yield verification analysis, thereby improving product reliability while shortening the project cycle.

[0009] To solve the above technical problems, the present invention adopts a technical solution: a circuit yield analysis method based on a multilayer perceptron neural network, the method comprising the following steps:

[0010] Step 1: Uniformly distributed sampling: For each process variation parameter of the circuit device, a uniformly distributed sampling method is used to obtain a total amount of samples;

[0011] Step 2, Monte Carlo simulation: using the Monte Carlo simulation method to perform circuit simulation on the total amount samples obtained in step 1, and obtaining circuit failure samples by statistically analyzing the circuit simulation results;

[0012] Step 3: Importance sampling: Calculate the mean of each parameter of the circuit failure samples, and use the mean as the center point of the circuit failure area. Perform Gaussian distribution sampling in the circuit failure area with the center point as the origin to obtain important samples.

[0013] Step 4: Multilayer Perceptron Neural Network Screening: Input important samples into the pre-trained multilayer perceptron neural network for screening to obtain sampling points of circuit failure;

[0014] Step 5: Calculate the circuit yield: Calculate the circuit yield using the importance sampling formula based on the result of step 4.

[0015] In the above-mentioned circuit yield analysis method based on a multilayer perceptron neural network, the training process of the multilayer perceptron neural network in step 4 is as follows:

[0016] Step A: Get the training data set. The specific process is as follows:

[0017] Step A1: using a uniformly distributed sampling method to obtain a total amount of samples for each process variation parameter of the circuit device;

[0018] Step A2: performing SPICE simulation and Monte Carlo simulation on the total amount of samples, and combining the SPICE simulation result data and the Monte Carlo simulation result data as a training data set;

[0019] Step B: establishing a multilayer perceptron neural network model based on the characteristics of circuit yield analysis, wherein the multilayer perceptron neural network model includes an input layer, an output layer, and one or more hidden layers connected between the input layer and the output layer;

[0020] Step C: Use the training data set obtained in step A to train the multilayer perceptron neural network model established in step B, minimize the loss function or cost function, and obtain a trained multilayer perceptron neural network.

[0021] The above-mentioned circuit yield analysis method based on a multilayer perceptron neural network, the multilayer perceptron neural network model includes an input layer, an output layer, and a hidden layer connected between the input layer and the output layer, the input layer and the hidden layer each include multiple neurons, the output layer includes one neuron, the multiple neurons in the input layer are fully connected to the multiple neurons in the hidden layer, the multiple neurons in the hidden layer are fully connected to one neuron in the output layer, the multiple neurons in the input layer use different weights, and the activation function of the hidden layer is a Sigmoid function, a tanh function or a step function.

[0022] The above-mentioned circuit yield analysis method based on a multilayer perceptron neural network, the number of neurons contained in the input layer is the same as the number of random process variables provided in the process library file, which are each random process variable; the number of neurons in the hidden layer is equal to the number of actual physical parameters of the circuit; the neurons contained in the output layer are the circuit yield analysis results; the activation function of the hidden layer is the Sigmoid function.

[0023] In the above-mentioned circuit yield analysis method based on multilayer perceptron neural network, when the result of step 4 is used to calculate the circuit yield using the importance sampling formula in step 5, the importance sampling formula used is: Yield=1-P fail Among them, P fail is the failure probability, f(x) is the original distribution provided in the process library file, g(x) is the sampling point of circuit failure determined in step 4; I(x) is the indicator function, which is 1 when the circuit fails and 0 otherwise; Yield is the circuit yield.

[0024] Compared with the prior art, the present invention has the following advantages:

[0025] 1. This invention utilizes multi-layer neural perceptron technology combined with importance sampling for fast Monte Carlo yield analysis, increasing simulation efficiency by over 1,000 times compared to conventional Monte Carlo techniques. This enables high-precision simulation of large-scale circuits within a limited timeframe. For example, performing overall functional yield analysis on a memory chip to achieve 6 sigma accuracy could take months. However, using this invention, accurate analysis results can be obtained within a single day.

[0026] 2. The present invention can be applied to circuit reliability analysis of high-end processes (14nm and below), and can perform fast and accurate yield analysis, effectively avoiding the impact on circuit performance and yield, without causing chip costs to soar.

[0027] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a flowchart of the method of the present invention.

[0029] Figure 2 This is a network topology diagram of the multilayer perceptron neural network of the present invention. DETAILED DESCRIPTION

[0030] like Figure 1 and Figure 2 As shown, the circuit yield analysis method based on the multilayer perceptron neural network of the present invention includes the following steps:

[0031] Step 1: Uniformly distributed sampling: For each process variation parameter of the circuit device, a uniformly distributed sampling method is used to obtain a total amount of samples;

[0032] In specific implementation, the number of total samples can be set by the user according to the actual acceptable simulation time;

[0033] Step 2, Monte Carlo simulation: using the Monte Carlo simulation method to perform circuit simulation on the total amount samples obtained in step 1, and obtaining circuit failure samples by statistically analyzing the circuit simulation results;

[0034] Step 3: Importance sampling: Calculate the mean of each parameter of the circuit failure samples (i.e., the average deviation from the origin), and use this mean as the center point of the circuit failure area. Gaussian distribution sampling is performed in the circuit failure area with this center point as the origin to obtain important samples.

[0035] In specific implementation, the number of samples for Gaussian distribution sampling can be set by the user according to the actual acceptable simulation time;

[0036] Step 4: Multilayer Perceptron Neural Network Screening: Input important samples into the pre-trained multilayer perceptron neural network for screening to obtain sampling points of circuit failure;

[0037] In this embodiment, the training process of the multilayer perceptron neural network in step 4 is as follows:

[0038] Step A: Get the training data set. The specific process is as follows:

[0039] Step A1: using a uniformly distributed sampling method to obtain a total amount of samples for each process variation parameter of the circuit device;

[0040] Step A2: performing SPICE simulation and Monte Carlo simulation on the total amount of samples, and combining the SPICE simulation result data and the Monte Carlo simulation result data as a training data set;

[0041] Step B: establishing a multilayer perceptron neural network model based on the characteristics of circuit yield analysis, wherein the multilayer perceptron neural network model includes an input layer, an output layer, and one or more hidden layers connected between the input layer and the output layer;

[0042] Step C: Use the training data set obtained in step A to train the multilayer perceptron neural network model established in step B, minimize the loss function or cost function, and obtain a trained multilayer perceptron neural network.

[0043] The Multi-Layer Perceptron (MLP) neural network originates from a biomimetic neural network and achieves target screening by connecting multiple existing eigenvalues ​​and combining them linearly or nonlinearly.

[0044] In this embodiment, the multilayer perceptron neural network model includes an input layer, an output layer, and a hidden layer connected between the input layer and the output layer, the input layer and the hidden layer each include multiple neurons, the output layer includes one neuron, the multiple neurons in the input layer are fully connected to the multiple neurons in the hidden layer, the multiple neurons in the hidden layer are fully connected to one neuron in the output layer, the multiple neurons in the input layer use different weights, and the activation function of the hidden layer is a Sigmoid function, a tanh function, or a step function.

[0045] In this embodiment, the number of neurons included in the input layer is the same as the number of random process variables provided in the process library file, which are respectively random process variables; the number of neurons in the hidden layer is equal to the number of actual physical parameters of the circuit; the neurons included in the output layer are the circuit yield analysis results; the activation function of the hidden layer is the Sigmoid function.

[0046] For example, if the number of random process variables provided in the process library file is 20, then the input layer has 20 neurons; assuming that the actual physical parameters of the circuit affected by these 20 random process variables are 20,000, then the number of neurons in the hidden layer is 20,000; finally, the output layer is a node, that is, whether it is a sampling point of circuit failure.

[0047] In this embodiment, when the circuit yield is calculated using the importance sampling formula in step 5, the importance sampling formula used is: Yield=1-P fail Among them, P fail is the failure probability, f(x) is the original distribution provided in the process library file, g(x) is the sampling point of circuit failure determined in step 4; I(x) is the indicator function, which is 1 when the circuit fails and 0 otherwise; Yield is the circuit yield.

[0048] When the input layer is connected to the hidden layer, the neurons in each input layer must not have the same weights. If the same weights are used, it is not possible to construct the optimal classifier model based on the importance of each data. The input feature values ​​are supplemented with different weights and then weighted operations are performed. The linear rules are then changed through activation functions to activate neurons.

[0049] Step 5: Calculate the circuit yield: Use the importance sampling formula to calculate the circuit yield based on the result of step 4, thereby verifying the reliability of the circuit and outputting the circuit reliability result.

[0050] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0051] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0052] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0053] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0054] The foregoing descriptions of specific exemplary embodiments of the present invention are for purposes of illustration and description. These descriptions are not intended to limit the invention to the precise forms disclosed, and it is apparent that many variations and modifications are possible in light of the foregoing teachings. The exemplary embodiments have been selected and described for the purpose of explaining the specific principles of the invention and their practical application, thereby enabling those skilled in the art to realize and utilize a variety of exemplary embodiments of the invention and various options and modifications. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A circuit yield analysis method based on a multilayer perceptron neural network, characterized in that: The method comprises the following steps: Step 1: Uniformly distributed sampling: For each process variation parameter of the circuit device, a uniformly distributed sampling method is used to obtain a total amount of samples; Step 2, Monte Carlo simulation: using the Monte Carlo simulation method to perform circuit simulation on the total amount samples obtained in step 1, and obtaining circuit failure samples by statistically analyzing the circuit simulation results; Step 3: Importance sampling: Calculate the mean of each parameter of the circuit failure samples, and use the mean as the center point of the circuit failure area. Perform Gaussian distribution sampling in the circuit failure area with the center point as the origin to obtain important samples. Step 4: Multilayer Perceptron Neural Network Screening: Input important samples into the pre-trained multilayer perceptron neural network for screening to obtain sampling points of circuit failure; Step 5: Calculate the circuit yield: Calculate the circuit yield using the importance sampling formula based on the result of step 4. The training process of the multilayer perceptron neural network in step 4 is as follows: Step A: Get the training data set. The specific process is as follows: Step A1: using a uniformly distributed sampling method to obtain a total amount of samples for each process variation parameter of the circuit device; Step A2: performing SPICE simulation and Monte Carlo simulation on the total amount of samples, and combining the SPICE simulation result data and the Monte Carlo simulation result data as a training data set; Step B: establishing a multilayer perceptron neural network model based on the characteristics of circuit yield analysis, wherein the multilayer perceptron neural network model includes an input layer, an output layer, and one or more hidden layers connected between the input layer and the output layer; Step C: Use the training data set obtained in step A to train the multilayer perceptron neural network model established in step B, minimize the loss function or cost function, and obtain a trained multilayer perceptron neural network.

2. The circuit yield analysis method based on a multilayer perceptron neural network according to claim 1, characterized in that: The multilayer perceptron neural network model includes an input layer, an output layer, and a hidden layer connected between the input layer and the output layer. The input layer and the hidden layer each include multiple neurons. The output layer includes one neuron. The multiple neurons in the input layer are fully connected to the multiple neurons in the hidden layer. The multiple neurons in the hidden layer are fully connected to one neuron in the output layer. The multiple neurons in the input layer use different weights, and the activation function of the hidden layer is a Sigmoid function, a tanh function, or a step function.

3. The circuit yield analysis method based on a multilayer perceptron neural network according to claim 2, characterized in that: The number of neurons contained in the input layer is the same as the number of random process variables provided in the process library file, which are each random process variable; the number of neurons in the hidden layer is equal to the number of actual physical parameters of the circuit; the neurons contained in the output layer are the circuit yield analysis results; the activation function of the hidden layer is the Sigmoid function.

4. The circuit yield analysis method based on a multilayer perceptron neural network according to claim 1, characterized in that: When the result of step 4 is used to calculate the circuit yield using the importance sampling formula in step 5, the importance sampling formula used is Among them, P fail is the failure probability, f(x) is the original distribution provided in the process library file, g(x) is the sampling point of circuit failure determined in step 4; I(x) is the indicator function, which is 1 when the circuit fails and 0 otherwise; Yield is the circuit yield.

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