Memory device and method of operation thereof and page buffer

Abstract

This document provides a memory device, its operation method, and a page buffer. The memory device may include multiple memory cells and multiple page buffers. The multiple page buffers may be connected to the multiple memory cells via multiple bit lines. The multiple page buffers may perform a bit line precharge operation, which precharges the first bit line of a first memory cell connected to the multiple memory cells to a first voltage. This bit line precharge operation is included in a memory operation that detects a threshold voltage of the first memory cell, and during the memory operation, clamps the potential of a second bit line of a second memory cell connected to the multiple memory cells to a second voltage.

Description

Technical Field

[0001] Various embodiments of this disclosure generally relate to electronic devices, and more specifically to memory devices and methods of operating memory devices. Background Technology

[0002] Storage devices store data under the control of a host device such as a computer or smartphone. A storage device may include a memory device that stores the data and a memory controller that controls the memory device. Typically, there are two types of memory devices: volatile memory devices and non-volatile memory devices.

[0003] In volatile memory devices, data is stored only while power is supplied; when power is interrupted, the stored data is lost. Examples of volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0004] In non-volatile memory devices, stored data is retained even if power is interrupted. Examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory. Summary of the Invention

[0005] Various embodiments of this disclosure relate to improved bit-line coupled memory devices and methods of operating memory devices.

[0006] Embodiments of this disclosure may provide a memory device. The memory device may include a plurality of memory cells and a plurality of page buffers. The plurality of page buffers may be connected to the plurality of memory cells via a plurality of bit lines. The plurality of page buffers may perform a bit line precharge operation, which precharges a first bit line of a first memory cell connected to the plurality of memory cells to a first voltage. The bit line precharge operation is included in a memory operation that detects a threshold voltage of the first memory cell. Furthermore, during the memory operation, the potential of a second bit line of a second memory cell connected to the plurality of memory cells is clamped to a second voltage.

[0007] Embodiments of this disclosure may provide a page buffer. The page buffer may include a switch, a first precharge circuit, and a second precharge circuit. The switch may be connected between a bit line and a node. The first precharge circuit may be connected between a node and a power supply voltage node, and precharges the node to a first voltage based on whether the memory cell connected to the bit line is a selected memory cell for which a memory operation is performed. The second precharge circuit may be connected between the node and the power supply voltage node, and clamps the node's potential to a second voltage based on whether the memory cell is a selected memory cell.

[0008] Embodiments of this disclosure may provide a method for operating a memory device comprising a plurality of memory cells. The method may include the following steps: performing a bit line precharge operation to precharge a first bit line of a first memory cell coupled to the plurality of memory cells to a first voltage; during the bit line precharge operation, precharging a second bit line of a second memory cell coupled to the plurality of memory cells to a second voltage; after the bit line precharge operation, performing an evaluation operation to sense a voltage of the first bit line determined based on a threshold voltage of the first memory cell; and during the evaluation operation, clamping the potential of the second bit line to the second voltage.

[0009] Embodiments of this disclosure provide a method for operating a memory device. The method includes the steps of: precharging even-numbered bit lines and odd-numbered bit lines to a first voltage level and a second voltage level, respectively, during a precharge period, wherein the even-numbered bit lines and odd-numbered bit lines are respectively connected to an even-numbered memory cell and an odd-numbered memory cell; sensing the voltage level of at least one of the even-numbered bit lines while maintaining the second voltage level during an evaluation period; and latching data stored in at least one of the even-numbered memory cells based on the sensed voltage level during a latching period. Attached Figure Description

[0010] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0011] Figure 2 Examples include, for example Figure 1 A diagram showing the structure of a memory device, such as a memory device.

[0012] Figure 3 Examples include, for example Figure 2 A diagram of a memory cell array, such as a memory cell array.

[0013] Figure 4 This is a diagram illustrating read operations performed on some pages.

[0014] Figure 5 Examples of implementation methods, such as Figure 2 A diagram showing the structure of a page buffer, such as a page buffer.

[0015] Figure 6 Examples include, for example Figure 5 A timing diagram of the operation of page buffers, such as page buffers.

[0016] Figure 7 Examples of implementation methods, such as Figure 2 A diagram showing the structure of a page buffer, such as a page buffer.

[0017] Figure 8A This is an example of a memory cell, such as a selected memory cell, to which memory operations are performed. Figure 7 A timing diagram of the operation of page buffers, such as page buffers.

[0018] Figure 8B This is an example of a memory cell, such as one that is connected to an unselected memory cell to which no memory operation is performed. Figure 7 A timing diagram of the operation of page buffers, such as page buffers.

[0019] Figure 9 This is a flowchart illustrating the operation of a memory device according to an embodiment. Detailed Implementation

[0020] This document provides specific structural and functional descriptions to describe embodiments of the present disclosure. However, the invention can be practiced and carried out in various forms and in various ways; therefore, the invention is not limited to the disclosed embodiments. Furthermore, throughout the specification, references to “implementation,” etc., are not necessarily limited to only one embodiment, and different references to any such phrase are not necessarily the same embodiment. Moreover, unless explicitly stated that only one is intended to be used, the use of the indefinite article (i.e., “a” or “one”) means one or more. Similarly, when used herein, the terms “comprising,” “including,” “having,” etc., do not exclude the presence or addition of one or more other elements besides those stated.

[0021] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0022] Reference Figure 1 The storage device 50 may include a memory device 100 and a memory controller 200 for controlling the operation of the memory device. The storage device 50 can store data under the control of a host computer such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, television (TV), tablet PC, or in-vehicle infotainment system.

[0023] Depending on the host interface specifying the communication protocol with the host, storage device 50 can be manufactured as any of various types of storage devices. For example, storage device 50 can be implemented as any of various types of storage devices, such as solid-state drives (SSDs), multimedia cards such as MMC, embedded MMC (eMMC), size-reduced MMC (RS-MMC), or micro MMC, secure digital cards such as SD, mini SD, or micro SD, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card-type storage devices, peripheral component interconnect (PCI) card-type storage devices, high-speed PCI (PCI-E) card-type storage devices, compact flash memory (CF) cards, smart media cards, and / or memory sticks.

[0024] Storage device 50 can be manufactured in any of a variety of package types. For example, storage device 50 can be manufactured in any of a variety of package types such as point-of-purchase (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and / or wafer-level stacked package (WSP).

[0025] The memory device 100 can store data. The memory device 100 can be operated in response to the control of the memory controller 200. The memory device 100 may include a memory cell array comprising a plurality of memory cells for storing data.

[0026] Each memory cell can be implemented as a single-level cell (SLC) capable of storing one data bit, a multi-level cell (MLC) capable of storing two data bits, a three-level cell (TLC) capable of storing three data bits, or a four-level cell (QLC) capable of storing four data bits.

[0027] The memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells. A single memory block may include multiple pages. In an embodiment, a page may be a unit through which data is stored in the memory device 100 or through which data stored in the memory device 100 is read.

[0028] A memory block can be a unit through which data is erased. In embodiments, the memory device 100 may take the form of various alternatives such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Generation 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory devices, Resistive RAM (RRAM), Phase Change Memory (PRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FRAM), or Spin-Torque RAM (STT-RAM). In this specification, features and aspects of the invention are described by way of example in the case where the memory device 100 is NAND flash memory.

[0029] Memory device 100 can receive commands and addresses from memory controller 200 and can access regions in the memory cell array selected by address. That is, memory device 100 can perform operations instructed by commands on the regions selected by address. For example, memory device 100 can perform write operations (i.e., programming operations), read operations, and erase operations. During a programming operation, memory device 100 can program data into the region selected by address. During a read operation, memory device 100 can read data from the region selected by address. During an erase operation, memory device 100 can erase data stored in the region selected by address.

[0030] The memory controller 200 controls the overall operation of the storage device 50.

[0031] When power is supplied to storage device 50, memory controller 200 can run firmware (FW). When storage device 100 is a flash memory device, memory controller 200 can run firmware such as flash translation layer (FTL) to control communication between the host and storage device 100.

[0032] In one implementation, the memory controller 200 may receive data and logical block addresses (LBAs) from the host and may convert the logical block addresses (LBAs) into physical block addresses (PBAs) that indicate the addresses of memory cells included in the memory device 100 and in which data is to be stored.

[0033] The memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations in response to requests received from the host. During a programming operation, the memory controller 200 can provide a write command, a physical block address, and data to the memory device 100. During a reading operation, the memory controller 200 can provide a read command and a physical block address to the memory device 100. During an erasing operation, the memory controller 200 can provide an erase command and a physical block address to the memory device 100.

[0034] In this implementation, the memory controller 200 can autonomously generate commands, addresses, and data without a request from the host and can send them to the memory device 100. For example, the memory controller 200 can autonomously generate commands, addresses, and data and provide them to the memory device 100 to perform background operations such as programming operations for wear leveling and programming operations for garbage collection.

[0035] In this implementation, the memory controller 200 can control at least two memory devices 100. In this case, the memory controller 200 can control the memory devices 100 according to an interleaving scheme to improve operational performance. The interleaving scheme can be an operation mode in which the operation periods of at least two memory devices 100 overlap with each other.

[0036] The host can communicate with the storage device 50 using at least one of a variety of communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCIe), High Speed ​​Non-Volatile Memory (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM) and / or Loaded DIMM (LRDIMM).

[0037] Figure 2 This is an example Figure 1 A diagram of the structure of a memory device.

[0038] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0039] The memory cell array 110 includes multiple memory blocks BLK1 to BLKz connected to the address decoder 121 via row lines RL. Memory blocks BLK1 to BLKz are connected to the read / write circuitry 123 via bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz may include multiple memory cells. In embodiments, the multiple memory cells may be non-volatile memory cells. Memory cells connected to the same word line among the multiple memory cells are defined as a physical page. In other words, the memory cell array 110 may include multiple physical pages. In embodiments of this disclosure, each of the memory blocks BLK1 to BLKz included in the memory cell array 110 may include multiple dummy cells. One or more dummy cells may be connected in series between a drain select transistor and a memory cell, and between a source select transistor and a memory cell.

[0040] Each memory cell of the memory device 100 can be implemented as a single-level cell (SLC) capable of storing one data bit, a multi-level cell (MLC) capable of storing two data bits, a three-level cell (TLC) capable of storing three data bits, or a four-level cell (QLC) capable of storing four data bits.

[0041] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read / write circuit 123, a data input / output circuit 124, and a sensing circuit 125.

[0042] The peripheral circuitry 120 can drive the memory cell array 110. For example, the peripheral circuitry 120 can drive the memory cell array 110 to perform programming operations, reading operations, and erasing operations.

[0043] Address decoder 121 is connected to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to embodiments of this disclosure, word lines may include normal word lines and dummy word lines. According to embodiments of this disclosure, row lines RL may also include pipe select lines.

[0044] Address decoder 121 can operate under the control of control logic 130. Address decoder 121 receives address ADDR from control logic 130.

[0045] Address decoder 121 can decode the block address in the received address ADDR. Address decoder 121 selects at least one of the memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 can decode the row address in the received address ADDR. Address decoder 121 selects at least one word line in the selected memory block based on the decoded row address. Address decoder 121 can apply the operating voltage Vop provided from voltage generator 122 to the selected word line.

[0046] During programming operations, address decoder 121 may apply a programming voltage to the selected word line and apply a pass voltage having a level lower than the programming voltage to the unselected word line. During programming verification operations, address decoder 121 may apply a verification voltage to the selected word line and apply a verification pass voltage higher than the verification voltage to the unselected word line.

[0047] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and apply a read pass voltage higher than the read voltage to the unselected word line.

[0048] According to embodiments of this disclosure, an erase operation of the memory device 100 is performed based on memory blocks. During the erase operation, the address ADDR input to the memory device 100 includes a block address. The address decoder 121 can decode the block address and select at least one memory block based on the decoded block address. During the erase operation, the address decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0049] According to embodiments of this disclosure, address decoder 121 can decode the column address in the received address ADDR. The decoded column address can be transmitted to read / write circuit 123. In embodiments, address decoder 121 may include components such as row decoder, column decoder, and address buffer.

[0050] Voltage generator 122 can use the external power supply voltage provided to memory device 100 to generate multiple operating voltages Vop. Voltage generator 122 can operate under the control of control logic 130.

[0051] In this embodiment, the voltage generator 122 can generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as the operating voltage of the memory device 100.

[0052] In this implementation, voltage generator 122 can use an external power supply voltage or an internal power supply voltage to generate multiple operating voltages Vop. Voltage generator 122 can generate various voltages used by memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0053] Voltage generator 122 may include multiple pumping capacitors for receiving internal power supply voltages to generate multiple operating voltages Vop with various voltage levels, and can generate multiple operating voltages Vop by selectively activating multiple pumping capacitors under the control of control logic 130.

[0054] The generated operating voltage Vop can be provided to the memory cell array 110 through the address decoder 121.

[0055] The read / write circuit 123 includes first page buffers PB1 to PBm of the memory cell array 110, which are respectively connected to the first page line BL1 to the m-th page line BLm. The first page buffers PB1 to PBm are operated under the control of the control logic 130.

[0056] Page buffers PB1 through PBm (page m) communicate with the data input / output circuit 124. During programming operations, page buffers PB1 through PBm receive the data to be stored, DATA, through the data input / output circuit 124 and the data line DL.

[0057] During programming operations, when a programming voltage is applied to the selected word line, the first page buffer PB1 to the m-th page buffer PBm can transmit the data DATA to be stored, received via the data input / output circuit 124, to the selected memory cell via bit lines BL1 to BLm. The memory cell in the selected page is programmed based on the received data DATA. Memory cells connected to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification operations, the first page buffer PB1 to the m-th page buffer PBm read the data DATA stored in the selected memory cell from the selected memory cell via bit lines BL1 to BLm.

[0058] During a read operation, the read / write circuit 123 can read data DATA from the memory cell in the selected page via the bit line BL, and can store the read data DATA in the first page buffer PB1 to the m-th page buffer PBm.

[0059] During the erase operation, the read / write circuit 123 may allow the bit line BL to float. In one embodiment, the read / write circuit 123 may include column select circuitry.

[0060] The data input / output circuit 124 is connected to the first page buffer PB1 to the m-th page buffer PBm via data lines DL. The data input / output circuit 124 is operated in response to the control logic 130.

[0061] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 receives data DATA to be stored from an external controller (not shown). During read operations, the data input / output circuit 124 outputs data DATA received from the first page buffer PB1 to the m-th page buffer PBm included in the read / write circuit 123 to the external controller.

[0062] During a read or verification operation, the sensing circuit 125 can generate a reference current in response to the enable bit signal VRYBIT generated by the control logic 130, and can output a pass signal or a failure signal to the control logic 130 by comparing the sensed voltage VPB received from the read / write circuit 123 with the reference voltage generated by the reference current.

[0063] Control logic 130 can be connected to address decoder 121, voltage generator 122, read / write circuit 123, data input / output circuit 124, and sensing circuit 125. Control logic 130 can control the overall operation of memory device 100. Control logic 130 can operate in response to commands (CMD) sent from external devices.

[0064] Control logic 130 can control peripheral circuit 120 by generating various types of signals in response to command CMD and address ADDR. For example, in response to command CMD and address ADDR, control logic 130 can generate operation signal OPSIG, address ADDR, read / write circuit control signal PBSIGNALS, and enable bit VRYBIT. Control logic 130 can output operation signal OPSIG to voltage generator 122, address ADDR to address decoder 121, read / write circuit control signal PBSIGNALS to read / write circuit 123, and enable bit VRYBIT to sensing circuit 125. Additionally, control logic 130 can determine whether the verification operation passed or failed in response to pass signal PASS or failure signal FAIL output from sensing circuit 125.

[0065] Figure 3 This is an example Figure 2 A diagram of a memory cell array.

[0066] Reference Figure 3 The first storage block BLK1 to the z-th storage block BLKz are all connected to the first bit line BL1 to the m-th bit line BLm. Figure 3 The diagram illustrates, by way of example, the elements included in the first storage block BLK1 of a plurality of storage blocks BLK1 to BLKz. It will be understood that each of the remaining storage blocks BLK2 to BLKz has the same configuration as the first storage block BLK1.

[0067] The memory block BLK1 may include multiple cell strings CS1_1 to CS1_m (where m is a positive integer of 2 or greater). The first cell string CS1_1 to the m-th cell string CS1_m are respectively connected to the first bit line BL1 to the m-th bit line BLm. Each of the first cell string CS1_1 to the m-th cell string CS1_m may include a drain selection transistor DST, multiple memory cells MC1 to MCn (where n is a positive integer of 2 or greater) connected in series with each other, and a source selection transistor SST.

[0068] The gate terminal of the drain select transistor DST included in each of the first unit strings CS1_1 to the m-th unit string CS1_m is connected to the drain select line DSL1. The gate terminals of the first memory cell MC1 to the n-th memory cell MCn included in each of the first unit strings CS1_1 to the n-th word line WL1 to WLn, respectively. The gate terminal of the source select transistor SST included in each of the first unit strings CS1_1 to the m-th unit string CS1_m is connected to the source select line SSL1.

[0069] The structure of the first unit string CS1_1 among multiple unit strings CS1_1 to CS1_m is described by way of example. Each of the remaining unit strings CS1_2 to CS1_m is configured in the same way as the first unit string CS1_1.

[0070] The drain terminal of the drain select transistor DST included in the first unit string CS1_1 is connected to the first bit line BL1. The source terminal of the drain select transistor DST included in the first unit string CS1_1 is connected to the drain terminal of the first memory cell MC1 included in the first unit string CS1_1. The first memory cells MC1 to the nth memory cell MCn can be connected in series with each other. The drain terminal of the source select transistor SST included in the first unit string CS1_1 is connected to the source terminal of the nth memory cell MCn included in the first unit string CS1_1. The source terminal of the source select transistor SST included in the first unit string CS1_1 is connected to the common source line CSL. In an embodiment, the common source line CSL can be connected to the first memory block BLK1 to the zth memory block BLKz.

[0071] Drain select line DSL1, first word line WL1 to nth word line WLn and source select line SSL1 are included Figure 2 In the row line RL, the drain selection line DSL1, the first word lines WL1 to the nth word lines WLn, and the source selection line SSL1 are controlled by the address decoder 121. The common source line CSL is controlled by the control logic 130. The first bit line BL1 to the mth bit line BLm are controlled by the read / write circuit 123.

[0072] Figure 4 This is a diagram illustrating read operations performed on some pages.

[0073] Reference Figure 4 A single page can include multiple memory units.

[0074] Memory cells connected to even-numbered bit lines are labeled as even-numbered memory cells. Memory cells connected to odd-numbered bit lines are labeled as odd-numbered memory cells.

[0075] Even-number read operations on even-number memory cells and odd-number read operations on odd-number memory cells can be performed separately.

[0076] Read operations can include bit line precharge operations, evaluation operations, and latch operations.

[0077] Bit line precharge operation may include increasing the potential of a bit line connected to a memory cell. Evaluation operation may include sensing the potential or current of the bit line determined based on a threshold voltage of the memory cell. Latch operation may include storing data from the memory cell in a latch based on the sensed potential or current of the bit line.

[0078] In this implementation, when performing an even-numbered read operation, the even-numbered bit lines connected to the even-numbered memory cells can be pre-charged during the bit line pre-charge operation. When performing an odd-numbered read operation, the odd-numbered bit lines connected to the odd-numbered memory cells can be pre-charged during the bit line pre-charge operation.

[0079] In one implementation, when performing an even-number read operation or an odd-number read operation, all bit lines connected to multiple memory cells can be precharged during the bit line precharge operation.

[0080] When all bit lines are precharged, the voltage difference between adjacent bit lines is smaller than when even or odd bit lines are selectively precharged, and therefore, interference caused by bit line coupling can be minimized.

[0081] In various implementations, even-numbered pages, which are half-pages, can be divided into smaller units (e.g., quarter-page units), and thus read operations can be performed on a quarter-page basis. Odd-numbered pages, which are half-pages, can be divided into smaller units (e.g., quarter-page units), and thus read operations can be performed on a quarter-page basis.

[0082] Figure 5 This is an example based on the implementation method. Figure 2 A diagram showing the structure of the page buffer.

[0083] Reference Figure 5 The bit line BL, connected to the memory cell, can be connected to the first node CSO via the first switch T1. When the first node CSO is precharged and the first switch T1 is turned on, the potential of the first node CSO can be transferred to the bit line BL via the first switch T1. That is, the bit line BL can be precharged.

[0084] The following description is performed in the context of a memory operation that detects the threshold voltage of an even number of memory cells. The memory operation can be a read operation or a program verification operation.

[0085] The same first precharge signal SA_PRECH_N can be input to both the even-page buffer connected to even-numbered memory cells and the odd-page buffer connected to odd-numbered memory cells.

[0086] When performing an even-numbered read operation, each even-numbered bit line connected to the even-numbered page buffer can be precharged via the first precharge path (BL precharge path 1). When performing an even-numbered read operation, each odd-numbered bit line connected to the odd-numbered page buffer can be precharged via the first precharge path (BL precharge path 1).

[0087] In other words, even when performing an even-number read operation, all bit lines can be precharged via the first precharge path (BL precharge path 1) during the bit line precharge operation.

[0088] The memory operation of detecting the threshold voltage on the odd number of memory cells is performed in the same manner as described above.

[0089] Figure 6 This is an example Figure 5 The timing diagram for the operation of the page buffer.

[0090] Reference Figure 6 When performing even-number read operations, an odd-number page buffer can be used. An odd-number page buffer can be linked to an odd-number memory cell to which even-number read operations are not performed.

[0091] When performing an even-number read operation, even-numbered memory cells can be selected, and odd-numbered memory cells can be left unselected and thus marked as unselected memory cells. In this implementation, during an even-numbered read operation, odd-numbered bit lines can also be precharged together with even-numbered bit lines, and therefore precharging can be performed faster compared to the case where only even-numbered bit lines are precharged. Furthermore, since all bit lines are precharged, interference caused by bit line coupling can be minimized. An even-numbered read operation may include a bit line precharging operation (time period from t1 to t2), an evaluation operation (time period from t2 to t4), and a latching operation (not shown).

[0092] During the bit line precharge operation included in even-number read operations, the first node CSO of the odd-number page buffer can be precharged to voltage VCSO1. The bit line BL of the odd-number page buffer can be precharged to voltage VBL1.

[0093] In this implementation, during the evaluation operation, the voltage of the first node CSO can vary (oscillate) based on the amount of current flowing through the memory cell connected to the bit line BL. The amount of current flowing through the memory cell can be determined based on the threshold voltage of the memory cell.

[0094] exist Figure 6 During the evaluation operation, the voltage of the first node CSO can drop from voltage VCSO1 to voltage VCSO1' (CSO swing). When a CSO swing occurs in the voltage of the first node CSO, the voltage of the bit line BL can also drop from voltage VBL1 to voltage VBL1' (BL drop).

[0095] To minimize bit-line coupling, the voltage on the odd-numbered bit lines connected to the odd-numbered page buffer should be constant during even-numbered read operations. In other words, a drop in BL (Block Line Drop) should not occur on the odd-numbered bit lines during even-numbered read operations. Figure 5In the case of a page buffer structure, during evaluation operation, the voltage of the odd bit lines drops (BL drops) due to voltage changes in the first node CSO (CSO swing), and therefore the effects of bit line coupling may increase.

[0096] The reason for the CSO swing on the first node CSO of the odd page buffer and the BL drop on the odd bit line during even read operations is that the same precharge signal SA_PRECH_N is applied to both the even page buffer and the odd page buffer, and therefore the first node CSO of the odd page buffer, which is not subjected to even read operations, is precharged to voltage VCOS1.

[0097] In this implementation, when performing an odd-number read operation, the operation of the even-number page buffer can be performed in the same way.

[0098] Figure 7 This is an example based on the implementation method. Figure 2 A diagram showing the structure of the page buffer.

[0099] Reference Figure 7 The page buffer 400 may include a first switch T1, a first precharge circuit 410, and a second precharge circuit 420.

[0100] The first switch T1 can be connected between the bit line BL, which is connected to the memory cell, and the first node CSO.

[0101] The first pre-charge circuit 410 can be connected to the bit line BL via the first switch T1. The first pre-charge circuit 410 can respond to the first pre-charge signal SA_PRECH_N. <x>The first node, CSO, is pre-charged.

[0102] In the implementation, the first precharge signal SA_PRECH_N <x>It can be the first precharge signal SA_PRECH_N input to the even-numbered page buffer. <even>Alternatively, the first precharge signal SA_PRECH_N input to the odd-page buffer. <odd>.

[0103] In this implementation, the first precharge signal SA_PRECH_N input to the even-numbered page buffer can be determined based on the common precharge signal SA_PRECH and the even-numbered page buffer control signal PB_EVENDISABLE. <even>The first precharge signal SA_PRECH_N input to the odd-page buffer can be determined based on the common precharge signal SA_PRECH and the odd-page buffer control signal PB_ODDDISABLE. <odd>.

[0104] The second pre-charge circuit 420 can be connected to the bit line BL via the first switch T1. The second pre-charge circuit 420 can pre-charge the first node CSO in response to the second pre-charge signal SA_CSOC2.

[0105] In the implementation, when the first precharge signal SA_PRECH_N <x>When enabled, the second precharge signal SA_CSOC2 can be disabled. When the first precharge signal SA_PRECH_N is enabled... <x>When disabled, the second precharge signal SA_CSOC2 can be enabled.

[0106] exist Figure 7 The description is based on the assumption that an even number read operation is performed.

[0107] References above Figure 5 Unlike the page buffer 300 described, the first precharge signal SA_PRECH_N is input to the even-numbered page buffer. <even>and the first precharge signal SA_PRECH_N input to the odd-page buffer <odd>They can be distinguished from each other.

[0108] In the implementation, when the precharge signal SA_PRECH_N is input to the even-numbered page buffer... <even>When enabled, the precharge signal SA_PRECH_N is input to the odd-page buffer. <odd>It can be disabled. When the precharge signal SA_PRECH_N is input to the odd-page buffer... <odd>When enabled, the precharge signal SA_PRECH_N is input to the even-numbered page buffer. <even>It can be disabled.

[0109] Due to the precharge signal SA_PRECH_N during even-number read operations. <even>When enabled, the first precharge circuit 410 of the even-numbered page buffer can respond to the precharge signal SA_PRECH_N. <even>The first node CSO of the even-numbered page buffer is precharged. The path for precharging the bit line BL of the even-numbered page buffer via this path is similar to the above reference. Figure 5 The first pre-charge path described is the same.

[0110] Since the second precharge signal SA_CSOC2 of the even-numbered page buffer is disabled during even-numbered read operations, the second precharge circuit 420 can not affect the first node CSO of the even-numbered page buffer.

[0111] Due to the precharge signal SA_PRECH_N during even-number read operations. <odd>Since it is disabled, the first precharge circuit 410 of the odd-page buffer can remain unaffected by the first node CSO of the odd-page buffer.

[0112] Because the second precharge signal SA_CSOC2 of the odd-page buffer is enabled during even-number read operations, the second precharge circuit 420 of the odd-page buffer can precharge the first node CSO of the odd-page buffer. The path for precharging the bit line BL of the odd-page buffer can be the same as the second precharge path (BL precharge path 2).

[0113] In the implementation, odd number read operations are performed in the same manner as even number read operations.

[0114] Figure 8A This is an example of a selected memory cell that is connected to which a memory operation is performed. Figure 7 The timing diagram for the operation of the page buffer.

[0115] Reference Figure 8A When the memory operation is an even-numbered read operation, the operation of the even-numbered page buffer connected to the even-numbered memory cell that is the selected memory cell can be performed. An even-numbered read operation may include a bit line precharge operation (from t1' to t2'), an evaluation operation (from t2' to t4'), and a latch operation (not shown).

[0116] During even-numbered read operations, the second precharge signal SA_CSOC2 of the even-numbered page buffer can be disabled.

[0117] During the bit line precharge operation, the first precharge signal SA_PRECH_N of the even-numbered page buffer is... <even>It can be enabled, and the first node CSO can be precharged to voltage VCSO2 via the first precharge circuit of the even-numbered page buffer. Because the control signal PB_SENSE of the first switch is enabled, and then the first node CSO is connected to the bit line BL, the bit line BL can be precharged to voltage VBL2.

[0118] In the implementation method, the above references Figure 7 The even-page buffer control signal PB_EVENDISABLE, as described, can be disabled during bit-line precharge operation and can be enabled during evaluation operation.

[0119] During the evaluation operation, the first precharge signal SA_PRECH_N of the even-numbered page buffer... <even>It can be disabled.

[0120] During evaluation, the voltage of bit line BL can be determined based on the threshold voltage of the even-numbered memory cells. When the threshold voltage of the even-numbered memory cells is lower than the read voltage, the even-numbered memory cells are on-cells, and therefore bit line current can flow through the memory cells, and the voltage of bit line BL can be discharged. When the threshold voltage of the even-numbered memory cells is equal to or higher than the read voltage, the memory cells are off-cells, and therefore, bit line current does not flow through the memory cells, and the voltage of bit line BL can be maintained at voltage VBL2.

[0121] In one implementation, when the page buffer is connected to a programmed cell in an even-numbered memory cell via bit line BL, the first node CSO can be maintained at a pre-charge voltage VCSO2 during evaluation operations. When the page buffer is connected to an erased cell in an even-numbered memory cell via bit line BL, the voltage of the first node CSO can be discharged during evaluation operations.

[0122] Figure 8B This is an example of a memory cell, such as one that is connected to an unselected memory cell to which no memory operation is performed. Figure 7 The timing diagram for the operation of the page buffer.

[0123] Reference Figure 8B When a memory operation is an even-number read operation, the operation of the odd-number page buffer connected to the odd-number memory cell that is not selected can be performed. An even-number read operation may include a bit-line precharge operation (from t1” to t2”), an evaluation operation (from t2” to t4”), and a latch operation (not shown).

[0124] During even-numbered read operations, the first precharge signal SA_PRECH_N of the odd-numbered page buffer is used. <odd>It can be disabled. During even-numbered read operations, the second precharge signal SA_CSOC2 for the odd-numbered page buffer can be enabled.

[0125] Since the second precharge signal SA_CSOC2 of the odd-page buffer is enabled during the bit line precharge operation, the first node CSO can be precharged to voltage VCSO3 via the second precharge circuit of the odd-page buffer. Because the control signal PB_SENSE of the first switch is enabled and then the first node CSO is connected to the bit line BL, the bit line BL can be precharged to voltage VBL3.

[0126] In the implementation method, during even-number read operations, the above references Figure 7 The odd-page buffer control signal PB_ODDDISABLE, as described, can be enabled.

[0127] Since the second precharge signal SA_CSOC2 of the odd-page buffer remains enabled during the evaluation operation, the voltage of the first node CSO can continue to be maintained at voltage VCSO3.

[0128] Therefore, during an even-number read operation, the potential of the first node CSO can be clamped to a constant voltage VCSO3. Because the voltage of the first node CSO is clamped, there is no voltage change in the first node CSO (CSO swing X), and the voltage of the bit line BL can be maintained at VBL3 without causing a voltage drop (BL drop X). During even-number read operations, the voltage of the odd-numbered bit lines adjacent to the even-numbered bit lines can be maintained at a constant level, and the effects of interference caused by bit line coupling can be minimized.

[0129] In this implementation, the voltage at which the first node CSO is precharged during the bit line precharge operation can be set such that voltage VCSO3 is less than or equal to Figure 6 The voltage shown is VCSO1.

[0130] For reference Figure 8B As mentioned above, in order to eliminate voltage variations (CSO oscillations) in the first node CSO, referencing the above... Figure 5 The page buffer 300 described is different; refer to the above. Figure 7 The page buffer 400 described may also include a second precharge circuit 420.

[0131] The same first precharge signal can be input to the first precharge circuit 310 of the page buffer 300, regardless of whether the corresponding page buffer is an even-numbered or odd-numbered page buffer. In contrast, different first precharge signals SA_PRECH_N can be used for even-numbered and odd-numbered page buffers. <even>and SA_PRECH_N <odd>Separate input to Figure 7 The first precharge circuit 410 of the page buffer 400.

[0132] Figure 9 This is a flowchart illustrating the operation of a memory device according to an embodiment.

[0133] Reference Figure 9 In operation S901, the memory device can perform a bit line precharge operation to precharge the first bit line of the first memory cell connected to a plurality of memory cells to a first voltage.

[0134] During operation S903, the memory device can precharge the second bit line of the second memory cell connected to one of the plurality of memory cells to the second voltage during the bit line precharge operation.

[0135] In operation S905, the memory device can perform an evaluation operation after the bit line precharge operation to sense the voltage of the first bit line determined based on the threshold voltage of the first memory cell.

[0136] During operation S907, the memory device can clamp the potential of the second bit line to a second voltage during evaluation operation.

[0137] In one implementation, the first bit can be an even number of bit lines, and the second bit can be an odd number of bit lines.

[0138] According to this disclosure, an improved bit-line coupled memory device and a method for operating the memory device are provided.

[0139] While the invention has been shown and described in conjunction with various embodiments, those skilled in the art will understand from this disclosure that various modifications consistent with the teachings can be made to any of the disclosed embodiments. Therefore, the invention covers all modifications falling within the scope of the claims.

[0140] Cross-references to related applications

[0141] This application claims priority to Korean Patent Application No. 10-2020-0094267, filed on July 29, 2020, the entire contents of which are incorporated herein by reference.< / odd> < / even> < / odd> < / even> < / even> < / odd> < / even> < / even> < / even> < / odd> < / odd> < / even> < / odd> < / even> < / x> < / x> < / odd> < / even> < / odd> < / even> < / x> < / x>

Claims

1. A memory device, comprising: a plurality of memory cells; and a plurality of page buffers coupled to the plurality of memory cells by a plurality of bit lines, wherein the plurality of page buffers: perform a bit line pre-charge operation to pre-charge a first bit line coupled to a first memory cell among the plurality of memory cells to a first voltage, the bit line pre-charge operation being included in a memory operation to detect a threshold voltage of the first memory cell, and clamp a potential of a second bit line coupled to a second memory cell among the plurality of memory cells to a second voltage during the memory operation, for which the memory operation is not performed.

2. The memory device of claim 1, wherein, each of the plurality of page buffers comprises: a first pre-charge circuit to pre-charge a node coupled to a respective bit line by a switch to pre-charge the respective bit line to the first voltage in response to a first pre-charge signal; and a second pre-charge circuit to pre-charge the node to clamp a potential of the respective bit line to the second voltage in response to a second pre-charge signal.

3. The memory device of claim 2, wherein, the page buffers comprise: a first page buffer coupled to the first bit line; and a second page buffer coupled to the second bit line.

4. The memory device of claim 3, wherein: each of the first page buffers pre-charges a respective bit line among the first bit lines to the first voltage by a first pre-charge path, and each of the second page buffers clamps a potential of a respective bit line among the second bit lines to the second voltage by a second pre-charge path different from the first pre-charge path.

5. The memory device of claim 4, wherein: a first pre-charge signal provided to the first page buffers is enabled, and a second pre-charge signal provided to the first page buffers is disabled, and a second pre-charge signal provided to the second page buffers is enabled, and a first pre-charge signal provided to the second page buffers is disabled.

6. The memory device of claim 3, wherein, the memory operation comprises the bit line pre-charge operation and an evaluation operation to sense a potential of the first bit line determined from the threshold voltage of the first memory cell.

7. The memory device of claim 6, wherein, the second pre-charge circuit in each of the second page buffers: pre-charges the node of a respective second page buffer to a third voltage during the bit line pre-charge operation, and clamps a potential of the node of the respective second page buffer to the third voltage during the evaluation operation.

8. The memory device of claim 7, wherein, the first pre-charge circuit in each of the first page buffers pre-charges the node of a respective first page buffer to a fourth voltage during the bit line pre-charge operation.

9. The memory device of claim 8, wherein, the third voltage is lower than or equal to the fourth voltage.

10. The memory device of claim 3, wherein, during the memory operation, the first pre-charge signal provided to the second page buffers is disabled, and the second pre-charge signal provided to the second page buffers is enabled.

11. The memory device of claim 1, wherein, the first bit lines are disposed alternately with respect to the second bit lines.

12. The memory device of claim 1, wherein, The memory operation is a read operation or a program verify operation performed on the first memory cell.

13. A page buffer, the page buffer comprising: a switch coupled between a bit line and a node; a first pre-charge circuit coupled between the node and a supply voltage node and to pre-charge the node to a first voltage based on a memory cell coupled to the bit line being a selected memory cell on which a memory operation is performed; and a second pre-charge circuit coupled between the node and the supply voltage node and to clamp a potential of the node to a second voltage based on the memory cell not being the selected memory cell.

14. The page buffer of claim 13, wherein, The second pre-charge circuit clamps the potential of the node to the second voltage when the memory cell is an unselected memory cell on which the memory operation is not performed.

15. The page buffer of claim 14, wherein, The memory operation includes a bit line pre-charge operation to pre-charge the node to the first voltage and an evaluation operation to sense a potential of the bit line determined from a threshold voltage of the memory cell when the memory cell is the selected memory cell.

16. The page buffer of claim 15, wherein, The second pre-charge circuit pre-charges the node to the second voltage during the bit line pre-charge operation and clamps the potential of the node to the second voltage during the evaluation operation when the memory cell is the unselected memory cell.

17. The page buffer of claim 13, wherein, The second voltage is less than or equal to the first voltage.

18. The page buffer of claim 13, wherein, The memory operation is a read operation or a program verify operation performed on the first memory cell.

19. A method of operating a memory device including a plurality of memory cells, the method comprising: performing a bit line pre-charge operation to pre-charge a first bit line coupled to a first memory cell among the plurality of memory cells to a first voltage; pre-charging a second bit line coupled to a second memory cell among the plurality of memory cells to a second voltage during the bit line pre-charge operation; performing an evaluation operation to sense a voltage of the first bit line determined from a threshold voltage of the first memory cell after the bit line pre-charge operation; and clamping a potential of the second bit line to the second voltage during the evaluation operation, wherein the first memory cell is a selected memory cell on which a memory operation including the bit line pre-charge operation and the evaluation operation is performed and the second memory cell is not the selected memory cell. The first bit line is alternately arranged with respect to the second bit line.

20. The method of claim 19, wherein, ​

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