Temperature interpolation technique for multiple integrated circuit references

Abstract

This application relates to temperature interpolation techniques for multiple integrated circuit references. Techniques are provided for providing temperature trim codes to multiple reference circuits of an integrated circuit. In an example, a string of primary latch circuits can provide a set of predefined temperature trim codes to a multiplexer in response to a token of a series of tokens. The multiplexer can provide two of the trim codes to an interpolator based on a temperature reading of the integrated circuit. The interpolator can provide an interpolated trim code and the trim code can be distributed to the reference circuits based on the token.

Description

TECHNICAL FIELD

[0001] Embodiments described herein generally relate to integrated circuits (ICs), and more specifically, to trimming a voltage reference of an IC based on temperature. SUMMARY

[0002] In one aspect, the present application provides a temperature trimming architecture for an integrated circuit (IC), the architecture comprising: a string of primary latches configured to pass a set of pre-programmed trimming codes to an output of the string, the set of pre-programmed trimming codes based on a first token received at each of the primary latches in the string; a multiplexer coupled to the output of the string, the multiplexer configured to receive a temperature measurement and to pass at least two temperature trimming codes of the set of pre-programmed trimming codes to an output of the multiplexer; and an interpolator configured to receive the at least two temperature trimming codes and to interpolate a first output trimming code based on the temperature measurement and the at least two trimming codes.

[0003] In another aspect, the present application further provides a circuit comprising: a token generator configured to provide a series of tokens generated in series; a plurality of primary latches each associated with a respective reference circuit of a plurality of reference circuits, arranged in a sequential chain, wherein a first primary latch of the plurality of primary latches is configured to pass a first set of predetermined temperature trimming codes to an output of the first primary latch in response to a first token of the series of tokens generated in series, the first set corresponding to a first respective reference circuit of the plurality of reference circuits, and to pass a second set of predetermined trimming codes received from a previous primary latch of the sequential chain to the output of the first primary latch in response to a second token of the series of tokens generated in series; a multiplexer coupled to the output of a last primary latch of the sequential chain, the multiplexer configured to receive a temperature measurement and to pass at least two temperature trimming codes of the first set of predetermined temperature trimming codes to an output of the multiplexer; and an interpolator configured to receive the at least two temperature trimming codes and to interpolate an output trimming code based on the temperature measurement and the at least two trimming codes.

[0004] In yet another aspect, the present application further provides a method comprising: serially generating a series of tokens; receiving the series of tokens at a plurality of latches serially connected to inputs of a multiplexer; in response to a first token of the series of tokens, serially passing a first stored temperature trimming code of a first latch of the plurality of latches to the inputs of the multiplexer via at least one other latch of the plurality of latches; passing two temperature trimming codes of the first stored trimming code to an output of the multiplexer in response to a temperature measurement; and interpolating a first reference trimming code from the two temperature trimming codes. BACKGROUND

[0005] Voltage or current references and associated circuitry for generating the reference are common components of integrated circuits (ICs). An individual IC can have multiple reference circuits. The operation and accuracy or resolution of a particular IC can depend on a particular level provided by a reference circuit. Temperature is an environmental condition that can cause a reference level to drift from an intended reference level. Conventional techniques for compensating a reference level based on temperature can include storing temperature trim values or temperature trim codes in a non-volatile memory indexed, for example, by temperature over a range of temperatures. An IC can include a temperature sensor or can receive an indication of an ambient temperature of the IC and can interpolate a trim code to apply to a reference circuit based on, for example, two stored trim codes associated with temperature indices closest to the indicated temperature. The interpolated trim code can then be applied to the reference circuit to adjust the reference level to the intended reference level. Application of a trim code to adjust a reference circuit can be implemented in several ways known to those of skill in the art.

[0006] Memory devices are but one of many types of ICs that can include multiple reference circuits. Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory requires power to maintain its data and includes various forms of random access memory (RAM) such as dynamic random access memory (DRAM) or synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered (may be implemented in some cases as read only memory (ROM)) and can include one or more storage technologies such as flash memory (e.g., NAND or NOR flash), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), ferroelectric RAM (FeRAM), erasable programmable ROM (EPROM), resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or 3D XPoint™ memory, among others.

[0007] Flash memory is used as non-volatile memory for a wide range of electronic applications. Flash memory devices typically include one or more groups of single transistor floating gate or charge trap memory cells that allow for high memory density, high reliability, and low power consumption. Two common types of flash memory array architectures include NAND and NOR architectures, named in the logical form in which the basic memory cell configuration of each is arranged. Memory cells of a memory array are typically arranged in a matrix. In an example, the gate of each floating gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drains of each memory cell in a string of the array are coupled together in a source-to-drain fashion between a source line and a bit line.

[0008] The accuracy and reliability of memory circuits, as well as other types of ICs, can depend on precise reference levels. However, conventional techniques for temperature-compensated reference levels employ interpolator circuits and a number of local latches for providing each reference circuit on an IC. Such temperature compensation schemes occupy a large amount of resources and area of the IC. BRIEF DESCRIPTION OF DRAWINGS

[0009] In the drawings, which are not necessarily drawn to scale, like numerals can describe similar components in different views. Like numerals having different letter suffixes can represent different instances of the components. The drawings illustrate generally, by way of example, various embodiments discussed in the present document.

[0010] Figure 1 A block diagram generally illustrating an example integrated circuit (IC) is shown.

[0011] Figure 2 A block diagram generally illustrating a temperature trim code architecture for a multi-reference IC is shown.

[0012] Figure 3 An example primary latch circuit in accordance with the subject matter of the present disclosure is generally shown.

[0013] Figure 4 An example local latch circuit and corresponding reference circuit are generally shown.

[0014] Figure 5 A method of operating a temperature trim architecture including serially connected primary latch circuits is generally shown.

[0015] Figure 6 A block diagram of an example machine upon which any one or more of the temperature trim techniques (e.g., methods) discussed herein can be performed is shown. DETAILED DESCRIPTION

[0016] Figure 1 This section provides a general block diagram of example integrated circuit (IC) 100. IC 100 may include several reference circuits (Ref1, Ref2, Ref3, ..., Ref...). n The IC 100 includes a temperature sensor 101 and a trimming circuit 102. The IC 100 may contain other circuitry specific to the functions performed by the IC 100, but those circuits are not included in the above description. Figure 1 As shown in the diagram. In some instances, IC100 may be a memory device, but the subject matter of this invention is not limited thereto. Reference circuits (Ref1, Ref2, Ref3, ..., Ref... n The reference level can provide certain operating characteristics to assist the operation of IC 100. Such operating characteristics may include, but are not limited to, supply voltage, supply current, reference voltage, and reference current. In some instances, the consistency of the levels of the operating characteristics can determine the performance limits of IC 100. Temperature changes can affect the levels of many operating characteristics of IC 100 and can cause the reference level to drift from the desired level. Alternatively, a temperature slope on the reference level may be desired. One method of temperature compensation is to dynamically trim each individual reference circuit based on a representation of the ambient temperature provided by the temperature sensor 101 of IC 100. A common method for dynamic temperature compensation trimming may involve adjusting the reference circuit based on the temperature of each reference circuit (Ref1, Ref2, Ref3, ..., Ref...) for IC 100. n The circuit test stores predetermined trimming codes. The set of predetermined trimming codes for a reference circuit can contain multiple multi-bit codes indexed by temperature. The predetermined trimming codes can be programmed into the broadcast block of the production non-volatile register, main latch, or fuse register to become pre-programmed temperature trimming codes. After IC startup, the trimming codes for each reference circuit can be transferred from the broadcast block to the local latch near the corresponding reference circuit. When IC 100 operates, and in each reference circuit (Ref1, Ref2, Ref3, ..., Ref...),... n After receiving a temperature reading from temperature sensor 101, the local interpolator circuit can receive two predetermined trimming codes associated with the temperature closest to the temperature reading and can interpolate the values ​​that can be passed to the corresponding reference circuits (Ref1, Ref2, Ref3, ..., Ref...). n The final trimming code of the trimming circuit system. As an example, for an IC containing 6 reference circuits and capable of storing 21 predetermined 6-bit trimming codes for each reference circuit, the temperature trimming compensation architecture can include a broadcast block, 736 local latches, 6 multiplexers (e.g., 21:2 multiplexers), 6 interpolators, and can occupy approximately 48,000 μm of the IC.2 area.

[0017] The present inventors have recognized techniques that can significantly reduce the size of a temperature trim architecture for a multi-reference IC without significantly reducing the performance of the reference circuit trim functions. Additionally, example architectures allow for very clean integration of additional reference circuits. Figure 2 A block diagram of a temperature trim code architecture 202 for a multi-reference IC is generally illustrated. For simplicity, the block diagram of the temperature trim code architecture 202 does not include the reference circuits or the actual trim circuitry for the reference circuits, but does indicate how the interpolated temperature trim code can be distributed to local latches at each of the reference circuits. In certain examples, the temperature trim code architecture 202 can include or be coupled to the temperature sensor 101. The temperature trim code architecture 202 can include a token generator 203, a string 204 of a plurality of primary latch circuits (TC x ), a multiplexer 205, and an interpolator 206. In some examples, a single IC, such as a memory IC, can include the above-described components of a temperature trim code architecture, a plurality of reference circuits, and local latch circuitry for each reference circuit. In certain examples, the memory IC can include, but is not limited to, a flash memory, an EPROM, an EEPROM, an SRAM, a FeRAM, a resistance variable memory, such as a PCRAM, a RRAM, an MRAM, or a 3D XPoint™ memory, among others.

[0018] The temperature sensor 101 can take periodic measurements of the temperature of the IC and can digitize the measurements to provide a temperature measurement reading (TEMP). In certain examples, the temperature sensor 101 can include a strobe (DN) to indicate when the temperature measurement reading (TEMP) is updated. The temperature measurement reading (TEMP) can include a multi-bit representation of the temperature measured by the temperature sensor 101.

[0019] The token generator (TG) 203 can be triggered by the strobe (DN) of the temperature sensor 101 or by some other signal, such as a clock or oscillator signal. In certain examples, upon the trigger signal, the token generator 203 can generate and output one or more individual tokens. A given token can be associated with one of the plurality of reference circuits. In certain examples, a single token in a sequence of tokens can be generated on the trigger signal. In some examples, a series of tokens can be generated serially upon receipt of the trigger signal. As discussed below, each token can initiate the provision of a temperature trim code to a respective reference circuit.

[0020] The plurality of primary latch circuits (TC xThe string 204 of primary latch circuits (TC x ) includes a plurality of temperature trim codes. Each temperature trim code of an individual primary latch circuit can correspond to a particular temperature. In certain examples, the temperature trim codes are indexed by a code representing a particular temperature. As an example, each primary latch circuit can include 21 temperature trim codes for a particular reference circuit (e.g., n = 21). As an example, the 21 temperature trim codes can correspond to every 8 degree temperature value from -40 °C to +120 °C. The 21 temperature trim codes of each primary latch circuit or each preprogrammed set of temperature trim codes can be programmed during testing of the IC and each preprogrammed set of temperature trim codes can be specific to the corresponding reference circuit.

[0021] In addition to the preprogrammed set of temperature trim codes, each primary latch circuit can include logic responsive to a token and responsive to an input received from a preceding primary latch circuit of the string 204 of primary latch circuits, for example. For a given token, one primary latch circuit (TC x ) can pass its own preprogrammed set of temperature trim codes to the output of one primary latch circuit. For that same given token, all other primary latch circuits (TC x ) can pass through the input received from the immediately preceding primary latch circuit (TC x ) of the string 204 of primary latch circuits. Thus, for a given token, a single preprogrammed set of temperature trim codes is passed to the input of the multiplexer 205. The terminal primary latch circuit (e.g., TC0) within the string of primary latch circuits furthest from the multiplexer can terminate its input in an inactive state.

[0022] The multiplexer 205 can receive the preprogrammed set of temperature trim codes discussed above from the string 204 of primary latch circuits (TC x ) and receive a digital representation of the measured temperature (TEMP) from the temperature sensor 101. Using both of these inputs, the multiplexer 205 can pass two preprogrammed temperature trim codes closest to the received digital representation of the measured temperature (TEMP) to the interpolator 206. In certain examples, the multiplexer 205 can receive a strobe (DN) from the temperature sensor 101 and can update the multiplexer output on the condition of a particular translation of the strobe or a particular level of the strobe, for example. In certain examples, such conditioning of the strobe to the temperature sensor can ensure that the representation of the measured temperature (TEMP) is valid.

[0023] The interpolator 206 can receive the two temperature trim codes provided from the output of the multiplexer 205 and can generate a single trim code for a reference circuit corresponding to a given token. In certain instances, the interpolator interpolates the single trim code using a conventional interpolation algorithm. In some instances, for example when the trim codes of the measured temperatures and represent at least 5 bits in length, the interpolation can be performed according to the following algorithm or formula:

[0024] ,

[0025] where Tc A and Tc B are preprogrammed trim codes received at the interpolator 206 and Tc C is the single trim code generated by the interpolator 206. Following the generation of the single trim code by the interpolator 206, the single trim code can be distributed to a local latch circuit at, near or associated with the corresponding reference circuit.

[0026] In certain instances, the output of the interpolator 206 can be routed to a second multiplexer (not shown) and distributed to the corresponding reference circuit via a dedicated bus based on the given token. In some instances, the output of the interpolator 206 can be a bus common to the local latches associated with the reference circuits and the trim code can be received by the appropriate local latch based on the given token which can also be placed on the common bus. In some instances, the output of the interpolator 206 can be routed to a serial communication bus controller and the trim code and given token can be broadcast on a serial communication bus coupled to the local latches.

[0027] Figure 3 An example primary latch circuit (Tc i ) according to the subject matter of the present application is generally illustrated, where 0 <= i <= n. For simplicity, the example primary latch circuit (Tc i ) illustrates a 2-bit trim code (temperature code X; 0 <= X <= M) or only two bits (e.g., bit 0, bit 1) of a larger bit count trim code. It should be understood that a complex circuit generally employs more than four bits of trim code. The primary latch circuit (Tc i ) can include a latch array 310, an AND gate circuit 311, an OR gate circuit 312, and a token detection circuit 313. The primary latch circuit (Tc i) can include a first input interface 314 and an output interface 315. Each of the first input interface 314 and the output interface 315 can have a width equal to the product of the number of preprogrammed temperature codes within a preprogrammed set of temperature trim codes and the number of bits in the preprogrammed trim codes. For example, if each set of predetermined trim codes includes 21 codes, and each code is six bits wide, then the first input interface 314 and the output interface 315 can be at least 126 bits wide. The first input interface 314 is generally connected to the output interface of an adjacent primary latch circuit (TC i-1 ). The output interface 315 is generally connected to the first input interface of a second adjacent primary latch circuit (TC i+1 ). If the primary latch circuit (TC i ) is a terminal primary latch circuit located farthest from the multiplexer with respect to the string of primary latch circuits (e.g., i = 0), then the first input interface 314 can terminate in an inactive state. If the primary latch circuit (TC i ) is a terminal primary latch circuit located closest to the multiplexer with respect to the string of primary latch circuits (e.g., i = n), then the output interface 315 can be coupled to an input of the multiplexer. The primary latch circuit (TC i ) can also have a second input interface coupled to the token generator for receiving a token.

[0028] As discussed above, during testing of the IC, the primary latches can be programmed with a temperature trim code (TEMP CODE x) specific to the corresponding reference circuit. Each primary latch circuit can include one or more test mode control inputs (TST EN ) and test mode data inputs (TST DATA ) to assist in preprogramming the temperature trim code (TEST CODE x). It should be understood that other techniques for preprogramming each primary latch circuit are possible without departing from the scope of the subject matter. The preprogrammed temperature trim code (Temp Code x) can be stored by some type of memory, for example, types of non-volatile memory including, but not limited to, programmable fuses, non-volatile latches, etc.

[0029] During operation, the token generator can generate a series of recurring tokens and the temperature sensor can generate a representation of the measured temperature (TEMP). Each latch circuit can include a token reference (TKN i ) that identifies the individual primary latch circuit and optionally the reference circuit corresponding to the individual primary latch circuit. In certain examples, the token reference (TKN i ) can also be programmed using test modes. In certain examples, the token reference (TKN i) can be a numeric value. In some instances, the token reference (TKN) i The reference can be analog. Comparator 316 can compare the generated token (TKN) with the token reference (TKN). i It can also generate binary output indicating comparisons and token matching indicators.

[0030] AND gate 311 can use the output of comparator 316 to determine whether to pass the pre-programmed temperature trimming code set to the main latch circuit (TC). i Output interface 315. If the generated token (TKN) is equal to the token reference (TKN) i If the value of each bit latch containing the pre-programmed temperature trimming code set can be passed by AND gate 311.

[0031] OR gate 312 sets the current main latch circuit (TC) i The output interface 315 displays the value of each temperature trimming bit. Generally, the OR gate 312 is used in conjunction with the main latch circuit (TC). i-1 The output bit of the current main latch circuit (TC) i The AND gated bits of the main latch are ORed. The resulting token (TKN) is equal to any previous reference token (TKN) in the main latch chain. x The main latch circuit (TC) was in operation before this time. i-1 The output of ) can be active. If the generated token (TKN) does not match any reference token (TKN) of the previous main latch circuit. x ), then the current main latch circuit (TC) i The state of the bit of the first input interface 314 can be inactive. If the currently generated token (TKN) is not equal to the current main latch circuit (TC)... i Reference token (TKN) i ), then the current main latch circuit (TC) i The state of the bit at the output interface 315 can also be inactive. If the currently generated token (TKN) equals the current main latch (TC)... i Reference token (TKN) i ), then the current main latch circuit (TC) i The state of bit 315 of the output interface can be set to the current main latch circuit (TC). i The state of the bits in a preprogrammed temperature trimming code set. Figure 3The active state can be a state in which all bits of the interface are driven to a low logic level, and the inactive state is a state in which at least some of the bits of the interface are not driven to a high logic level. It should be understood that the combination of logic gates and signal levels for the active and inactive states can differ from the illustrated example and not depart from the scope of the subject matter.

[0032] An example trim code architecture according to the subject matter of the present application that allows for a serial connection of a string of primary latch circuits can employ a single N:2 multiplexer and a single interpolator to generate individual temperature trim codes to a plurality of reference circuits. Thus, the example trim architecture can save a significant amount of IC area and peak power, as only a single N:2 multiplexer and a single interpolator consume peak energy at any point in time as compared to the potential for all multiplexers and all interpolators of conventional technology to consume peak energy at the same time.

[0033] Figure 4 An example of a local latch circuit 420 and a corresponding reference circuit 421 is generally illustrated. The local latch circuit 420 can include a plurality of individual latches 422, such as D-type latches, and control logic 423. The plurality of individual latches 422 can hold bit values of an interpolated temperature trim code received from the interpolator. In addition, once loaded, the plurality of individual latches 422 can output the interpolated temperature trim code to the corresponding reference circuit 421, such as a voltage reference circuit, to provide a reference voltage (VREF i ) based on the interpolated temperature trim code. In some examples, each latch 422 can have a programmable default reset value in order to allow each reference circuit 421 to receive an individual default temperature trim code when needed, such as at startup or during a fault condition. In the illustrated example, the control logic 423 can include a delay circuit (DELAY) and can be responsive to a control signal received from the interpolator or a corresponding primary latch circuit. The control logic 423 can coordinate loading of the individual latch circuits 422 and provide an indication to the reference circuit 421 when the trim code is valid or when the trim code has changed. Figure 4 The illustrated example of FIG. 4 assumes that the signals generated at the interpolator include an interpolated temperature trim code for each local latch circuit 420 and an individual control signal (e.g., CLK). The control signal for a given local latch can be activated based on a token associated with the corresponding primary latch circuit.

[0034] It should be understood Figure 4 that the example of FIG. 4 is only one of many examples for distributing an interpolated temperature trim code to local latch circuits 420 and corresponding reference circuits 421, and other distribution techniques are possible without departing from the scope of the subject matter. For example, instead of providing an individual control signal for each local latch circuit 420 to control the local latches 422 and a ready indication (T_RDYi ) of the interpolator, the interpolator can provide a token value (TKN) on a general purpose bus to each local latch circuit 420 and the control logic 423 of each local latch circuit 420 can compare the token to a token reference at each local latch circuit 420 to initiate and control loading of the new temperature trim code into the local latch 422. As an alternative, the local latch circuits 420 can be connected on a serial bus, the interpolator can include a serializer, and each of the local latch circuits 420 can include a parallelizer. After interpolating the temperature trim code, the interpolator can transmit the interpolated temperature trim code and the token via the serial bus. The control logic 423 of each local latch circuit 420 can receive each communication from the interpolator and parallelize each communication and can determine whether the re-serialized token equals the token reference of the local latch circuit 420. When the token received with the serially transmitted interpolated temperature trim code matches the token reference, the control logic 423 can load the new interpolated trim code into the local latch 422 and the control logic 423 can generate a trim ready indication (T_RDY i ) for the corresponding reference circuit 421 when the new trim code (TRIM i ) is valid. When the token received with the serially transmitted interpolated temperature trim code does not match the token reference, the associated trim code can be ignored by that local latch circuit.

[0035] Figure 5 A method of operating a temperature trim architecture including serially connected primary latch circuits is generally described. At 501, a series of tokens can be generated. In certain examples, the generation of the tokens can be initiated by a signal received from a temperature sensor indicating that the temperature sensor has valid temperature data available. In some examples, the generation of the tokens can be initiated by a clock. At 503, the tokens can be received at each of a plurality of serially connected primary latch circuits. The chain of serially connected primary latch circuits can be connected to an input of a multiplexer. At 505, in response to a first token, a first set of preprogrammed temperature trim codes of a first latch circuit can be passed to the input of the multiplexer via at least one other latch circuit. At 507, an interpolator can pass two preprogrammed temperature trim codes of the first set to an output of the multiplexer based on a temperature reading of a temperature sensor. At 509, a first interpolated trim code can be interpolated from the two preprogrammed temperature trim codes. After completing the interpolation, at 511, the first interpolated trim code can be passed to a corresponding local latch associated with a corresponding reference circuit.

[0036] In certain examples, after interpolating the first interpolated temperature trim code, a second token can be generated and the method can continue. When a token corresponding to a last primary latch in the string of primary latches is generated, the last primary latch can pass its predetermined set of temperature trim codes directly to an input of the multiplexer without passing the set through one of the other primary latches in the serially connected string of primary latches. In certain examples, after an IC is launched with an example temperature trim architecture as discussed above, each local latch can pass a default trim code to the respective reference circuit. In certain examples, the individual default trim codes can be preprogrammed into each local latch.

[0037] In contrast to conventional trim architectures, the subject innovation uses a serial technique that can provide individualized interpolated temperature trim codes for multiple reference circuits of an IC using a single trim code set multiplexer and a single interpolator, can do so without sacrificing overall performance, can reduce IC area dedicated to providing temperature trim to reference circuits by as much as 70%, can add additional primary and local latches with minimal circuit changes, and can provide individualized default trim codes at each reference circuit.

[0038] Figure 6 A block diagram of an example machine 600 upon which any one or more of the temperature trim techniques (e.g., methods) discussed herein can be executed is illustrated. For example, any of the integrated circuits within the machine 600 (the main memory 604, the static memory 606, and the storage device (e.g., a mass storage device 608)) can implement the temperature trim techniques of the reference circuits as discussed herein with respect to Figures 1 to 5 In alternative embodiments, the machine 600 can operate as a standalone device or can be connected (e.g., networked) to other machines. In a networked deployment, the machine 600 can operate in the capacity of a server machine, a client machine, or both in server-client network environments. In an example, the machine 600 can act as a peer machine in peer-to-peer (P2P) (or other distributed) network environment. The machine 600 can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, an IoT device, an automotive system, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations.

[0039] Examples, as described herein, can include, or can operate by, logic, a component, device, package, or mechanism configured to provide a particular functionality. Circuitry is a collective term to describe the physical electronic components, such as simple circuits, gates, logic, etc., that collectively implement a complete module. Circuitry can be implemented in layers of different materials, such as semiconductor materials, conductive and non-conductive materials, etc. In examples, a hardware component can include a physical component, such as a transistor, resistor, inductor, etc., which can have well-defined boundaries that are not altered during operation, and therefore, are not variable. In examples, a hardware component can also include a programmable component, such as a processor, a programmable gate array, etc., which can be variable in nature, either by design or operation. For example, a programmable component can be capable of being programmed, reprogrammed, or otherwise changed to perform different tasks. In examples, a hardware component can include a combination of hard-coded and programmable components. In examples, a hardware component can include a combination of different types of hardware components, such as a combination of a physical component and a programmable component. In examples, a hardware component can include a combination of hardware components that are not necessarily physically combined, such as a combination of a physical component and a programmable component that are not physically combined.

[0040] A machine (e.g., computer system) 600 (e.g., a host device, a memory device, etc.) can include a hardware processor 602 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, e.g., a memory controller or the like), a main memory 604, and a static memory 606, some or all of which can communicate with one another via an interlink (e.g., bus) 630. The machine 600 can further include a display unit 610, an alphanumeric input device 612 (e.g., a keyboard), and a user interface (UI) navigation device 614 (e.g., a mouse). In an example, the display unit 610, input device 612 and UI navigation device 614 can be a touch screen display. The machine 600 can additionally include a storage device (e.g., drive unit) 608, a signal generation device 618 (e.g., a speaker), a network interface device 620, and one or more sensors 616, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. The machine 600 can include an output controller 628, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).

[0041] The storage device 608 can include a machine-readable medium 622 on which is stored one or more sets of data structures or instructions 624 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions 624 can also reside completely, or at least partially, within the main memory 604, static memory 606, or hardware processor 602 during execution thereof by the machine 600. In an example, one or any combination of the hardware processor 602, the main memory 604, the static memory 606, or the storage device 608 can constitute machine-readable media 622.

[0042] While the machine-readable medium 622 is illustrated as a single medium, the term "machine-readable medium" can include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store the one or more instructions 624.

[0043] The term "machine-readable medium" can include any medium that is capable of storing, encoding, or carrying instructions for execution by the machine 600 and that cause the machine 600 to perform any one or more of the techniques of the present disclosure, or that is capable of storing, encoding or carrying data structures used by or associated with such instructions. Non-limiting machine-readable medium examples can include solid-state memories, and optical and magnetic media. In an example, a massed machine-readable medium includes a plurality of particles en masse, having a fixed (e.g., static) mass. Thus, a massed machine-readable medium is not a transitory propagating signal. Particular examples of massed machine-readable media can include: non-volatile memory, such as semiconductor memory devices (e.g., Electrically Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0044] Instructions 624 (e.g., software, programs, operating system (OS), etc.) or other data are stored on mass storage device 608, which can be accessed by memory 604 for use by the processor 602. Memory 604 (e.g., DRAM) is typically fast, but volatile, and thus belongs to a different class of storage than mass storage device 608 (e.g., SSD), which is suitable for long-term storage, including long-term storage in "off' conditions. Instructions 624 or data for use by a user or the machine 600 are usually loaded in memory 604 for use by the processor 602. When memory 604 is full, virtual space from mass storage device 608 can be allocated to supplement memory 604; however, because mass storage device 608 is typically slower than memory 604 and write speeds are typically at least twice as slow as read speeds, the use of virtual memory can greatly degrade user experience due to storage device latencies (compared to memory 604, e.g., DRAM). Moreover, using mass storage device 608 for virtual memory can greatly shorten the usable life of mass storage device 608.

[0045] In contrast to virtual memory, virtual memory compression (e.g., Linux ® kernel feature "ZRAM") uses a portion of memory as compressed blocks to avoid paging to mass storage device 608. Paging occurs in compressed blocks until such data must be written to mass storage device 608. Virtual memory compression increases the available size of memory 604 while reducing wear on mass storage device 608.

[0046] Storage devices optimized for mobile electronic devices or mobile storage devices have traditionally included MMC solid-state storage devices (e.g., microSD™ cards). MMC devices contain several parallel interfaces (e.g., 8-bit parallel interfaces) with the host device and are typically removable and separate components from the host device. In contrast, eMMC™ devices are attached to a circuit board and treated as components of the host device, offering read speeds comparable to SSD devices based on Serial ATA™ (Serial Advanced Technology (AT) Attachment, or SATA). However, the increasing demand for mobile device performance to fully realize virtual or augmented reality devices, leverage increased network speeds, and so on, has led to a shift in storage devices from parallel to serial communication interfaces. Universal Flash Memory (UFS) devices, which include controllers and firmware, communicate with the host device using a Low Voltage Differential Signaling (LVDS) serial interface with dedicated read / write paths, further advancing read / write speeds.

[0047] The system can further utilize any of several transport protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.) to transmit or receive commands 624 on the communication network 626 via the network interface device 620 using the transport medium. Example communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), conventional telephone (POTS) networks, and wireless data networks (e.g., known as Wi-Fi). ® The Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards, known as WiMax ® This includes standards such as the IEEE 802.16 series, IEEE 802.15.4 series, peer-to-peer (P2P) networks, etc. In an example, network interface device 620 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to communication network 626. In an example, network interface device 620 may include multiple antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" should be considered as including any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 600, and including digital or analog communication signals or other intangible media to facilitate communication of such software.

[0048] Additional examples:

[0049] In a first example - Example 1, a temperature trim architecture for an integrated circuit (IC) can include a string of primary latch circuits configured to pass a set of preprogrammed trim codes to an output of the string, the set of preprogrammed trim codes based on a first token received at each of the primary latch circuits in the string; a multiplexer coupled to the output of the string, the multiplexer configured to receive a temperature measurement and to pass at least two temperature trim codes of the set of preprogrammed trim codes to an output of the multiplexer; and an interpolator configured to receive the at least two temperature trim codes and to interpolate a first output trim code based on the temperature measurement and the at least two trim codes.

[0050] In Example 2, the architecture of Example 1 optionally includes a plurality of local latch circuits, where a first local latch circuit of the plurality of local latch circuits is configured to receive the first output trim code from the interpolator.

[0051] In Example 3, the first local latch circuit of any one or more of Examples 1-2 is optionally configured to pass the first output trim code to a corresponding reference circuit.

[0052] In Example 4, the first local latch circuit of any one or more of Examples 1-3 optionally includes control circuitry configured to determine whether the first token corresponds to the first local latch circuit and a corresponding reference circuit coupled with the first local latch, to pass the first output trim code to the corresponding reference circuit when the first token corresponds to the corresponding reference circuit, and to not pass the first trim code when the first token does not correspond to the first local latch.

[0053] In Example 5, a first primary latch circuit of the string of primary latch circuits of any one or more of Examples 1-4 optionally includes a plurality of latches configured to store a set of preprogrammed temperature trim codes, and a token detection circuit configured to determine whether the first token corresponds to the first primary latch, to pass the set of preprogrammed temperature trim codes in response to the first token corresponding to the first primary latch, and to pass a state of an input interface of the first primary latch in response to the first token not corresponding to the first primary latch.

[0054] In Example 6, the token detection circuit of any one or more of Examples 1-5 optionally includes a first gate circuit configured to pass the set of preprogrammed temperature trim codes when the first token corresponds to the first primary latch, and to pass the state of the input interface when the first token does not correspond to the first primary latch circuit.

[0055] In Example 7, the token detection circuit of any one or more of Examples 1-6 optionally includes a second gate circuit configured to pass a set of preprogrammed temperature trim codes from a plurality of latches to the first gate circuit when the first token corresponds to the first primary latch, and not pass the set of preprogrammed temperature trim codes from the plurality of latches to the first gate circuit when the first token does not correspond to the first primary latch.

[0056] In Example 8, a circuit can include a token generator configured to provide serially generated tokens; a plurality of primary latch circuits each associated with a respective reference circuit of a plurality of reference circuits arranged in a sequential chain, wherein a first primary latch circuit of the plurality of primary latch circuits is configured to pass a first set of predetermined temperature trim codes to an output of the first primary latch circuit in response to a first token of the serially generated tokens, the first set corresponding to a first respective reference circuit of the plurality of reference circuits, and to pass a second set of predetermined trim codes received from a previous primary latch circuit of the sequential chain to the output of the first primary latch circuit in response to a second token of the serially generated tokens; a multiplexer coupled to an output of a last primary latch circuit of the sequential chain, the multiplexer configured to receive a temperature measurement and to pass at least two temperature trim codes of the first set of predetermined temperature trim codes to an output of the multiplexer; and an interpolator configured to receive the at least two temperature trim codes and to interpolate an output trim code based on the temperature measurement and the at least two trim codes.

[0057] In Example 9, the token generator of any one or more of Examples 1-8 is optionally configured to sequentially generate series of tokens, wherein each series of tokens includes a token configured to match a reference token of each latch circuit of the plurality of latch circuits.

[0058] In Example 10, the plurality of reference circuits of any one or more of Examples 1-9 optionally includes a plurality of voltage reference circuits.

[0059] In Example 11, each primary latch of any one or more of Examples 1-10 optionally includes a plurality of trim codes indexed by discrete temperatures in a range of temperatures.

[0060] In Example 12, each latch circuit of any one or more of Examples 1-11 optionally includes a first gate responsive to the serially generated tokens and a second gate responsive to an active output of a previous latch circuit.

[0061] In Example 13, the method can include: serially generating a series of tokens; receiving the series of tokens at a plurality of latch circuits serially connected to inputs of a multiplexer; in response to a first token in the series of tokens, serially passing, via at least one other latch circuit of the plurality of latch circuits, a first stored temperature trim code of a first latch circuit of the plurality of latch circuits to the inputs of the multiplexer; passing two temperature trim codes of the first stored trim code to an output of the multiplexer in response to the temperature measurement; and interpolating the first reference trim code from the two temperature trim codes.

[0062] In Example 14, the method of any one or more of Examples 1-2 optionally includes, in response to a second token in the series of tokens, serially passing a second stored temperature trim code of a second latch circuit of the plurality of latch circuits to the inputs of the multiplexer.

[0063] In Example 15, the method of any one or more of Examples 1-14 optionally includes, at the first reference circuit, optionally receiving the first reference trim code and trimming a first reference generated by the first reference circuit based on the first reference trim code.

[0064] In Example 16, the serially passing of the first stored temperature trim code of any one or more of Examples 1-15 optionally includes, prior to receiving the first token, deactivating outputs of latches of each of the plurality of latch circuits.

[0065] In Example 17, the serially passing of the first stored temperature trim code of any one or more of Examples 1-16 optionally includes: comparing the first token to a token reference of each of the plurality of latch circuits to provide a token match indication for each of the plurality of latch circuits, and ANDing the outputs of the latches of each of the plurality of latch circuits with the token match indication.

[0066] In Example 18, the serially passing of the first stored temperature trim code of any one or more of Examples 1-17 optionally includes ORing the outputs of the latches of all but one of the plurality of latch circuits with the output of a previous latch circuit of the serially coupled plurality of latch circuits.

[0067] In Example 19, the method of any one or more of Examples 1-18 optionally includes transmitting the first reference trim code to the plurality of reference circuits on a bus having a width commensurate with a width of the first reference trim code.

[0068] In Example 20, the method of any one or more of Examples 1-19 optionally includes transmitting the first reference trim code to the plurality of reference circuits on a bus having a width commensurate with a width of the first reference trim code and the tokens.

[0069] In Example 21, the method of any one or more of Examples 1-20 optionally includes transmitting the first reference trim code to the plurality of reference circuits over a serial communication bus.

[0070] Example 22 is at least one machine readable medium including instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of Examples 1-21.

[0071] Example 23 is an apparatus comprising means for implementing any of Examples 1-21.

[0072] Example 24 is a system for implementing any of Examples 1-21.

[0073] Example 25 is a method for implementing any of Examples 1-21.

[0074] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the application can be practiced. These embodiments are also referred to as "examples." Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0075] In this document, the terms "a" or "an" are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of "at least one" or "one or more." In this document, the term "or" is used to refer to a nonexclusive or, such that "A or B" can include "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein." Also, in the following claims, the terms "including" and "comprising" are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0076] In various examples, components, controllers, processors, units, engines, or tables described herein can include physical circuitry or firmware stored on a physical device, among other things. As used herein, "processor" means any type of computational circuit, such as, but not limited to, a microprocessor, microcontroller, graphics processor, digital signal processor (DSP), or any other type of processor or processing circuit, including groups of processors or multi-core devices.

[0077] The term "horizontal" as used in this document is defined as a plane parallel to the general plane or surface of a substrate, e.g., the general plane or surface underlying a wafer or die, regardless of the actual orientation of the substrate at any point in time. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Prepositions such as "on," "above," and "below" are defined relative to the top or exposed surface of the substrate with respect to the general plane or surface, regardless of the orientation of the substrate; and while "on" is intended to indicate direct contact of one structure relative to another structure it is "on" (in the absence of expressions to the contrary); the terms "above" and "below" are expressly intended to identify the relative placement of structures (or layers, features, etc.), which expressly includes, but is not limited to, direct contact between the identified structures, unless specifically so identified. Similarly, the terms "above" and "below" are not limited to horizontal orientations, as if a structure is the outermost portion of the construction at some point in time, such structure can be "above" or "below" a reference structure even if such structure extends vertically relative to the reference structure rather than in a horizontal orientation.

[0078] The terms "wafer" and "substrate" are used herein to generally refer to any structure upon which integrated circuitry is formed, and also to refer to such structures during various phases of integrated circuit fabrication. Thus, the following detailed description should not be construed to limit the scope of various embodiments, which is defined by the appended claims and their full range of equivalents.

[0079] Various embodiments described herein in accordance with the present disclosure include memory that utilizes vertical structures of memory cells (e.g., NAND strings of memory cells). As used herein, directional adjectives with respect to a surface of a substrate upon which memory cells are formed (i.e., a vertical structure will be considered to extend away from the substrate surface, a bottom end of a vertical structure will be considered to be the end closest to the substrate surface, and a top end of a vertical structure will be considered to be the end farthest from the substrate surface) will be employed.

[0080] As used herein, directional adjectives such as horizontal, vertical, orthogonal, parallel, perpendicular, etc. can refer to relative orientations and are not intended to require strict adherence to a particular geometric property unless otherwise indicated. For example, as used herein, a vertical structure need not be exactly perpendicular to a surface of a substrate, but can instead be generally perpendicular to a surface of a substrate and can form an acute angle (e.g., between 60 and 120 degrees, etc.) with a surface of a substrate.

[0081] As used herein, operating a memory cell includes reading from, writing to, or erasing the memory cell. An operation that places a memory cell in an intended state is referred to herein as “programming” and can include both writing to or erasing from the memory cell (e.g., a memory cell can be programmed to an erased state).

[0082] According to one or more embodiments of the present disclosure, a memory controller (e.g., a processor, a controller, firmware, etc.) located internal or external to a memory device can determine (e.g., select, set, adjust, calculate, change, clear, transfer, adapt, derive, define, utilize, modify, apply, etc.) an amount of wear cycles or a wear state (e.g., record wear cycles, count operations of the memory device as they occur, track operations of the memory device that initiate it, evaluate memory device characteristics corresponding to the wear state, etc.).

[0083] According to one or more embodiments of the present disclosure, a memory access device can be configured to provide wear cycle information to a memory device in connection with each memory operation. Memory device control circuitry (e.g., control logic) can be programmed to compensate for memory device performance changes corresponding to the wear cycle information. The memory device can receive the wear cycle information and determine one or more operational parameters (e.g., values, characteristics) in response to the wear cycle information.

[0084] It will be understood that when an element is referred to as being “on” another element, “connected to” another element, or “coupled to” another element, it can be directly on, directly connected, or directly coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly on,” “directly connected,” or “directly coupled” to another element, there are no intervening elements or layers present. If two elements are shown to be connected by a line, then unless otherwise indicated, the two elements can be coupled or directly coupled.

[0085] Method examples described herein can be machine or computer- implemented at least in part. Some examples can include a computer- readable media or machine-readable media encoded with instructions that operable to configure an electronic device to perform methods as described in above examples. Embodiments of such methods can include code, such as microcode, assembly language code, a higher-level languages code, or the like. Such code can include computer readable instructions for performing various methods. The code can form portions of computer program products. Further, the code can be tangibly stored in one or more volatile or non-volatile tangible computer-readable media during execution. Examples of these tangible computer-readable media can include, but are not limited to: a hard disk, a removable magnetic disk, a removable magnetic disk, a magnetic cassette, a memory card or stick, a Random Access Memory (RAM), a Read Only Memory (ROM), a Solid State Drive (SSD), a Universal Flash Storage (UFS) device, an Embedded Multi-Media Controller (eMMC) device, and the like.

[0086] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used as well, which will be apparent to those of ordinary skill in the art upon reviewing the above description. It is to be understood that the embodiments are not limited to the particular examples described above. Rather, the scope of the embodiments will be defined by the appended claims, and equivalents thereof, as further modified by the full range of equivalents permissible under the law. Furthermore, in the foregoing detailed description, various features are grouped together in examples for the purpose of streamlining the disclosure. This should not be interpreted as intending that the claimed embodiments require more features than are expressly identified in the claims. Rather, the claimed subject matter might be practiced without all of the features in some embodiments. Additionally, some embodiments can provide for more flexible implementation than others. Accordingly, the claimed subject matter intends to embrace all such possible embodiments, and that the patent rights are not limited to the disclosed examples.

Claims

1. A temperature trimming architecture for an integrated circuit (IC), the architecture comprising: A string of main latching circuits configured to pass a set of pre-programmed trimming codes to the output of the string, the set of pre-programmed trimming codes being based on a first token received at each of the main latching circuits in the string. A multiplexer coupled to the output of the string, the multiplexer being configured to receive temperature measurements and to pass at least two temperature trimming codes from the set of pre-programmed trimming codes to the output of the multiplexer. as well as An interpolator configured to receive the at least two temperature trimming codes and interpolate a first output trimming code based on the temperature measurements and the at least two trimming codes.

2. The architecture of claim 1, comprising a plurality of local latch circuits, wherein a first local latch circuit of the plurality of local latch circuits is configured to receive the first output trimming code from the interpolator.

3. The architecture of claim 2, wherein the first local latch circuit is configured to pass the first output trimming code to the corresponding reference circuit.

4. The architecture of claim 2, wherein the first local latch circuit includes a control circuit system configured to determine whether the first token corresponds to the first local latch circuit and a corresponding reference circuit coupled to the first local latch circuit, such that when the first token corresponds to the corresponding reference circuit, the first output trimming code is passed to the corresponding reference circuit, and when the first token does not correspond to the first local latch circuit, the first output trimming code is not passed.

5. The architecture of claim 1, wherein the first main latch circuit in the string of main latch circuits comprises: Multiple latches configured to store a set of pre-programmed temperature trimming codes; and A token detection circuit is configured to determine whether the first token corresponds to the first main latch circuit, in response to the first token corresponding to the first main latch circuit transmitting the set of pre-programmed temperature trimming codes, and in response to the first token not corresponding to the first main latch circuit transmitting the state of the input interface of the first main latch circuit.

6. The architecture of claim 5, wherein the token detection circuit includes a first gate configured to pass the set of pre-programmed temperature trimming codes when the first token corresponds to the first main latch circuit, and to pass the state of the input interface when the first token does not correspond to the first main latch circuit.

7. The architecture of claim 6, wherein the token detection circuit includes a second gate configured to pass the set of pre-programmed temperature trimming codes from the plurality of latches to the first gate when the first token corresponds to the first main latch circuit, and not to pass the set of pre-programmed temperature trimming codes from the plurality of latches to the first gate when the first token does not correspond to the first main latch circuit.

8. A circuit for temperature trimming, the circuit comprising: A token generator configured to provide serially generated tokens; Multiple primary latch circuits, each associated with a corresponding reference circuit in a plurality of reference circuits, are arranged in a sequential chain. A first primary latch circuit is configured to pass a first set of predetermined temperature trimming codes to the output of the first primary latch circuit in response to a first token in the serially generated tokens, the first set corresponding to a first corresponding reference circuit in the plurality of reference circuits, and to pass a second set of predetermined trimming codes received from a previous primary latch circuit in the sequential chain to the output of the first primary latch circuit in response to a second token in the serially generated tokens. A multiplexer coupled to the output of the last main latch circuit of the sequential chain, the multiplexer being configured to receive temperature measurements and to pass at least two temperature trimming codes from a first set of predetermined temperature trimming codes to the output of the multiplexer. as well as An interpolator configured to receive the at least two temperature trimming codes and to interpolate and output trimming codes based on the temperature measurements and the at least two trimming codes.

9. The circuit of claim 8, wherein the token generator is configured to sequentially generate a series of tokens, wherein each series of tokens includes a token configured to match a reference token of each of the plurality of primary latching circuits.

10. The circuit of claim 8, wherein the plurality of reference circuits comprises a plurality of voltage reference circuits.

11. The circuit of claim 8, wherein each primary latch comprises a plurality of trim codes indexed by discrete temperatures within a temperature range.

12. The circuit of claim 8, wherein each main latch circuit comprises: The first gate, which responds to the token generated by the serialization; and The second gate responds to the active output of the previous main latch circuit.

13. A method for temperature trimming, the method comprising: A series of tokens generated serially; A series of latch circuits that receive the token at multiple latch circuits serially connected to the input of the multiplexer; In response to the first token in the series of tokens, the first temperature trimming code stored in the first latch of the plurality of latch circuits is serially transmitted to the input of the multiplexer via at least one other latch circuit of the plurality of latch circuits. In response to the temperature measurement value, two temperature trimming codes from the first stored temperature trimming codes are transmitted to the output of the multiplexer; as well as The first reference trimming code is interpolated from the two temperature trimming codes.

14. The method of claim 13, further comprising serially transmitting a second stored temperature trimming code of a second latch circuit in the plurality of latch circuits to the input of the multiplexer in response to a second token in the series of tokens.

15. The method of claim 13, further comprising: Receive the first reference trimming code at the first reference circuit; and The first reference generated by the first reference circuit is modified based on the first reference modification code.

16. The method of claim 13, wherein the serial transmission of the first stored temperature trimming code includes deactivating the output of the latch of each of the plurality of latch circuits before receiving the first token.

17. The method of claim 16, wherein the serial transmission of the first stored temperature trimming code comprises: Compare the first token with a token reference for each of the plurality of latching circuits to provide a token matching indication for each of the plurality of latching circuits; and The output of the latch in each of the plurality of latch circuits is ANDed with the token matching indication.

18. The method of claim 17, wherein the serial transmission of the first stored temperature trimming code performs an OR operation on the output of the latch of all but one of the plurality of latch circuits and the output of the previous latch circuit in the serially coupled plurality of latch circuits.

19. The method of claim 13, wherein the first reference trimming code is transmitted to a plurality of reference circuits on a bus having a width commensurate with the width of the first reference trimming code.

20. The method of claim 13, comprising transmitting the first reference trimming code to a plurality of reference circuits on a bus having a width commensurate with the width of the first reference trimming code and the token.

21. The method of claim 13, further comprising transmitting the first reference trimming code to a plurality of reference circuits on a serial communication bus.

Images