Digit line and body contact for semiconductor devices

Abstract

This application relates to digit lines and body contacts for semiconductor devices. Systems, methods, and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices with a first source / drain region and a second source / drain region separated by a channel region, and a gate opposite the channel region, and vertically oriented access lines coupled to the gate and separated from the channel region by a gate dielectric. The memory cells have a horizontally oriented storage node coupled to the second source / drain region and a horizontally oriented digit line coupled to the first source / drain region. Vertical body contacts are formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separated from the first source / drain region and the horizontally oriented digit line by a dielectric.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically, to digital lines and body contacts for semiconductor devices. Background Technology

[0002] Memory is commonly implemented in electronic systems such as computers, mobile phones, and handheld devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and can include Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Synchronous Dynamic Random Access Memory (SDRAM). Non-volatile memory provides permanent data by maintaining stored data when not powered and can include NAND flash memory, NOR flash memory, NDI read-only memory (NROM), phase-change memory (e.g., phase-change random access memory), resistive memory (e.g., resistive random access memory), crosspoint memory, ferroelectric random access memory (FeRAM), or the like.

[0003] As design rules shrink, less semiconductor space is available to fabricate memory, including DRAM arrays. A corresponding memory cell in DRAM may contain access means, such as transistors, having first and second source / drain regions separated by a channel region. The gate may be opposite the channel region and separated from it by a gate dielectric. Access lines, such as word lines, are electrically connected to the gate of the DRAM cell. A DRAM cell may contain storage nodes, such as capacitor cells, coupled to digital lines via access means. Access means can be activated (e.g., to select a cell) via access lines coupled to access transistors. Capacitors may store charge corresponding to the data value (e.g., logic "1" or "0") of the corresponding cell. Summary of the Invention

[0004] One aspect of this disclosure relates to a method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines, comprising: vertically depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material in repeated iterations to form a vertical stack, wherein the semiconductor material comprises a lightly doped semiconductor material, and forming first and second source / drain regions laterally separated by channel regions within the lightly doped semiconductor material; forming a vertical opening using a first etchant process to expose vertical sidewalls in the vertical stack; selectively etching the second dielectric material to form a first horizontal opening that removes the second dielectric material backward from the vertical opening by a first distance; and in the... The process involves vapor-phase doping of the top surface of a lightly doped semiconductor material to form a first source / drain region; depositing a conductive material onto the top surface above the first source / drain region in the first horizontal opening; selectively etching the conductive material, the first source / drain region, and a first portion of the lightly doped semiconductor material below the first source / drain region to form a second horizontal opening having a second horizontal rearward distance from the vertical opening; depositing a third dielectric material laterally adjacent to the conductive material and the first source / drain region in the second horizontal opening; and depositing a heavily doped semiconductor material into the vertical opening to form a conductive body contact to the second portion of the lightly doped semiconductor material.

[0005] Another aspect of this disclosure relates to a method for forming a memory array having vertically stacked memory cells and horizontally oriented access devices and vertically oriented access lines, comprising: vertically depositing layers of oxide material, semiconductor material, and first nitride material in repeated iterations to form a vertical stack, wherein the semiconductor material comprises a lightly doped semiconductor material to form first and second source / drain regions laterally separated by channel regions; forming a vertical opening using a first etchant process to expose vertical sidewalls in the vertical stack; selectively etching the first nitride material to form a first horizontal opening having a first height (H1) and such that the first nitride material is recessed from the vertical opening formed through the repeated layers by a first distance (D1); vapor-phase doping a dopant in the top surface of the lightly doped semiconductor material to form the first source / drain regions; and depositing a conductive material onto the stack. On the top surface of the lightly doped semiconductor material above the first source / drain region beneath the laterally recessed first nitride material; selectively etching the conductive material, the first source / drain region, and a first portion of the lightly doped semiconductor material below the first source / drain region via the vertical opening to leave a portion of the conductive material above the first source / drain region to form a second horizontal opening having a second distance from the vertical opening; depositing a second nitride material having a second height (H2) and laterally adjacent to the conductive material and the first source / drain region in the second horizontal opening; and vertically etching the stack to maintain the vertical opening and expose the sidewalls to the second nitride material, the second portion of the lightly doped semiconductor material, and the oxide material to form a body contact region to prevent source / drain leakage and hole formation in the horizontally oriented access device.

[0006] Another aspect of this disclosure relates to a memory device having vertically stacked memory cells, horizontally oriented access devices, and vertically oriented access lines, comprising: a vertically stacked memory cell array, the vertically stacked memory cell array including: a horizontally oriented access device having a first source / drain region and a second source / drain region separated by a channel region, and a gate opposite to the channel region and separated from it by a gate dielectric; a vertically oriented access line coupled to the gate and separated from the channel region by the gate dielectric; a horizontally oriented memory node electrically coupled to the second source / drain region of the horizontally oriented access device; a horizontally oriented digital line electrically coupled to the first source / drain region of the horizontally oriented access device; and a vertical body contact formed to directly electrically contact the body region of one or more of the horizontally oriented access devices and separated from the first source / drain region and the horizontally oriented digital line by a dielectric. Attached Figure Description

[0007] Figure 1 This is an illustrative description of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0008] Figure 2 This is a perspective view illustrating a portion of the digital lines and body contacts of a semiconductor device according to several embodiments of the present disclosure.

[0009] Figure 3 This is a perspective view illustrating a portion of the digital lines and body contacts of a semiconductor device according to several embodiments of the present disclosure.

[0010] Figure 4A to 4K This is a cross-sectional view of a vertically stacked memory cell array at various stages of a semiconductor manufacturing process for forming digital lines and body contacts of a semiconductor device, according to several embodiments of the present disclosure.

[0011] Figures 5A to 5B This describes an example method, according to several embodiments of the present disclosure, at another stage of a semiconductor manufacturing process for forming a vertically stacked array of memory cells having digital lines and body contacts for a semiconductor device and vertically oriented access lines.

[0012] Figures 6A to 6E This describes an example method, according to several embodiments of the present disclosure, at another stage of a semiconductor manufacturing process for forming a vertically stacked array of memory cells having digital lines and body contacts for a semiconductor device and vertically oriented access lines.

[0013] Figures 7A to 7E This describes an example method, according to several embodiments of the present disclosure, at another stage of a semiconductor manufacturing process for forming a vertically stacked array of memory cells having digital lines and body contacts for a semiconductor device and vertically oriented access lines.

[0014] Figures 8A to 8E This describes an example method, according to several embodiments of the present disclosure, at another stage of a conductor manufacturing process for forming a vertically stacked array of memory cells having digital lines and body contacts for a semiconductor device and vertically oriented access lines.

[0015] Figure 9 The illustration shows a cross-sectional view of an example of a horizontally oriented access device coupled to a horizontally oriented memory node and coupled to a vertically oriented access line and a horizontally oriented digital line, according to several embodiments of the present disclosure.

[0016] Figure 10 This is a block diagram of a device in the form of a computing system including a memory device, according to several embodiments of the present disclosure. Detailed Implementation

[0017] Embodiments of this disclosure describe digital lines and body contacts for a semiconductor device. The digital lines and body contacts are formed together with horizontal access devices in a vertically stacked array of memory cells. The horizontal access devices are integrated with vertically oriented access lines and with horizontally oriented digital lines. The body contacts may be formed to provide better body bias control to the horizontally oriented access devices (e.g., transistors). This further provides better access device channel control to silicon oxide channel access devices and provides device refresh improvements. Vertically oriented body contact lines are integrated to form body contacts to the body region of the horizontally oriented access devices.

[0018] According to an embodiment, the digital lines can be better isolated from the body contact lines, resulting in lower digital line capacitance and less capacitive coupling to the body contact lines. The isolation technique further reduces potential dopant diffusion to the source / drain and digital line contacts, with potentially more uniform and lower digital line contact resistance and lower source / drain doping requirements.

[0019] The figures in this document follow a numbering convention, where the first digit or the first few digits correspond to the figure number, and the remaining digits identify elements or components in the figure. Similar elements or components between different figures can be identified by using similar digits. For example, reference digit 104 can be cited. Figure 1 The element "04" in the text, and similar elements can be referenced as Figure 2 In the diagram, 204. Multiple similar elements within a single figure can be referenced using a following character and another number or letter as a reference number. For example, 302-1 could refer to... Figure 3 Components 302-1 and 302-2 in the text may refer to a reference component 302-2 that is similar to component 302-1. Such similar components may be generally referred to without hyphens and additional numbers or letters. For example, components 302-1 and 302-2 or other similar components may be collectively referred to as 302.

[0020] Figure 1 This is a block diagram of an apparatus according to several embodiments of the present disclosure. Figure 1 The illustration shows a circuit diagram of a cell array of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present disclosure. Figure 1The cell array can have multiple sub-cell arrays 101-1, 101-2, ..., 101-N. Sub-cell arrays 101-1, 101-2, ..., 101-N can be arranged along a second direction (D2) 105. Each sub-cell array (e.g., sub-cell array 101-2) can contain multiple access lines 103-1, 103-2, ..., 103-Q (which may also be called word lines). Furthermore, each sub-cell array (e.g., sub-cell array 101-2) can contain multiple digital lines 107-1, 107-2, ..., 107-P (which may also be called bit lines, data lines, or sensing lines). Figure 1 In this document, digital lines 107-1, 107-2, ..., 107-P are described as extending in a first direction (D1) 109, and access lines 103-1, 103-2, ..., 103-Q are described as extending in a third direction (D3) 111. According to an embodiment, the first direction (D1) 109 and the second direction (D2) 105 can be considered to be in a horizontal (“XY”) plane. The third direction (D3) 111 can be considered to be in a vertical (“Z”) plane. Therefore, according to the embodiment described herein, access lines 103-1, 103-2, ..., 103-Q extend in a vertical direction (e.g., the third direction (D3) 111).

[0021] A memory cell (e.g., 110) may include access means (e.g., access transistors) and a storage node located at the intersection of each access line 103-1, 103-2, ..., 103-Q and each digital line 107-1, 107-2, ..., 107-P. The memory cell can be written to or read from using the access lines 103-1, 103-2, ..., 103-Q and the digital lines 107-1, 107-2, ..., 107-P. The digital lines 107-1, 107-2, ..., 107-P may electrically interconnect the memory cells along the horizontal columns of each sub-cell array 101-1, 101-2, ..., 101-N, and the access lines 103-1, 103-2, ..., 103-Q may electrically interconnect the memory cells along the vertical rows of each sub-cell array 101-1, 101-2, ..., 101-N. A memory cell (e.g., 110) can be located between an access line (e.g., 103-2) and a digital line (e.g., 107-2). Each memory cell can be uniquely addressed by a combination of access lines 103-1, 103-2, ..., 103-Q and digital lines 107-1, 107-2, ..., 107-P.

[0022] Digital lines 107-1, 107-2, ..., 107-P may be or include conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. Digital lines 107-1, 107-2, ..., 107-P may extend in a first direction (D1) 109. Digital lines 107-1, 107-2, ..., 107-P in a sub-cell array (e.g., 101-2) are spaced apart from each other in a vertical direction (e.g., in a third direction (D3) 111).

[0023] Access lines 103-1, 103-2, ..., 103-Q may be or be contained in conductive patterns (e.g., metal lines) extending in a direction perpendicular to the substrate (e.g., in a third direction (D3) 111). Access lines in a sub-cell array (e.g., 101-2) are spaced apart from each other in a first direction (D1) 109.

[0024] The gate of a memory cell (e.g., memory cell 110) may be connected to an access line (e.g., 103-2), and the first conductive node (e.g., a first source / drain region) of the access means (e.g., a transistor) of memory cell 110 may be connected to a digital line (e.g., 107-2). Each of the memory cells (e.g., memory cell 110) may be connected to a storage node (e.g., a capacitor). The second conductive node (e.g., a second source / drain region) of the access means (e.g., a transistor) of memory cell 110 may be connected to a storage node (e.g., a capacitor). Although the references to the first and second source / drain regions are used herein to denote two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as "first" and / or "second" source / drain regions have a single meaning. It is desirable that only one of the source / drain regions is connected to a digital line (e.g., 107-2), and the other source / drain regions are connected to a storage node.

[0025] Figure 2 The illustration shows a three-dimensional (3D) semiconductor memory device according to some embodiments of the present disclosure (e.g., Figure 1 The image shows a perspective view of a portion of a vertically oriented stacked subcell array 101-2 of memory cells in an array.

[0026] Figure 3 Explanation and display Figure 2 The unit cell of the 3D semiconductor memory device shown in the image (e.g.) Figure 1 A perspective view of the memory cell 110 shown in the image.

[0027] like Figure 2 As shown in the diagram, substrate 200 can be formed on it. Figure 1One of the described multiple sub-cell arrays (e.g., 101-2). For example, substrate 200 may be or comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0028] like Figure 2 As shown in the example embodiments, the substrate 200 may be fabricated thereon with memory cells extending in a vertical direction (e.g., a third direction (D3) 111). Figure 1 The memory cells 110 in the memory are vertically oriented stacked. According to some embodiments, the vertically oriented stack of memory cells can be manufactured such that each memory cell (e.g., Figure 1 The memory cells 110 are formed on multiple vertical levels (e.g., a first level (L1), a second level (L2), and a third level (L3)). Repeating vertical levels L1, L2, and L3 can be arranged (e.g., "stacked") in the vertical direction (e.g., ...). Figure 1 The third-party orientation (D3) 111 shown in the figure is separated from the substrate 200 by an insulating material 220. Each of the repeating vertical levels L1, L2, and L3 may include multiple discrete components (e.g., regions) to the laterally oriented access device 230 (e.g., transistors), and memory nodes (e.g., capacitors) including access lines 103-1, 103-2, ..., 103-Q connections and digital lines 107-1, 107-2, ..., 107-P connections. The multiple discrete components to the laterally oriented access device 230 (e.g., transistors) may be formed in multiple iterations of vertical repeating layers within each level, as described below regarding Figure 4A to 4K More detailed description, and can extend horizontally in the second direction (D2)205, similar to Figure 1 The second direction (D2) 105 is shown in the middle.

[0029] Multiple discrete components of a laterally oriented access device 230 (e.g., a transistor) may include a first source / drain region 221 and a second source / drain region 223, separated by a channel region 225, extending laterally in a second direction (D2) 205 and formed within the body of the access device. In some embodiments, the channel region 225 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise an n-type dopant region formed within a p-type doped body to the access device to form an n-type conductive transistor. In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise a p-type dopant region formed within an n-type doped body to the access device to form a p-type conductive transistor. By way of example (and not by way of limitation), the n-type dopant may comprise phosphorus (P) atoms and the p-type dopant may comprise boron (B) atoms formed in the opposite doped body region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0030] Storage node 227 (e.g., a capacitor) can be connected to a corresponding terminal of the access device. For example... Figure 2 As shown, a storage node 227 (e.g., a capacitor) may be connected to a second source / drain region 223 of the access device. The storage node may be or contain a memory element capable of storing data. Each of the storage nodes may be a memory element using one of a capacitor comprising a phase change material, a magnetic tunneling junction pattern, and / or a variable resistor body. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g., Figure 1 The memory node associated with each access device of the memory cell 110 in the memory cell can similarly extend in the second direction (D2) 205, similar to Figure 1 The second direction (D2) 105 is shown in the middle.

[0031] like Figure 2 As shown in the image, multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P extend along the first direction (D1) 209, similar to... Figure 1 The first direction (D1) is 109. Multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P can be similar to... Figure 1The digital lines 107-1, 107-2, ..., 107-P shown are illustrated. Multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P may be arranged along a third direction (D3) 211, such as in a "stacked" manner. The multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P may contain conductive materials. For example, the conductive materials may include one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, the embodiments are not limited to these examples.

[0032] In each of the vertical hierarchies (L1)213-1, (L2)213-2, and (L3)213-P, the horizontally oriented memory cells (e.g. Figure 1 The memory cells 110 in the memory may be horizontally spaced apart from each other in the first direction (D1) 209. However, as described below... Figure 4A to 4K In more detail, multiple discrete components of the laterally oriented access device 230 (e.g., first source / drain regions 221 and second source / drain regions 223 separated by channel region 225 extending in the second direction (D2) 205, and multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending laterally in the first direction (D1) 209) can be formed in different vertical layers within each level. For example, the multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 can be disposed on and electrically contacted with the top surface of the first source / drain region 221 and orthogonal to the laterally oriented access device 230 extending laterally in the second direction (D2) 205 (e.g., transistors). In some embodiments, a plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 are formed in a higher vertical layer further from the substrate 200 than the layer in which the discrete components of the laterally oriented access device (e.g., the first source / drain region 221 and the second source / drain region 223 separated by the channel region 225) are formed. In some embodiments, the plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending in the first direction (D1) 209 may be directly and / or connected to the top surface of the first source / drain region 221 via additional contacts comprising metal silicide.

[0033] like Figure 2As shown in the example embodiments, access lines 203-1, 203-2, ..., 203-Q extend in a direction perpendicular to the substrate 200, for example, extending in the third direction (D3) 211. Furthermore, as... Figure 2 As shown in the image, a sub-cell array (e.g.) Figure 1 Access lines 203-1, 203-2, ..., 203-Q in the sub-cell array 101-2 can be spaced apart from each other in the first direction (D1) 209. Access lines 203-1, 203-2, ..., 203-Q extending vertically relative to the substrate 200 in a third direction (D3) 211 between a pair of laterally oriented access devices 230 (e.g., transistors), the pair of laterally oriented access devices 230 extending laterally in the second direction (D2) 205 but adjacent to each other in the first direction (D1) 209 at a level (e.g., first level L1). Each of the access lines 203-1, 203-2, ..., 203-Q can extend vertically in the third direction (D3) on the sidewall of the corresponding one of the vertically stacked plurality of laterally oriented access devices 230 (e.g., transistors).

[0034] For example, and such Figure 3 As shown in more detail, the first of the vertically extending access lines (e.g., 203-1) may be adjacent to the sidewall of the channel region 225 of the first of the laterally oriented access devices 230 (e.g., transistors) in the first level (L1) 213-1, adjacent to the sidewall of the channel region 225 of the first of the laterally oriented access devices 230 (e.g., transistors) in the second level (L2) 213-2, and adjacent to the sidewall of the channel region 225 of the first of the laterally oriented access devices 230 (e.g., transistors) in the third level (L3) 213-P, etc. Similarly, the second vertically extending access line (e.g., 203-2) may be adjacent in the first level (L1) 213-1 to the sidewall of the channel region 225 of the second laterally oriented access device 230 (e.g., transistor) spaced apart from the first laterally oriented access device 230 (e.g., transistor) in the first direction (D1) 209. The second vertically extending access line (e.g., 203-2) may also be adjacent in the second level (L2) 213-2 to the sidewall of the channel region 225 of the second laterally oriented access device 230 (e.g., transistor), and in the third level (L3) 213-P to the sidewall of the channel region 225 of the second laterally oriented access device 230 (e.g., transistor), etc. The embodiments are not limited to a specific number of levels.

[0035] The vertically extending access lines 203-1, 203-2, ..., 203-Q may contain a conductive material, such as (for example) a doped semiconductor material, conductive metal silicon nitride, a metal, and / or a metal semiconductor compound. Access lines 203-1, 203-2, ..., 203-Q may correspond to... Figure 1 The word line (WL) of the description.

[0036] like Figure 2 As shown in the example embodiment, the conductive body contact 295 may extend via the end surface of an access device 230 (e.g., a transistor) laterally oriented in a first direction (D1) 209 in each layer (L1) 213-1, (L2) 213-2, and (L3) 213-P formed above the substrate 200. The body contact 295 may be connected to each memory cell (e.g., Figure 1 The body of the laterally oriented access device 230 (e.g., a transistor) in the memory cell 110 (as in the memory cell 110) (such as the body of the laterally oriented access device 230) (e.g., a transistor) Figure 3 (e.g., the body area shown in 326). The body contact 295 may contain a conductive material, such as (for example) a doped semiconductor material, conductive metal silicon nitride, a metal, and / or a metal semiconductor compound.

[0037] Despite Figure 2 Not shown, but insulating material may fill other spaces in the vertically stacked array of memory cells. For example, the insulating material may comprise one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments are not limited to these examples.

[0038] Figure 3 A more detailed description of memory cells according to some embodiments of the present disclosure (e.g., in) Figure 1 The unit cells of the vertically stacked array (e.g., within the sub-cell array 101-2) are sub-cell arrays. Figure 1 (Memory unit 110 in the memory). For example Figure 3 As shown, the first source / drain region 321 and the second source / drain region 323 can be impurity-doped regions of a laterally oriented access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be similar to... Figure 2 The first source / drain region 221 and the second source / drain region 223 are shown in the diagram. The first and second source / drain regions can be separated by a channel 325 formed in a semiconductor material body (e.g., body region 326) of a laterally oriented access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be formed by n-type or p-type dopant doped in the body region 326. The embodiments are not limited thereto.

[0039] For example, in an n-type conductive transistor configuration, the body region 326 of the laterally oriented access device 330 (e.g., a transistor) can be formed of a lightly doped (p-)p-type semiconductor material. In one embodiment, the body region 326 and the channel 325 separating the first source / drain region 321 and the second source / drain region 323 can comprise a lightly doped p-type (e.g., low dopant concentration (p-)) polysilicon material composed of boron (B) atoms as an impurity dopant to the polysilicon. The first source / drain region 321 and the second source / drain region 323 may also comprise metals, and / or metal composition materials containing ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), and copper (Cu), highly doped degenerate semiconductor materials, and / or indium oxide (In₂O₃) or indium tin oxide (In₂O₃) formed using atomic layer deposition processes. 2-x Sn x At least one of O3). However, the embodiments are not limited to these examples. As used herein, degenerate semiconductor material is intended to refer to a semiconductor material (e.g., polycrystalline silicon) containing a high degree of doping with significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.). In contrast, non-degenerate semiconductors contain a medium degree of doping, wherein the dopant atoms are well separated from each other in the semiconductor host lattice with negligible interactions.

[0040] In this example, the first source / drain region 321 and the second source / drain region 323 may contain highly doped, n-type conductive impurities (e.g., highly doped (n+)). In some embodiments, the highly doped, n-type conductive first drain region 321 and the second drain region 323 may contain a high concentration of phosphorus (P) atoms deposited therein. However, the embodiments are not limited to this example. In other embodiments, the laterally oriented access device 330 (e.g., a transistor) may have a p-type conductive configuration, in which case the conductivity type of the impurity (e.g., dopant) will be reversed.

[0041] like Figure 3 As shown in the example embodiment, the first source / drain region 321 may occupy the upper portion of the body 326 of the laterally oriented access device 330 (e.g., a transistor). For example, the first source / drain region 321 may have a bottom surface 324 within the body 326 of the laterally oriented access device 330 that is vertically positioned in a third direction (D3) 311 and is higher than the bottom surface of the bottom surface of the body 326 of the laterally oriented access device 220. Thus, the laterally, horizontally oriented transistor 330 may have a contact element (e.g., a transistor) located below the first source / drain region 321 and in contact with the body. Figure 2 The main body 326 of the electrical contact shown in Figure 295. Furthermore, as... Figure 3 As shown in the example embodiments, similar to Figure 2The number lines 207-1, 207-2, ..., 207-P and Figure 1 The digital lines 107-1, 107-2, ..., 107-P shown in the figure (e.g., 307-1) can be disposed on the top surface 322 of the first source / drain region 321 and electrically coupled to the top surface 322.

[0042] like Figure 3 As shown in the example embodiments, similar to Figure 2 Access lines 203-1, 203-2, ..., 203-Q and Figure 1 The access lines 103-1, 103-2, ..., 103-Q (e.g., 303-1) may extend vertically along the sidewall of the channel region 325 portion of the body 326 of the laterally oriented access device 330 (e.g., a transistor that conducts horizontally between the first source / drain region 321 and the second source / drain region 323 along the second direction (D2) 305) on a third direction (D3) 311. A gate dielectric material 304 may be inserted between the access line 303-1 (a portion of which is formed to the gate of the laterally oriented access device 330 (e.g., a transistor)) and the channel region 325. The gate dielectric material 304 may comprise, for example, a high-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, etc., or combinations thereof. Embodiments are not limited thereto. For example, in high-k dielectric material examples, the gate dielectric material 304 may include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobium iron oxide, etc.

[0043] Figure 4A It is used to form access devices with horizontal orientation and access lines with vertical orientation (e.g.) Figures 1 to 3 The cross-sectional view is shown at a stage of the semiconductor manufacturing process of the digital lines and body contacts of the semiconductor device (described in the description) and according to several embodiments of the present disclosure.

[0044] exist Figure 4AIn the example embodiments shown in the examples, the method includes depositing alternating layers of a first dielectric material 430-1, 430-2, ..., 430-N (collectively referred to as first dielectric material 430), semiconductor materials 432-1, 432-2, ..., 432-N (collectively referred to as semiconductor material 432), and a second dielectric material 433-1, 433-2, ..., 433-N (collectively referred to as second dielectric 433) in repeated iterations to form a vertical stack 401 on the working surface of a semiconductor substrate 400. The alternating materials in the repeated, vertical stack 401 may be separated from the substrate 400 by an insulating material 420. In one embodiment, the first dielectric material 430 may be deposited to have a thickness ranging from twenty (20) nanometers (nm) to sixty (60) nm, for example, a vertical height in a third direction (D3). In one embodiment, the semiconductor material 432 may be deposited to have a thickness ranging from twenty (20) nm to one hundred (100) nm, for example, a vertical height. In one embodiment, the second dielectric material 433 may be deposited to have a thickness ranging from ten (10) nm to thirty (30) nm, for example, in a vertical height. However, the embodiments are not limited to these examples. Figure 4A to 4K As shown in the diagram, the vertical direction 411 is described as a third direction (D3), such as the z-direction in the xyz coordinate system, similar to... Figures 1 to 3 The first, second, and third-party directions (D3) shown in the text.

[0045] In some embodiments, the first dielectric materials 430-1, 430-2, ..., 430-N may be interlayer dielectrics (ILDs). By way of example and not limitation, the first dielectric materials 430-1, 430-2, ..., 430-N may include oxide materials, such as SiO2. In another example, the first dielectric materials 430-1, 430-2, ..., 430-N may include silicon nitride (Si3N4) material (also referred to herein as “SiN”). In yet another example, the first dielectric materials 430-1, 430-2, ..., 430-N may include silicon oxycarbide (SiO2). x C y In another example, the first dielectric material 430-1, 430-2, ..., 430-N may comprise silicon oxynitride (SiO2). x N y Materials (also referred to herein as "SiON"), and / or combinations thereof. Examples are not limited to these instances.

[0046] In some embodiments, semiconductor materials 432-1, 432-2, ..., 432-N may comprise silicon (Si) material in a polycrystalline and / or amorphous state. Semiconductor materials 432-1, 432-2, ..., 432-N may be lightly doped p-type (p-) silicon materials. Semiconductor materials 432-1, 432-2, ..., 432-N can be formed by vapor-phase doping of boron atoms (B) (as an impurity dopant) at a low concentration to form lightly doped p-type (p-) silicon materials. Lightly doped p-type (p-) silicon materials may be polycrystalline silicon materials. However, the embodiments are not limited to these examples.

[0047] In some embodiments, the second dielectric materials 433-1, 433-2, ..., 433-N may be interlayer dielectrics (ILDs). By way of example and not limitation, the second dielectric materials 433-1, 433-2, ..., 433-N may include nitride materials. The nitride material may be silicon nitride (Si3N4) material (also referred to herein as “SiN”). In another example, the second dielectric materials 433-1, 433-2, ..., 433-N may include silicon oxycarbide (SiOC) material. In yet another example, the second dielectric materials 433-1, 433-2, ..., 433-N may comprise silicon oxynitride (SiON) and / or combinations thereof. Embodiments are not limited to these examples. However, according to embodiments, the second dielectric materials 433-1, 433-2, ..., 433-N are intentionally selected to be different from the first dielectric materials 430-1, 430-2, ..., 430-N in terms of material or composition, so that a selective etching process that selectively etches the other of the first and second dielectric layers can be performed on one of the first and second dielectric layers. For example, the second SiN dielectric materials 433-1, 433-2, ..., 433-N can be selectively etched relative to the semiconductor materials 432-1, 432-2, ..., 432-N and the first oxide dielectric materials 430-1, 430-2, ..., 430-N.

[0048] Alternating layers of first dielectric material 430-1, 430-2, ..., 430-N, semiconductor material 432-1, 432-2, ..., 432-N, and second dielectric material 433-1, 433-2, ..., 433-N can be deposited in a semiconductor manufacturing apparatus according to a semiconductor manufacturing process (e.g., chemical vapor deposition (CVD)). However, the embodiments are not limited to this example, and other suitable semiconductor manufacturing techniques can be used to deposit alternating layers of first dielectric material, semiconductor material, and second dielectric material in repeated iterations to form a vertical stack 401.

[0049] The layer can appear in vertically repeated iterations. Figure 4AThe example illustrates three layers numbered 1, 2, and 3 in repeated iterations. For instance, the stack may include: a first dielectric material 430-1, a semiconductor material 432-1, a second dielectric material 433-1, a third dielectric material 430-2, a second semiconductor material 432-2, a fourth dielectric material 433-2, a fifth dielectric material 430-3, a third semiconductor material 432-3, and a sixth dielectric material 433-3. Therefore, the stack may also include: a first oxide material 430-1, a first semiconductor material 432-1, a first nitride material 433-1, a second oxide material 430-2, a second semiconductor material 432-2, a second nitride material 433-2, a third oxide material 430-3, a third semiconductor material 432-3, and a third nitride material 433-3 in additional repeated iterations. However, the embodiments are not limited to this example and may include more or fewer repeated iterations.

[0050] Figure 4B It is used to form access devices with horizontal orientation and access lines with vertical orientation (e.g.) Figures 1 to 3 The cross-sectional view is shown in the illustration below, which describes another stage of the semiconductor manufacturing process of the digital lines and body contacts of the semiconductor device, and according to several embodiments of the present disclosure.

[0051] According to an embodiment, Figure 4B to 4K The semiconductor manufacturing process described herein can form elongated pillars and access lines that have been extended in a second direction (e.g.) Figures 5A to 6E (This happened after the event was shown in the video).

[0052] like Figure 4B As shown, a vertical opening 471 can be formed through layers within a vertically stacked memory cell to expose the vertical sidewalls in the vertical stack. The vertical opening 471 can be formed through repeated iterations of oxide material 430, semiconductor material 432, and nitride material 433. Thus, the vertical opening 471 can be formed using a first oxide material 430-1, a first semiconductor material 432-1, a first nitride material 433-1, a second oxide material 430-2, a second semiconductor material 432-2, a second nitride material 433-2, a third oxide material 430-3, a third semiconductor material 432-3, and a third nitride material 433-3. However, the embodiments are not limited to this. Figure 4B The image shows a single vertical opening. Multiple vertical openings can be formed through material layers. Vertical opening 471 can be formed to expose the vertical sidewalls in a vertical stack.

[0053] Figure 4C It is used to form access devices with horizontal orientation and access lines with vertical orientation (e.g.) Figures 1 to 3The cross-sectional view is shown in the illustration below, which describes another stage of the semiconductor manufacturing process of the digital lines and body contacts of the semiconductor device, and according to several embodiments of the present disclosure.

[0054] The etchant can be directed into the vertical opening 471 to selectively etch the second dielectric material 433. For example, the etchant can be directed into the vertical opening 471 to selectively etch the nitride material 433. The etchant can target all iterations of the second dielectric material 433 within the stack. Thus, the etchant can target the first nitride material 433-1, the second nitride material 433-2, and the third nitride material 433-3 within the stack.

[0055] Selective etchant processes can consist of one or more etchants selected from aqueous etchants, semi-aqueous etchants, vapor-phase etchants, plasma etchants, and other potentially selective etchants. For example, dry etchants composed of oxygen (O2) or O2 and sulfur dioxide (SO2) (O2 / SO2) can be used. Dry etchants composed of O2 or O2 and nitrogen (N2) (O2 / N2) can be used to selectively etch the second dielectric material 433. Alternatively or additionally, selective etching for removing the second dielectric material 433 may include selective etchants composed of sulfuric acid (H3PO4) or hydrogen fluoride (HF) and / or selective solvents (e.g., NH4OH or HF) and other potentially selective etchants or solvents to dissolve the second dielectric material 433. The etchant process may cause oxidation of only the nitride material 433. Figure 4C As shown in the examples, the etchant process can form a protective oxide coating, such as a second oxide material 434, on the semiconductor material 432. Therefore, the first dielectric material 430 and the semiconductor material 432 can remain intact during the selective etchant process. For example, the selective etchant process can etch a portion of the nitride material 433 without removing the oxide material 430 and the polysilicon material 432.

[0056] As mentioned, semiconductor material 432 may be protected by a second oxide material 434 formed on semiconductor material 432 during a selective etchant process. The second oxide material 434 may be present on all iterations of semiconductor material 432. For example, the second oxide material 434 may be present on the sidewalls of first semiconductor material 432-1, second semiconductor material 432-2, and third semiconductor material 432-3, etc., within the vertical opening 471 in the stack.

[0057] Figure 4D It is used to form access devices with horizontal orientation and access lines with vertical orientation (e.g.) Figures 1 to 3The cross-sectional view is shown in the illustration below, which describes another stage of the semiconductor manufacturing process of the digital lines and body contacts of the semiconductor device, and according to several embodiments of the present disclosure.

[0058] A selective etchant process can etch nitride material 433 to form a first horizontal opening 473. The selective etchant process can be performed such that the first horizontal opening 473 has a length or depth (D1) 476 at a first distance 476 from the vertical opening 471. The distance (D1) 476 can be controlled by controlling time, the composition of the etchant gas, and the etching rate (e.g., rate, concentration, temperature, pressure, and time parameters) of the reactant gas flowing into the vertical opening 471. Thus, the nitride material 433 can be etched to a distance of the first distance 476 from the vertical opening 471. The selective etching can be isotropic but selective for the second dielectric material 433, essentially stopping on the first dielectric material 430 and the semiconductor material. Therefore, in one example embodiment, a selective etchant process can substantially remove all nitride material 433 from the top surface of semiconductor material 432 to the bottom surface of a first dielectric material (e.g., oxide material) in the upper layer while simultaneously etching a horizontal distance (D1) 476 between semiconductor material 432 and oxide material 430 from the vertical opening 471. In this example, the horizontal opening 473 will have a height (H1) 435 that is substantially equivalent to the thickness to which the second dielectric layer 433 (e.g., nitride material) is deposited and controlled by said thickness. However, the embodiment is not limited to this example. As described herein, a selective etchant process can etch nitride material 433 to a first distance (D1) 476 and a height (H1) 435.

[0059] Figure 4E It is used to form access devices with horizontal orientation and access lines with vertical orientation (e.g.) Figures 1 to 3 The cross-sectional view is shown in the illustration below, which describes another stage of the semiconductor manufacturing process of the digital lines and body contacts of the semiconductor device, and according to several embodiments of the present disclosure.

[0060] The first source / drain region 475 can be formed by vapor-phase doping of a dopant into a portion of the top surface of the semiconductor material 432 via a horizontal opening 473. Vapor-phase doping can be used to achieve high isotropy, such as non-directional doping. In another example, thermal annealing using a dopant gas (e.g., phosphorus) can be used in conjunction with a high-energy plasma to help break bonds. The embodiments are not limited thereto and other suitable semiconductor fabrication techniques can be utilized. The width of the first source / drain region 475 doped into the top surface portion of the semiconductor material 432 can be formed substantially entirely from the vertical opening 471 along a first distance (D1) 476 of the first horizontal opening 473. The source / drain region 475 can be formed by vapor-phase doping of phosphorus (P) atoms (as an impurity dopant) at high plasma energy (e.g., PECVD) to form a highly concentrated, n-type doped (n+) region in the top surface of the semiconductor material 432.

[0061] Figure 4F It is used to form access devices with horizontal orientation and access lines with vertical orientation (e.g.) Figures 1 to 3 The cross-sectional view is shown in the illustration below, which describes another stage of the semiconductor manufacturing process of the digital lines and body contacts of the semiconductor device, and according to several embodiments of the present disclosure.

[0062] The conductive material 477 may be conformally deposited into a portion of the vertical opening 471, for example, using a chemical vapor deposition (CVD) process, such that the conductive material may also be deposited into the first horizontal opening 473. In some embodiments, the conductive material 477 may comprise titanium nitride (TiN) material. In some embodiments, the conductive material 477 may be tungsten (W). The conductive material 477 may be formed into laterally oriented digital lines.

[0063] Figure 4G It is used to form access devices with horizontal orientation and access lines with vertical orientation (e.g.) Figures 1 to 3 The cross-sectional view is shown in the illustration below, which describes another stage of the semiconductor manufacturing process of the digital lines and body contacts of the semiconductor device, and according to several embodiments of the present disclosure.

[0064] The conductive material 477 may be recessed in the horizontal opening 473, for example, etched away from the vertical opening 471 using atomic layer etching (ALE) or other suitable techniques. In some instances, the conductive material 477 may be etched back a second distance (D2) 483 from the vertical opening 471 in the horizontal opening 473. The conductive material 477 may be selectively etched, thereby leaving the oxide material 430, a portion of the conductive material 477, the semiconductor material 432, and the source / drain region 475 intact. The conductive material 477 may be etched using a third etchant process. In some embodiments, the conductive material 477 may be etched using an atomic layer etching (ALE) process. In some embodiments, the conductive material 477 may be etched using an isotropic etching process. The conductive material 477 may be recessed a second distance (D2) 483 in the horizontal opening 473 to maintain direct electrical contact on the top surface of the first source / drain region 475 formed in the semiconductor material 432. Therefore, the conductive material 477 maintains electrical contact with the source / drain region 475 and can form an integral, horizontally oriented conductive digital line (e.g., in...). Figures 1 to 3 The middle part consists of the numbers 107, 207, and 307 respectively.

[0065] Figure 4H It is used to form access devices with horizontal orientation and access lines with vertical orientation (e.g.) Figures 1 to 3 The cross-sectional view is shown in the illustration below, which describes another stage of the semiconductor manufacturing process of the digital lines and body contacts of the semiconductor device, and according to several embodiments of the present disclosure.

[0066] like Figure 4H The diagram shows an oxide material protecting the sidewalls of the semiconductor material in the vertical opening 471. Figure 4C to 4G The portion of the first source / drain region 475 (described as 434) and a first portion 478 of the semiconductor material 432 below the first source / drain region 475 may be selectively etched away to allow the formation of body contacts to the body region of the horizontal access device. In this example, a portion of the source / drain region 475 and the top portion (e.g., the first portion 478) of the semiconductor material 432 below the first source / drain region 475 may also be etched back from the vertical opening 471 to a second distance (D2) 483. Etching may be performed using a fourth etchant process, such as atomic layer etching (ALE) or other suitable techniques. In some embodiments, the source / drain region 475 may be etched from the vertical opening 471 to the same horizontal distance (D2) 483 as the conductive material 477.

[0067] Therefore, the second horizontal opening 472 can be formed by etching a portion of the source / drain region 475 from the vertical opening 471 and the top surface (e.g., 478) of the semiconductor material 432 below the first source / drain region 475 by a second horizontal distance (D2) 483. Thus, the second horizontal opening 472 may have a second vertical height (H2) 485. The second vertical height (H2) 485 may be greater than, for example, vertically higher than, a combination of the height (H1) 435 of the first horizontal opening 473 formed in the second dielectric material (e.g., a nitride material) and the height of the source / drain region 475 (e.g., the depth of vapor phase doping in the top surface of the semiconductor material 432). For example, the second height (H2) 485 may also include the height of the etched-away top portion (e.g., 478) of the semiconductor material 432. Therefore, the second distance (D2) 483 may be shorter than the first distance (D1) 476, but the second height 485 may be higher than the first height (in...). Figures 4D to 4E The description is H1).

[0068] Figure 4I It is used to form access devices with horizontal orientation and access lines with vertical orientation (e.g.) Figures 1 to 3 The cross-sectional view is shown in the illustration below, which describes another stage of the semiconductor manufacturing process of the digital lines and body contacts of the semiconductor device, and according to several embodiments of the present disclosure.

[0069] like Figure 4I As shown, the third dielectric material 474 is conformally deposited into the vertical opening 471 using a CVD process, and can conformally fill the vertical opening 471 and the second horizontal opening (in Figure 4D to 4H The description is 472). The third dielectric material 474 may be horizontally adjacent to the conductive material 477 (e.g., in...). Figure 1 The first portion of the conductive material 477, source / drain region 475, and low-doped (e.g., p-type low-doped) semiconductor material 432 extends in the first direction (D1) 109. For example, in some embodiments, a third dielectric material 474 may be below the first dielectric material 430 and in direct contact with the conductive material 477, the source / drain region 475, and the first portion of the low-doped semiconductor material 432. However, the embodiments are not limited to this example.

[0070] The third dielectric material 474 may be the same as or a different material from the second dielectric material 433. For example, the second dielectric material may be Si2N3, and the third dielectric material may also be Si3N4. In another example, the third dielectric material 474 may include silicon dioxide (SiO2) material. In yet another example, the third dielectric material 474 may include silicon oxycarbide (SiO2). x C yIn another example, the third dielectric material 474 may comprise silicon oxynitride (SiO2). x N y ( ), and / or combinations thereof. Examples are not limited to these instances.

[0071] Figure 4J It is used to form access devices with horizontal orientation and access lines with vertical orientation (e.g.) Figures 1 to 3 The cross-sectional view is shown in the illustration below, which describes another stage of the semiconductor manufacturing process of the digital lines and body contacts of the semiconductor device, and according to several embodiments of the present disclosure.

[0072] The third dielectric material 474 can be retracted to remove from the first vertical opening 471 and the first vertical opening 471 is maintained to allow deposition of conductive material (in Figure 4K (As shown in the image) This conductive material, deposited within a vertical opening 471, is used in a vertically stacked configuration with a horizontally oriented access device (e.g., Figure 9 Direct electrical contacts (e.g., body region contacts) are formed between the second portions 479 of the low-doped (e.g., p-type low-doped (p-)) semiconductor material 432 (901). In some embodiments, the third dielectric material 474 may be etched away from the vertical opening 471 to expose the sidewalls of the first dielectric material 430, the third dielectric material 474, and the second portions 479 of the semiconductor material 432.

[0073] Figure 4K It is used to form access devices with horizontal orientation and access lines with vertical orientation (e.g.) Figures 1 to 3 The cross-sectional view is shown in the illustration below, which describes another stage of the semiconductor manufacturing process of the digital lines and body contacts of the semiconductor device, and according to several embodiments of the present disclosure.

[0074] like Figure 4KAs shown, conductive material 495 is deposited into a vertical opening 471 to form a direct electrical contact with a second portion 479 of a lightly doped (e.g., p-type lightly doped (p-)) semiconductor material 432. In some embodiments, the conductive material may be a metal, such as tungsten (W). However, the embodiments are not limited thereto. In some embodiments, conductive material 495 is a highly doped (e.g., p-type highly doped (p+)) semiconductor material that can be deposited into the vertical opening 471. In this example, the highly doped semiconductor material 495 may be a highly doped p-type (p+) silicon material. The highly doped p-type (p+) silicon material 495 may be a polycrystalline silicon material. In one example, forming the conductive host contact includes depositing a degenerate semiconductor material. As used herein, degenerate semiconductor material is intended to refer to a semiconductor material (e.g., polycrystalline silicon) containing a high degree of doping with significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.). In contrast, non-degenerate semiconductors contain a medium degree of doping, where dopant atoms are well separated from each other in the semiconductor host lattice with negligible interactions.

[0075] In some instances, the highly doped semiconductor material 495 may be a highly doped p-type (p+) silicon-germanium (SiGe) material. The SiGe material may be deposited into the vertical opening 471 at a relatively low temperature. However, the embodiments are not limited to these examples. The highly doped p-type (p+) silicon material 495 may form a conductive body contact with the second portion 479 of the semiconductor material 432.

[0076] The highly doped p-type (p+) silicon material 495 can reduce holes generated during operation of the laterally oriented access device by gate-induced drain leakage (GIDL). The highly doped p-type (p+) silicon material 495 can control the channel potential within the semiconductor material 432 by controlling hole formation within the semiconductor material 432. For example, if the first source / drain region 475 is not electrically isolated from the conductive material 495 by the third dielectric material 474, then hole formation can occur between the first source / drain region 475, the highly doped (p+) polysilicon material, and the body region of the laterally oriented access device.

[0077] Figure 5A Explanation of the use of horizontally oriented access devices and vertically oriented access lines (e.g.) Figures 1 to 3 This describes another stage in the semiconductor manufacturing process of a vertically stacked memory cell array (as illustrated in the description) and an example method according to several embodiments of this disclosure. Figure 5A A top view illustrating a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 5AIn the example embodiment shown in the example, the method includes forming a plurality of first vertical openings 500 having a first horizontal direction (D1) 509 and a second horizontal direction (D2) 505 by vertically stacking to a substrate using an etchant process. In one example, such as Figure 5A As shown, a plurality of first vertical openings 500 extend primarily in a second horizontal direction (D2) 505 and can form elongated vertical pillars 513 with sidewalls 514 in a vertical stack. The plurality of first vertical openings 500 can be formed using photolithography techniques to pattern a photomask 535, for example to form a hard mask (HM) on the vertical stack prior to etching the plurality of first vertical openings 500.

[0078] Figure 5B It is along Figure 5A The image shows a cross-sectional view of the semiconductor structure at a specific point in the semiconductor manufacturing process, cut along line A-A'. Figure 5B The cross-sectional view shown in the image illustrates the formation of vertical stacks (e.g., on a semiconductor substrate 500). Figure 4A to 4K The repeated iteration of alternating layers of first dielectric material 530-1, 530-2, ..., 530-N, semiconductor material 532-1, 532-2, ..., 532-N and second dielectric material 533-1, 533-2, ..., 533-N shown in 401). Figure 5B The conductive materials 540-1, 540-2, ..., 540-4 can be formed on the gate dielectric material 538 in the plurality of first vertical openings 500. By way of example and not limitation, the gate dielectric material 538 can be conformally deposited in the plurality of first vertical openings 500 using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings. The gate dielectric 538 can be deposited to a specific thickness (t1) as appropriate for a particular design rule, for example, a gate dielectric thickness of about 10 nanometers (nm). However, the embodiments are not limited to this example. By way of example and not limitation, the gate dielectric 538 can include silicon dioxide (SiO2) material, alumina (Al2O3) material, high dielectric constant (k) (e.g., high k) dielectric material and / or combinations thereof, as well as... Figure 3 As described in the text.

[0079] In addition, such as Figure 5BAs shown, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited on the surface of gate dielectric material 538 within a plurality of first vertical openings 500. By way of example and not limitation, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited on the surface of gate dielectric material 538 within a plurality of first vertical openings 500 using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings above the gate dielectric 538. Conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited to a specific thickness (t2) to form vertically oriented access lines (e.g., shown as...). Figure 1 Access lines 103-1, 103-2, ..., 103-Q (which may also be referred to as word lines) shown below and suitable for specific design rules. For example, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited to a thickness of about 20 nanometers (nm). However, the embodiments are not limited to this example. By way of example and not by way of limitation, conductive materials 540-1, 540-2, ..., 540-4 may include one or more of the following other combinations: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). Figure 3 As described in the text.

[0080] like Figure 5B As shown in the diagram, conductive materials 540-1, 540-2, ..., 540-4 can be routed through a concave path only along the current path. Figure 5B The cross-sectional view shows the vertical sidewalls of the slender vertical pillars 542-1, 542-2, and 542-3. Multiple separate, vertical access lines formed of conductive materials 540-1, 540-2, ..., 540-4 can be obtained from the first vertical opening (e.g., using a suitable selective isotropic etching process). Figure 5A The bottom surface of the 500) is recessed by removing conductive materials 540-1, 540-2, ..., 540-4, thereby exposing the gate dielectric 538 on the bottom surface to form discrete, vertical access lines 540-1, 540-2, ..., 540-4. For example... Figure 5BAs shown, dielectric material 539 (e.g., oxide or other suitable spin-on dielectric (SOD)) is then deposited into the first vertical opening 500 using a process such as CVD to fill the first vertical opening 500. The dielectric can be planarized onto the top surface of the hard mask 535 of the vertical semiconductor stack using chemical mechanical planarization (CMP) or other suitable semiconductor manufacturing techniques. Subsequently, photolithography material 536 (e.g., the hard mask) can be deposited using CVD and planarized using CMP to cover and close the first vertical opening 500 above the separated vertical access lines 540-1, 540-2, ..., 540-4. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0081] Figure 6A Explanation of the use of horizontally oriented access devices and vertically oriented access lines (e.g.) Figures 1 to 3 This describes another stage in the semiconductor manufacturing process of a vertically stacked memory cell array (as illustrated in the description) and an example method according to several embodiments of this disclosure. Figure 6A A top view illustrating a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 6A In an example embodiment, the method includes patterning using a photolithography process. Figure 5B The photolithography masks in the middle are 636 and 536. Figure 6A The method further illustrates the use of a selective, isotropic etchant process to remove portions of the exposed conductive material 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z, to separately and individually form multiple separate, vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z (e.g., Figure 1 Access lines 103-1, 103-2, ..., 103-O in the following examples. Therefore, multiple separate, vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z are shown as running along the sidewall of a slender, vertical, support column, for example along... Figure 5B The slender vertical support columns 542-1, 542-2 and 542-3 in the cross-sectional view.

[0082] like Figure 6A The examples demonstrate that the exposed conductive materials 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z can be removed back to the first vertical opening using a suitable selective, isotropic etching process (e.g., Figure 5A The gate dielectric material 638 in (500) is as follows. Figure 6A As shown, subsequently, a dielectric material 641 (e.g., oxide or other suitable spin-on dielectric (SOD)) can be deposited to fill the remaining openings removed from the exposed conductive materials 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and 640-Z using a process such as CVD or other suitable techniques. The dielectric material 641 can be planarized to a vertical semiconductor stack (e.g., using a process such as CMP or other suitable techniques). Figure 4A to 4K The top surface of the previous hard mask 635 (shown as 401). In some embodiments, subsequent photolithography material 537 (e.g., a hard mask) may be deposited using CVD and planarized using CMP to cover and close the mask. Figure 4A to 4K Multiple discrete, vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and 640-Z are located on the working surface of the vertical semiconductor stack 401, thereby protecting the multiple discrete, vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and 640-Z along the sidewalls of the elongated vertical pillars. However, the embodiments are not limited to these process examples.

[0083] Figure 6B Explanation along Figure 6A The cut line A-A' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 6B The cross-sectional view shown is away from multiple separate, vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and is shown on a semiconductor substrate 600 for forming vertical stacks (e.g., Figure 4A to 4K The diagram shows a repeated iteration of alternating layers of first dielectric materials 630-1, 630-2, ..., 630-N, semiconductor materials 632-1, 632-2, ..., 632-N, and second dielectric materials 633-1, 633-2, ..., 633-N. For example... Figure 6B As shown in the diagram, the vertical direction 611 is described as a third direction (D3), such as the z-direction in the xyz coordinate system, similar to... Figures 1 to 3 The first, second, and third aspects are shown in the drawing, specifically the third aspect (D3) 111. The plane of the drawing extending left and right is on the first aspect (D1) 609. Figure 6B In the example embodiment, dielectric material 641 is shown filling the vertical opening during the deposition of the residual gate dielectric 638. The hard mask 637 described above covers the illustrated structure.

[0084] Figure 6C Explanation along Figure 6A The cut line B-B' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 6C The cross-sectional view shown is illustrated as extending along a repeating iterative axis in a second direction (D2) 605 along alternating layers of first dielectric materials 630-1, 630-2, ..., 630-N, semiconductor materials 632-1, 632-2, ..., 632-N, and second dielectric materials 633-1, 633-2, ..., 633-N. Along this axis, and within this axis, horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) may be formed within the layers of semiconductor materials 632-1, 632-2, ..., 632-N. Figure 6C In the drawing, adjacent and opposite vertical access lines 640-3 are indicated by dashed lines that indicate the set of positions from the plane and orientation inwards on the drawing.

[0085] Figure 6D Explanation along Figure 6A The cut line C-C' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 6D The cross-sectional view shown is illustrated as follows: along the axis of repeated iterations of alternating layers of first dielectric materials 630-1, 630-2, ..., 630-N, semiconductor materials 632-1, 632-2, ..., 632-N, and second dielectric materials 633-1, 633-2, ..., 633-N in the second direction (D2) 605, the horizontally oriented access device and the horizontally oriented storage node (e.g., capacitor cell) extend outside the region formed within the layers of semiconductor materials 632-1, 632-2, ..., 632-N. Figure 6C The image shows dielectric material 641 filling the space between horizontally oriented access devices and horizontally oriented memory nodes, with a three-dimensional array of vertically oriented memory cells spaced along a first direction (D1) extending into and out of the drawing. At the left end of the drawing, a repeating iteration of alternating layers of first dielectric materials 630-1, 630-2, ..., 630-N, semiconductor materials 632-1, 632-2, ..., 632-N, and second dielectric materials 633-1, 633-2, ..., 633-N is shown. Figure 1 The horizontally oriented digital lines shown below (e.g., digital lines 107-1, 107-2, ..., 107-P) can be integrated to form electrical contacts with the second source / drain region or the digital line conductive contact material, as described in more detail below.

[0086] Figure 6E Explanation along Figure 6A The cut line D-D' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 6E The cross-sectional view shown is illustrated as extending from right to left along a repeating iterative axis in the first direction (D1) 609 in the plane of the drawing, along the alternating layers of first dielectric material 630-1, 630-2, ..., 630-N, semiconductor material 632-1, 632-2, ..., 632-N, and second dielectric material 633-1, 633-2, ..., 633-N, spanning multiple separate, vertical access lines 640- 1. Intersecting with regions 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and intersecting with regions of semiconductor materials 632-1, 632-2, ..., 632-N, a channel region can be formed therein, separated from multiple separate, vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) by a gate dielectric 638. Figure 6E The first dielectric filling material 639 is shown to separate the space between adjacent horizontally oriented access devices and horizontally oriented storage nodes, which can be formed by extending into and out of the drawing, as described in more detail below, and can be spaced apart along the first direction (D1) 609 and stacked vertically in an array extending along the third direction (D3) 611 in a three-dimensional (3D) memory.

[0087] Figure 7A Explanation of the use of horizontally oriented access devices and vertically oriented access lines (e.g.) Figures 1 to 3 This describes another stage in the semiconductor manufacturing process of a vertically stacked memory cell array (as illustrated in the description) and an example method according to several embodiments of this disclosure. Figure 7A A top view illustrating a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 7A In an example embodiment, the method includes patterning photomasks 735, 736, and / or 737 using a photolithography process, for example... Figures 6A to 6E 635, 636 and / or 637. Figure 7A The method further illustrates the use of one or more etchant processes in the memory node region 750 (and) which extends through vertical stacking and primarily in the first horizontal direction (D1) 709. Figure 7A and 7C A vertical opening 751 is formed in 744). One or more etchant processes form the vertical opening 751 to expose Figures 7B to 7EThe third sidewall is shown in the vertical stacking of the second region adjacent to the semiconductor materials, in a repeating iteration of alternating layers of first dielectric materials 730-1, 730-2, ..., 730-N, semiconductor materials 732-1, 732-2, ..., 732-N, and second dielectric materials 733-1, 733-2, ..., 733-N. Other numbered components may be similar to those shown in the figure. Figures 6A to 6E Components for presentation and discussion.

[0088] In some embodiments, this process is about Figure 4A to 4K The semiconductor manufacturing process described is performed prior to this. However, Figures 7B to 7E The embodiments shown illustrate the storage node manufacturing process in relation to... Figure 4A to 4K The described digital line 777 and the first source / drain region formation are executed in a "after" order, such as digital line formation priority. Here, digital line 777 can be described as along a plurality of separate, vertical access lines 740.

[0089] according to Figures 7B to 7E The example embodiments shown in the figure include methods comprising vertical stacking ( Figure 4A A second vertical opening 751 is formed in (401) and the second regions 744 of semiconductor materials 732-1, 732-2, ..., 732-N are selectively etched to form from the vertically stacked ( Figure 4A The vertical opening 751 in (401) extends backward by a second horizontal distance (D2 opening) to form a second horizontal opening 779. According to an embodiment, selectively etching the second region 744 of the semiconductor materials 732-1, 732-2, ..., 732-N may include using an atomic layer etching (ALE) process. (See also: Regarding...) Figure 7C To explain further, the second source / drain region 778 may be formed in the semiconductor material 732-1, 732-2, ..., 732-N at the distal end of the second horizontal opening 779 relative to the vertical opening.

[0090] Figure 7B Explanation along Figure 7A The cut line A-A' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 7B The cross-sectional view shown is away from multiple separate, vertical access lines 740-1, 740-2, ..., 740-N, 740-(N+1), ..., 740-(Z-1), and shows repeated iterations of alternating layers of dielectric materials 730-1, 730-2, ..., 730-(N+1), semiconductor materials 732-1, 732-2, ..., 732-N, and second dielectric materials 733-1, 733-2, ..., 733-N separated by openings 751 on a semiconductor substrate 700 for forming vertically stacked layers. Figure 7B As shown in the diagram, the vertical direction 711 is described as a third direction (D3), such as the z-direction in the xyz coordinate system, similar to... Figures 1 to 3 The first, second, and third aspects are shown in the drawing, specifically the third aspect (D3) 111. The left and right extensions of the drawing plane are on the first aspect (D1) 709. Figure 7B In an example embodiment, the materials within the vertical stack—dielectric materials 730-1, 730-2, ..., 730-(N+1), semiconductor materials 732-1, 732-2, ..., 732-N, and second dielectric materials 733-1, 733-2, ..., 733-N—extend into and out of the plane in the second direction (D2) along the orientation axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0091] Figure 7C Explanation along Figure 7A The cut line B-B' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 7C The cross-sectional view shown is illustrated as extending left and right along the plane of the drawing in the second direction (D2) 705, along an axis of repeated iterations of alternating layers of first dielectric material 730-1, 730-2, ..., 730-N, semiconductor material 732-1, 732-2, ..., 732-N and second dielectric material 733-1, 733-2, ..., 733-N. Along this axis and within this axis, horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) may be formed within the layers of semiconductor material 732-1, 732-2, ..., 732-N.

[0092] exist Figure 7C In an example embodiment, the vertical opening 751 and the horizontal opening 779 are shown as being composed of about Figure 7A The masking, patterning, and etching processes described are used to create the image. For example... Figure 7C As shown, semiconductor materials 732-1, 732-2, ..., 732-N in the second region 744 have been selectively removed to form a horizontal opening 779. In one example, an atomic layer deposition (ALE) process is used to selectively etch semiconductor materials 732-1, 732-2, ..., 732-N and remove a second distance (D2 opening) backward from the vertical opening 751. Horizontally oriented memory nodes (e.g., capacitor cells) can be positioned relative to... Figure 4A to 4K The manufacturing process shown in the image may be followed or first as follows: Figures 8A to 8E As shown in the diagram, it is formed in the second horizontal opening 779.

[0093] Figure 7CThe diagram also shows that the first source / drain region 775 can be formed by vapor-doping a dopant into a portion of the top surface of the semiconductor material 732. In some embodiments, the first source / drain region 775 may be adjacent to the vertical access line 740. According to one example embodiment, such as Figure 7C As shown, the second source / drain region 778 can be formed by flowing a high-energy vapor dopant (e.g., phosphorus (P) for n-type transistors) into a second horizontal opening 779 to dope the semiconductor material 732-1, 732-2, ..., 732-N at the distal end of the second horizontal opening 779 relative to the vertical opening 751. In one example, vapor doping can be used to achieve high isotropy (e.g., non-directional doping) to form the second source / drain region 778 of the horizontally oriented access device in region 742. In another example, thermal annealing using a dopant gas (e.g., phosphorus) can be used in conjunction with a high-energy plasma to help break the bond. However, the embodiments are not limited to this and other suitable semiconductor manufacturing techniques can be utilized.

[0094] Conductive material 777 may be deposited adjacent to second dielectric material 733. Conductive material 777 may maintain electrical contact on the top surface of first source / drain region 775. Thus, conductive material 777 maintains electrical contact with source / drain region 775. In some embodiments, third dielectric material 774 may simultaneously maintain direct contact with conductive material 777, first source / drain region 775, and a first portion of lightly doped semiconductor material 732 below first dielectric material 730. Third dielectric material 774 may form a direct electrical contact with heavily doped p-type (p+) silicon material 795, such as a body region contact of a horizontally oriented access device.

[0095] like Figure 7C Further, it is shown that the first electrode (e.g., 761) of the horizontally oriented memory node will be coupled to the second source / drain region 778 of the horizontal access device. As will be shown later... Figure 7C As shown in the diagram, such horizontally oriented storage nodes are depicted as extending laterally in the plane of the drawing along a second direction (D2), and as formed in a vertically stacked manner (e.g., Figure 4A The vertical opening 751 in 401) is located at a second distance (D2 opening) and in the second horizontal opening 779 along the orientation axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory. Figure 7C In the middle, the adjacent opposite vertical access lines 740-3 are indicated by dashed lines that indicate the set of positions from the plane and orientation inwards of the drawing.

[0096] Figure 7D Explanation along Figure 7AThe cut line C-C' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 7D The cross-sectional view shown is illustrated as an axis of repeated iteration along the plane of the drawing in the second direction (D2) 705, along the alternating layers of first dielectric materials 730-1, 730-2, ..., 730-N, semiconductor materials 732-1, 732-2, ..., 732-N, and second dielectric materials 733-1, 733-2, ..., 733-N. Horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) will be formed outside the regions of the semiconductor materials 732-1, 732-2, ..., 732-N layers. The left end of the drawing shows the repeated iteration of the alternating layers of first dielectric materials 730-1, 730-2, ..., 730-N, semiconductor materials 732-1, 732-2, ..., 732-N, and second dielectric materials 733-1, 733-2, ..., 733-N. Figure 1 The horizontally oriented digital lines shown below (e.g., digital lines 107-1, 107-2, ..., 107-P) can be integrated to form the above-mentioned... Figure 4A to 4K The electrical contact described is made of a material that is conductive to the first source / drain region or digital line.

[0097] Furthermore, while the references to the first and second source / drain regions are used herein to denote two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as "first" and / or "second" have a single meaning. It is desirable that only one of the source / drain regions is connected to a digital line (e.g., 107-2), and the other source / drain regions are connected to the memory node.

[0098] In some embodiments, the conductive material 777 may be described as being adjacent to the second dielectric material 733. The conductive material 777 may be adjacent to the dielectric material 741. The body contact area 795 may be described as a repeated iteration along alternating layers of the first dielectric material 730-1, 730-2, ..., 730-N, the semiconductor material 732-1, 732-2, ..., 732-N, and the second dielectric material 733-1, 733-2, ..., 733-N.

[0099] Figure 7E Explanation along Figure 7A The cut line D-D' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 7EThe cross-sectional view shown is illustrated as extending laterally along a repeating iterative axis in the first direction (D1) 709 on the plane of the drawing, along alternating layers of first dielectric materials 730-1, 730-2, ..., 730-N, semiconductor materials 732-1, 732-2, ..., 732-N, and second dielectric materials 733-1, 733-2, ..., 733-N, intersecting multiple separate, vertical access lines 740-1, 740-2, ..., 740-4, and intersecting with regions of semiconductor materials 732-1, 732-2, ..., 732-N, where a channel region can be formed, separated from the multiple separate, vertical access lines 740-1, 740-2, ..., 740-4 by a gate dielectric 738. Figure 7E In the diagram, a first dielectric filling material 739 is shown separating the space between adjacent horizontally oriented access devices, which can extend into and out of the drawing via a plane, as shown in the diagram. Figure 4A to 4K The array is described and can be spaced apart along a first direction (D1) 709 and stacked vertically in an array extending along a third direction (D3) 711 in a three-dimensional (3D) memory.

[0100] Figure 8A Explanation of the use of horizontally oriented access devices and vertically oriented access lines (e.g.) Figures 1 to 3 This describes another stage in the semiconductor manufacturing process of a vertically stacked memory cell array (as illustrated in the description) and an example method according to several embodiments of this disclosure. Figure 8A A top view illustrating a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 8A In an example embodiment, the method includes patterning photomasks 835, 836, and / or 837 using a photolithography process, for example... Figures 6A to 6E 635, 636 and / or 637 or Figures 7A to 7E 735, 736 and / or 737. Figure 8A The method further illustrates the use of one or more etchant processes in the memory node region 850 (and) which extends through vertical stacking and primarily in the first horizontal direction (D1) 809. Figure 8A and 8C A vertical opening 851 is formed in 844). One or more etchant processes form the vertical opening 851 to expose Figures 8B to 8E The third sidewall is shown in the vertical stacking of the second region adjacent to the semiconductor material, in a repeating iteration of alternating layers of first dielectric material 830-1, 830-2, ..., 830-N, semiconductor material 832-1, 832-2, ..., 832-N, and second dielectric material 833-1, 833-2, ..., 833-N. Other numbered components may be similar to those shown in the figure. Figures 6A to 6E And the components shown and discussed in 7A to 7E.

[0101] In some embodiments, this process is performed after the access device region in which semiconductor material is selectively removed to form the first source / drain region, the channel region, and the second source / drain region of the horizontally oriented access device, such as... Figures 7A to 7E The explanation is as follows. According to... Figures 8B to 8E The example embodiment shown in the figure, the method includes selectively etching second regions of semiconductor materials 832-1, 832-2, ..., 832-N to deposit second source / drain regions and capacitor cells through a second horizontal opening extending backward a second horizontal distance from a vertical opening 851 in a vertical stack. In some embodiments, such as Figures 8B to 8E As shown, the method includes forming a capacitor cell as a storage node in a second horizontal opening. By way of example, and not by way of limitation, forming the capacitor includes sequentially depositing a first electrode 861 and a second electrode 856 separated by a cell dielectric 863 in the second horizontal opening using an atomic layer deposition (ALD) process. Other suitable semiconductor manufacturing techniques and / or storage node structures may be used. Digital lines 877 are visible along a plurality of separate, vertical access lines 840.

[0102] Figure 8B Explanation along Figure 8A The cut line A-A' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 8B The cross-sectional view shown is away from multiple separate, vertical access lines 840-1, 840-2, ..., 840-N, 840-(N+1), ..., 840-(Z-1), and shows repeated iterations of alternating layers of dielectric material 830-1, 830-2, ..., 830-(N+1) separated by horizontally oriented capacitor cells having a first electrode 861 (e.g., bottom cell contact electrode), a cell dielectric 863, and a second electrode 856 (e.g., top, common node electrode). As shown... Figure 8B As shown in the diagram, the vertical direction 811 is described as a third direction (D3), such as the z-direction in the xyz coordinate system, similar to... Figures 1 to 3 The first, second, and third directions shown are the third direction (D3) 111. The left and right extensions of the drawing plane are on the first direction (D1) 809. Figure 8B In an example embodiment, the first electrode 861 (e.g., the bottom electrode coupled to the source / drain region of the horizontal access device) and the second electrode 856 are described as being separated by a cell dielectric material 863 extending into and out of the plane of the drawing in a second direction (D2) and along the orientation axis of the vertically stacked memory cell array of the three-dimensional (3D) memory.

[0103] Figure 8C Explanation along Figure 8A The cut line B-B' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 8C The cross-sectional view shown is illustrated as extending left and right along the plane of the drawing in the second direction (D2) 805, along an axis of repeated iterations of alternating layers of first dielectric materials 830-1, 830-2, ..., 830-N, semiconductor materials 832-1, 832-2, ..., 832-N, and second dielectric materials 833-1, 833-2, ..., 833-N. Along this axis and within it, horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) may be formed within the layers of semiconductor materials 832-1, 832-2, ..., 832-N. Figure 8C In the example embodiment, a horizontally oriented memory node (e.g., a capacitor cell) is illustrated as having been formed in this semiconductor manufacturing process, and a first electrode 861 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and a second electrode 856 (e.g., a top electrode to be coupled to a common electrode plane (e.g., a ground plane)) separated by a cell dielectric 863 are shown. However, the embodiments are not limited to this example. In other embodiments, the first electrode 861 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and the second electrode 856 (e.g., a top electrode to be coupled to a common electrode plane (e.g., a ground plane) separated by a cell dielectric 863 may be formed after the first source / drain region, channel region, and second source / drain region are formed in regions of semiconductor material 832-1, 832-2, ..., 832-N, intended for positioning (e.g., placement formation) of the horizontally oriented access device described below.

[0104] exist Figure 8C In an example embodiment, a horizontally oriented memory node having a first electrode 861 (e.g., a bottom electrode coupling to the source / drain region of a horizontal access device) and a second electrode 856 (e.g., a top electrode coupling to a common electrode plane (e.g., a ground plane)) is shown formed on a plane extending laterally in the second direction (D2) and formed on a vertically stacked plane (e.g., a horizontally oriented memory node). Figure 4A The vertical opening in 401) (e.g.) Figure 7C The second horizontal opening (e.g., 751) is located at a second distance (D2 opening) and along the orientation axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory. Figure 7C In (779) shown in the image. Figure 8CIn the middle, adjacent opposite vertical access lines 840-3 are indicated by dashed lines that indicate the set of positions from the plane and orientation inwards of the drawing.

[0105] The conductive material 877 may be described as being adjacent to the second dielectric material 833. The conductive material 877 may maintain electrical contact on the top surface of the first source / drain region 875. Thus, the conductive material 877 maintains electrical contact with the source / drain region 875. In some embodiments, the third dielectric material 874 may simultaneously maintain direct contact with the conductive material 877, the first source / drain region 875, and a first portion of the lightly doped semiconductor material 832 below the first dielectric material 830. The third dielectric material 874 may form a direct electrical contact with the heavily doped p-type (p+) silicon material 895, such as a body region contact of a horizontally oriented access device.

[0106] Figure 8D Explanation along Figure 8A The cut line C-C' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 8D The cross-sectional view shown is illustrated as follows: along the second direction (D2) 805, in the plane of the drawing, along the repeating axis of alternating layers of first dielectric materials 830-1, 830-2, ..., 830-N, semiconductor materials 832-1, 832-2, ..., 832-N, and second dielectric materials 833-1, 833-2, ..., 833-N, extending laterally outside the regions formed within the layers of semiconductor materials 832-1, 832-2, ..., 832-N. Figure 8C The image shows a dielectric material 841 filling the space between horizontally oriented access devices, whose three-dimensional array of vertically oriented memory cells is spaced along a first direction (D1) extending into and out of the drawing. However, in Figure 8D In the cross-sectional view, a second electrode 856 (e.g., to the top common electrode of the capacitor cell structure) is additionally shown in the space between horizontally adjacent devices. At the left end of the drawing, a repeating iteration of alternating layers of first dielectric materials 830-1, 830-2, ..., 830-N, semiconductor materials 832-1, 832-2, ..., 832-N, and second dielectric materials 833-1, 833-2, ..., 833-N is shown at this location. Figure 1 The horizontally oriented digital lines (e.g., digital lines 107-1, 107-2, ..., 107-P) shown below can be integrated to form electrical contacts with the second source / drain region or the conductive contact material of the digital line, as described in more detail below.

[0107] In some embodiments, the conductive material 877 may be described as being adjacent to the second dielectric material 833. The conductive material 877 may be adjacent to the dielectric material 841. The body contact region 895 may also be described as a repeated iteration along alternating layers of the first dielectric material 830-1, 830-2, ..., 830-N, the semiconductor material 832-1, 832-2, ..., 832-N, and the second dielectric material 833-1, 833-2, ..., 833-N.

[0108] Figure 8E Explanation along Figure 8A The cut line D-D' in the diagram shows another cross-sectional view of the semiconductor structure at this particular point in an example semiconductor manufacturing process illustrating an embodiment of this disclosure. Figure 8E The cross-sectional view shown is illustrated as extending laterally along a repeating iterative axis in the first direction (D1) 809 on the plane of the drawing, along alternating layers of first dielectric materials 830-1, 830-2, ..., 830-N, semiconductor materials 832-1, 832-2, ..., 832-N, and second dielectric materials 833-1, 833-2, ..., 833-N, intersecting multiple separate, vertical access lines 840-1, 840-2, ..., 840-4, and intersecting with regions of semiconductor materials 832-1, 832-2, ..., 832-N, where a channel region can be formed, separated from the multiple separate, vertical access lines 840-1, 840-2, ..., 840-4 by a gate dielectric 838. Figure 8E The first dielectric filling material 839 is shown to separate the space between adjacent horizontally oriented access devices and horizontally oriented storage nodes. It can be formed into a plane extending into and out of the drawing, as described in more detail below, and can be spaced along a first direction (D1) 809 and stacked vertically in an array extending along a third direction (D3) 811 in a three-dimensional (3D) memory.

[0109] Figure 9 This illustration shows a cross-sectional view of a portion of an example of a horizontally oriented access device, as described in several embodiments of the present disclosure, coupled to a horizontally oriented memory node and coupled to vertically oriented access lines and horizontally oriented digital lines, such as a portion forming a vertically stacked array of memory cells. The horizontally oriented access device 901 may have a first source / drain region and a second source / drain region separated by a channel region, and a gate opposite to the channel region and separated from it by a gate dielectric.

[0110] like Figure 9As shown in the example, the first source / drain region 975-1 is illustrated as being in direct electrical contact with the horizontally oriented digital line 977-1. In some embodiments, the conductive digital lines 977-1 and 977-2 are formed of a metal composition including tungsten (W). However, the embodiments are not limited to this example. Although the terms "first" and "second" source / drain regions may be used herein to designate different and separate source / drain regions, the terms "first" and / or "second" are not limited to their counterparts in the source / drain regions, and their respective placement and their respective "first" or "second" designations used herein for convenience are interchangeable within the horizontally oriented access device described herein. For example, the first source / drain region 975-1 may also be labeled as a "second" source / drain region 975-1. Whether labeled "first" or "second," the source / drain regions can be separated from the other source / drain region by a channel region in the body of the horizontal access device.

[0111] exist Figure 9 In this example, the first source / drain region 975-1 is illustrated as being formed in the body region of the lightly doped p-type (p-) channel and the body region of the horizontally oriented access device 901. The first source / drain region 975-1 is separated from the vertical body contact 995 by a dielectric material 974. As shown, interlayer dielectric (ILD) materials 930-1 and 930-2 can separate the horizontally oriented access devices of the vertically stacked memory cells. Interlayer dielectric materials 930-1 and 930-2 can be of a first dielectric material type, such as an oxide-based dielectric material. However, the embodiments are not limited to this example.

[0112] exist Figure 9 In one example, horizontally oriented digital lines (e.g., 977-1 and 977-2) are formed in a second dielectric material type (e.g., a nitride-based dielectric material). However, the embodiments are not limited to this example. According to an embodiment, the first dielectric material and the second dielectric material are different compositions and are dissimilar, such that a nitride material (e.g., the second dielectric) can be selectively etched relative to the first dielectric material (e.g., an oxide material). The first dielectric materials 930-1 and 930-2, the horizontally oriented access device 901 including the first source / drain region 975-1 in the body region 932-1 and the p-type channel, and the digital lines 977-1 and 977-2 are formed into three layers of vertically stacked memory cells.

[0113] like Figure 9As shown in the example embodiments, the vertical body contact 995 is formed in direct electrical contact with the body region 932-1 of one or more of the horizontally oriented access devices 901. In some embodiments, the vertical body contact 995 may be a metal, such as tungsten (W). In some embodiments, the vertical body contact 995 may be a conductive doped polycrystalline silicon material, such as a highly doped p-type (P+) polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples. As used herein, the term "highly doped" is intended to mean a high concentration of dopant impurities such that there are significant interactions between the dopant atoms. The p-type dopant may contain boron atoms (B), and the n-type dopant may contain phosphorus atoms (P). According to the embodiments, the vertical body contact 995 is separated from the first source / drain region 975-1 and the horizontally oriented digital lines 977-1 and 977-2 by a dielectric 974 (e.g., SiN in this example).

[0114] In some embodiments, dielectric 974 further separates a first portion of the body region 932-1 of the horizontally oriented access device 901 (e.g., Figure 4H 478) and vertical body contact 995 to reduce void formation in body region 932-1 between vertical body contact 995 and body region 932-1. In some embodiments, dielectric 974 further separates a first portion of the body region 932-1 of the horizontally oriented access device 901 (e.g., ...). Figure 4H 478) and vertical body contact 995 to reduce gate-induced drain leakage (GIDL) in the horizontally oriented access device 901. In some embodiments, the horizontally oriented memory node (e.g., Figure 7C The capacitor cell shown in the image is coupled to the second source / drain region. Figure 9 (Not shown in the image). In this example, the capacitor cell has a first horizontally oriented electrode electrically coupled to a second source / drain region and a second horizontally oriented electrode separated from the first horizontally oriented electrode by the cell dielectric.

[0115] Therefore, as Figure 9 As shown in the example embodiment, a vertical, conductive body contact line 995 (e.g., a highly doped semiconductor material) can be deposited into a vertical opening 995 to form a conductive body contact that is directly connected to and only connected to a portion of a low-doped semiconductor material channel and body region 932-1 of a horizontally oriented access device.

[0116] According to an embodiment, a second dielectric material 974 is deposited to form a small-area direct electrical contact between the conductive body contact 995 and the channel in the horizontally oriented access device body region 932-1, while also electrically isolating the first source / drain region 975-1 from the digital lines 977-1 and 977-2 to prevent them from directly contacting each other. The small-area direct electrical contact between the conductive body region 995 and the channel in the body region 932-1, and the electrical isolation between the first source / drain region 975-1 and the digital lines 977-1 and 977-2, reduces capacitive coupling between the body contact 995 and the first source / drain region 975-1 and the digital lines 977-1 and 977-2. The small-area direct electrical contact also prevents hole diffusion between the highly doped semiconductor material 995 and the body region 932-1.

[0117] Figure 10 This is a block diagram of a device in the form of a computing system 1000 including a memory device 1003, according to several embodiments of the present disclosure. As used herein, the memory device 1003, memory array 1010, and / or host 1002 may also be considered as a single "device". According to an embodiment described herein, the memory device 1002 may include at least one memory array 1010 having memory cells with digital lines and body contacts formed thereon.

[0118] In this example, system 1000 includes a host 1002 coupled to memory device 1003 via interface 1004. The computing system 1000 may be a personal laptop, desktop computer, digital camera, mobile phone, memory card reader, or Internet of Things (IoT) enabled device, and other types of systems. Host 1002 may include several processing resources (e.g., one or more processors, microprocessors, or other types of control circuitry) capable of accessing memory 1003. System 1000 may include a separate integrated circuit, or both host 1002 and memory device 1003 may be on the same integrated circuit. For example, host 1002 may be a system controller for a memory system including multiple memory devices 1003, wherein system controller 1005 provides access to the respective memory devices 1003 via another processing resource (e.g., a central processing unit (CPU)).

[0119] exist Figure 10In the example shown, host 1002 is responsible for executing the operating system (OS) and / or various applications (e.g., processes) that can be loaded onto it (e.g., loaded onto it from memory device 1003 via controller 1005). The OS and / or the various applications can be loaded from memory device 1003 by providing access commands from host 1002 to memory device 1003 for accessing data including the OS and / or the various applications. Host 1002 can also access data used by the OS and / or the various applications by retrieving access commands for executing the data of the OS and / or the various applications.

[0120] For clarity, system 1000 has been simplified to focus on features particularly relevant to this disclosure. Memory array 1010 may be a DRAM array, comprising at least one memory cell having digital lines and body contacts formed according to the techniques described herein. For example, memory array 1010 may be an unshielded DL 4F2 array, such as a 3D-DRAM memory array. Array 1010 may include memory cells arranged in rows coupled via word lines (which may be referred to herein as access lines or select lines) and columns coupled via digital lines (which may be referred to herein as sense lines or data lines). Although in Figure 10 The illustration shows a single array 1010, but the embodiments are not limited thereto. For example, the memory device 1003 may include several arrays 1010 (e.g., several banks of memory cells in a DRAM).

[0121] Memory device 1003 includes an address circuitry 1006 for latching address signals provided via interface 1004. The interface may include, for example, a physical interface employing a suitable protocol (e.g., a data bus, address bus, and command bus, or a combined data / address / command bus). This protocol may be custom or proprietary, or interface 1004 may employ a standardized protocol, such as Peripheral Component Interconnect High Speed ​​(PCIe), Gen-Z, CCIX, or the like. Address signals are received and decoded by row decoder 1008 and column decoder 1012 to access memory array 1010. Data can be read from memory array 1010 by sensing voltage and / or current changes on a sensing line using sensing circuitry 1011. Sensing circuitry 1011 may include, for example, a sense amplifier capable of reading and latching a page (e.g., a row) of data from memory array 1010. I / O circuitry 1007 can be used for bidirectional data communication with host 1002 via interface 1004. The read / write circuitry 1013 is used to write data to or read data from the memory array 1010. As an example, the circuitry 1013 may include various drivers, latching circuitry, etc.

[0122] The control circuitry system 1005 decodes signals provided by the host 1002. These signals may be commands provided by the host 1002. These signals may include chip enable signals, write enable signals, and address latch signals, which are used to control operations performed on the memory array 1010, including data read operations, data write operations, and data erase operations. In various embodiments, the control circuitry system 1005 is responsible for executing instructions from the host 1002. The control circuitry system 1005 may include a state machine, a sequencer, and / or some other type of control circuitry system, which may be implemented in hardware, firmware, or software, or any combination of the three. In some instances, the host 1002 may be a controller external to the memory device 103. For example, the host 1002 may be a memory controller coupled to the processing resources of a computing device.

[0123] The term semiconductor can refer to, for example, a material, a wafer, or a substrate, and includes any basic semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a basic semiconductor structure, and other semiconductor structures. Furthermore, when referring to semiconductors in the foregoing description, prior process steps may have been used to form regions / junctions in the basic semiconductor structure, and the term semiconductor can include an underlying material containing such regions / junctions.

[0124] The figures in this document follow a numbering convention, where the first digit or the first few digits correspond to the drawing number and the remaining digits identify elements or components in the figure. Similar (e.g., identical) elements or components between different figures can be identified by using similar digits. It should be understood that elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide several additional embodiments of this disclosure. Furthermore, it should be understood that the scale and relative size of the elements provided in the figures are intended to illustrate embodiments of this disclosure and should not be construed as limiting.

[0125] As used herein, “several” or “a certain amount” of something may refer to one or more such things. For example, “several” or “a certain amount” of memory cells may refer to one or more memory cells. “A certain amount” of something is intended to be two or more. As used herein, “multiple actions performed simultaneously” refers to actions that at least partially overlap within a specific time period. As used herein, the term “coupling” may include electrical coupling, direct coupling, and / or direct connection without intermediary elements (e.g., by direct physical contact), indirect coupling and / or connection using intermediary elements, or wireless coupling. The term coupling may further include two or more elements that cooperate or interact with each other (e.g., as in a causal relationship). An element coupled between two elements may be between the two elements and may be coupled to each of the two elements.

[0126] It should be recognized that the term "vertical" indicates a variation from "precise" vertical due to common manufacturing, measurement, and / or assembly variations, and those skilled in the art should understand what the term "vertical" means. For example, vertical may correspond to the z-direction. As used herein, when a particular element is "adjacent" to another element, the particular element may cover the other element, may be on top of the other element, or may be transverse to the other element and / or may be in direct physical contact with the other element. Transverse to may refer to, for example, a horizontal direction that may be perpendicular to the z-direction (e.g., the y-direction or x-direction).

[0127] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements that achieve the same computational results may be used instead of the specific embodiments shown. This disclosure is intended to cover adjustments or variations of the various embodiments of this disclosure. It should be understood that the foregoing description is illustrative and non-limiting. Those skilled in the art will understand, upon reviewing the foregoing description, combinations of the foregoing embodiments and other embodiments not explicitly described herein. The scope of the various embodiments of this disclosure includes other applications in which the foregoing structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined with reference to the appended claims and the full scope of the equivalents entitled to by such claims.

Claims

1. A method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines, comprising: vertically depositing layers of a first dielectric material (430, 530, 630, 730), a semiconductor material (432, 532, 632, 732, 832, 932), and a second dielectric material (433, 533, 633, 733, 833) in repeated iterations to form a vertical stack, wherein the semiconductor material (432, 532, 632, 732, 832, 932) includes a low doped semiconductor material within which are formed first and second source / drain regions (475, 575, 675, 775, 875, 975) laterally separated by a channel region; forming a vertical opening (471) using a first etchant process to expose a vertical sidewall in the vertical stack; selectively etching the second dielectric material (433, 533, 633, 733, 833) to form a first horizontal opening (473) by removing the second dielectric material (433, 533, 633, 733, 833) from the vertical opening (471) a first distance (476) back; vapor phase doping a dopant in a top surface of the low doped semiconductor material (432, 532, 632, 732, 832, 932) to form the first source / drain region (475, 575, 675, 775, 875, 975); depositing a conductive material (477, 577, 677, 777, 877) onto the top surface over the first source / drain region (475, 575, 675, 775, 875, 975) in the first horizontal opening; selectively etching the conductive material (477, 577, 677, 777, 877), a first portion of the low doped semiconductor material (432, 532, 632, 732, 832, 932) and the first source / drain region (475, 575, 675, 775, 875, 975) below the first source / drain region (475, 575, 675, 775, 875, 975) to form a second horizontal opening (472) having a horizontal second distance (482) back from the vertical opening (471); depositing a third dielectric material (474, 574, 674, 774, 874) in the second horizontal opening laterally adjacent to the conductive material (477, 577, 677, 777, 877) and the first source / drain region (475, 575, 675, 775, 875, 975); and depositing a highly doped semiconductor material into the vertical opening to form a conductive body contact to a second portion of the low doped semiconductor material.

2. The method of claim 1, wherein vertically depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material in repeated iterations to form a vertical stack comprises: depositing an oxide material as the first dielectric material; depositing a low doped p-type (p-) polysilicon as the semiconductor material; and depositing a silicon nitride (SiN) material as the second dielectric material.

3. The method of claim 2, further comprising selectively etching the second dielectric layer using a second etchant process to form the first horizontal opening to a first height that is laterally recessed from the vertical opening by the first distance.

4. The method of claim 1, wherein depositing a conductive material comprises depositing a metal-containing material through the vertical opening to form a horizontally oriented digit line to each of the horizontally oriented access devices.

5. The method of any one of claims 1-4, further comprising: selectively etching the metal-containing material horizontally back from the vertical opening by the second distance to remain over and in electrical contact with the first source / drain region; and selectively etching the metal-containing material using a third etchant process to form the second horizontal opening having a second height prior to selectively etching the first source / drain region and the first portion of the low doped semiconductor material under the first source / drain region using a fourth etchant process.

6. The method of any one of claims 1-4, further comprising selectively etching the metal-containing material using an atomic layer deposition (ALE) etchant process.

7. The method of any one of claims 1-4, further comprising depositing a silicon nitride (SiN) material as the third dielectric.

8. The method of any one of claims 1-4, further comprising etching the stack using a fifth etchant process to: maintain the vertical opening; and expose a sidewall of the third dielectric material, a second portion of the low doped semiconductor material, and the second dielectric material.

9. A method for forming a memory array having vertically stacked memory cells with horizontally oriented access devices and vertically oriented access lines, comprising: vertically depositing layers of an oxide material (430, 530, 630, 730), a semiconductor material (432, 532, 632, 732, 832, 932), and a first nitride material (433, 533, 633, 733, 833) in repeated iterations to form a vertical stack, wherein the semiconductor material (432, 532, 632, 732, 832, 932) includes a low doped semiconductor material to form a first source / drain region (475, 575, 675, 775, 875, 975) and a second source / drain region (778, 878, 932) laterally separated by a channel region; forming a vertical opening (471) to expose a vertical sidewall in the vertical stack using a first etchant process; selectively etching the first nitride material (433, 533, 633, 733, 833) to form a first horizontal opening (473) having a first height (H1) and recessing the first nitride material (433, 533, 633, 733, 833) from the vertical opening (471) formed by the repeating layers by a first distance (D1) (476); vapor phase doping a dopant in a top surface of the low doped semiconductor material (432, 532, 632, 732, 832, 932) to form the first source / drain region (475, 575, 675, 775, 875, 975); depositing a conductive material (477, 577, 677, 777, 877) onto a top surface of the low doped semiconductor material over the first source / drain region (475, 575, 675, 775, 875, 975) under the laterally recessed first nitride material (433, 533, 633, 733, 833); selectively etching the conductive material (477, 577, 677, 777, 877), the first source / drain region (475, 575, 675, 775, 875, 975), and a first portion of the low doped semiconductor material (432, 532, 632, 732, 832, 932) under the first source / drain region (475, 575, 675, 775, 875, 975) via the vertical opening leaving a portion of the conductive material (477, 577, 677, 777, 877) over the first source / drain region (475, 575, 675, 775, 875, 975) to form a second horizontal opening (472) having a second distance (482) from the vertical opening (471); depositing a second nitride material (474, 574, 674, 774, 874) having a second height (H2) and laterally adjacent to the conductive material (477, 577, 677, 777, 877) and the first source / drain region (475, 575, 675, 775, 875, 975) in the second horizontal opening (472); and vertically etching the stack to maintain the vertical opening (471) and expose a sidewall to a second nitride material (474, 574, 674, 774, 874), a second portion of the low doped semiconductor material (432, 532, 632, 732, 832, 932), and the oxide material (430, 530, 630, 730) to form a body contact region to prevent source / drain leakage and hole formation in the horizontally oriented access devices.

10. The method of claim 9, wherein forming the first source / drain region comprises depositing a high concentration n-type dopant (n+) phosphorus (P) material into the top surface of a low doped p-type (p-) semiconductor material.

11. The method of claim 9, further comprising selectively etching the first nitride material using an atomic layer deposition (ALE) process.

12. The method of claim 9, further comprising depositing a highly doped p-type (p+) polysilicon semiconductor material into the vertical opening to form a direct electrical body contact to only the second portion of the low doped semiconductor material.

13. The method of claim 12, further comprising forming the second horizontal opening to have a second height (H2) that is greater than the first height (HI) of the second nitride material.

14. The method of claim 12, further comprising depositing the second nitride material to block diffusion between the highly doped p-type (p+) semiconductor material and the first source / drain region.

15. The method of claim 9, further comprising depositing a conductive material into the vertical opening to form a conductive body contact to only the second portion of the low doped semiconductor material.

16. The method of claim 15, further comprising depositing the conductive material comprising a highly doped (p+) polysilicon germanium (SiGe) material.

17. The method of claim 15, further comprising depositing a composition material that is a highly doped (p+) polysilicon (Si) layer in electrical contact with the low doped semiconductor material, a titanium / titanium nitride (Ti / TiN) layer on the highly doped (p+) polysilicon (Si) layer to form titanium silicide, and a tungsten (W) material to form the conductive body contact.

18. A memory device having vertically stacked memory cells and horizontally oriented access devices and vertically oriented access lines, comprising: a vertically stacked memory cell array comprising: a horizontally oriented access device having first source / drain regions (475, 575, 675, 775, 875, 975) and second source / drain regions (778, 878, 932) separated by a channel region, and a gate opposite the channel region and separated therefrom by a gate dielectric (538, 638, 738, 838); a vertically oriented access line coupled to the gate and separated from the channel region by the gate dielectric (538, 638, 738, 838); a horizontally oriented digit line electrically coupled to the first source / drain regions (475, 575, 675, 775, 875, 975) of the horizontally oriented access device; and a vertical body contact formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separated from the first source / drain regions (475, 575, 675, 775, 875, 975) and the horizontally oriented digit line by a dielectric. ​ 19. The memory device of claim 18, wherein the dielectric further separates a first portion of the body region of the horizontally oriented access device from the vertical body contact to reduce hole formation between the vertical body contact and the body region in the body region.

20. The memory device of claim 18, dielectric further separates a first portion of the body region of the horizontally oriented access device from the vertical body contact to reduce gate induced drain leakage (GIDL) in the horizontally oriented access device.

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