Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor packaging device and a manufacturing method thereof. By adopting a Face up method to combine an active surface of an electronic component to a carrier plate, covering the active surface of the electronic component with a metal sacrificial layer, and then molding, the metal sacrificial layer is polished to expose the metal sacrificial layer arranged on the active surface of the electronic component, the conductive pads exposed by the active surface of the electronic component are removed after the metal sacrificial layer, and a redistribution layer is continuously formed. Since no conductive pillars are formed, the cost of forming the conductive pillars can be reduced. The non-active surface of the electronic component is not provided with a molding layer and does not need to be polished separately, which can reduce the cost of polishing the molding layer of the non-active surface of the electronic component. Since the Face up method is adopted, the flip-chip process is not required, which can improve the UPH and further reduce the overall manufacturing cost of the product.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to semiconductor packaging apparatus and manufacturing methods thereof. Background Technology

[0002] Current fan-out semiconductor packaging devices are manufactured using two methods: chip-first and chip-last, to enable signal connections between the chip and the redistribution layer (RDL) and effectively improve the electrical performance of the product. The chip-first method is further divided into face-up and face-down approaches.

[0003] like Figure 1A and 1B As shown, Figure 1A This is a schematic diagram of the longitudinal cross-sectional structure of a chip used in the existing chip fabrication process, where the chip is fabricated with the active side facing up. Figure 1B This is a schematic diagram of a longitudinal cross-sectional structure of the chip after molding, during the chip fabrication process using the chip-first (face-up) method in existing technologies. Figure 1A As shown, conductive pillars (e.g., copper studs) 12 are formed on the active surface of chip 11. After subsequent molding, a molding layer 23 is formed covering chip 11 and conductive pillars 12, and as shown... Figure 1B As shown, the active surface of chip 11 is ground to expose the chip I / O, i.e., the conductive pillars 12 formed on the active surface of chip 11. RDLs can then be formed to obtain a fan-out semiconductor package device, but the manufacturing cost of the conductive pillars 12 is relatively high during this process.

[0004] like Figure 1C and 1D As shown, Figure 1C This is a schematic diagram of the longitudinal cross-sectional structure of a chip used in the existing chip manufacturing process, where the chip is fabricated with the active side facing down. Figure 1D This is a schematic diagram of the longitudinal cross-sectional structure of the chip after molding, during the chip fabrication process using a chip-first, face-down orientation in existing technologies. (Example:) Figure 1CAs shown, using the face-down method, the active side of chip 11 is positioned downwards and molded to form a molding layer 23 covering the non-active side of chip 11. This process can achieve the connection between chip I / O and RDL without forming conductive pillars. However, heat accumulates on the non-active side of chip 11 and needs to be dissipated, i.e., the non-active side of chip 11 needs to be exposed for heat dissipation. Furthermore, as... Figure 1D As shown, grinding is required to remove the molding layer 23 on the non-active side of chip 11 to expose the non-active side for heat dissipation. However, the additional grinding process increases manufacturing costs, and the molding layer 23 produced using the facedown method constitutes a large proportion of the product. Due to the significant difference in the coefficient of thermal expansion (CTE) between the molding layer 23 and chip 11, the product will warp considerably after debonding, making subsequent operations difficult. Even if warpage adjustment is used, internal stress can cause wire breakage and functional damage. Furthermore, since the facedown method requires placing the active side of the chip face down on the carrier, a flip-chip process is necessary to make the active side face up for the redistribution layer. This additional flip-chip process reduces the overall UPH (Units Per Hour), indirectly increasing product manufacturing costs. Summary of the Invention

[0005] This disclosure presents a semiconductor packaging apparatus and a method for manufacturing the same.

[0006] In a first aspect, this disclosure provides a semiconductor packaging apparatus, comprising:

[0007] Electronic components;

[0008] A conductive pad is disposed on the active surface of the electronic component and its surface does not protrude from the active surface of the electronic component.

[0009] A molding layer covers the active surface of the electronic component but does not cover the conductive pad;

[0010] A redistribution layer is disposed on the active surface of the electronic component and electrically connected to the conductive pad.

[0011] In some alternative embodiments, the electronic component has a positioning mark disposed in a positioning area adjacent to the active surface of the electronic component and the portion of the active surface of the electronic component corresponding to the positioning area contacts the molding layer.

[0012] In some alternative embodiments, the molding layer has a cutout molding layer disposed between the active surface of the electronic component and the redistribution layer.

[0013] In some alternative embodiments, the distance between the first surface of the molding layer adjacent to the active surface of the electronic component and the non-active surface of the electronic component is greater than the distance between the active surface and the non-active surface of the electronic component.

[0014] In some optional embodiments, the semiconductor packaging device further includes:

[0015] A shielding layer is disposed on at least one side of the electronic component.

[0016] In some alternative implementations, the shielding layer contacts the sidewall of the electronic component.

[0017] In some alternative implementations, the shielding layer contacts the active surface of the electronic component.

[0018] In some alternative implementations, the shielding layer is electrically connected to the grounding line of the redistribution layer.

[0019] In some optional embodiments, the semiconductor packaging device further includes:

[0020] An electrical connector is disposed on the surface of the redistribution layer away from the electronic component.

[0021] Secondly, this disclosure provides a method for manufacturing a semiconductor packaging device, comprising:

[0022] Electronic components are bonded to a carrier board, and the active surface of the electronic components is provided with a conductive pad, the surface of which does not protrude from the active surface of the electronic components.

[0023] A metal sacrificial layer is formed on the active surface of the electronic component, wherein the metal sacrificial layer covers the conductive pad;

[0024] Molding to form a molding layer, and grinding the molding layer to expose the metal sacrificial layer;

[0025] Remove the metal sacrificial layer to expose the conductive pad;

[0026] A redistribution layer is formed on the surface of the molding layer and the active surface of the electronic component to electrically connect the redistribution layer to the conductive pad.

[0027] In some alternative embodiments, forming a metal sacrificial layer on the active surface of the electronic component includes:

[0028] The metal sacrificial layer is formed on the active surface and sidewalls of the electronic component.

[0029] To address the issues of high cost associated with forming conductive pillars on the active side of the chip in the chip-first fan-out semiconductor packaging process, and high cost associated with grinding the molding layer on the non-active side of the chip in the face-up method, this disclosure provides a semiconductor packaging apparatus and its manufacturing method. This method uses a face-up approach to bond the active side of the electronic component to a carrier substrate, then covers the active side with a metal sacrificial layer before molding. Grinding is then performed to expose the metal sacrificial layer on the active side, followed by removal of the sacrificial layer to expose the conductive pads on the active side, and finally, the formation of a redistribution layer. Since no conductive pillars are formed, the cost of forming conductive pillars is reduced. Furthermore, the non-active side of the electronic component does not have a molding layer and does not require separate grinding, reducing the cost of grinding the molding layer on the non-active side. Because a face-up approach eliminates the need for flip-chip bonding, the up-needle time (UPH) is increased, further reducing the overall manufacturing cost of the product. Attached Figure Description

[0030] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0031] Figure 1A This is a schematic diagram of the longitudinal cross-sectional structure of a chip used in the existing technology of chip fabrication with the active side facing upwards.

[0032] Figure 1B This is a schematic diagram of a longitudinal cross-sectional structure of a chip after molding, which is being ground during the chip fabrication process in the prior art, where the chip is first manufactured with the active side facing upwards.

[0033] Figure 1C This is a schematic diagram of the longitudinal cross-sectional structure of a chip used in the existing technology of chip fabrication with the active side facing down.

[0034] Figure 1D This is a schematic diagram of a longitudinal cross-sectional structure of a chip after molding, which is being ground during the chip fabrication process where the active side is facing down, in the existing technology.

[0035] Figure 2A-1 This is a longitudinal cross-sectional structural schematic diagram of an embodiment 2a of the semiconductor packaging apparatus according to the present disclosure;

[0036] Figure 2A-2 This is a dimension marking diagram of D1 and D2 in one embodiment 2a of the semiconductor packaging apparatus according to the present disclosure;

[0037] Figure 2A-3This is a schematic diagram of the longitudinal cross-sectional structure of the cut-out mold sealing layer in one embodiment 2a of the semiconductor packaging apparatus according to the present disclosure;

[0038] Figure 2A-4 This is a schematic diagram of the longitudinal cross-sectional structure of the shielding layer in an embodiment 2a of the semiconductor packaging apparatus according to the present disclosure;

[0039] Figure 2B This is a longitudinal cross-sectional structural schematic diagram of an embodiment 2b of the semiconductor packaging apparatus according to the present disclosure;

[0040] Figure 3A-3N These are longitudinal cross-sectional structural diagrams of semiconductor packaging devices 3a-3n manufactured at various stages according to the method for manufacturing semiconductor packaging devices disclosed herein.

[0041] Symbol explanation:

[0042] 11-Chip; 12-Conductive pillar; 21-Electronic component; 21a-Active surface of electronic component; 21b-Non-active surface of electronic component; 211-Positioning mark; 212-Positioning area; 22-Conductive pad; 23-Molding layer; 23a-First surface; 231-Cut molding layer; 24-Rewiring layer; 25-Shielding layer; 26-Electrical connector; 27-First carrier board; 28-Temporary protective material; 29-Second carrier board; 30-Metal sacrificial layer; D1-Distance between the first surface 23a of the molding layer 23 adjacent to the active surface 21a of electronic component 21 and the non-active surface 21b of electronic component 21; D2-Distance between the active surface 21a and the non-active surface 21b of electronic component 21. Detailed Implementation

[0043] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0044] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0045] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0046] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0047] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

[0048] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0049] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0050] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0051] refer to Figure 2A-1 , Figure 2A-2 , Figure 2A-3 and Figure 2A-4 , Figure 2A-1 This is a longitudinal cross-sectional structural schematic diagram of an embodiment 2a of the semiconductor packaging apparatus according to the present disclosure. Figure 2A-2 This is a dimension marking diagram of D1 and D2 according to an embodiment 2a of the semiconductor packaging apparatus of this disclosure. Figure 2A-3 This is a schematic diagram of the longitudinal cross-sectional structure of the notched molding layer in one embodiment 2a of the semiconductor packaging apparatus according to the present disclosure. Figure 2A-4 This is a schematic diagram of the longitudinal cross-sectional structure of the shielding layer in an embodiment 2a of the semiconductor packaging apparatus according to the present disclosure.

[0052] like Figure 2A-1 , Figure 2A-2 , Figure 2A-3 and Figure 2A-4 As shown, the semiconductor packaging device 2a includes: an electronic component 21, a conductive pad 22, a molding layer 23, and a redistribution layer 24. Wherein:

[0053] The conductive pad 22 is disposed on the active surface 21a of the electronic component 21, and the surface of the conductive pad 22 does not protrude from the active surface 21a of the electronic component 21.

[0054] The molding layer 23 covers the active surface 21a of the electronic component 21 but does not cover the conductive pad 22.

[0055] The redistribution layer 24 is disposed on the active surface 21a of the electronic component 21 and is electrically connected to the conductive pad 22.

[0056] Here, electronic component 21 can be various active components, such as various chips, including but not limited to logic function chips, memory chips, communication chips, microprocessor chips, graphics chips, micro-electro-mechanical system (MEMS) chips, radio frequency chips, die or chip-scale packages, inserts or combinations thereof.

[0057] The conductive pad 22 can be formed of various conductive materials, such as gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu) or their alloys.

[0058] The molding layer 23 can be formed from various molding compounds. For example, molding compounds may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0059] The redistribution layer 24 can be a redistribution layer composed of conductive and dielectric materials. It should be noted that the fabrication process can employ currently known or future-developed redistribution layer formation technologies, and this disclosure does not specifically limit this. For example, redistribution layer 24 can be formed using methods including, but not limited to, photolithography, electroplating, and electroless plating. Here, the dielectric material can include organic and / or inorganic materials. Organic materials can be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0060] In some alternative embodiments, the electronic component 21 may have a positioning mark 211 disposed in the positioning region 212. The positioning region 212 is adjacent to the active surface 21a of the electronic component 21, and the active surface 21a of the electronic component 21 partially contacts the molding seal layer 23 of the positioning region 212. Thus, during the reconciliation of the electronic component 21 with the conductive pad 22 to the carrier board, the positioning mark 211 can be used to assist in the positioning of the electronic component 21, thereby improving the accuracy of the reconciliation.

[0061] In some alternative implementations, such as Figure 2A-3 As shown, the molding layer 23 may have a cut-out molding layer 231 disposed between the active surface 21a of the electronic component 21 and the redistribution layer 24. This is because a metal sacrificial layer was previously formed on the active surface 21a of the electronic component 21, and the metal sacrificial layer covers the conductive pad 22. That is, it can be understood that the metal sacrificial layer protrudes from the active surface 21a of the electronic component 21. Subsequently, the molding layer 23 is formed on this basis, and the molding layer 23 is ground to expose the metal sacrificial layer, so that the surface of the molding layer 23 is higher than the active surface 21a of the electronic component 21. And since the metal sacrificial layer is subsequently removed and the redistribution layer 24 is formed on the surface of the molding layer 23 and the active surface 21a of the electronic component 21, the molding layer 23 held between the active surface 21a of the electronic component 21 and the redistribution layer 24 forms a cut-out molding layer 231.

[0062] In some alternative implementations, such as Figure 2A-2 As shown, the distance D1 between the first surface 23a of the molding layer 23 adjacent to the active surface 21a of the electronic component 21 and the non-active surface 21b of the electronic component 21 is greater than the distance D2 between the active surface 21a and the non-active surface 21b of the electronic component 21. Similarly, this is also due to the manufacturing method described in the optional embodiments above.

[0063] In some alternative implementations, such as Figure 2A-4 As shown, the semiconductor packaging device 2a may further include a shielding layer 25. The shielding layer 25 is disposed on at least one side of the electronic component 21 and is used to shield electromagnetic signals between the electronic component 21 and the outside world. In this way, the shielding effect of the semiconductor packaging device 2a can be improved.

[0064] In some alternative implementations, the shielding layer 25 may contact the sidewall of the electronic component 21, thereby further improving the shielding effect.

[0065] In some alternative implementations, the shielding layer 25 may be electrically connected to the grounding line of the redistribution layer 24 to facilitate shielding.

[0066] In some alternative implementations, such as Figure 2A-1 ,2A-2 As shown in 2A-3 and 2A-4, the semiconductor packaging device 2a may further include an electrical connector 26 disposed on the surface of the redistribution layer 24 away from the electronic component 21. This enables electrical connection between the semiconductor packaging device 2a and external components.

[0067] The following is for reference. Figure 2B , Figure 2B This is a longitudinal cross-sectional structural schematic diagram of an embodiment 2b of the semiconductor packaging apparatus according to the present disclosure. Figure 2B The semiconductor packaging device 2b shown is similar to Figure 2A-1 , 2A-2 The semiconductor packaging device 2a shown in 2A-3 and 2A-4 differs in that the shielding layer 25 can also contact the active surface 21a of the electronic component 21. That is, the shielding layer 25 can be disposed not only on the outer wall of the electronic component 21 but also on the active surface 21a of the electronic component 21, thereby further improving the shielding effect of the product.

[0068] The following is for reference. Figure 3A-3N , Figure 3A-3N These are longitudinal cross-sectional structural diagrams of semiconductor packaging devices 3a-3n manufactured at various stages according to the method for manufacturing semiconductor packaging devices according to this disclosure. The figures have been simplified for better understanding of the aspects of this disclosure.

[0069] refer to Figure 3A The strip-shaped electronic component 21 is placed on the first carrier plate 27.

[0070] The active surface 21a of the electronic component 21 may be provided with a conductive pad 22, and the surface of the conductive pad 22 does not protrude from the active surface 21a of the electronic component 21. Optionally, a positioning mark 211 may be provided adjacent to the active surface 21a of the electronic component 21.

[0071] refer to Figure 3B Cut strip-shaped electronic components 21 to form independent electronic components 21.

[0072] refer to Figure 3C The wafer is expanded to increase the spacing between two adjacent electronic components 21.

[0073] refer to Figure 3D Temporary protective material 28 is provided on the positioning mark 211 provided on the active surface 21a of the electronic component 21.

[0074] refer to Figure 3E A metal sacrificial layer 30 is formed on the active surface 21a of the electronic component 21, and the metal sacrificial layer 30 covers the conductive pad 22.

[0075] The methods for forming the metal sacrificial layer 30 can include, but are not limited to, sputtering, plating, electroless plating, printing, lamination, potting, coating, etc.

[0076] Optionally, a metal sacrificial layer 30 may be formed on the active surface 21a and sidewall of the electronic component 21.

[0077] refer to Figure 3F Remove the temporary protective material 28 set on the positioning mark 211.

[0078] refer to Figure 3G Each electronic component 21 is taken from the first carrier 27 and placed on the second carrier 29.

[0079] refer to Figure 3H The molding process forms a molding layer 23.

[0080] refer to Figure 3I The grinding mold seal layer 23 is used to expose the metal sacrificial layer 30.

[0081] refer to Figure 3J Remove the metal sacrificial layer 30 to expose the conductive pad 22.

[0082] The manufacturing method can be, for example, but not limited to, dry engraving or wet engraving, to remove the metal sacrificial layer 30.

[0083] refer to Figure 3K Remove the second carrier plate 29.

[0084] refer to Figure 3L A redistribution layer 24 is formed on the surface of the molding layer 23 and the active surface 21a of the electronic component 21, so that the redistribution layer 24 is electrically connected to the conductive pad 22.

[0085] refer to Figure 3M They are cut to form independent semiconductor packaging devices.

[0086] refer to Figure 3N Electrical connectors 26 are formed on the surface of redistribution layer 24 in a separate semiconductor packaging device.

[0087] Here, the electrical connector 26 can be, for example, a pad, solder ball, or bump. The bump can be, for example, a gold bump, a solder bump, or a pillar bump.

[0088] In the method for manufacturing a semiconductor packaging device provided in this embodiment, the active side of the electronic component is bonded to the carrier board using the face-up method. After covering the active side of the electronic component with a metal sacrificial layer, it is molded. Then, it is ground to expose the metal sacrificial layer on the active side of the electronic component. After removing the metal sacrificial layer, the conductive pads on the active side of the electronic component are exposed, and a redistribution layer is formed. Since no conductive pillars are formed, the cost of forming conductive pillars can be reduced. In addition, the non-active side of the electronic component does not have a molding layer and does not need to be ground separately, which can reduce the cost of grinding the molding layer on the non-active side of the electronic component. Since the face-up method is used, there is no need for flip-chip processing, which can improve UPH and further reduce the overall manufacturing cost of the product.

[0089] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A method for manufacturing a semiconductor packaging device, comprising: Electronic components are bonded to a carrier board, and the active surface of the electronic components is provided with a conductive pad, the surface of which does not protrude from the active surface of the electronic components. Temporary protective material is applied to the positioning marks on the active surface of the electronic component; A metal sacrificial layer is formed on the active surface and sidewall of the electronic component, wherein the metal sacrificial layer covers the conductive pad; Remove the temporary protective material; Molding to form a molding layer, and grinding the molding layer to expose the metal sacrificial layer; A portion of the metal sacrificial layer is removed to expose the conductive pad, while the remaining metal sacrificial layer serves as a shielding layer that contacts the active surface of the electronic component. A redistribution layer is formed on the surface of the molding layer and the active surface of the electronic component to electrically connect the redistribution layer to the conductive pad.

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