Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The method includes: providing a substrate with a gate structure, having a gate capping layer on top of the gate structure, source / drain doping regions in the substrate on both sides of the gate structure, a bottom dielectric layer on the substrate, the substrate including a shared contact region for forming a shared contact plug, the source / drain doping region located in the shared contact region being a first source / drain doping region, and the rest being a second source / drain doping region; forming a first source / drain interconnect layer connected to the second source / drain doping region and a source / drain capping layer on top of the first source / drain interconnect layer in the bottom dielectric layer; forming a second source / drain interconnect layer connected to the first source / drain doping region in the bottom dielectric layer; forming a top dielectric layer covering the gate capping layer, the source / drain capping layer, the second source / drain interconnect layer, and the bottom dielectric layer; and forming a shared contact plug penetrating through the top dielectric layer and the gate capping layer in the shared contact region. The present invention reduces the difficulty of forming the shared contact plug and improves the performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, the requirements for the integration and performance of integrated circuits have become increasingly high. In order to improve the integration and reduce the cost, the critical dimensions of components are continuously reduced, and the circuit density inside the integrated circuit is getting larger and larger. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnect lines.

[0003] To meet the requirements of the interconnect lines after the critical dimensions are reduced, the current conduction between different metal layers or between a metal layer and a substrate is achieved through an interconnect structure. The interconnect structure includes interconnect lines and contact hole plugs formed in contact openings. The contact hole plugs are connected to semiconductor devices, and the interconnect lines realize the connection between the contact hole plugs, thereby forming a circuit.

[0004] The contact hole plugs in the transistor structure include gate contact hole plugs located on the surface of the gate structure for connecting the gate structure to an external circuit, source / drain contact hole plugs located on the surface of the source / drain doped regions for connecting the source / drain doped regions to an external circuit, and also include shared contact plugs (share contact) for electrically connecting the gate and the source / drain doped regions.

[0005] Currently, in order to further reduce the area of the transistor, the Contact Over Active Gate (COAG) process is introduced. Compared with the traditional gate contact hole plugs located above the gate structure in the isolation region, the COAG process can place the gate contact hole plugs above the gate structure in the Active Area (AA), thereby further saving the chip area. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which can reduce the difficulty of forming the shared contact plugs while improving the performance of the semiconductor structure.

[0007] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, on which a gate structure is formed, a gate capping layer is formed on the top of the gate structure, source / drain doping regions are formed in the substrate on both sides of the gate structure, a bottom dielectric layer is formed on the substrate on the side of the gate structure, and the bottom dielectric layer covers the sidewalls of the gate structure and the gate capping layer, wherein a region on the substrate for forming a shared contact plug for electrically connecting the gate structure and the source / drain doping regions is used as a shared contact region, the source / drain doping region located in the shared contact region is used as a first source / drain doping region, and the remaining source / drain doping regions are used as second source / drain doping regions; forming a first source / drain interconnect layer connected to the second source / drain doping region in the bottom dielectric layer on the top of the second source / drain doping region, and a source / drain capping layer located on the top of the first source / drain interconnect layer; forming a second source / drain interconnect layer connected to the first source / drain doping region in the bottom dielectric layer on the top of the first source / drain doping region; forming a top dielectric layer covering the gate capping layer, the source / drain capping layer, the second source / drain interconnect layer and the bottom dielectric layer; in the shared contact region, forming a shared contact plug penetrating through the top dielectric layer and the gate capping layer, and the shared contact plug electrically connects the gate structure and the second source / drain interconnect layer.

[0008] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate, on which a gate structure is formed, a gate capping layer is formed on the top of the gate structure, source / drain doping regions are formed in the substrate on both sides of the gate structure, a bottom dielectric layer is formed on the substrate on the side of the gate structure, and the bottom dielectric layer covers the sidewalls of the gate structure and the gate capping layer, wherein a region on the substrate for forming a shared contact plug for electrically connecting the gate structure and the source / drain doping regions is used as a shared contact region, the source / drain doping region located in the shared contact region is used as a first source / drain doping region, and the remaining source / drain doping regions are used as second source / drain doping regions; a first source / drain interconnect layer, located in the bottom dielectric layer on the top of the second source / drain doping region and connected to the second source / drain doping region, and the top of the first source / drain interconnect layer is lower than the top of the gate capping layer; a source / drain capping layer, located in the region surrounded by the top of the first source / drain interconnect layer and the bottom dielectric layer; a second source / drain interconnect layer, penetrating through the bottom dielectric layer on the top of the first source / drain doping region; a top dielectric layer, covering the gate capping layer, the source / drain capping layer, the second source / drain interconnect layer and the bottom dielectric layer.

[0009] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0010] In the formation method provided by the embodiment of the present invention, a first source / drain interconnect layer connected to the second source / drain doped region and a source / drain capping layer located on top of the first source / drain interconnect layer are formed in the bottom dielectric layer on top of the second source / drain doped region, and a second source / drain interconnect layer connected to the first source / drain doped region is formed in the bottom dielectric layer on top of the first source / drain doped region; subsequently, in the process of forming a shared contact plug that penetrates the top dielectric layer and the gate capping layer in the shared contact region, the step of forming the shared contact plug includes etching the top dielectric layer and the gate capping layer in the shared contact region to form a shared contact hole exposing the gate structure and the second source / drain interconnect layer. Since there is no source / drain capping layer formed on top of the second source / drain interconnect layer, when forming the shared contact hole, there is no need to etch the source / drain capping layer, thereby reducing the difficulty of the etching process used to form the shared contact plug, correspondingly reducing the formation difficulty of the shared contact plug. Moreover, this is conducive to shortening the process time required to form the shared contact hole, thereby reducing the influence of lateral etching on the top dielectric layer, ensuring the cross-sectional shape and opening size of the shared contact hole, correspondingly reducing the probability of the shared contact hole exposing adjacent other gate structures or the first source / drain interconnect layer, and thus reducing the probability of short circuit between the shared contact plug and adjacent other gate structures or the first source / drain interconnect layer, and further improving the performance of the semiconductor structure. Description of the Drawings

[0011] Figures 1 to 4 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure;

[0012] Figures 5 to 19 is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention. Detailed Embodiments

[0013] After the introduction of the Contact Over Active Gate (COAG) process, the formation difficulty of the shared contact plug is relatively high, and the process risk is relatively high. Now, in combination with a semiconductor structure, the reasons for the relatively high formation difficulty and process risk of the shared contact plug are analyzed.

[0014] Figures 1 to 4 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure.

[0015] Reference Figure 1, a substrate 10 is provided, on which a gate structure 20 is formed. A gate capping layer 21 is formed on top of the gate structure 20. Source / drain doping regions 30 are formed in the substrate 10 on both sides of the gate structure 20. A bottom dielectric layer (not shown in the figure) is formed on the substrate 10 on the side of the gate structure 20, and the bottom dielectric layer covers the sidewalls of the gate structure 20 and the gate capping layer 21. A source / drain interconnect layer 31 is formed in the bottom dielectric layer on top of the source / drain doping regions 30, and a source / drain capping layer 32 is located on top of the source / drain interconnect layer 31.

[0016] Among them, the area on the substrate 10 for forming a shared contact plug (share contact) that electrically connects the gate structure 20 and the source / drain doping regions 30 is used as a shared contact region (not labeled).

[0017] Continue to refer to Figure 1 , a top dielectric layer 40 is formed to cover the gate capping layer 21 and the source / drain capping layer 32.

[0018] Subsequently, a gate plug that penetrates the top dielectric layer 40 and the gate capping layer 21 is formed on top of the gate structure 20, and the gate plug is formed on the active region. The gate plug is a Contact Over Active Gate (COAG). Moreover, a source / drain plug that penetrates the top dielectric layer 30 and the source / drain capping layer 32 is formed on top of the source / drain interconnect layer 31.

[0019] In the COAG process, in order to reduce the probability of bridging between the source / drain plug and the gate structure 20, and between the gate plug and the source / drain interconnect layer 31, there is a high etch selectivity between the gate capping layer 21 and the source / drain capping layer 32. Thus, during the formation of the gate plug, the source / drain capping layer 32 can protect the source / drain interconnect layer 31, and during the formation of the source / drain plug, the gate capping layer 21 can protect the gate structure 20.

[0020] According to the design requirements, during the formation of the semiconductor structure, not only a source / drain plug needs to be formed on top of the source / drain interconnect layer 31 and a gate plug needs to be formed on top of the gate structure 20, but also a shared contact plug (share contact) that electrically connects the gate structure 20 and the source / drain interconnect layer 31 needs to be formed.

[0021] Combined with reference Figures 2 to 4 , in the shared contact region, a shared contact plug 60 that penetrates the top dielectric layer 40, the gate capping layer 21, and the source / drain capping layer 32 is formed (as shown in Figure 4 ), and the shared contact plug 60 is in contact with the gate structure 20 and the source / drain interconnect layer 31.

[0022] Specifically, the steps of forming the shared contact plug 50 include: as Figure 2 shown, etching the top dielectric layer 40 of the shared contact region to form an opening 41 exposing the gate capping layer 21 and the source / drain capping layer 32; as Figure 3 shown, etching the gate capping layer 21 and the source / drain capping layer 32 at the bottom of the opening 41 to form a shared contact hole 50 penetrating through the top dielectric layer 40, the gate capping layer 21, and the source / drain capping layer 32, and the shared contact hole 50 exposes the gate structure 20 and the source / drain interconnect layer 31; as Figure 4 shown, forming a shared contact plug 60 in the shared contact hole 50.

[0023] Since there is a high etching selectivity between the gate capping layer 21 and the source / drain capping layer 32, after etching the top dielectric layer 40, different etching processes are required to etch the gate capping layer 21 and the source / drain capping layer 32 respectively. During the process of etching the gate capping layer 21 and the source / drain capping layer 32, the opening 41 in the top dielectric layer 40 is easily affected by lateral etching, thereby having an adverse effect on the cross-sectional morphology of the opening 41, and even causing the problem that the size of the opening 41 becomes larger. Furthermore, it is easy to cause mis-etching of adjacent other gate capping layers 21 or source / drain capping layers 32, correspondingly increasing the probability of short circuit between the shared contact plug 60 and adjacent other gate structures 20 or source / drain interconnect layers 31.

[0024] Therefore, currently, the formation of the shared contact plug 60 is difficult, and it is easy to cause a decline in the performance of the semiconductor structure.

[0025] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, on which a gate structure is formed, a gate capping layer is formed on the top of the gate structure, source / drain doping regions are formed in the substrate on both sides of the gate structure, a bottom dielectric layer is formed on the substrate on the side of the gate structure, and the bottom dielectric layer covers the sidewalls of the gate structure and the gate capping layer. Among them, the area on the substrate for forming a shared contact plug for electrically connecting the gate structure and the source / drain doping regions is used as a shared contact area, the source / drain doping region located in the shared contact area is used as a first source / drain doping region, and the remaining source / drain doping regions are used as second source / drain doping regions; forming a first source / drain interconnect layer connected to the second source / drain doping region and a source / drain capping layer located on the top of the first source / drain interconnect layer in the bottom dielectric layer on the top of the second source / drain doping region; forming a second source / drain interconnect layer connected to the first source / drain doping region in the bottom dielectric layer on the top of the first source / drain doping region; forming a top dielectric layer covering the gate capping layer, the source / drain capping layer, the second source / drain interconnect layer and the bottom dielectric layer; in the shared contact area, forming a shared contact plug penetrating the top dielectric layer and the gate capping layer, and the shared contact plug electrically connects the gate structure and the second source / drain interconnect layer.

[0026] In the forming method provided by the embodiment of the present invention, a first source / drain interconnect layer connected to the second source / drain doping region and a source / drain capping layer located on the top of the first source / drain interconnect layer are formed in the bottom dielectric layer on the top of the second source / drain doping region, and a second source / drain interconnect layer connected to the first source / drain doping region is formed in the bottom dielectric layer on the top of the first source / drain doping region; subsequently, in the process of forming a shared contact plug penetrating the top dielectric layer and the gate capping layer in the shared contact area, the step of forming the shared contact plug includes etching the top dielectric layer and the gate capping layer in the shared contact area to form a shared contact hole exposing the gate structure and the second source / drain interconnect layer. Since no source / drain capping layer is formed on the top of the second source / drain interconnect layer, when forming the shared contact hole, there is no need to etch the source / drain capping layer, thereby reducing the difficulty of the etching process used for forming the shared contact plug, correspondingly reducing the forming difficulty of the shared contact plug. Moreover, this is beneficial to shortening the process time required for forming the shared contact hole, thereby reducing the influence of lateral etching on the top dielectric layer, ensuring the cross-sectional shape and opening size of the shared contact hole, correspondingly reducing the probability that the shared contact hole exposes adjacent other gate structures or the first source / drain interconnect layer, and thus reducing the probability of short circuit between the shared contact plug and adjacent other gate structures or the first source / drain interconnect layer, and further improving the performance of the semiconductor structure.

[0027] To make the above objects, features and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0028] Figures 5 to 19 FIG. 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0029] Referring to Figures 5 to 6 , Figure 5 FIG. 2 is a top view, Figure 6 and Figure 5 FIG. 3 is a cross-sectional view along the cutting line A1A2. A substrate (not labeled) is provided. A gate structure 200 is formed on the substrate. A gate capping layer 240 is formed on the top of the gate structure 200. Source / drain doping regions 210 are formed in the substrate on both sides of the gate structure 200. A bottom dielectric layer 101 is formed on the substrate on the side of the gate structure 200. The bottom dielectric layer 101 covers the sidewalls of the gate structure 200 and the gate capping layer 240. Among them, the region on the substrate for forming a shared contact plug (share contact) for electrically connecting the gate structure 200 and the source / drain doping regions 210 is used as a shared contact region 100S. The source / drain doping region 210 located in the shared contact region 100S is used as a first source / drain doping region 210a, and the remaining source / drain doping regions 210 are used as second source / drain doping regions 210b.

[0030] For the convenience of illustration, Figure 2 only the fin portion 210, the gate capping layer 240, and the bottom dielectric layer 101 are schematically shown.

[0031] The substrate is used to provide a process platform for subsequent process steps.

[0032] In this embodiment, the substrate is used to form a fin field-effect transistor (FinFET). Therefore, the substrate includes a substrate 100 and fin portions 110 protruding from the substrate 100. In other embodiments, when the substrate is used to form a planar field-effect transistor, the substrate is correspondingly a planar substrate.

[0033] In this embodiment, the substrate 100 is a silicon substrate.

[0034] In other embodiments, the substrate can also be a substrate of other material types. For example, the material of the substrate can be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0035] In this embodiment, the material of the fin portion 110 is the same as that of the substrate 100.

[0036] In this embodiment, the substrate is used to form SRAM (Static Random Access Memory) devices. According to the design requirements of the SRAM devices, part of the gate structure 200 and the source / drain doping regions 210 need to be electrically connected through shared contact plugs.

[0037] In this embodiment, the region on the substrate for forming the shared contact plugs (share contact) that electrically connect the gate structure 200 and the source / drain doping regions 210 is used as the shared contact region 100S.

[0038] In this embodiment, the gate structure 200 extends along a first direction (as shown by the Y direction in Figure 5 ), and the direction parallel to the surface of the substrate and perpendicular to the first direction is the second direction (as shown by the X direction in Figure 5 ), and the shared contact region 100S extends along the second direction.

[0039] Specifically, the number of the gate structures 200 is multiple, and the multiple gate structures 200 are arranged in parallel along the second direction.

[0040] In this embodiment, the remaining region outside the shared contact region 100S is used as the non-shared contact region 100T (as shown in Figure 6 ). Subsequently, in the non-shared contact region 100T, gate plugs connected to the gate structures 200 one by one, and source / drain plugs connected to the source / drain doping regions 210 one by one are formed.

[0041] In this embodiment, the method for forming the semiconductor structure further includes: after forming the fin 110, forming an isolation layer (not shown in the figure) on the substrate 100 exposed by the fin 110, and the isolation layer covers part of the sidewalls of the fin 110.

[0042] The isolation layer is used to isolate adjacent devices. The material of the isolation layer can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer is silicon nitride.

[0043] In this embodiment, the gate structure 200 is located on the isolation layer, and the gate structure 200 straddles the fin 110 and covers part of the top surface and part of the sidewalls of the fin 110.

[0044] In this embodiment, the gate structure is a device gate structure, and during device operation, the gate structure 200 is used to control the opening or closing of the conductive channel.

[0045] Specifically, the gate structure 200 is a metal gate structure, and the gate structure 200 includes a high-k gate dielectric layer (not shown in the figure), a work function layer (not shown in the figure) located on the high-k gate dielectric layer, and a gate electrode layer (not shown in the figure) located on the work function layer.

[0046] The material of the high-k gate dielectric layer is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon dioxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0047] The work function layer is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or several of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or several of TiAl, Mo, MoN, AlN, and TiAlC.

[0048] The gate electrode layer is used to lead out the electrical property of the gate structure 200. In this embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0049] In this embodiment, the source / drain doping regions 210 are located in the fins 110 on both sides of the gate structure 200.

[0050] Specifically, adjacent gate structures 200 share a source / drain doping region 210.

[0051] When forming an NMOS transistor, the source / drain doping region 210 includes a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, and the stress layer provides a tensile stress effect on the channel region of the NMOS transistor, thereby facilitating the improvement of the carrier mobility of the NMOS transistor. Among them, the N-type ions are P ions, As ions, or Sb ions; when forming a PMOS transistor, the source / drain doping region 210 includes a stress layer doped with P-type ions, the material of the stress layer is Si or SiGe, and the stress layer provides a compressive stress effect on the channel region of the PMOS transistor, thereby facilitating the improvement of the carrier mobility of the PMOS transistor. Among them, the P-type ions are B ions, Ga ions, or In ions.

[0052] In this embodiment, the source / drain doping region 210 located in the shared contact region 100S serves as the first source / drain doping region 210a, and the remaining source / drain doping regions 210 serve as the second source / drain doping regions 210b, that is, the source / drain doping regions 210 located in the non-shared contact region 100T serve as the second source / drain doping regions 210b.

[0053] It should be noted that in this embodiment, a spacer 205 is further formed on the sidewall of the gate structure 200.

[0054] The spacer 205 is used to define the formation region of the source / drain doping region 210, and the spacer 205 is also used to protect the sidewall of the gate structure 200. The spacer 205 can be a single-layer structure or a stacked structure, and the material of the spacer 205 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitroxide, silicon oxynitride, boron nitride, and boron carbonitride.

[0055] As an example, the spacer 205 is a single-layer structure, and the material of the spacer 205 is silicon nitride.

[0056] Subsequently, a first source / drain interconnect layer connected to the second source / drain doping region 210b and a source / drain capping layer located on top of the first source / drain interconnect layer are formed in the bottom dielectric layer 101 on the top of the second source / drain doping region 210b. And after forming the top dielectric layer on the bottom dielectric layer 101, a source / drain plug in contact with the first source / drain interconnect layer is formed on the top of the first source / drain interconnect layer. The gate capping layer 240 is located on the top surface of the gate structure 200 and is used to protect the gate structure 200, thereby reducing the probability of damage to the gate structure 200 and short circuit between the source / drain plug and the gate structure 200 during the formation of the source / drain plug.

[0057] The gate capping layer 240 is selected to be a material having an etching selectivity with respect to the source / drain capping layer, the bottom dielectric layer 101, and the subsequently formed top dielectric layer, thereby facilitating ensuring that the gate capping layer 240 can protect the gate structure 200.

[0058] In this embodiment, the material of the gate capping layer 240 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitroxide, silicon oxynitride, boron nitride, and boron carbonitride.

[0059] As an example, the material of the gate capping layer 240 is silicon nitride.

[0060] The materials of the gate capping layer 240 and the sidewall 205 are the same, which is convenient for subsequent formation of a shared contact hole. When etching the gate capping layer 240, the sidewall 205 can be etched simultaneously, thereby reducing the complexity of the etching process. Moreover, the formation process of the semiconductor structure uses fewer types of film materials, which is also beneficial to reducing the process complexity.

[0061] In other embodiments, different materials may be selected for the gate capping layer and the sidewall.

[0062] In this embodiment, the gate structure 200 is formed by a process of forming a high-k gate dielectric layer first and then a gate electrode layer (high k last metal gate last). Therefore, the sidewall 205 covers the sidewalls of the gate structure 200 and the gate capping layer 240.

[0063] Specifically, after forming the gate structure 200 in the bottom dielectric layer 101, a part of the thickness of the gate structure 200 is etched back; after etching back a part of the thickness of the gate structure 200, a gate capping layer 240 is formed in the region surrounded by the bottom dielectric layer 101 and the remaining gate structure 200.

[0064] Among them, the step of forming the gate capping layer 240 includes the steps of sequentially depositing a gate capping material layer and planarizing the gate capping material layer (for example: chemical mechanical polishing process).

[0065] The bottom dielectric layer 101 is used to isolate adjacent devices.

[0066] Subsequently, a first source / drain interconnect layer in contact with the second source / drain doping region 210b is also formed in the bottom dielectric layer 101 on top of the second source / drain doping region 210b, and a second source / drain interconnect layer connected to the first source / drain doping region 210a is formed in the bottom dielectric layer 101 on top of the first source / drain doping region 210a. The bottom dielectric layer 101 is also used to achieve electrical isolation between the first source / drain interconnect layer and the second source / drain interconnect layer.

[0067] In this embodiment, the bottom dielectric layer 101 is an interlayer dielectric layer (ILD).

[0068] The material of the bottom dielectric layer 101 is an insulating material. The material of the bottom dielectric layer 101 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the bottom dielectric layer 101 is silicon nitride.

[0069] In this embodiment, the tops of the bottom dielectric layer 101, the gate capping layer 240, and the sidewall 205 are all flush.

[0070] Combined reference Figures 7 to 11 A first source-drain interconnect layer 220 connected to the second source-drain doped region 210b and a source-drain capping layer 230 located on top of the first source-drain interconnect layer 220 are formed in the bottom dielectric layer 101 on top of the second source-drain doped region 210b.

[0071] The first source-drain interconnect layer 220 is in contact with the second source-drain doped region 210b and is used to electrically connect the second source-drain doped region 210b to an external circuit or other interconnect structures.

[0072] In this embodiment, a source-drain plug in contact with the first source-drain interconnect layer 220 is formed on the first source-drain interconnect layer 220 later, and the source-drain plug is electrically connected to the second source-drain doped region 210b through the first source-drain interconnect layer 220.

[0073] In this embodiment, the material of the first source-drain interconnect layer 220 is copper. Copper has a low resistivity, which is beneficial to improving the signal delay of the back-end RC, increasing the processing speed of the chip, and at the same time is beneficial to reducing the resistance of the first source-drain interconnect layer 220, thereby reducing the power consumption accordingly. In other embodiments, the material of the first source-drain interconnect layer may also be a conductive material such as tungsten or cobalt.

[0074] After a top dielectric layer is formed on the bottom dielectric layer 101 later, in the non-shared contact region 100T, a gate plug in contact with the gate structure 200 is formed on top of the gate structure 200 in the active area (AA). The source-drain capping layer 230 is located on the top surface of the first source-drain interconnect layer 220 and is used to protect the first source-drain interconnect layer 220 during the formation of the gate plug, which is beneficial to reducing the probability of damage to the first source-drain interconnect layer 220 and short circuit between the gate plug and the first source-drain interconnect layer 220.

[0075] The source-drain capping layer 230 is selected to have a high etch selectivity with respect to the gate capping layer 240, the sidewall 205, the bottom dielectric layer 101, and the subsequently formed top dielectric layer, so as to be beneficial to ensuring that the source-drain capping layer 230 can protect the first source-drain interconnect layer 220.

[0076] In this embodiment, the material of the source-drain capping layer 230 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0077] Specifically, the materials of the source-drain capping layer 230 and the gate capping layer 240 are different, and the materials of the source-drain capping layer 230 and the sidewall 205 are different.

[0078] As an example, the material of the source-drain capping layer 230 is silicon carbide.

[0079] In this embodiment, after forming the gate capping layer 240, the source-drain interconnect layer 220 and the source-drain capping layer 230 are formed, so that under the protection of the gate capping layer 240, the influence of the formation processes of the source-drain interconnect layer 220 and the source-drain capping layer 230 on the gate structure 200 is reduced.

[0080] Specifically, the steps of forming the first source-drain interconnect layer 220 and the source-drain capping layer 230 include: as Figure 7 shown, removing the bottom dielectric layer 101 on the top of the second source-drain doping region 210b to form a first trench 211 exposing the second source-drain doping region 210b; as Figures 8 to 10 shown, forming a first source-drain interconnect layer 220 in the first trench 211, the top of the first source-drain interconnect layer 220 being lower than the top of the bottom dielectric layer 101; as Figure 11 shown, forming a source-drain capping layer 230 in the region surrounded by the bottom dielectric layer 101 and the first source-drain interconnect layer 220.

[0081] The first trench 211 is used to provide a spatial position for forming the first source-drain interconnect layer 220 and the source-drain capping layer 230.

[0082] In this embodiment, a dry etching process (e.g., an anisotropic dry etching process) is used to etch the bottom dielectric layer 101 on the top of the second source-drain doping region 210b. The anisotropic dry etching process has the characteristic of anisotropic etching, which is beneficial to improving the profile controllability of the first trench 211.

[0083] As Figure 7 shown, in this embodiment, the steps of forming the first trench 211 include: forming a first mask layer 300 having a first mask opening 310 on the bottom dielectric layer 101, the first mask opening 310 exposing the bottom dielectric layer 101 on the top of the second source-drain doping region 210b; using the first mask layer 300 as a mask to etch the bottom dielectric layer 101 exposed by the first mask opening 310 to form a first trench 211.

[0084] In this embodiment, after forming the first trench 211, the first mask layer 300 is removed.

[0085] As an example, the material of the first mask layer 300 is photoresist. The first mask layer 300 is formed by photolithography processes such as photoresist coating, exposure, and development.

[0086] Note that, due to the high etching selectivity between the gate capping layer 240 and the bottom dielectric layer 101, and also between the sidewall 205 and the bottom dielectric layer 101, the process window for forming the first mask opening 310 is improved.

[0087] For example, in the second direction, the first mask opening 310 not only exposes the bottom dielectric layer 101 at the top of the second source / drain doping region 210b, but may also expose the sidewall 205, and even the gate capping layer 240.

[0088] In this embodiment, the step of forming the first source / drain interconnect layer 220 in the first trench 211 includes: as Figure 8 shown, filling the first trench 211 with a conductive material 221; as Figure 9 shown, using the top surface of the gate capping layer 240 as the stop position to planarize the conductive material 221; as Figure 10 shown, after the planarization process, performing a re-etching process on the remaining conductive material 221 in the first trench 211, and the remaining conductive material 221 after the re-etching process serves as the first source / drain interconnect layer 220.

[0089] By performing a re-etching process on the remaining conductive material 221 in the first trench 211, the top of the first source / drain interconnect layer 220 is made lower than the top of the bottom dielectric layer 101, thereby reserving space for forming the source / drain capping layer 230.

[0090] In this embodiment, a dry etching process (e.g., an anisotropic dry etching process) is used to perform a re-etching process on the remaining conductive material 221 in the first trench 211.

[0091] The dry etching process is beneficial for precisely controlling the etching thickness of the remaining conductive material 221 in the first trench 211. Correspondingly, it is beneficial for the thickness of the first source / drain interconnect layer 220 to meet the process requirements.

[0092] Correspondingly, the step of forming the source / drain capping layer 230 in the region surrounded by the bottom dielectric layer 101 and the first source / drain interconnect layer 220 includes: filling the remaining space of the first trench 211 with a source / drain capping material layer; using the top surface of the gate capping layer as the stop position to planarize the source / drain capping material layer, and the remaining source / drain capping material layer after the planarization process serves as the source / drain capping layer 230.

[0093] The gate capping layer 240 has a high hardness and density. Therefore, the top surface of the gate capping layer 240 can preferably serve as the stop position for defining the planarization process.

[0094] Specifically, the planarization process can be a chemical mechanical polishing process.

[0095] With reference to Figures 12 to 14 , a second source / drain interconnect layer 260 in contact with the first source / drain doping region 210a is formed in the bottom dielectric layer 101 on top of the first source / drain doping region 210a.

[0096] The first source / drain doping region 210a is located in the shared contact region 100S. Subsequently, a shared contact plug electrically connecting the gate structure 200 and the first source / drain doping region 210a is formed in the shared contact region 100S, and the process of forming the shared contact plug generally includes the step of forming a shared contact hole by an etching process. A gate capping layer 240 is formed on top of the gate structure 200. However, no source / drain capping layer 230 is formed on top of the second source / drain interconnect layer 260. Therefore, during the subsequent process of forming the shared contact plug in the shared contact region 100S, there is no need to etch the source / drain capping layer, thereby reducing the difficulty of the etching process used to form the shared contact plug, correspondingly reducing the difficulty of forming the shared contact plug. Moreover, this is conducive to shortening the process time required to form the shared contact plug, thereby reducing the influence of lateral etching on the top dielectric layer, ensuring the cross-sectional shape and opening size of the shared contact hole, and correspondingly reducing the probability that the shared contact hole exposes adjacent other gate structures 200 or source / drain interconnect layers, thereby improving the performance of the semiconductor structure.

[0097] Among them, in this embodiment, the second source / drain interconnect layer 260 and the first source / drain interconnect layer 220 are respectively formed in different manufacturing processes, with little modification to the current manufacturing process and high process compatibility.

[0098] In this embodiment, the step of forming the second source / drain interconnect layer 260 includes: as Figure 12 shown, removing the bottom dielectric layer 101 on top of the first source / drain doping region 210a to form a second trench 212 exposing the first source / drain doping region 210a; as Figures 13 to 14 shown, forming a second source / drain interconnect layer 260 in the second trench 212.

[0099] The second trench 212 is used to provide a spatial position for forming the second source / drain interconnect layer 260.

[0100] In this embodiment, a dry etching process (for example: an anisotropic dry etching process) is used to etch the bottom dielectric layer 101 on top of the first source / drain doping region 210a. The anisotropic dry etching process has the characteristic of anisotropic etching, which is conducive to improving the profile control of the second trench 212.

[0101] As Figure 12As shown, in this embodiment, the steps of forming the second trench 212 include: forming a second mask layer 320 having a second mask opening 340 on the bottom dielectric layer 101, where the second mask opening 340 exposes the bottom dielectric layer 101 at the top of the first source / drain doping region 210a; using the second mask layer 320 as a mask, etching the bottom dielectric layer 101 exposed by the second mask opening 340 to form the second trench 212.

[0102] In this embodiment, after forming the second trench 212, the second mask layer 320 is removed.

[0103] As an example, the material of the second mask layer 320 is photoresist. The second mask layer 320 is formed by photolithography processes such as photoresist coating, exposure, and development.

[0104] It should be noted that since there is a high etching selectivity between the gate capping layer 240 and the bottom dielectric layer 101, and there is also a high etching selectivity between the sidewall 205 and the bottom dielectric layer 101, the process window for forming the second mask opening 340 is thus improved.

[0105] For example, in the second direction, the second mask opening 340 not only exposes the bottom dielectric layer 101 at the top of the first source / drain doping region 210a, but may also expose the sidewall 205, and even may expose the gate capping layer 240 on both sides of the first source / drain doping region 210a.

[0106] In this embodiment, the steps of forming the second source / drain interconnect layer 260 in the second trench 212 include: as Figure 13 shown, filling a conductive material 261 into the second trench 212; as Figure 14 shown, using the top surface of the gate capping layer 240 as a stop position, performing planarization on the conductive material 261, and the remaining conductive material 261 in the second trench 212 serves as the second source / drain interconnect layer 260.

[0107] Among them, the hardness and density of the gate capping layer 240 are relatively high. Therefore, the top surface of the gate capping layer 240 can preferably serve as a stop position for defining the planarization process.

[0108] Specifically, the process of the planarization process may be a chemical mechanical polishing process.

[0109] In this embodiment, after forming the source / drain capping layer 230, the second source / drain interconnect layer 260 is formed, thereby avoiding damage to the second source / drain interconnect layer 260 caused by the processes of forming the first source / drain interconnect layer 220 and the source / drain capping layer 230. Correspondingly, during the process of forming the second source / drain interconnect layer 260, the source / drain capping layer 230 can also protect the first source / drain interconnect layer 220.

[0110] Reference Figure 15 , a top dielectric layer 102 covering the gate capping layer 240, the source / drain capping layer 230, the second source / drain interconnect layer 260, and the bottom dielectric layer 101 is formed.

[0111] The top dielectric layer 102 is used to jointly achieve electrical isolation between subsequent gate plugs, source / drain plugs, and shared contact plugs with the bottom dielectric layer 101.

[0112] The material of the top dielectric layer 102 is a dielectric material, and the material of the top dielectric layer 102 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.

[0113] In this embodiment, the top dielectric layer 102 is formed by a deposition process (e.g., chemical vapor deposition process).

[0114] In this embodiment, the top surfaces of the gate capping layer 240, the source / drain capping layer 230, the second source / drain interconnect layer 260, and the bottom dielectric layer 101 are flush with each other. Therefore, the flatness of the top surface of the top dielectric layer 102 is relatively high.

[0115] Combined with reference Figures 16 to 18 , in the shared contact region 100S, a shared contact plug 410 penetrating through the top dielectric layer 102 and the gate capping layer 240 is formed, and the shared contact plug 410 is in contact with the gate structure 200 and the second source / drain interconnect layer 260.

[0116] The shared contact plug 410 electrically connects the gate structure 200 and the second source / drain interconnect layer 260, so that the gate structure 200 and the second source / drain interconnect layer 260 can be connected to a common potential, thereby meeting the requirements of device operation.

[0117] In this embodiment, the steps of forming the shared contact plug 410 include:

[0118] As Figure 16 shown, in the shared contact region 100S, the top dielectric layer 102 and the gate capping layer 240 are etched to form a shared contact hole 415 exposing the gate structure 200 and the second source / drain interconnect layer 260.

[0119] In this embodiment, when forming the shared contact hole 415, only the top dielectric layer 102 and the gate capping layer 240 need to be etched, without etching the source / drain capping layer 230. Thus, the formation process of the shared contact hole 415 is not affected by the etching selectivity between the source / drain capping layer 230 and the gate capping layer 240, thereby reducing the process difficulty of forming the shared contact hole, and correspondingly reducing the process difficulty of forming the shared contact plug 410. Moreover, this is conducive to shortening the process time required for forming the shared contact plug 415, thereby reducing the influence of the top dielectric layer 102 being laterally etched, ensuring the cross-sectional shape and opening size of the shared contact hole 415, and correspondingly reducing the probability of the shared contact hole 415 exposing adjacent other gate structures 200 or the first source / drain interconnect layer 220, thereby improving the performance of the semiconductor structure.

[0120] In this embodiment, since there is no need to etch the source / drain capping layer 230, the top dielectric layer 102 is less affected by lateral etching. Correspondingly, a single photomask can be used to define the shape and position of the shared contact hole 415, thereby avoiding an increase in the number of photomasks and correspondingly facilitating process cost control.

[0121] As Figure 17 and Figure 18 shown, Figure 17 is a top view, Figure 18 and Figure 17 is a cross-sectional view along the A1A2 cut line. A shared contact plug 410 is formed in the shared contact hole 415 (as Figure 16 shown).

[0122] Specifically, after filling the shared contact hole 415 with a conductive material, using the top surface of the top dielectric layer 102 as the stop position, the conductive material is planarized, and the remaining conductive material serves as the shared contact plug 410.

[0123] In this embodiment, the process of filling the shared contact hole with a conductive material includes one or several of electroless plating process, physical vapor deposition process, and chemical vapor deposition process.

[0124] In this embodiment, a chemical mechanical polishing process is used to planarize the conductive material.

[0125] In this embodiment, the material of the shared contact plug 410 is copper. Copper has a relatively low resistivity, which is conducive to improving the signal delay of the subsequent RC and increasing the chip processing speed. At the same time, it is also conducive to reducing the resistance of the shared contact plug 410 and correspondingly reducing the power consumption. In other embodiments, the material of the shared contact plug can also be tungsten or cobalt.

[0126] It should be noted that in this embodiment, after forming the shared contact plug 410, in the second direction, the shared contact plug 410 is isolated from the adjacent source / drain capping layer 230 by the sidewall 205.

[0127] By isolating the shared contact plug 410 from the adjacent source / drain capping layer 230 through the sidewall 205, during the process of forming the shared contact hole 415, the probability of the sidewall 205 near the non-shared contact region 100T being etched by mistake is reduced, thereby reducing the probability of a short circuit occurring between the shared contact plug 410 and the first source / drain interconnect layer 220 in the adjacent non-shared contact region 100T.

[0128] Continue to refer to Figure 17 and, in combination with reference to Figure 19 , Figure 19 is Figure 17 a cross-sectional view along the B1B2 secant line. The forming method further includes: in the non-shared contact region 100T, forming a gate plug 420 in the top dielectric layer 102 and the gate capping layer 240 on top of the gate structure 200. In the second direction (as shown by the X direction in Figure 17 ), the gate plug 420 is isolated from the adjacent second source / drain interconnect layer 260 by the sidewall 205.

[0129] The gate plug 420 is used to achieve electrical connection between the gate structure 200 and an external circuit or other interconnect structures.

[0130] In this embodiment, the gate plug 420 is formed above the gate structure 200 in the active region. That is to say, the gate plug 420 is a Contact Over Active Gate (COAG). Compared with the scheme where the gate plug is in contact with the gate structure in the isolation region, this embodiment omits the part of the gate structure 200 in the isolation region, which is beneficial to saving the chip area and further reducing the chip size.

[0131] Specifically, the steps of forming the gate plug 420 include: in the non-shared contact region 100T, etching the top dielectric layer 102 and the gate capping layer 240 to form a gate contact hole (not shown in the figure) exposing the top of the gate structure 200; forming a gate plug 420 in the gate contact hole.

[0132] Among them, there is a high etching selectivity between the gate capping layer 240 and the source / drain capping layer 230. Therefore, during the process of forming the gate contact hole, the source / drain capping layer 230 plays a protective role for the second source / drain interconnect layer 220, thereby reducing the probability of a short circuit occurring between the gate plug 420 and the second source / drain interconnect layer 220.

[0133] In this embodiment, after filling the gate contact hole with a conductive material, the conductive material is planarized with the top surface of the top dielectric layer 102 as the stop position, and the remaining conductive material serves as the gate plug 420.

[0134] In this embodiment, in the second direction (such as Figure 17 the X direction shown), the gate plug 420 and the adjacent second source / drain interconnect layer 260 are isolated by the sidewall 205.

[0135] No source / drain capping layer 230 is formed on the top of the second source / drain interconnect layer 260. Therefore, by isolating the gate plug 420 and the adjacent second source / drain interconnect layer 260 through the sidewall 205, the probability of short - circuit between the gate plug 420 and the adjacent second source / drain interconnect layer 260 is reduced.

[0136] In this embodiment, the forming method further includes: in the non - shared contact region 100T, a source / drain plug (not shown in the figure) is formed in the top dielectric layer 102 and the source / drain capping layer 230 on the top of the first source / drain interconnect layer 220.

[0137] The source / drain plug is used to achieve electrical connection between the second source / drain doping region 210b and an external circuit or other interconnect structures.

[0138] The specific description of the gate plug 420 and the source / drain plug will not be elaborated in this embodiment.

[0139] Correspondingly, the present invention also provides a semiconductor structure. Continuing to refer to Figure 14 , a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown.

[0140] The semiconductor structure includes: a substrate (not labeled), a gate structure 200 is formed on the substrate, a gate capping layer 240 is formed on the top of the gate structure 200, source / drain doping regions 210 are formed in the substrate on both sides of the gate structure 200, a bottom dielectric layer 101 is formed on the substrate on the side of the gate structure 200, and the bottom dielectric layer 101 covers the sidewalls of the gate structure 200 and the gate capping layer 240. Among them, the region on the substrate for forming a shared contact plug (share contact) for electrically connecting the gate structure 200 and the source / drain doping region 210 is used as the shared contact region 100S, the source / drain doping region 210 in the shared contact region 100S is used as the first source / drain doping region 210a, and the remaining source / drain doping regions 210 are used as the second source / drain doping regions 210b; a first source / drain interconnect layer 220, the bottom dielectric layer 101 on the top of the second source / drain doping region 210b (such as Figure 6is located in the structure shown in the figure and is connected to the second source-drain doping region 210b. The top of the first source-drain interconnect layer 220 is lower than the top of the gate capping layer 240; a source-drain capping layer 230 is located in the region surrounded by the top of the first source-drain interconnect layer 220 and the bottom dielectric layer 101; a second source-drain interconnect layer 260 penetrates the bottom dielectric layer 101 at the top of the first source-drain doping region 210a; a top dielectric layer 102 covers the gate capping layer 240, the source-drain capping layer 230, the second source-drain interconnect layer 260, and the bottom dielectric layer 101.

[0141] The first source-drain doping region 210a is located in the shared contact region 100S. Subsequently, a top dielectric layer covering the gate capping layer 240, the source-drain capping layer 230, the second source-drain interconnect layer 260, and the bottom dielectric layer 101 is formed. After the top dielectric layer is formed, a shared contact plug electrically connecting the gate structure 200 and the first source-drain doping region 210a is formed in the shared contact region 100S. The step of forming the shared contact plug includes etching the top dielectric layer and the gate capping layer 240 in the shared contact region 100S to form a shared contact hole exposing the gate structure 200 and the second source-drain interconnect layer 260. A gate capping layer 240 is formed on the top of the gate structure 200. However, no source-drain capping layer 230 is formed on the top of the second source-drain interconnect layer 260. Therefore, during the subsequent formation of the shared contact hole, there is no need to etch the source-drain capping layer 230, thereby reducing the difficulty of the etching process used to form the shared contact plug, correspondingly reducing the formation difficulty of the shared contact plug. Moreover, this is conducive to shortening the process time required to form the shared contact hole, thereby reducing the influence of lateral etching on the top dielectric layer, ensuring the profile shape and opening size of the shared contact hole, correspondingly reducing the probability of the shared contact hole exposing adjacent other gate structures or the first source-drain interconnect layer, and thus reducing the probability of short-circuiting between the shared contact plug and adjacent other gate structures or the first source-drain interconnect layer, and further improving the performance of the semiconductor structure.

[0142] In addition, since there is no need to etch the source-drain capping layer 230, the top dielectric layer is less affected by lateral etching. When the shared contact hole is subsequently formed, the shape and position of the shared contact hole 415 can be defined by using a single photomask correspondingly, thereby reducing the process cost.

[0143] In this embodiment, the semiconductor structure is a fin field-effect transistor (FinFET). Therefore, the substrate includes a substrate 100 and fins 110 protruding from the substrate 100. In other embodiments, when the semiconductor structure is a planar field-effect transistor, the substrate is correspondingly a planar substrate.

[0144] In this embodiment, the substrate 100 is a silicon substrate.

[0145] In some other embodiments, the substrate may also be a substrate of other material types. For example, the material of the substrate may be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0146] In this embodiment, the material of the fin 110 is the same as that of the substrate 100.

[0147] In this embodiment, the semiconductor structure is an SRAM (Static Random Access Memory) device. According to the design requirements of the SRAM device, part of the gate structure 200 and the source / drain doping regions 210 need to be electrically connected through a shared contact plug.

[0148] In this embodiment, the region on the substrate for forming the shared contact plug (share contact) that electrically connects the gate structure 200 and the source / drain doping regions 210 is used as the shared contact region 100S.

[0149] In this embodiment, the gate structure 200 extends along a first direction (as shown by the Y direction in Figure 5 ), and the direction parallel to the substrate surface and perpendicular to the first direction is the second direction (as shown by the X direction in Figure 5 ), and the shared contact region 100S extends along the second direction.

[0150] Specifically, the number of the gate structures 200 is multiple, and the multiple gate structures 200 are arranged in parallel along the second direction.

[0151] In this embodiment, the remaining region outside the shared contact region 100S is used as the non-shared contact region 100T. Subsequently, in the non-shared contact region 100T, gate plugs connected to the gate structures 200 one by one and source / drain plugs connected to the source / drain doping regions 210 one by one are formed.

[0152] In this embodiment, the semiconductor structure further includes: an isolation layer (not shown in the figure), located on the substrate 100 exposed by the fin 110, and the isolation layer covers part of the sidewalls of the fin 110.

[0153] The isolation layer is used to isolate adjacent devices. The material of the isolation layer may be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer is silicon nitride.

[0154] In this embodiment, the gate structure 200 is located on the isolation layer, and the gate structure 200 straddles the fin 110 and covers part of the top surface and part of the sidewalls of the fin 110.

[0155] In this embodiment, the gate structure 200 is a device gate structure. During device operation, the gate structure 200 is used to control the opening or closing of the conductive channel.

[0156] Specifically, the gate structure 200 is a metal gate structure, and the gate structure 200 includes a high-k gate dielectric layer (not shown in the figure), a work function layer located on the high-k gate dielectric layer (not shown in the figure), and a gate electrode layer located on the work function layer (not shown in the figure).

[0157] The material of the high-k gate dielectric layer is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon dioxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0158] The work function layer is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0159] The gate electrode layer is used to lead out the electrical property of the gate structure 200. In this embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0160] In this embodiment, the source / drain doped regions 210 are located in the fins 110 on both sides of the gate structure 200.

[0161] Specifically, adjacent gate structures 200 share a source / drain doped region 210.

[0162] When forming an NMOS transistor, the source / drain doped region 210 includes a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, and the stress layer provides a tensile stress effect on the channel region of the NMOS transistor, thereby facilitating the improvement of the carrier mobility of the NMOS transistor. Among them, the N-type ions are P ions, As ions, or Sb ions; when forming a PMOS transistor, the source / drain doped region 210 includes a stress layer doped with P-type ions, the material of the stress layer is Si or SiGe, and the stress layer provides a compressive stress effect on the channel region of the PMOS transistor, thereby facilitating the improvement of the carrier mobility of the PMOS transistor. Among them, the P-type ions are B ions, Ga ions, or In ions.

[0163] In this embodiment, the source / drain doping regions 210 located in the shared contact region 100S serve as the first source / drain doping regions 210a, and the remaining source / drain doping regions 210 serve as the second source / drain doping regions 210b, that is, the source / drain doping regions 210 located in the non-shared contact region 100T serve as the second source / drain doping regions 210b.

[0164] It should be noted that in this embodiment, spacers 205 are further formed on the sidewalls of the gate structure 200.

[0165] The spacers 205 are used to define the formation regions of the source / drain doping regions 210, and the spacers 205 are also used to protect the sidewalls of the gate structure 200. The spacers 205 can be a single-layer structure or a stacked structure, and the materials of the spacers 205 include one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the spacers 205 are a single-layer structure, and the materials of the spacers 205 are silicon nitride.

[0166] Subsequently, source / drain plugs in contact with the first source / drain interconnect layer 220 are formed on the top of the first source / drain interconnect layer 220. The gate capping layer 240 is located on the top surface of the gate structure 200 and is used to protect the gate structure 200, thereby reducing the probability of damage to the gate structure 200 and short-circuiting between the source / drain plugs and the gate structure 200 during the formation of the source / drain plugs.

[0167] The gate capping layer 240 is selected to have an etching selectivity with respect to the source / drain capping layer 230, the bottom dielectric layer 101, and the top dielectric layer, which is beneficial to ensuring that the gate capping layer 240 can protect the gate structure 200.

[0168] In this embodiment, the materials of the gate capping layer 240 include one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride.

[0169] As an example, the material of the gate capping layer 240 is silicon nitride.

[0170] The materials of the gate capping layer 240 and the spacers 205 are the same, which is convenient for etching the gate capping layer 240 and the spacers 205 simultaneously when forming the shared contact holes subsequently, thereby reducing the complexity of the etching process. Moreover, the formation process of the semiconductor structure uses fewer types of film materials, which is also beneficial to reducing the process complexity.

[0171] In other embodiments, different materials can also be selected for the gate capping layer and the spacers.

[0172] In this embodiment, the gate structure 200 is formed by a process of forming a high-k gate dielectric layer first and then a gate electrode layer (high k last metal gate last). Therefore, the sidewall 205 covers the sidewalls of the gate structure 200 and the gate capping layer 240.

[0173] The bottom dielectric layer 101 is used to isolate adjacent devices, and the bottom dielectric layer 101 is also used to achieve electrical isolation between the first source / drain interconnect layer 220 and the second source / drain interconnect layer 260.

[0174] In this embodiment, the bottom dielectric layer 101 is an interlayer dielectric (ILD).

[0175] The material of the bottom dielectric layer 101 is an insulating material, and the material of the bottom dielectric layer 101 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the bottom dielectric layer 101 is silicon nitride.

[0176] In this embodiment, the tops of the bottom dielectric layer 101, the gate capping layer 240, and the sidewall 205 are flush.

[0177] The first source / drain interconnect layer 220 is in contact with the second source / drain doping region 210b, and is used to electrically connect the second source / drain doping region 210b to an external circuit or other interconnect structures.

[0178] In this embodiment, a source / drain plug in contact with the first source / drain interconnect layer 220 is formed on the first source / drain interconnect layer 220 later, and the source / drain plug realizes electrical connection with the second source / drain doping region 210b through the first source / drain interconnect layer 220.

[0179] In this embodiment, the material of the first source / drain interconnect layer 220 is copper. Copper has a low resistivity, which is beneficial to improving the signal delay of the back-end RC and increasing the processing speed of the chip. At the same time, it is also beneficial to reducing the resistance of the first source / drain interconnect layer 220, thereby reducing the power consumption. In other embodiments, the material of the first source / drain interconnect layer may also be a conductive material such as tungsten or cobalt.

[0180] In the non-shared contact region 100T, a gate plug in contact with the gate structure 200 is formed on the top of the gate structure 200 in the active area (AA) later. The source / drain capping layer 230 is located on the top surface of the first source / drain interconnect layer 220, and is used to protect the first source / drain interconnect layer 220 during the formation of the gate plug, which is beneficial to reducing the probability of damage to the first source / drain interconnect layer 220 and short circuit between the gate plug and the first source / drain interconnect layer 220.

[0181] The source-drain capping layer 230 is made of a material that has a high etching selectivity with respect to the gate capping layer 240, the sidewall 205, the bottom dielectric layer 101, and the top dielectric layer 102, which is conducive to ensuring that the source-drain capping layer 230 can protect the first source-drain interconnect layer 220.

[0182] In this embodiment, the material of the source-drain capping layer 230 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0183] Specifically, the materials of the source-drain capping layer 230 and the gate capping layer 240 are different, and the materials of the source-drain capping layer 230 and the sidewall 205 are different.

[0184] As an example, the material of the source-drain capping layer 230 is silicon carbide.

[0185] The top dielectric layer 102 is used together with the bottom dielectric layer 101 to achieve electrical isolation between subsequent gate plugs, source-drain plugs, and shared contact plugs.

[0186] The material of the top dielectric layer 102 is a dielectric material, and the material of the top dielectric layer 102 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride.

[0187] In this embodiment, the top surfaces of the gate capping layer 240, the source-drain capping layer 230, the second source-drain interconnect layer 260, and the bottom dielectric layer 101 are flush with each other. Therefore, the flatness of the top surface of the top dielectric layer 102 is relatively high.

[0188] The semiconductor structure can be formed by the formation method described in the foregoing embodiment or by other formation methods. For a specific description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the foregoing embodiment, and details are not repeated herein.

[0189] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: A substrate is provided, on which a gate structure is formed. A gate capping layer is formed on the top of the gate structure. Source / drain doping regions are formed in the substrate on both sides of the gate structure. A bottom dielectric layer is formed on the substrate on the side of the gate structure, and the bottom dielectric layer covers the sidewalls of the gate structure and the gate capping layer. Among them, the region on the substrate for forming a shared contact plug for electrically connecting the gate structure and the source / drain doping regions is used as a shared contact region. The source / drain doping region located in the shared contact region is used as a first source / drain doping region, and the remaining source / drain doping regions are used as second source / drain doping regions; A first source / drain interconnect layer connected to the second source / drain doping region and a source / drain capping layer located on the top of the first source / drain interconnect layer are formed in the bottom dielectric layer on the top of the second source / drain doping region; A second source / drain interconnect layer connected to the first source / drain doping region is formed in the bottom dielectric layer on the top of the first source / drain doping region, and the top of the second source / drain interconnect layer is exposed by the bottom dielectric layer; A top dielectric layer covering the gate capping layer, the source / drain capping layer, the second source / drain interconnect layer, and the bottom dielectric layer is formed; In the shared contact region, a shared contact plug penetrating the top dielectric layer and the gate capping layer is formed, and the shared contact plug electrically connects the gate structure and the second source / drain interconnect layer.

2. The method for forming a semiconductor structure according to claim 1, wherein After forming the source / drain capping layer, the second source / drain interconnect layer is formed.

3. The method for forming a semiconductor structure according to claim 1 or 2, wherein The steps of forming the first source / drain interconnect layer and the source / drain capping layer include: removing the bottom dielectric layer on the top of the second source / drain doping region to form a first trench exposing the second source / drain doping region; A first source / drain interconnect layer is formed in the first trench, and the top of the first source / drain interconnect layer is lower than the top of the bottom dielectric layer; A source / drain capping layer is formed in the region surrounded by the bottom dielectric layer and the first source / drain interconnect layer.

4. The method for forming a semiconductor structure according to claim 3, wherein, The step of forming the first source / drain interconnect layer in the first trench includes: filling the first trench with a conductive material; Using the top surface of the gate capping layer as a stop position, the conductive material is planarized; After the planarization, the remaining conductive material in the first trench is subjected to a re-etching process, and the remaining conductive material after the re-etching process is used as the first source / drain interconnect layer.

5. The method for forming a semiconductor structure according to claim 1 or 2, characterized in that, The steps of forming the second source / drain interconnect layer include: removing the bottom dielectric layer on the top of the first source / drain doping region to form a second trench exposing the first source / drain doping region; A second source / drain interconnect layer is formed in the second trench.

6. The method for forming a semiconductor structure as described in claim 5, wherein, The step of forming the second source / drain interconnect layer in the second trench includes: filling the second trench with a conductive material; Using the top surface of the gate capping layer as a stop position, the conductive material is planarized, and the remaining conductive material in the second trench is used as the second source / drain interconnect layer.

7. The method for forming a semiconductor structure according to claim 3, wherein, The steps of forming the first trench include: forming a first mask layer having a first mask opening on the bottom dielectric layer, and the first mask opening exposes the bottom dielectric layer on the top of the second source / drain doping region; Using the first mask layer as a mask, the bottom dielectric layer exposed by the first mask opening is etched to form a first trench; After forming the first trench, the first mask layer is removed.

8. The method for forming a semiconductor structure according to claim 5, wherein The step of forming the second trench includes: forming a second mask layer having a second mask opening on the bottom dielectric layer, the second mask opening exposing the bottom dielectric layer on top of the first source / drain doping region; Using the second mask layer as a mask, etching the bottom dielectric layer exposed by the second mask opening to form a second trench; After forming the second trench, the second mask layer is removed.

9. The method for forming a semiconductor structure according to claim 1, wherein, The materials of the gate capping layer and the source / drain capping layer are different.

10. The method for forming a semiconductor structure according to claim 1, wherein, The material of the gate capping layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride; The material of the source / drain capping layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

11. The method for forming a semiconductor structure according to claim 1, wherein, The step of forming the shared contact plug includes: in the shared contact region, etching the top dielectric layer and the gate capping layer to form a shared contact hole exposing the gate structure and the second source / drain interconnect layer; Forming a shared contact plug in the shared contact hole.

12. The method for forming a semiconductor structure according to claim 1, wherein In the step of providing the substrate, the gate structures extend along a first direction and are arranged in parallel along a second direction, the first direction and the second direction are perpendicular to each other, and sidewalls are formed on the sidewalls of the gate structures and the gate capping layer; In the step of forming the shared contact plug, in the second direction, the shared contact plug and the adjacent source / drain capping layer are isolated from each other by the sidewalls.

13. The method for forming a semiconductor structure according to claim 1, wherein In the step of providing the substrate, the gate structures extend along a first direction and are arranged in parallel along a second direction, the first direction and the second direction are perpendicular to each other, and sidewalls are formed on the sidewalls of the gate structures and the gate capping layer; The forming method further includes: forming a gate plug in the top dielectric layer and the gate capping layer on top of the gate structure, and in the second direction, the gate plug and the adjacent second source / drain interconnect layer are isolated from each other by the sidewalls.

14. The method for forming a semiconductor structure according to claim 1, wherein The semiconductor structure is an SRAM device.

15. A semiconductor structure, characterized in that, Including: A substrate, on which a gate structure is formed, a gate capping layer is formed on top of the gate structure, source / drain doping regions are formed in the substrate on both sides of the gate structure, a bottom dielectric layer is formed on the substrate on the side of the gate structure, the bottom dielectric layer covers the sidewalls of the gate structure and the gate capping layer, wherein, the region on the substrate for forming a shared contact plug for electrically connecting the gate structure and the source / drain doping region is used as a shared contact region, the source / drain doping region located in the shared contact region is used as a first source / drain doping region, and the remaining source / drain doping regions are used as second source / drain doping regions; A first source / drain interconnect layer, located in the bottom dielectric layer on top of the second source / drain doping region and connected to the second source / drain doping region, the top of the first source / drain interconnect layer is lower than the top of the gate capping layer; A source / drain capping layer, located in the region surrounded by the top of the first source / drain interconnect layer and the bottom dielectric layer; A second source / drain interconnect layer, penetrating through the bottom dielectric layer on top of the first source / drain doping region, the top of the second source / drain interconnect layer is exposed by the bottom dielectric layer; The top dielectric layer covers the gate capping layer, the source / drain capping layer, the second source / drain interconnect layer, and the bottom dielectric layer.

16. The semiconductor structure according to claim 15, wherein, The materials of the gate capping layer and the source / drain capping layer are different.

17. The semiconductor structure according to claim 15, characterized in that, The material of the gate capping layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride; The material of the source / drain capping layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

18. The semiconductor structure according to claim 15, wherein The semiconductor structure is an SRAM device.

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