Semiconductor capacitor structure and method of manufacturing the same, memory, electronic device

Abstract

The disclosure provides a semiconductor capacitor structure and a manufacturing method thereof, a memory, and an electronic device. The capacitor structure includes a semiconductor substrate, a plurality of pads are formed on the semiconductor substrate at intervals, and a bottom of a lower electrode is located on the pad. At least one lower support and an upper support are arranged between the sidewalls of the lower electrode, and the thickness of the lower electrode is uniformly distributed from the top of the lower electrode. The memory includes the semiconductor capacitor structure. The electronic device includes the memory. The manufacturing method includes: forming a first stack and a second stack on the semiconductor substrate. Etching the second and first stacks to form a groove through the lower support layer and backfilling. Etching the second and first stacks to form a capacitor hole and then forming a lower electrode. Etching based on the groove to form an upper support and a lower support. The disclosure innovatively performs a support layer etching process before depositing the lower electrode, solving the problem of damaging the lower electrode when etching the support layer in the conventional technology.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device technology, and more specifically, this disclosure provides semiconductor capacitor structures and manufacturing methods thereof, memory, and electronic devices. Background Technology

[0002] The capacitor manufacturing process for Dynamic Random Access Memory (DRAM) involves contact processes with a high aspect ratio. After separating the node of the lower electrode, the oxide molding layer needs to be removed by etching the support layer. However, this etching process inevitably damages the tip of the lower electrode. Figure 9 As shown, the height of a conventional electrode decreases after damage, leading to capacitance storage loss (Csloss) in semiconductor capacitors. Furthermore, the pointed tip of the conventional electrode, meaning its thinner tip, often results in deterioration of the properties of the subsequently deposited dielectric layer (e.g., dielectric layer degradation due to sharp points). Therefore, conventional techniques easily lead to reduced capacitance and decreased reliability in semiconductor capacitors. Summary of the Invention

[0003] To address the problems that conventional techniques inevitably cause damage to the tip of the lower electrode, leading to reduced capacitance and lower reliability of semiconductor capacitors, this disclosure provides a semiconductor capacitor structure and its manufacturing method, as well as a memory and electronic device.

[0004] To achieve the aforementioned technical objectives, this disclosure provides a semiconductor capacitor structure, which includes, but is not limited to, a semiconductor substrate, bonding pads, a lower electrode, a lower support member, and an upper support member. A plurality of bonding pads are formed on the semiconductor substrate at intervals, and the bottom of the lower electrode is located on the bonding pads. At least one lower support member is formed and disposed between the sidewalls of adjacent lower electrodes, and at least one upper support member is also formed and disposed between the sidewalls of adjacent lower electrodes, with the upper support member positioned above the lower support member. The thickness of the lower electrode is uniformly distributed downwards from its top tip.

[0005] To achieve the above-mentioned technical objectives, this disclosure may also provide a dynamic random access memory, which includes the semiconductor capacitor structure in any embodiment of this disclosure.

[0006] To achieve the above-mentioned technical objectives, this disclosure may also provide an electronic device, which includes the dynamic random access memory in any embodiment of this disclosure.

[0007] To achieve the above technical purposes, the present disclosure can also provide a manufacturing method of a semiconductor capacitor structure, which can include but is not limited to the following steps. A semiconductor substrate is provided, and a plurality of pads are formed on the semiconductor substrate in a spaced distribution. At least one first layer and at least one second layer are sequentially formed above the semiconductor substrate; wherein the first layer includes a lower molding layer and a lower support layer, and the second layer includes an upper molding layer and an upper support layer. The second layer and the first layer are etched in sequence to form at least one groove through the lower support layer. The groove is filled with the same material as the lower molding layer or the upper molding layer. The second layer and the first layer are etched again to form a capacitor hole, thereby exposing each pad. A lower electrode is formed in each capacitor hole. Finally, the lower molding layer and the upper molding layer are removed to form at least one upper support and at least one lower support.

[0008] The present disclosure has the following advantages: The present disclosure innovatively performs a support layer etching process before depositing a lower electrode, which can avoid the problem of lower electrode damage caused by the conventional technology when etching the support layer. The lower electrode structure formed by the present disclosure is significantly better than that of the conventional technology. The capacitor lower electrode provided by the present disclosure has no height loss, i.e., avoids the problem of capacitance loss. Therefore, the semiconductor capacitor formed based on the present disclosure can meet the design requirements and has an ideal capacitance. Moreover, the capacitor lower electrode provided by the present disclosure will not have the problem of a sharp top end, i.e., will not have the problem of media layer characteristic degradation caused by a media layer sharp point, so the semiconductor capacitor formed based on the present disclosure has the advantages of high reliability, etc. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A longitudinal cross-sectional structure diagram of the device after forming the groove by sequentially etching the second layer and the first layer is shown.

[0010] Figure 2 A longitudinal cross-sectional structure diagram of the device after filling the groove with the same material as the lower molding layer or the upper molding layer is shown.

[0011] Figure 3 A longitudinal cross-sectional structure diagram of the device after sequentially forming a protective layer, a hard mask layer, and a photoresist layer is shown.

[0012] Figure 4 A longitudinal cross-sectional structure diagram of the device after forming a capacitor hole by etching the second layer and the first layer again is shown.

[0013] Figure 5 A longitudinal cross-sectional structure diagram of the device after removing the hard mask layer is shown.

[0014] Figure 6 A longitudinal cross-sectional structure diagram of the device after forming a lower electrode in each capacitor hole is shown.

[0015] Figure 7 A longitudinal cross-sectional structure diagram of a device after sequentially removing the lower molding layer and the upper molding layer based on the groove is shown.

[0016] Figure 8 A cross-sectional structure diagram of a lower electrode with a complete top end structure formed by the present disclosure is shown.

[0017] Figure 9 A cross-sectional structure diagram of a lower electrode with a missing top end structure and a sharp top end shape formed by conventional techniques is shown.

[0018] In the drawings,

[0019] 100, semiconductor substrate.

[0020] 200, solder pad.

[0021] 300, lower electrode.

[0022] 400, lower support.

[0023] 500, upper support.

[0024] 600, lower molding layer.

[0025] 700, upper molding layer.

[0026] 800, groove.

[0027] 900, photoresist layer; 901, hard mask layer; 902, protective layer. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. Furthermore, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0029] In the drawings, various structure diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity and precision, and certain details can be omitted. The shapes of various regions, layers, and their relative sizes and positional relationships shown in the drawings are merely exemplary, and in actuality, there can be deviations due to manufacturing tolerances or technical limitations, and a person skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0030] In the context of the present disclosure, when one layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or there can be intervening layers / elements therebetween. Also, if a layer / element is on another layer / element in one orientation, it can be under the other layer / element when the orientation is reversed.

[0031] The present disclosure can provide a manufacturing method of a semiconductor capacitor structure, which can effectively solve the problems of top electrode tip loss and tip sharpening in the existing semiconductor capacitor processing technology. The manufacturing method includes but is not limited to the following steps.

[0032] As shown in Figure 1 A semiconductor substrate 100 is provided, and a plurality of pads 200 are formed on the semiconductor substrate 100 in a spaced distribution. At least one first layer and at least one second layer are sequentially formed above the semiconductor substrate 100. The first layer includes a lower molding layer 600 and a lower support layer, and the second layer includes an upper molding layer 700 and an upper support layer. Therefore, the present disclosure can form a stacked structure, and some or part of the structure in the stacked structure can be removed in the process of forming the capacitor structure. For example, the lower support layer in the present disclosure is used to form a lower support 400, and the upper support layer is used to form an upper support 500. One or more embodiments of the present disclosure first etch the second layer and the first layer formed in sequence to form at least one groove 800, which is used as a wet etching path for removing the molding layer. The groove 800 can pass through the lower support layer (the lowermost lower support layer in the device layer), and the groove 800 in some embodiments of the present disclosure passes through the upper support layer, the upper molding layer 700, the lower support layer, and then enters the lower molding layer 600.

[0033] In some embodiments of the present disclosure, the lower molding layer 600 and the upper molding layer 700 can be made of the same material, for example, both can be mold oxide. The mold oxide can be one of flowable oxide (FOX), undoped silicon dioxide glass (USG), boron-silicon glass (BSG), phosphorus-silicon glass (PSG), boron-phosphorus-silicon glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), fluorinated silicate glass (FSG), plasma-enhanced oxide (PEOX), and high-density plasma CVD (HDP-CVD) oxide.

[0034] As shown in Figure 2As shown, the groove 800 is filled with the same material as the lower molding layer 600 or the upper molding layer 700, for example, by depositing a molding oxide layer. That is, this disclosure can backfill the groove 800 with the same material as the lower molding layer 600, or backfill the groove 800 with the same material as the upper molding layer 700. In some embodiments of this disclosure, the process of filling the groove 800 with the same material as the lower molding layer 600 or the upper molding layer 700 includes the following steps: First, the same material as the lower molding layer 600 or the upper molding layer 700 is deposited, and the deposited material accumulates on top of the second stack after filling the groove 800. Then, the deposited material layer (the excess accumulation) is subjected to chemical mechanical planarization (CMP) treatment. Polishing continues until the second stack is exposed, so that the upper surface of the material layer and the upper surface of the second stack are on the same plane, thus completing the process of filling the groove 800. This disclosure then forms capacitor holes by re-etching the second stack and the first stack.

[0035] like Figure 3 As shown, a hard mask layer 901 and a photoresist layer 900 are sequentially formed on the upper part of the second stack. A photomask with a capacitor hole pattern is disposed above the photoresist layer 900, and the photoresist layer 900 is patterned according to the capacitor hole pattern to be formed. The hard mask layer 901 is etched using the patterned photoresist layer 900 as a mask to form a node hole mask. In this case, the node hole mask may only include the hard mask layer 901. To improve the reliability of semiconductor device processes, in some embodiments of this disclosure, a protective layer 902 is formed on the upper part of the second stack before the hard mask layer 901 and the photoresist layer 900 are sequentially formed. The protective layer 902 and the hard mask layer 901 are etched using the patterned photoresist layer 900 as a mask to form a node hole mask. Therefore, in some embodiments of this disclosure, the node hole mask may consist of a hard mask layer 901 and a protective layer 902.

[0036] like Figure 4 As shown, the second and first stacks are etched again based on the node hole mask, that is, the device layers above the semiconductor substrate 100 are etched based on the node hole mask. In some embodiments of this disclosure, capacitor nodes are formed by the aforementioned method of re-etching the second and first stacks, thereby exposing each bonding pad 200. In some embodiments of this disclosure, capacitor nodes can be formed by sequentially etching the upper support layer, the upper molding layer 700, the lower support layer, and the lower molding layer 600. Multiple capacitor nodes can be spaced apart and arranged in a honeycomb pattern, for example, they can be repeatedly arranged in a honeycomb pattern.

[0037] like Figure 5 As shown, after forming the aforementioned plurality of capacitor vias, the remaining hard mask layer 901 can be removed. In some embodiments of this disclosure, the hard mask layer 901 can be removed by etching, thereby preparing for the formation of the lower electrode.

[0038] like Figure 6 As shown, in some embodiments of this disclosure, the protective layer 902 can be removed, and then the lower electrode 300 can be formed in each capacitor hole. In some embodiments of this disclosure, the lower electrode 300 can be formed independently in each capacitor hole by depositing lower electrode 300 material. In practice, after depositing the lower electrode 300 material, a lower electrode 300 node separation process is often required to form each lower electrode.

[0039] like Figure 7 As shown, some embodiments of this disclosure remove the lower molding layer 600 and the upper molding layer 700 based on the groove 800 to form at least one upper support 500 and at least one lower support 400. In specific implementations of this disclosure, the step of removing the lower molding layer 600 and the upper molding layer 700 based on the groove 800 includes the following steps: Using at least one groove 800 as an etching path, the upper molding layer 700 in each second stack and the lower molding layer 600 in each first stack are then wet-etched away. One or more embodiments of this disclosure may utilize a BOE-based solution to etch away the upper molding layer 700 and the lower molding layer 600 along the groove 800, allowing the BOE-based solution to penetrate to the lower portion along the etching path. Using a BOE-based solution to remove the upper molding layer 700 and the lower molding layer 600 can reduce the possibility of profile degradation during memory node etching, thereby avoiding problems such as bowing of the support film surface and the molding layer film surface. The BOE-type solution in one or more embodiments of this disclosure is a buffered oxide etching solution, which can be a mixture of hydrofluoric acid, water, and ammonium fluoride.

[0040] In other embodiments of this disclosure, the method further includes the step of sequentially depositing a dielectric layer and an upper electrode within each lower electrode 300, for example, after removing the aforementioned upper molding layer 700 and lower molding layer 600. The dielectric layer can be formed along the bottom wall and inner sidewall of the lower electrode 300, and the upper electrode is formed after the dielectric layer is formed. The upper electrode is filled in the space enclosed by the dielectric layer. Therefore, this disclosure also enables the formation of a complete electrode structure including a lower electrode, a dielectric layer, and an upper electrode in each capacitor hole.

[0041] Based on the same inventive concept as the method for manufacturing a semiconductor capacitor structure, one or more embodiments of this disclosure can also provide a semiconductor capacitor structure. Figure 9 Unlike conventional lower electrodes 300, the lower electrode 300 provided in this disclosure has no tip loss and the tip does not become sharp.

[0042] like Figure 7 and Figure 8As shown, the semiconductor capacitor structure includes, but is not limited to, a semiconductor substrate 100, a pad 200, a lower electrode 300, a lower support 400, an upper support 500, etc.

[0043] The semiconductor substrate 100 is provided with a plurality of pads 200 distributed at intervals, and the plurality of pads 200 can be disposed in a nitride layer. The nitride layer can be formed on the semiconductor substrate 100 and can be used for insulation between different pads 200. The semiconductor substrate 100 can be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, a III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by performing selective epitaxial growth (SEG). The semiconductor substrate 100 of some embodiments of the present disclosure can have structures such as an active region, an interlayer dielectric layer, a bit line, a bit line node contact, a word line, a storage node contact, a pad, and a sidewall. The bit line material is at least one of a doped semiconductor material (for example, doped silicon or doped germanium), a conductive metal nitride (for example, titanium nitride or tantalum nitride), a metal (for example, tungsten, titanium, or tantalum), and / or a metal-semiconductor compound (for example, tungsten silicide, cobalt silicide, or titanium silicide), and the bit line node contact can adopt the same material as the bit line. The positions and connection relationships between these structures disposed on the active region can be intelligently selected from existing designs, and the present disclosure will not be described in detail.

[0044] The bottom of the lower electrode 300 is located on the pad 200, and the pad 200 has a conductive effect, so the nitride layer is used to insulate between different pads 200. The material of the pad 200 can be tungsten or cobalt, or at least one of a doped semiconductor material (for example, doped silicon or doped germanium), a conductive metal nitride (for example, titanium nitride or tantalum nitride), a metal (for example, tungsten, titanium, or tantalum), and / or a metal-semiconductor compound (for example, tungsten silicide, cobalt silicide, or titanium silicide).

[0045] At least one layer of the lower support 400 is disposed between the sidewalls of adjacent lower electrodes 300. The material of the lower support 400 can be a relatively hard nitride, thereby achieving the effect of supporting the electrode.

[0046] At least one layer of the upper support 500 is also disposed between the sidewalls of adjacent lower electrodes 300, and the upper support 500 is above the lower support 400. The material of the upper support 500 can be a relatively hard nitride, thereby achieving the effect of supporting the electrode.

[0047] As shown in FIG. 1, the semiconductor capacitor structure includes a semiconductor substrate 100, a pad 200, a lower electrode 300, a lower support 400, an upper support 500, etc. Figure 7 , 8As shown, the thickness of the lower electrode 300 is uniform from the top end of the lower electrode 300 to the bottom end of the lower electrode 300; the top end of the lower electrode 300 can be flush with the top surface of the upper support 500. The material of the lower electrode 300 can be at least one of a metal, a conductive metal oxide, and doped polysilicon, such as at least one of a high melting point metal (e.g., cobalt, titanium, nickel, tungsten, or molybdenum), a metal nitride (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), and / or tungsten nitride (WN)), a noble metal (e.g., platinum (Pt), ruthenium (Ru), or iridium (Ir)), a conductive noble metal oxide (e.g., PtO, RuO2, or IrO2), and / or a conductive oxide (e.g., SrRuO3, RuO3, CaRuO3).

[0048] The semiconductor capacitor structure can further include a dielectric layer and an upper electrode. The dielectric layer can be formed on the bottom wall and the inner sidewall of the lower electrode 300 by depositing a dielectric layer material such that the dielectric layer adheres to the bottom wall and the inner sidewall of the lower electrode 300. The upper electrode can be formed within the dielectric layer by depositing an upper electrode material such that the dielectric layer is between the upper electrode and the lower electrode 300. The material of the upper electrode can be at least one of a metal, a conductive metal oxide, and doped polysilicon, such as at least one of a high melting point metal (e.g., cobalt, titanium, nickel, tungsten, or molybdenum), a metal nitride (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), and / or tungsten nitride (WN)), a noble metal (e.g., platinum (Pt), ruthenium (Ru), or iridium (Ir)), a conductive noble metal oxide (e.g., PtO, RuO2, or IrO2), and / or a conductive oxide (e.g., SrRuO3, RuO3, CaRuO3).

[0049] One or more embodiments of the present disclosure can also provide a dynamic random access memory, which can include the semiconductor capacitor structure of any of the embodiments of the present disclosure. The dynamic random access memory is a semiconductor memory device commonly used in computers, which includes a plurality of memory cells arranged in a matrix structure. Each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and each memory cell is electrically connected through a word line and a bit line. Data is transmitted from the bit line to the capacitor through the transistor, or data stored in the capacitor is output through the transistor and the bit line. One or more embodiments of the present disclosure can also provide an electronic device including the dynamic random access memory of any of the embodiments of the present disclosure. The electronic device can include, but is not limited to, a smart phone, a computer, a tablet computer, a wearable smart device, an artificial intelligence device, and a mobile power supply.

[0050] In the above description, the technical details of the patterning, etching, etc. of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions, etc. of the desired shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0051] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor capacitor structure, characterized in that, include: A semiconductor substrate is provided, on which a plurality of spaced-apart pads are formed; At least one first stack and at least one second stack are sequentially formed over the semiconductor substrate; wherein the first stack includes a lower molding layer and a lower support layer, and the second stack includes an upper molding layer and an upper support layer; The second stack and the first stack are etched sequentially to form at least one groove through the upper support layer and the lower support layer; The groove is filled with the same material as the lower molding layer or the upper molding layer; The second stack and the first stack are etched again to form capacitor holes, thereby exposing each solder pad; A lower electrode is formed within each of the capacitor holes; Remove the lower molding layer and the upper molding layer to form at least one upper support and at least one lower support; The process of re-etching the second stack and the first stack includes: A hard mask layer and a photoresist layer are sequentially formed on the upper part of the second stack; The photoresist layer is patterned according to the desired capacitor hole pattern; The hard mask layer is etched using the patterned photoresist layer as a mask to form a node hole mask; The second stack and the first stack are etched again based on the node hole mask.

2. The method for manufacturing a semiconductor capacitor structure according to claim 1, characterized in that, The process of filling the groove with the same material as the lower molding layer or the upper molding layer includes: Deposit the same material as the lower molding layer or the upper molding layer; The deposited material layer is subjected to chemical mechanical planarization and polished until the second stack is exposed, so that the upper surface of the material layer and the upper surface of the second stack are in the same plane.

3. The method for manufacturing a semiconductor capacitor structure according to claim 1, characterized in that, The process of etching the second stack and the first stack again further includes: Before the hard mask layer and the photoresist layer are formed sequentially, a protective layer is formed on the upper part of the second stack; The protective layer and the hard mask layer are etched using the patterned photoresist layer as a mask to form a node hole mask.

4. The method for manufacturing a semiconductor capacitor structure according to claim 1 or 2, characterized in that, The steps of removing the lower molding layer and the upper molding layer include: Using the groove as the etching path, the upper molding layer and the lower molding layer are wet-etched away along the groove using a BOE-type solution.

5. A semiconductor capacitor structure, characterized in that, Manufactured by a method for manufacturing a semiconductor capacitor structure according to any one of claims 1 to 4, comprising: A semiconductor substrate, wherein a plurality of spaced-apart pads are formed on the semiconductor substrate; The lower electrode, the bottom of which is located on the solder pad; At least one lower support member is disposed between the sidewalls of adjacent lower electrodes; At least one upper support member is also disposed between the sidewalls of the adjacent lower electrodes, and the upper support member is located above the lower support member; The thickness of the lower electrode is uniformly distributed from the top of the lower electrode downwards.

6. The semiconductor capacitor structure according to claim 5, characterized in that, The top of the lower electrode is flush with the top surface of the upper support.

7. The semiconductor capacitor structure according to claim 5 or 6, characterized in that, The lower support and / or upper support are nitrides.

8. The semiconductor capacitor structure according to claim 5 or 6, characterized in that, The material of the bonding pad is tungsten or cobalt.

9. A dynamic random access memory, characterized in that, Includes the semiconductor capacitor structure described in any one of claims 5 to 8.

10. An electronic device, characterized in that, Includes the dynamic random access memory as described in claim 9.

11. The electronic device according to claim 10, characterized in that, This includes smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and power banks.

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