Semiconductor device and method for manufacturing the same

Abstract

Embodiments of the present invention provide a semiconductor device comprising one or more active semiconductor components, wherein a front side is defined above a semiconductor substrate and a back side is defined below the semiconductor substrate. A front side power rail is formed on the front side of the semiconductor device and is configured to receive a first reference supply voltage. First and second back side power rails are formed on the back side of the semiconductor substrate and are configured to receive respective second and third reference supply voltages. The first, second, and third reference supply voltages are different. Embodiments of the present invention also provide a method for manufacturing the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of semiconductors, and more particularly, to semiconductor devices and methods of manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has produced a wide variety of analog and digital devices to solve problems in many different fields. As ICs become smaller and more complex, the operating voltages of these analog and digital devices decrease, affecting the operating voltage of these digital devices and overall IC performance. Summary of the Invention

[0003] One aspect of the present invention provides a semiconductor device comprising: a semiconductor substrate comprising one or more active semiconductor components, wherein a front side is defined above the semiconductor substrate and a back side is defined below the semiconductor substrate; a first front side power rail located on the front side of the semiconductor substrate, the first front side power rail being configured to receive a first reference supply voltage; and a first back side power rail and a second back side power rail located on the back side of the semiconductor substrate; the first back side power rail being configured to receive a second reference supply voltage; and the second back side power rail being configured to receive a third reference supply voltage; and wherein the first reference supply voltage, the second reference supply voltage, and the third reference supply voltage are different from each other.

[0004] Another aspect of the present invention provides a semiconductor device comprising: a semiconductor substrate comprising one or more active semiconductor components, wherein a front side is defined above the semiconductor substrate and a back side is defined below the semiconductor substrate; a first back side power rail, a second back side power rail, and a third back side power rail located on the back side of the semiconductor substrate; and wherein: the first back side power rail is configured to receive a first reference supply voltage; the second back side power rail is configured to receive a second reference supply voltage; and the third back side power rail is configured to receive a third reference supply voltage, wherein the first reference supply voltage, the second reference supply voltage, and the third reference supply voltage are different from each other.

[0005] Yet another aspect of the present invention provides a method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate having a first active region and a second active region extending correspondingly along a first direction; configuring the first active region to have a first conductivity; configuring the second active region to have a second conductivity; a front side being defined above the semiconductor substrate and a back side being defined below the semiconductor substrate; forming a first front side conductive line on the front side; configuring the first front side conductive line to receive an input signal or provide an output signal; forming a first front side power rail on the front side; configuring the first front side power rail to receive a first reference power supply voltage; forming a first back side power rail on the back side; configuring the first back side power rail to receive a second reference power supply voltage; and forming a first gate electrode on the front side, the first gate electrode extending along a second direction orthogonal to the first direction; arranging the first gate electrode to define a first drain / source region and a second drain / source region in the first active region, and a third drain / source region and a fourth drain / source region in the second active region; connecting the first gate electrode to the first front side conductive line; connecting the first drain / source region or the second drain / source region to the first front side power rail; and connecting the third drain / source region or the fourth drain / source region to the first back side power rail. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 1B is a cross-sectional view according to some embodiments.

[0009] Figure 2 is an integrated circuit (IC) circuit according to some embodiments.

[0010] Figure 3A and Figure 3B is a corresponding layout diagram of a unit according to some embodiments.

[0011] Figure 3C is a schematic diagram of a semiconductor device according to some embodiments.

[0012] Figure 3D According to some embodiments, Figure 3C Cross-sectional view of the cut line.

[0013] Figure 4A and Figure 4Bis a corresponding layout diagram of adjacent cells according to some embodiments.

[0014] Figure 5A and Figure 5B is a corresponding layout diagram of adjacent cells according to some embodiments.

[0015] Figure 6A and Figure 6B is a corresponding layout diagram of a unit according to some embodiments.

[0016] Figure 7A and Figure 7B is a corresponding layout diagram of a unit according to some embodiments.

[0017] Figure 8A and Figure 8B is a corresponding layout diagram of a unit according to some embodiments.

[0018] Figure 9 is a circuit diagram according to some embodiments.

[0019] Figure 10A and Figure 10B is a corresponding layout diagram of a cell according to some embodiments.

[0020] Figure 11A and Figure 11B is a corresponding layout diagram of a cell according to some embodiments.

[0021] Figure 12 is a circuit diagram of a NAND gate according to some embodiments.

[0022] Figure 13A and Figure 13B is a corresponding layout diagram of a cell according to some embodiments.

[0023] Figure 14A and Figure 14B is a corresponding layout diagram of a cell according to some embodiments.

[0024] Figure 15 is a flow chart of a method of manufacturing a semiconductor device according to some embodiments.

[0025] Figure 16 is a flow chart of a method of manufacturing a semiconductor device according to some embodiments.

[0026] Figure 17 is a flow chart of a method of manufacturing a semiconductor device according to some embodiments.

[0027] Figure 18 is a flowchart of a method of manufacturing a semiconductor device having a cell region according to some embodiments.

[0028] Figure 19 is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0029] Figure 20 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated therewith, according to some embodiments. DETAILED DESCRIPTION

[0030] The present invention provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0031] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another (or more) elements or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0032] In some embodiments, a semiconductor device includes one or more active semiconductor components, wherein a front side is defined above a semiconductor substrate and a back side is defined below the semiconductor substrate, i.e., on a side opposite the front side. In some embodiments, one or more front side power rails are formed on the front side of the semiconductor substrate, and one or more back side power rails are formed on the back side of the semiconductor substrate. Different reference voltages are distributed to the active semiconductor components via the front side power rails and / or the back side power rails. For example, reference voltages such as a gated version of VDD (referred to herein as VVDD), an ungated version of VDD (referred to herein as true VDD or TVDD), and VSS (e.g., ground) are received by one or more front side power rails and / or one or more back side power rails to distribute three different reference voltages, VDD, VVDD, and TVDD, to cell regions on the semiconductor substrate. Generally, reducing power rail congestion to distribute different operating voltages without generating significant noise helps reduce the circuit size of the IC. Therefore, in some embodiments, the front side power rails and the back side power rails help reduce power rail congestion and reduce noise, thereby helping to reduce the size of the active semiconductor components on the semiconductor substrate.

[0033] Figure 1A is a block diagram of a semiconductor device 100 according to an embodiment of the present disclosure.

[0034] exist Figure 1A In the embodiment of the present invention, semiconductor device 100 includes, among other things, a circuit macro (hereinafter referred to as macro) 101. In some embodiments, macro 101 is a header circuit. In some embodiments, macro 101 is a macro other than a header circuit. Macro 101 includes, among other things, region 102 having a front metal structure and a back metal structure, wherein the front metal structure has one or more front power rails configured to receive one or more reference voltages, and the back metal structure includes one or more back power rails configured to receive one or more reference voltages. In some embodiments, at least some of the reference voltages received by the front conductive rails are the same as at least some of the reference voltages received by the back conductive rails. In other embodiments, the reference voltage received by the front conductive rails is the same as the reference voltage received by the back conductive rails. In other embodiments, the reference voltage received by the front power rails and the reference voltage received by the back power rails are different. As described below, the conductive fingers increase the available area that can be used to connect to conductive segments that provide different voltages in a power gating scheme. Region 102 includes metal layers and interconnect layers above the semiconductor substrate, where "above" is relative to the Z-axis ( Figure 1A Region 102 also includes metal layers and interconnect layers below the semiconductor substrate, where “below” is relative to the Z direction ( Figure 1AThe front power rails are formed in the front metal layer above the semiconductor substrate, while the back power rails are formed in the metal layer below the semiconductor substrate.

[0035] In some embodiments, in region 102, the front power rail and the back power rail are configured to receive different reference voltages (e.g., GND, VVDD, TVDD). In some embodiments, by distributing power across the front and back sides of the semiconductor substrate, cell height is reduced and circuit area consumption is reduced. Furthermore, in some embodiments, distributing power across the front and back sides of the semiconductor substrate reduces electromigration sensitivity, parasitic capacitance, and internal resistance, thereby making the corresponding design more energy-efficient.

[0036] Figure 1B is a cross-sectional view according to some embodiments.

[0037] More specifically, Figure 1B The region of the semiconductor device (eg Figure 1A 1. A cross-sectional area of ​​a semiconductor device 100 (region 102) is shown in FIG.

[0038] Figure 1B The cross-sectional view includes a semiconductor substrate 113, a transistor element contact layer (contact-to-transistor-componentlayer ， 1 . The back metal layer BM0, the back via layer BVIA0 and the back metal layer BM1 are shown. Also shown are a metal-drain / source layer (MD layer), a via-gate / MD layer (VGD layer), a metal layer M0, a via layer VIA0 and a metal layer M1. In some embodiments, the VGD layer is referred to as a via-MD layer (VD layer). From top to bottom relative to the Z axis, the metal layer M1, the via layer VIA0, the metal layer M0, the VGD layer, the MD layer, the semiconductor substrate 113, the BVD layer, the back metal layer BM0, the back via layer BVIA0 and the back metal layer BM1 form a stack. The Z axis is orthogonal to both the X axis and the Y axis (for the latter, see Figure 1A ).

[0039] exist Figure 1BIn the figure, M0 represents the first metallization layer on the front side, and the corresponding first interconnect layer on the front side is VIA0, and BM0 represents the first metallization layer on the back side, and the corresponding first interconnect layer on the back side is BVIA0. In some embodiments, according to the numbering convention of the corresponding process node for manufacturing such semiconductor devices, the first metallization layer on the front side is M1, and the corresponding first interconnect layer is VIA1, and the first metallization layer on the back side is BM1, and the corresponding first interconnect layer on the back side is BVIA1. In some embodiments, M0 is the first metallization layer above the transistor layer (which includes the semiconductor layer 113) in which transistors are formed, and BM0 is the first metallization layer below the transistor layer.

[0040] like Figure 1B As shown, the metal layer M1, the via layer VIA0, the metal layer M0, the VGD layer, and the MD layer are stacked above the semiconductor substrate 113. The active (OD) region 210 is formed in the semiconductor substrate 113. Because the metal layer M1, the via layer VIA0, the metal layer M0, the VGD layer, and the MD layer are stacked above the semiconductor substrate 113, they are referred to as "front" layers. The BVD layer, the back metal layer BM0, the back via layer BVIA0, and the back metal layer BM1 are stacked below the semiconductor substrate 113 in order from top to bottom, that is, from closest to farthest from the semiconductor substrate 113. Because the BVD layer, the back metal layer BM0, the back via layer BVIA0, and the back metal layer BM1 are stacked below the semiconductor substrate 113, they are referred to as "back" layers.

[0041] Figure 2 is an integrated circuit (IC) circuit 200 according to some embodiments.

[0042] IC 200 is an example of a circuit that may be used in the aforementioned region 102. Thus, IC 200 is an example of a circuit that benefits from using a front-side metal architecture and a back-side metal architecture that include power rails configured to receive different reference voltages.

[0043] IC 200 includes: header circuit 202; control circuit 204; non-gated power driver circuit 203; gated power driver circuit 205A; and gated power driver circuit 205B. Typically, circuit power consumption increases due to leakage current. Power gating is a technique used to reduce power consumption within an IC by shutting down power to unused circuits within the IC. The power supplied to each of gated power driver circuits 205A and 205B is gated by the corresponding portion of header circuit 202, and therefore, each of circuits 205A and 205B is referred to herein as a gated power driver circuit. The power supplied to non-gated power driver circuit 203 is not gated by the corresponding header circuit; therefore, circuit 203 is referred to herein as a non-gated power driver circuit.

[0044] Each of the gated power driver circuits 205A and 205B is a type of circuit configured to operate in normal mode and sleep mode (the latter also referred to as standby mode). In normal mode, power is supplied to each of the gated power driver circuits 205A and 205B. In normal mode, each of the gated power driver circuits 205A and 205B is used by IC 200 and is either in an active state or an inactive state, consuming more power when active than when inactive. Although less power is consumed when each of the gated power driver circuits 205A and 205B is in an inactive state, a significant amount of power is consumed due to leakage current. In sleep mode, each of the gated power driver circuits 205A and 205B is not in use, and therefore no power is supplied to each of the gated power driver circuits 205A and 205B. Therefore, in sleep mode, each of the gated power driver circuits 205A and 205B is not only inactive, but also does not suffer from leakage current. In some embodiments, the sleep mode is referred to as a standby mode. In some embodiments, based on the different power states of the gated power driver circuits 205A and 205B, the header circuit 202 is configured to be turned on and thereby provide power to the gated power driver circuits 205A and 205B in response to a control signal from the control circuit 204, or to be turned off and thereby cut off the power provided to the gated power driver circuits 205A and 205B in response to the control signal. For example, when the gated power driver circuits 205A and 205B are in the sleep mode or standby mode, the header circuit 202 is configured to be turned off, thereby cutting off the power provided to the gated power driver circuits 205A and 205B. For example, when the gated power driver circuits 205A and 205B are in the active state, the header circuit 102 is configured to be turned on, thereby providing power to the gated power driver circuits 205A and 205B. The header circuit 202 is configured to reduce leakage current within the gated power driver circuits 205A and 205B, and thus reduce the power consumed by the gated power driver circuits 205A and 205B.

[0045] The header circuit 202 includes a PMOS transistor P1 and a PMOS transistor P2. The source of the PMOS transistor P1 and the source of the PMOS transistor P2 are both configured to receive a non-gated version of a reference voltage, such as VDD. Figure 2In FIG, the non-gated version of VDD is referred to as true VDD (TVDD). In addition, the body contact of PMOS transistor P1 and the body contact of PMOS transistor P2 are configured to receive the non-gated reference voltage TVDD. When transistors P1 and P2 are turned on, respectively, the drain of PMOS transistor P1 and the drain of PMOS transistor P2 provide a gated version of TVDD corresponding to gated power driver circuits 205A and 205B. The gated version of TVDD is Figure 2 In this example, the voltage VDD is referred to as virtual VDD (VVDD). Assuming the source-drain voltage drop (Vsd) of transistors P1 and P2 is negligibly small, VVDD = TVDD - Vsd ≈ TVDD. Therefore, VVDD is substantially similar to TVDD. When transistors P1 and P2 are turned off, the power to gate-controlled power driver circuits 205A and 205B is cut off.

[0046] The gate of the PMOS transistor P1 and the gate of the PMOS transistor P2 are both connected to the node nd01 and are configured to receive the control signal NSLEEPin'. The header circuit 202, more specifically, each of the transistors P1 and P2, is configured to be turned on and off based on the control signal NSLEEPin'. It should be noted that the header circuit 202 may have Figure 2 The embodiment shown has a different configuration. For example, in some alternative embodiments, the header circuit 202 has a single PMOS transistor, such as P1, which provides VVDD to each of the gate-controlled power driver circuits 205A and 205B. In such alternative embodiments, where the current sourcing capacity of transistor P1 is sufficient to source each of the gate-controlled power driver circuits 205A and 205B, the use of a single transistor P1 reduces the area consumed by the header circuit 202.

[0047] The control circuit 204 includes a first inverter 206 and a second inverter 208. The first inverter 206 is configured to receive the control signal NSLEEPin and invert it to generate the control signal NSLEEPin'. Therefore, if the control signal NSLEEPin is received at a high voltage state (e.g., at or near TVDD), the first inverter 206 is configured to generate the control signal NSLEEPin' at a low voltage state (e.g., at or near VSS). If the control signal NSLEEPin is received at a low voltage state (e.g., at or near VSS), the first inverter 206 is configured to generate the control signal NSLEEPin' at a high voltage state (e.g., at or near TVDD).

[0048] In this embodiment, the first inverter 206 includes a PMOS transistor P3 and an NMOS transistor N1. The PMOS transistor P3 has a source connected to receive a non-gated reference voltage TVDD and a drain connected to a node nd02. The body contact of the PMOS transistor P3 is connected to receive the non-gated reference voltage TVDD. Node nd02 is connected to a node nd01 of the circuit 202. The NMOS transistor N1 has a drain connected to the node nd02 and a source connected to receive a reference voltage VSS (e.g., a ground voltage). The body contact of the NMOS transistor N1 is connected to receive a reference voltage VBB. The gate contact of the PMOS transistor P3 and the gate contact of the NMOS transistor N1 are both connected to a node nd03. A control signal NSLEEPin is received at the node nd03.

[0049] Therefore, if the control signal NSLEEPin is received at a low voltage (e.g., at or near VSS), the PMOS transistor P3 is turned on and the NMOS transistor N1 is turned off. Consequently, the PMOS transistor P3 pulls the voltage at node nd02 up to or near TVDD, thereby providing the control signal NSLEEPin' at or near TVDD. Consequently, the voltage at node nd01 is at a high voltage at or near TVDD. Consequently, the PMOS transistors P1 and P2 are turned off, thereby cutting off the power to the gate-controlled power driver circuits 205A and 205B.

[0050] On the other hand, if control signal NSLEEPin is in a high voltage state (at or near TVDD), PMOS transistor P3 turns off and NMOS transistor N1 turns on. Consequently, NMOS transistor N1 pulls the voltage at node nd02 down to or near VSS, so that control signal NSLEEPin' is at or near VSS. Consequently, node nd01 is in a low voltage state at or near VSS. Consequently, PMOS transistors P1 and PMOS transistors P2 turn on to provide gate reference voltage VVDD to gate power driver circuits 205A and 205B.

[0051] The second inverter 208 is configured to generate a control signal NSLEEPout from the control signal NSLEEPin'. More specifically, the second inverter 208 is configured to invert the control signal NSLEEPin' and generate the control signal NSLEEPout. Therefore, if the second inverter 208 receives the control signal NSLEEPin' at a high voltage state (e.g., at or near TVDD), the second inverter 208 is configured to generate the control signal NSLEEPout at a low voltage state (e.g., at or near VSS). If the second inverter 208 receives the control signal NSLEEPin' at a low voltage state (e.g., at or near VSS), the second inverter 208 is configured to generate the control signal NSLEEPout at a high voltage state (e.g., at or near TVDD).

[0052] In this embodiment, the second inverter 208 includes a PMOS transistor P4 and an NMOS transistor N2. The PMOS transistor P4 has a source connected to receive a non-gated reference voltage TVDD and a drain connected to a node nd04. The body contact of the PMOS transistor P4 is connected to receive the non-gated reference voltage TVDD. The NMOS transistor N2 has a drain connected to the node nd04 and a source connected to receive a reference voltage VSS (e.g., a ground voltage). The body contact of the NMOS transistor N2 is connected to receive a reference voltage VBB. The gate contact of the PMOS transistor P4 and the gate contact of the NMOS transistor N2 are both connected to a node nd01. A control signal NSLEEPin' is provided at the node nd01.

[0053] Therefore, if the control signal NSLEEPin' is in a low voltage state (e.g., at or near VSS), the PMOS transistor P4 is turned on and the NMOS transistor N2 is turned off. The PMOS transistor P4 thus pulls the voltage at node nd04 up to or near TVDD, causing the control signal NSLEEPout to be at or near TVDD. Consequently, the voltage at node nd04 is in a high voltage state at or near TVDD. In this manner, the control signal NSLEEPout indicates that the header circuit 202 is turned on and is providing the gate control voltage VVDD to the gated power driver circuits 205A and 205B.

[0054] On the other hand, if the control signal NSLEEPin' is in a high voltage state (at or near TVDD), the PMOS transistor P4 is turned off and the NMOS transistor N2 is turned on. Consequently, the NMOS transistor N2 pulls the voltage at the node nd04 down to or near VSS, causing the control signal NSLEEPout to be in a low voltage state at or near VSS. In this manner, the control signal NSLEEPout instructs the header circuit 202 to shut down, thereby cutting off power to each of the gated power driver circuits 205A and 205B.

[0055] Figure 3A and Figure 3B 3 is a corresponding layout diagram 300 showing cell 302A and cell 302B according to some embodiments.

[0056] Cell 302A and cell 302B are representations of one embodiment of region 102 in semiconductor device 100 . Figure 3A The front side 304 of the layout diagram 300 is shown. Figure 3B Shown is a back side 306 of the layout diagram 300. The front side 304 is above a semiconductor substrate 308 and the back side 306 is below the semiconductor substrate 308.

[0057] Figures 3A to 3B The layout diagram is a representation of a semiconductor device. The structure in the semiconductor device is represented by the pattern (also called shape) in the layout diagram. For the sake of simplicity of discussion, we call it Figures 3A to 3B 3. The elements in the layout diagrams of FIG. 3 (and other layout diagrams included herein) are treated as if they were structures rather than patterns themselves. For example, pattern 210 represents an active area. In some embodiments, the active area is referred to as oxide-dimensioned (OD). In the following discussion, element 336 is referred to as front conductive line 336 rather than front conductive pattern 336.

[0058] For simplicity of explanation, Figure 3A The structure in the semiconductor substrate 308 and the structure in the metal layer M0 are shown, but the structures in other layers are not shown. Figure 3B The structure in the BMO layer is shown, but not the structure in other layers.

[0059] In this embodiment, cell 302A includes a top boundary 310 and a bottom boundary 312 extending in a first direction parallel to the X axis. Extending in a second direction parallel to the Y axis are a left boundary 314 and a right boundary 316. Thus, the first and second directions are orthogonal to each other.

[0060] In this embodiment, cell 302B includes a top boundary 312 and a bottom boundary 318 extending in a first direction. A left boundary 320 and a right boundary 322 extend in a second direction.

[0061] Cell 302A and cell 302B are adjacent to each other. Also, note that the bottom boundary 312 of cell 302A is the same as the top boundary 312 of cell 302B. Thus, cell 302A and cell 302B are adjacent to each other with respect to boundary 312 and with respect to the Y-axis.

[0062] The layout cell 302A is a dual-mode cell. The dual-mode cell (i.e., a gated power-driven cell) is powered by VVDD and can therefore be powered by a header circuit, such as Figure 2 The header circuit 202 shown in FIG is turned on and off. Layout cell 302B is a single-mode cell (or non-gated cell). Single-mode cells (i.e., non-gated power-driven cells) are powered by TVDD and therefore cannot be turned on and off by the header circuit. Conversely, single-mode cells are always powered by TVDD and cannot be turned on and off by the header circuit.

[0063] Power supply through Figure 3A The positive side of 304 and Figure 3B The back surface 306 is assigned to the adjacent unit 302A and unit 302B.

[0064] exist Figure 3A On the front side 304, from top to bottom relative to the Y-axis, cell 302A includes a front power rail 324, a front conductor 326, a front conductor 328, a front conductor 330, a front conductor 332, and a front power rail 334.

[0065] exist Figure 3B On the back side 306 , from top to bottom relative to the Y-axis, cell 302B includes a front power rail 334 , a front conductor 336 , a front conductor 338 , a front conductor 340 , a front conductor 342 , and a front power rail 344 .

[0066] Each of front-side conductive lines 326, 328, 330, 332, 336, 338, 340, and 342, and front-side power rails 324, 334, and 344 has a major axis extending in a first direction and a minor axis extending in a second direction. Furthermore, front-side conductive lines 326, 328, 330, 332, 336, 338, 340, and 342, and front-side power rails 324, 334, and 344 are parallel to one another in the first direction and spaced apart by a pitch P1 relative to the Y-axis. Each of front-side conductive lines 326, 328, 330, 332, front-side conductive lines 336, 338, 340, and 342, and front-side power rails 324, 334, and 344 has a width W1, where W1 is the length relative to the minor axis of the structure, i.e., the length relative to the Y-axis. In some embodiments, each of the front side conductive lines 326, 328, 330, 332, 336, 338, 340, and 342 and the front side power rails 324, 334, and 344 are formed in the same metal layer, such as described above with respect to FIG. Figure 1B In some embodiments, W1 is equal to about (0.4×P1) to (0.6×P1).

[0067] exist Figure 3A , relative to the Y-axis, the upper half (i.e., half the width) of front power rail 324 is outside of cell 302A, while the lower half (i.e., half the width) of front power rail 324 is inside of cell 302A. The dividing line between the upper half of front power rail 324 outside of cell 302A and the lower half of front power rail 324 is top boundary 310. Front power rail 324 is configured to receive reference voltage VVDD. However, front power rail 324 is not used to distribute reference voltage VVDD to other components (not shown) in cell 302A. Instead, the presence of reference voltage VVDD on front power rail 324 serves to shield cell 302A.

[0068] With respect to the X-axis, front-side conductive lines 326, 328, 330, and 332 each have a full width relative to cell 302A, that is, each extends from left side 314 to right side 316. In some embodiments, at least some of front-side conductive lines 326, 328, 330, and 332 and front-side power rail 334 are configured to receive various signals, such as control signals, input signals, output signals, etc. The various signals are distributed (or routed) to semiconductor components (not shown) formed on semiconductor substrate 308 through one or more of front-side conductive lines 326, 328, 330, and 332.

[0069] exist Figure 3A, with respect to the Y-axis, the upper half of front power rail 334 is within cell 302A and the lower half of front power rail 334 is within cell 302B. The dividing line between the upper half of front power rail 334 and the lower half of front power rail 334 is bottom boundary 312. Front power rail 334 is configured to receive a reference voltage VSS (e.g., ground). However, front power rail 334 is not used to distribute reference voltage VSS to other components (not shown) in cells 302A and 302B. Instead, the presence of reference voltage VSS on front power rail 334 serves to shield cells 302A and 302B.

[0070] Each of front-side conductive lines 336 , 338 , 340 , and 342 has a full width within cell 302B. In some embodiments, at least some of front-side conductive lines 336 , 338 , 340 , and 342 are configured to receive various signals, such as control signals, input signals, output signals, and the like. The various signals are distributed (or routed) to semiconductor components (not shown) formed on semiconductor substrate 308 through one or more of front-side conductive lines 336 , 338 , 340 , and 342 .

[0071] In this embodiment, the upper half of front power rail 344 is within cell 302B and the lower half of front power rail 344 is outside cell 302B. The dividing line between the upper half of front power rail 344 and the lower half of front power rail 344 is bottom boundary 318. Front power rail 344 is configured to receive reference voltage VVDD. However, front power rail 344 is not used to distribute reference voltage VVDD to cell 302B. Instead, front power rail 344 is used to shield cell 302B.

[0072] If front power rails 324, 334, and 344 are not connected to their respective reference voltages VVDD and VSS, in some embodiments, front conductors 336, 338, 340, and 342 will be affected by decoupling capacitance and noise. In some embodiments, connecting front power rails 324, 334, and 344 to their respective reference voltages VVDD and VSS stabilizes the signals on front conductors 336, 338, 340, and 342 and provides better performance. In other embodiments, layout 300 represents a circuit where circuit area must be minimized. In this case, front power rails 324, 334, and 344 are used to transmit signals and, therefore, will be front conductors 324, 334, and 344.

[0073] exist Figure 3BLayout 300 provides power distribution to semiconductor components (not shown) in semiconductor substrate 308 at back side 306. Layout 300 includes back side power rails 346, 348, 350, 352, and 354. Back side power rails 346, 348, 350, 352, and 354 have major axes extending in a first direction and minor axes extending in a second direction. Back side power rails 348, 350, and 352 are parallel to back side power rail 346 and back side power rail 354. However, each of back side power rails 348, 350, and 352 is located between back side power rail 346 and back side power rail 348 with respect to the Y-axis. Furthermore, back side power rails 348, 350, and 352 are substantially aligned with respect to the Y-axis but separated from each other with respect to the X-axis. In this embodiment, back side power rail 350 is located between back side power rail 348 and back side power rail 352 with respect to the X-axis. Furthermore, with respect to the X-axis, back power rail 348 is the left-most back power rail, and back power rail 352 is the right-most back power rail.

[0074] Each of back power rails 348, 350, and 352 is separated from back power rail 346 by a pitch P2 relative to the Y-axis. Furthermore, each of back power rails 348, 350, and 352 is separated from back power rail 354 by a pitch P2 relative to the Y-axis. In this embodiment, pitch P2 is approximately equal to the cell height of one of cells 302A and 302B. Each of back power rails 346, 348, 350, 352, and 354 has a width W2, where W2 is the length relative to the minor axis of the structure, i.e., the Y-axis. In some embodiments, width W2 is between approximately (0.2×P2) and (0.7×P2).

[0075] like Figure 3B As shown, with respect to the Y-axis, the upper half of back power rail 346 is outside of cell 302A, while the lower half of back power rail 346 is within cell 302A. The dividing line between the upper half of back power rail 346 and the lower half of back power rail 346 is cell 302A boundary line 310. The upper half of each of back power rails 348, 350, and 352 is within cell 302A, while the lower half of each of back power rails 348, 350, and 352 is within cell 302B. The dividing line between the upper half of each of back power rails 348, 350, and 352 and the lower half of each of back power rails 348, 350, and 352 is cell 302A and 302B boundary line 312. The upper half of back power rail 354 is inside cell 302B, while the lower half of back power rail 346 is outside cell 302B. The dividing line between the upper half of back power rail 354 and the lower half of back power rail 354 is boundary line 318 of cell 302B.

[0076] Each of back power rails 346 and 354 is configured to receive a reference voltage VVDD. Each of back power rails 348 and 352 is configured to receive a reference voltage VSS. Back power rail 350 is configured to receive a reference voltage TVDD. Back power rails 346, 348, 350, 352, 354 are thus used to distribute different reference voltages TVDD, VVDD, and VSS to semiconductor components (not shown) on semiconductor substrate 308. Back power rails 346, 348, 350, 352, and 354 on back side 306 are isolated from front side conductors 326 to 332 and 336 to 342 on front side 304. Furthermore, this arrangement allows a single-mode cell (e.g., cell 302A) to be adjacent to a single-mode cell (e.g., cell 302B) while distributing reference voltages TVDD, VVDD, and VSS.

[0077] Figure 3C is a layout diagram 356 representing a semiconductor device according to some embodiments.

[0078] Layout 356 is for viewing from the back side 306 (see Figure 3D ) is an illustration of a technique for providing reference voltages VVDD and VSS to the front side 304 so as to provide the reference voltages VVDD and VSS to the power rails 324, 334, and 344.

[0079] like Figure 3C As shown, the semiconductor device includes a plurality of rows and columns C of cells 302. In some embodiments, examples of cells 302 include cells 302A, 302B, another cell described herein, and the like.

[0080] exist Figure 3C , with respect to the X-axis, the pairs of columns C are adjacent to each other. A gap GB extends along the first direction and is located between the two pairs of columns C. With respect to the X-axis, the left side of the two pairs of columns C is the gap GL, and the right side of the two pairs of columns C is the gap GR. On the left side of the gap GL and / or on the right side of the gap GR, the layout diagram 356 includes a power fill region PF. The power fill region PF facilitates the power rails 324, 334, and 344 to obtain the reference voltages VVDD and VSS from the back side 306 of the semiconductor device. Figure 3C , the power rails 324 , 334 , and 344 extend in the direction of the X-axis along the boundaries of the adjacent cells 302 across the gaps GL, GB, GR and also across the power fill region PF.

[0081] Figure 3D According to some embodiments Figure 3C Cross-sectional view along line IIIC.

[0082] Figure 3DThe semiconductor substrate 308 is included. On the back side 306, the power fill region PF includes a transistor element contact layer BVD (contact-to-transistor-component) and a back side metal layer BM0. In this embodiment, back side power rails 346, 348, 354 are provided in the cell 302 (see FIG. Figure 3C ), gap GL, GB, GR (see Figure 3C ) and extends below the power fill region PF. As described above, backside power rail 346 is configured to receive a reference voltage VVDD, backside power rail 348 is configured to receive a reference voltage VSS, and backside power rail 354 is configured to receive a reference voltage VVDD. In this embodiment, backside power rails 346, 348, 354 are located in backside metal layer BM0. Backside vias 358 in backside via layer BVD connect backside power rails 346, 348, 354 to different semiconductor portions 360 of semiconductor substrate 308.

[0083] From the front to the back, relative to the Z axis, the front metal layer M1, the front via layer VIA0, the front metal layer M0, the front via layer VGD, and the front MD layer are in the power filling area PF in the front 304. The Z axis is parallel to the X axis (see Figure 1A ) and the Y-axis are orthogonal. Front metal vias 362 in front via layer VD connect semiconductor portion 360 to conductor 363 in front metal layer M0. Front metal vias 364 in front via layer VIA0 connect conductor 363 to conductors 324, 334, 344 in front metal layer M1. In other embodiments, conductors 324, 334, 344 are located in a front metal layer other than front metal layer M1, such as front metal layer M0. Conductors 324, 334, 344 are biased by reference voltages VVDD and VSS, as described above. Semiconductor portion 306 is configured to electrically connect corresponding VD structures 362 and backside vias 358. In some embodiments, semiconductor portion 306 is doped to conduct current.

[0084] Figure 4A and Figure 4B is a corresponding layout diagram 400 of cell 402A and cell 402B according to some embodiments.

[0085] Figure 4A is a schematic diagram of the front side 404 of the layout diagram 400, Figure 4B is a schematic diagram of the back side 406 of the layout diagram 400 .

[0086] Layout 400 and Figure 3A 、 3B Similar components in layout 400 have the same Figure 3A 、 3B300. Therefore, the discussion will focus on the differences between layout 300 and layout 400.

[0087] Regarding front side 404, front side conductor 407 is located at boundary 312 between cell 402A and cell 402B. The upper half of front side conductor 407 is within cell 402A, and the lower half of front side conductor 407 is within cell 402B. Front side conductor 407 has a major axis extending along the X-axis and a minor axis extending along the Y-axis. In this embodiment, front end power rail 407 is configured to receive control signal NSLEEPin'.

[0088] exist Figure 4A , cell 402A is located between front power rail 324 and front conductor 407. Cell 402A includes front power rails 408, 410, 412, and 414 in layout 402A. Each of front power rails 408, 410, 412, and 414 has a major axis extending in the X-axis direction and a minor axis extending in the Y-axis direction. Front power rail 408 is configured to receive a reference voltage TVDD, front power rail 410 is configured to receive a reference voltage VVDD, front power rail 412 is configured to receive a reference voltage TVDD, and front power rail 414 is configured to receive a reference voltage VVDD. Each of front power rails 408, 410, 412, and 414 is configured to distribute reference voltages TVDD and VVDD to circuits (not shown) in semiconductor substrate 308 within cell 402A.

[0089] Cell 402B is located between front-side conductor 407 and front-side power rail 324. In layout 402B, cell 402B includes front-side power rails 416, 418, 420, and 422. Each of front-side power rails 416, 418, 420, and 422 has a major axis extending in the X-axis direction and a minor axis extending in the Y-axis direction. Front-side power rail 416 is configured to receive a reference voltage VVDD, front-side power rail 418 is configured to receive a reference voltage TVDD, front-side power rail 420 is configured to receive a reference voltage VVDD, and front-side power rail 422 is configured to receive a reference voltage TVDD. Each of front-side power rails 416, 418, 420, and 422 is configured to distribute reference voltages TVDD and VVDD to circuitry (not shown) in semiconductor substrate 308 within cell 402B.

[0090] In this embodiment, Figure 4B The back side 406 of the layout diagram 400 shown in FIG. Figure 3B 3. In some embodiments, unit 402A and unit 402B are combined to provide a header unit including header circuit 202.

[0091] Figure 5A and Figure 5B 5 is a corresponding layout diagram 500 showing cell 502A and cell 502B according to some embodiments.

[0092] Figure 5A is a schematic diagram of the front side 504 of the layout diagram 500, Figure 5B is a schematic diagram of the back side 506 of the layout diagram 500.

[0093] Layout 500 and Figure 4A 、 4B The similar components in the layout 500 have the same Figure 4A 、 4B 400. Therefore, the discussion will focus on the differences between layout 500 and layout 400.

[0094] Figure 5A The front 504 and Figure 4A The back side 506 also includes back side power rails 346 and back side power rails 354, which are positioned and configured as described above with respect to Figure 3B As explained, and they receive the reference voltage VVDD accordingly. However, in this embodiment, Figure 5B The back side 506 includes the back side power rail 348' but omits the Figure 3B The back power rails 350 and 352 are configured to receive a reference voltage VSS. The back power rail 348' has a long axis extending in the X-axis direction and a short axis extending in the Y-axis direction. Figure 5B , back power rail 348 ′ has a width of W2 , similar to back power rail 346 and back power rail 354 .

[0095] Back power rail 348' is separated from back power rail 346 by a pitch P2. Furthermore, back power rail 348' is separated from back power rail 352 by a pitch P2. In this embodiment, pitch P2 is approximately equal to the cell height of one of cells 502A, 502B.

[0096] like Figure 5B As shown, the upper half of back power rail 348' is within cell 502A, while the lower half of back power rail 348' is within cell 302B. The dividing line between the upper half of back power rail 348' and the lower half of back power rail 348' is the boundary line 312 between cells 502A and 502B. In some embodiments, cell 502A and cell 502B are combined into a header cell that includes header circuit 202.

[0097] Figure 6A and Figure 6Bis a corresponding layout diagram 600 of cell 602A according to some embodiments.

[0098] Figure 6A is a schematic diagram of the front side 604 of the layout diagram 600, Figure 6B is a schematic diagram of the back side 606 of the layout diagram 600.

[0099] Regarding front side 604, unit 602A and Figure 3A The unit 302A and the front face 304 have similarities. Similar components in the unit 602A on the front face 604 have similarities. Figure 3A 304 in the same element number. Therefore, the discussion of the front face 604 will focus on the front face 604 in the unit 602A and the front face 604 in the unit 602A. Figure 3A The difference between the front face 304 of the unit 302A.

[0100] exist Figure 6A In the embodiment, the front conductor 326 is configured to receive the input signal IN and the front conductor 332 is configured to provide the output signal Out. Figure 3A ), cell 602A includes a front power rail 628 between front side conductor 326 and front side conductor 332 relative to the Y-axis. Front side power rail 328 is configured to receive a reference voltage TVDD. In some embodiments, reference voltage TVDD is distributed to semiconductor components (not shown) in semiconductor substrate 308 having front side power rail 328.

[0101] Back side 606 of cell 602A is identical to back side 506 of cell 502A. Thus, back side 606 of cell 602 also includes back side power rail 346 configured to receive VVDD and back side power rail 348' configured to receive VSS.

[0102] Figure 7A and Figure 7B is a corresponding layout diagram 700 of cell 702A according to some embodiments.

[0103] Figure 7A is a schematic diagram of the front side 704 of the layout diagram 700, Figure 7B is a schematic diagram of the back side 706 of the layout diagram 700.

[0104] The front face 704 of the unit 702A is Figure 6A The front side 604 of unit 602A is the same as that of the unit 702A. Figure 6B The back side 606 of the unit 602A is shown to be identical except for the Figure 7B In FIG. 4 , back power rail 346 is configured to receive reference voltage TVDD instead of reference voltage VVDD.

[0105] Figure 8A and Figure 8B is a corresponding layout diagram 800 of cell 802A according to some embodiments.

[0106] Figure 8A is a schematic diagram of the front side 804 of the layout diagram 800, Figure 8B is a schematic diagram of the back side 806 of the layout diagram 800.

[0107] The front face 804 of the unit 802A is Figure 6A The front side 604 of the unit 602A is identical except that the front side conductor 324 is configured to receive Figure 8A The back side 806 of the cell 802A is connected to the reference voltage TVDD instead of the reference voltage VVDD. Figure 6B The back side 606 of the unit 602A is the same.

[0108] Figure 9 is a circuit diagram according to some embodiments.

[0109] More specifically, circuit 900 includes four inverters / stages, including stages 902(1) to 902(4). Stage 902(1) includes a PMOS device P1 and an NMOS device N1. The gate of the PMOS device P1 and the gate of the NMOS device N1 are configured to receive an input signal IN at an input node I(1). The drain of the PMOS device P1 and the drain of the NMOS device N1 are connected to an output node O(1). The PMOS device P1 and the NMOS device N1 are configured to generate an output signal OUT at the output node O(1). The source of the PMOS device P1 is configured to receive a reference voltage TVDD, and the source of the NMOS device N1 is configured to receive a reference voltage VSS.

[0110] Stage 902(2) includes a PMOS device P2 and an NMOS device N2. The gate of the PMOS device P2 and the gate of the NMOS device N2 are configured to receive an input signal IN at an input node I(2). The drain of the PMOS device P2 and the drain of the NMOS device N2 are connected to an output node O(2). The PMOS device P2 and the NMOS device N2 are configured to generate an output signal OUT at the output node O(2). The source of the PMOS device P2 is configured to receive a reference voltage TVDD, and the source of the NMOS device N2 is configured to receive a reference voltage VSS.

[0111] Stage 902(3) includes a PMOS device P3 and an NMOS device N3. The gate of the PMOS device P3 and the gate of the NMOS device N3 are configured to receive an input signal IN at an input node I(3). The drain of the PMOS device P3 and the drain of the NMOS device N3 are connected to an output node O(3). The PMOS device P3 and the NMOS device N3 are configured to generate an output signal OUT at the output node O(3). The source of the PMOS device P3 is configured to receive a reference voltage TVDD, and the source of the NMOS device N3 is configured to receive a reference voltage VSS.

[0112] Stage 902(4) includes a PMOS device P4 and an NMOS device N4. The gate of the PMOS device P4 and the gate of the NMOS device N4 are configured to receive an input signal IN at an input node I(4). The drain of the PMOS device P4 and the drain of the NMOS device N4 are connected to an output node O(4). The PMOS device P4 and the NMOS device N4 are configured to generate an output signal OUT at the output node O(4). The source of the PMOS device P4 is configured to receive a reference voltage TVDD, and the source of the NMOS device N4 is configured to receive a reference voltage VSS.

[0113] exist Figure 9 In FIG. 9 , the sources of PMOS devices P1 through P4 are connected to one another. Furthermore, the sources of NMOS devices N1 through N4 are connected to one another. Input nodes I(1)-I(4) are connected to one another. Output nodes O(1) through O(4) are connected to one another. In this manner, stages 902(1) through 902(4) operate together to generate an output signal Out in response to input signal IN.

[0114] Figure 10A and Figure 10B is a corresponding layout diagram 600A(1) of cell 602A(1) according to some embodiments.

[0115] Layout 600A(1) and Figure 6A and Figure 6B The similar components in the layout 600A(1) have the same Figure 6A and Figure 6B Therefore, the discussion will focus on the differences between layout 600A(1) and layout 600. FIG. 10A to FIG. 10B yes Figure 9 900 is a representation of a circuit.

[0116] Figure 10A is a schematic diagram of the front face 604 of unit 602A(1), Figure 10B is a schematic diagram of the back side 606 of the unit 602A(1). The unit 602A(1) is Figure 6Aand Figure 6B A version of unit 602A is shown in FIG. Unit 602A(1) also represents Figure 9 An example of a four-stage circuit 900 is shown.

[0117] like Figure 10A As shown, the semiconductor substrate 308 includes active regions OD-1 and OD-2. The active regions are schematically shown with the label OD in the drawings (see FIG. Figure 1B The active regions OD-1 and OD-2 are elongated along a first direction, ie, parallel to the X-axis. In some embodiments, the active region OD-1 includes P-type conductivity and the active region OD-2 includes N-type conductivity.

[0118] A plurality of gates PO-1, PO-2, PO-3, and PO-4 are located above the active regions OD-1 and OD-2. The gates PO-1, PO-2, PO-3, and PO-4 extend along a second direction, that is, parallel to the Y-axis that transverses the X-axis. The gates PO-1, PO-2, PO-3, and PO-4 are arranged spaced apart from each other at regular pitches in the X-axis direction. If there are no other gates between two gates, the two gates are considered to be directly adjacent. In some embodiments, the regular pitch represents a contacted poly pitch (CPP) of a corresponding semiconductor process technology node. In some embodiments, the gates PO-1, PO-2, PO-3, and PO-4 include a conductive material, such as polysilicon, sometimes referred to as "poly". The gates PO-1, PO-2, PO-3, and PO-4 are schematically illustrated in the accompanying drawings with the label "PO". Other conductive materials for the gates, such as metals, are within the scope of various embodiments. In some embodiments, the gates PO-1, PO-2, PO-3, and PO-4 are in the PO layer, and the PO layer is relative to the Z-axis (see Figure 2 ) is located between the semiconductor substrate 308 and the via layer VGD (see Figure 2 )between.

[0119] Drain / source regions 1002, 1004, 1006, 1008, and 1110 are formed on either side of gates PO-1, PO-2, PO-3, and PO-4 in active region OD-1. Drain / source regions 1012, 1014, 1016, 1018, and 1020 are formed on corresponding sides of gates PO-1, PO-2, PO-3, and PO-4 in active region OD-2. PMOS device P1 includes gate PO-1, a drain in the form of drain / source region 1002, and a source in the form of drain / source region 1004. PMOS device P2 includes gate PO-2, a drain in the form of a drain / source region 1004. PMOS device P3 includes gate PO-3, a drain in the form of drain / source region 1006, and a source in the form of drain / source region 1008. Device P4 includes a gate PO- 4 , a drain in the form of drain / source region 1010 , and a source in the form of drain / source region 1008 .

[0120] NMOS device N1 includes gate PO-1, a drain in the form of drain / source region 1012, and a source in the form of drain / source region 1014. NMOS device N2 includes gate PO-2, a drain in the form of drain / source region 1016, and a source in the form of drain / source region 1014. NMOS device N3 includes gate PO-3, a drain in the form of drain / source region 1016, and a source in the form of drain / source region 1018. NMOS device N4 includes gate PO-4, a drain in the form of drain / source region 1020, and a source in the form of drain / source region 1018.

[0121] PMOS device P1 and NMOS device N1 are in stage 902(1) of circuit 900. PMOS device P2 and NMOS device N2 are in stage 902(2) of circuit 900. PMOS device P3 and NMOS device N3 are in stage 902(3) of circuit 900. PMOS device P4 and NMOS device N4 are in stage 902(4) of circuit 900.

[0122] exist Figure 10A In the embodiment, the front power rail 628 is configured to receive a reference voltage TVDD. Vias PS in the via layer VGD are configured to connect the drain / source regions 1002, 1006, 1010 to the front power rail 628, so that the source of each of the PMOS devices P1-P4 receives the reference voltage TVDD. More specifically, in this embodiment, drain / source contacts are in the MD metal layer and on each of the drain / source regions 1002, 1006, 1010. Each of the vias PS connects the front power rail 628 to a drain / source contact connected to each of the drain / source regions 1002, 1006, 1010.

[0123] exist Figure 10A, the front side conductive line 326 is configured to receive the input signal IN. The vias GI in the via layer VGD are configured to connect the gates PO-1, PO-2, PO-3, and PO-4 to the front side conductive line 326, so that the gate of each of the PMOS devices P1-P4 and the NMOS devices N1-N4 receives the input signal IN.

[0124] The drain / source contact in the MD layer connects the drain / source region 1004 to the drain / source region 1014. In addition, the drain / source contact in the MD layer connects the drain / source region 1008 to the drain / source region 1018. Figure 10A In the embodiment, the front side conductive line 332 is configured to receive the output signal Out. The via DO in the via layer VGD is configured to connect one of the drain / source contacts on the drain / source regions 1014 and 1018 to the front side conductive line 332, so that the drain of each of the PMOS devices P1-P4 and the NMOS devices N1-N4 outputs the output signal Out.

[0125] Finally, if Figure 10B As shown, the back power rail 348' is configured to receive a reference voltage VSS (eg, ground voltage). Back side vias SG are located in the back side via layer BVD and are each connected to a corresponding one of the drain / source regions 1012, 1016, 1020 (see FIG. Figure 10A ). The backside via SG is also connected to the backside power rail 348'. In this way, the source of each of the NMOS devices N1-N4 is configured to receive the reference voltage VSS.

[0126] Because the source of each of the PMOS devices P1 to P4 is configured to receive the reference voltage TVDD, the layout diagram 602A( 1 ) is an example of a single-mode cell (ie, a non-gated power driver cell).

[0127] Figure 11A and Figure 11B is a corresponding layout diagram 600A(2) of cell 602A(2) according to some embodiments.

[0128] Figure 11A is a schematic diagram of the front side 604 of unit 602A(2), Figure 11B is a schematic diagram of the back side 606 of the unit 602A(2). The unit 602A(2) is similar to Figure 10A 、 10B The unit 602A (2) shown in FIG. Similar components are Figure 11A 、 11B With Figure 10A 、 10B For brevity, this discussion focuses on the differences between unit 602A(2) and unit 602A(1).

[0129] exist Figure 11A and Figure 11B In the example, cell 602A(2) includes backside via PS' instead of via PS (see Figure 10A ). In addition, the positive conductor 628 is configured to receive the reference voltage VVDD instead of the reference voltage TVDD. Figure 11A , each backside via PS' is in the backside via layer BVD and is configured to connect a corresponding one of the drain / source regions 1002, 1006, 1010 to the backside reference rail 346. In this manner, the source of each PMOS device P1 to P4 is configured to receive the reference voltage VVDD. Thus, cell 602(A)(2) is an example of a dual-mode cell (i.e., a gated power driver cell).

[0130] Figure 12 is a circuit diagram of a NAND gate 1200 according to some embodiments.

[0131] exist Figure 12 In FIG, NAND1200 is a two-stage NAND gate. Stage 1202 (1) of NAND gate 1200 includes a PMOS device P1, a PMOS device P2, an NMOS device N1, and an NMOS device N2. The gate of PMOS device P1 and the gate of NMOS device N1 are both configured to receive an input signal A1. The drain of PMOS device P1 and the drain of NMOS device N1 are connected to each other. The gate of PMOS device P2 and the gate of NMOS device N2 are configured to receive an input signal A2. The source of PMOS device P1 and the source of PMOS device P2 are configured to receive a reference voltage TVDD. The source of NMOS device N2 is configured to receive a reference voltage VSS. The source of NMOS device N1 is connected to the drain of NMOS device N2. An output signal Out is generated at the drain of PMOS device P1, the drain of PMOS device P2, and the drain of NMOS device N1.

[0132] exist Figure 12In FIG, NAND gate 1200 is a two-stage NAND gate. Stage 1202(2) of NAND gate 1200 includes a PMOS device P3, a PMOS device P4, an NMOS device N3, and an NMOS device N4. The gate of PMOS device P3 and the gate of NMOS device N3 are both configured to receive an input signal A1. The drain of PMOS device P3 and the drain of NMOS device N3 are connected to each other. The gate of PMOS device P4 and the gate of NMOS device N4 are configured to receive an input signal A2. The source of PMOS device P3 and the source of PMOS device P4 are configured to receive a reference voltage TVDD. The source of NMOS device N4 is configured to receive a reference voltage VSS. The source of NMOS device N3 is connected to the drain of NMOS device N4. An output signal Out is generated at the drain of PMOS device P3, the drain of PMOS device P4, and the drain of NMOS device N3.

[0133] like Figure 12 As shown, the gates of PMOS device P1, NMOS device N1, PMOS device P3, and NMOS device N3 are all connected to each other. Furthermore, the source of PMOS device P1, the source of PMOS device P2, the drain of NMOS device N1, the source of PMOS device P3, the source of PMOS device P4, and the drain of NMOS device N3 are all connected to each other to generate output signal Out. The gate of NMOS device N2 is connected to the gate of NMOS device N4.

[0134] Figure 13A and Figure 13B is a corresponding layout diagram 600A(3) of cell 602A(3) according to some embodiments.

[0135] Layout 600A(3) and Figure 6A and 6B The similar components in the layout 600A(3) have the same Figure 6A and 6B Therefore, the discussion will focus on the differences between layout 600A(3) and layout 600. In some embodiments, Figures 13A to 13B The layout diagram is Figure 12 A representation of a NAND gate 1200.

[0136] Figure 13A is a schematic diagram of the front face 604 of unit 602A(3), Figure 13B is a schematic diagram of the back side 606 of the unit 602A(3). The unit 602A(3) is Figure 6A 、 6B A version of unit 602A is shown in FIG. Figure 11A and Figure 11BUnit 602A(1) in Figure 13A and Figure 13B The common components between units 602A(3) in FIG. 6 have the same element numbers and are therefore not discussed again here.

[0137] exist Figure 13A In FIG, the front side conductor 326 is configured to receive the output signal Out. The front side power rail 628 is configured to receive the reference voltage TVDD. The front side conductor 330 is configured to receive the input signal A1. The front side conductor 332 is configured to receive the input signal A2.

[0138] exist Figure 13A In FIG, the source of PMOS device P1 is in drain / source region 1004, and the drain of PMOS device P1 is in drain / source region 1006. Gate PO-2 is the gate of PMOS device P1. The source of PMOS device P2 is in drain / source region 1004, and the drain of PMOS device P2 is in drain / source region 1002. Gate PO-1 is the gate of PMOS device P2. The source of PMOS device P3 is located in drain / source region 1008, and the drain of PMOS device P3 is located in drain / source region 1006. Gate PO-3 is the gate of PMOS device P3. The source of PMOS device P4 is in drain / source region 1008, and the drain of PMOS device P4 is in drain / source region 1010. Gate PO04 is the gate of PMOS device P4.

[0139] exist Figure 13A In FIG. 1 , the source of NMOS device N1 is in drain / source region 1016, and the drain of NMOS device N1 is in drain / source region 1014. Gate PO-2 is the gate of NMOS device N1. The source of NMOS device N2 is in drain / source region 1012, and the drain of NMOS device N2 is in drain / source region 1014. Gate PO-1 is the gate of NMOS device N2. The source of NMOS device N3 is in drain / source region 1018, and the drain of NMOS device N3 is in drain / source region 1016. Gate PO-3 is the gate of NMOS device N3. The source of NMOS device N4 is in drain / source region 1020, and the drain of NMOS device N4 is in drain / source region 1018. Gate PO-4 is the gate of NMOS device N4.

[0140] The drain / source contact in metal layer MD is located on drain / source region 1002. The drain / source contact is connected to via LO1 in via layer VGD, and via LO1 is connected to front-side conductive line 326. The drain / source contact in metal layer MD is located on drain / source region 1006 and drain / source region 1016. The drain / source contact connects drain / source region 1006 and drain / source region 1016. The drain / source contact is connected to via LO2 in via layer VGD, and via LO2 is connected to front-side conductive line 326. The drain / source contact in metal layer MD is located on drain / source region 1010. The drain / source contact is connected to via LO3 in via layer VGD, and via LO3 is connected to front-side conductive line 326.

[0141] The drain / source feature contact in metal layer MD is located on drain / source region 1004. The drain / source contact is connected to via HO1 in via layer VGD, and via HO1 is connected to front side power rail 628. The drain / source feature contact in metal layer MD is located on drain / source region 1008. The drain / source contact is connected to via HO2 in via layer VGD, and via HO2 is connected to front side power rail 628.

[0142] exist Figure 13A and Figure 13B In FIG. 3 , a via BO1 in the backside via layer BVD connects the drain / source region 1012 to the backside power rail 348 ′. Furthermore, a via BO2 in the backside via layer BVD connects the drain / source region 1020 to the backside power rail 348 ′.

[0143] Because the sources of the PMOS devices P1, P2, P3, and P4 are powered by the reference voltage TVDD, the cell 602A(3) is an example of a single-mode cell (ie, a non-gated power-driven cell).

[0144] Figure 14A and Figure 14B is a corresponding layout diagram 600A(4) of cell 602A(4) according to some embodiments.

[0145] Figure 14A is a schematic diagram of the front face 604 of unit 602A(4), Figure 14B is a schematic diagram of the back side 606 of the unit 602A(4). The unit 602A(4) is similar to Figure 13A 、 13B The unit 602A (3) is shown. Similar components are Figure 14A 、 14B In and in Figure 13A 、 13B For brevity, this discussion focuses on the differences between unit 602A(3) and unit 602A(4).

[0146] exist Figure 14A and Figure 14B In the example, unit 602A(4) includes backside vias HO1', HO2' instead of vias HO1, HO2 (see Figure 13A ). In addition, the front conductor 628 is configured to receive the reference voltage VVDD instead of the reference voltage TVDD. However, in this embodiment, the backside via HO1' is in the backside via layer BVD and is configured to connect the drain / source region 1004 to the backside reference rail 346. In addition, the backside via HO2' is in the backside via layer BVD and is configured to connect the drain / source region 1008 to the backside reference rail 346. In this way, the source of each of the PMOS devices P1 to P4 is configured to receive the reference voltage VVDD. Therefore, the cell 602(A)(4) is an example of a dual-mode cell (i.e., a gated power drive cell).

[0147] Figure 15 is a flow chart of a method 1500 of fabricating a semiconductor device according to some embodiments.

[0148] According to some embodiments, method 1500 may be implemented, for example, using EDA system 1900 ( Figure 19 , discussed below) and the Integrated Circuit (IC) Manufacturing System 2000 ( Figure 20 , discussed below). Examples of semiconductor devices that can be fabricated according to method 1500 include Figure 1A The semiconductor device 100, Figure 2 The circuit 200 is composed of Figure 3A 、 3B The semiconductor device represented by the layout diagram 300 is composed of Figure 3C 、 3D The semiconductor device represented by the layout diagram 356 is composed of Figure 4A 、 4B The semiconductor device represented by the layout diagram 400 is composed of Figure 5A 、 5B The semiconductor device represented by the layout diagram 500 is composed of Figure 6A 、 6B The semiconductor device represented by the layout diagram 600 is composed of Figure 7A 、 7B The semiconductor device represented by the layout diagram 700 is composed of Figure 8A 、 8B The semiconductor device represented by the layout diagram 800, Figure 9 The circuit 900 is composed of Figure 10A 、 10B The semiconductor device represented by unit 602A(1) in Figure 11A 、 11BThe semiconductor device represented by unit 602A(2) in FIG. Figure 12 The circuit 1200 is composed of Figure 13A , Figure 13B The semiconductor device represented by unit 602A(3) in Figure 14A , Figure 14B The unit 602A(4) in FIG. 4 represents a semiconductor device.

[0149] exist Figure 15 In the method 1500, blocks 1502 to 1504 are included. At block 1502, a layout diagram is generated, which includes, among other aspects, one or more of the layout diagrams disclosed herein. According to some embodiments, block 1502 may be implemented, for example, using the EDA system 1900 ( Figure 19 , discussed below). Flow proceeds from block 1502 to block 1504.

[0150] At block 1504, based on the layout, at least one of: (A) performing one or more photolithography exposures, (B) fabricating one or more semiconductor masks, and (C) fabricating at least one of one or more components in a semiconductor device layer is performed. Figure 20 Discussion.

[0151] Figure 16 is a flowchart 1600 of a method of fabricating a semiconductor device according to some embodiments.

[0152] exist Figure 16 , flowchart 1600 is executed Figure 15 One embodiment of block 1504 in 15. Figure 16 , flowchart 1600 includes blocks 1602 to 1612.

[0153] At block 1602, a semiconductor substrate includes one or more active semiconductor components, wherein a front side is defined above the semiconductor substrate and a back side is defined below the semiconductor substrate. Examples of semiconductor substrates include Figure 2 The semiconductor substrate 113, Figure 3A 、 3C , 3D, 5A, 6A, 7A, 8A, 10A, 11A, 13A, and 14A, etc. Flow proceeds from block 1602 to block 1604.

[0154] At block 1604, a first front side power rail is formed on the front side of the semiconductor substrate. Examples of the first front side power rail include Figure 3A 、 3C , 3D, 4A, 5A, 6A, 7A, 8A, 10A, 11A, 13A, 14A in each of the positive power rails 324, 334, 344. Figure 4A 、5A The positive power rails 408, 410, 412, 414, 416, 418, 420, 422 of each of Figure 6A 、 7A , 8A, 10A, 11A, 13A, 14A, etc. Flow proceeds from block 1604 to block 1606.

[0155] At block 1606, the first positive power rail is configured to receive a first reference supply voltage. Examples of the first reference supply voltage include corresponding Figure 2 、 3A To reference voltage TVDD, reference voltage VVDD, and reference voltage VSS in 3D, 4A-4B, 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9, 10A-10B, 11A-11B, 12, 13A-13B, and 14A-14B, etc. Flow proceeds from block 1606 to block 1608.

[0156] At block 1608, a first back side power rail and a second back side power rail are formed on the back side of the semiconductor substrate. Examples of the first back side power rail and the second back side power rail include Figure 3B 、 3D , 4B, 5B, 6B, 7B, 8B, 10B, 11B, 13B and 14B in the back power rails 346, 348, 350, 352, 354, Figure 5B 、 6B , back side power rails 348 ′ in 7B, 8B, 10B, 11B, 13B, and 14B, etc. Flow proceeds from block 1608 to block 1610 .

[0157] At block 1610, the first back power rail is configured to receive a second reference supply voltage. Examples of the second reference supply voltage include corresponding Figure 2 、 3A To reference voltage TVDD, reference voltage VVDD, and reference voltage VSS in 3D, 4A-4B, 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9, 10A-10B, 11A-11B, 12, 13A-13B, and 14A-14B, etc. Flow proceeds from block 1610 to block 1612.

[0158] At block 1612, the second back power rail is configured to receive a third reference supply voltage, wherein the first reference supply voltage, the second reference supply voltage, and the third supply reference voltage are different from each other. Examples of the third reference supply voltage include corresponding Figure 2 、 3AReference voltage TVDD, reference voltage VVDD, and reference voltage VSS in 3D, 4A to 4B, 5A to 5B, 6A to 6B, 7A to 7B, 8A to 8B, 9, 10A to 10B, 11A to 11B, 12, 13A to 13B, and 14A to 14B, etc.

[0159] Figure 17 is a flowchart 1700 of a method of fabricating a semiconductor device according to some embodiments.

[0160] exist Figure 17 , flowchart 1700 is executed Figure 15 One embodiment of block 1504 in . Figure 17 , flowchart 1700 includes blocks 1702 to 1710.

[0161] At block 1702, a semiconductor substrate includes one or more active semiconductor components, wherein a front side is defined above the semiconductor substrate and a back side is defined below the semiconductor substrate. Examples of semiconductor substrates include Figure 2 The semiconductor substrate 113, Figure 3A 、 3C , 3D, 5A, 6A, 7A, 8A, 10A, 11A, 13A, and 14A, etc. Flow proceeds from block 1702 to block 1704 .

[0162] At block 1704, a first back power rail, a second back power rail, and a third back power rail are formed on the back side of the semiconductor substrate. Examples of the first back power rail, the second back power rail, and the third back power rail include Figure 3B 、 3D , 4B, 5B, 6B, 7B, 8B, 10B, 11B, 13B and 14B in the back power rails 346, 348, 350, 352, 354, Figure 5B 、 6B , back side power rails 348 ′ in 7B, 8B, 10B, 11B, 13B, and 14B, etc. Flow proceeds from block 1704 to block 1706 .

[0163] At block 1706, the first back power rail is configured to receive a first reference supply voltage. Examples of the first reference supply voltage include corresponding Figure 2 、 3A To reference voltage TVDD, reference voltage VVDD, and reference voltage VSS in 3D, 4A-4B, 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9, 10A-10B, 11A-11B, 12, 13A-13B, and 14A-14B, etc. Flow proceeds from block 1706 to block 1708.

[0164] At block 1708, the second back power rail is configured to receive a second reference supply voltage. Examples of the second reference supply voltage include corresponding Figure 2 、 3A From block 1708 , the flow proceeds to block 1710 .

[0165] At block 1710, the third back power rail is configured to receive a third reference supply voltage, wherein the first reference supply voltage, the second reference supply voltage, and the third supply reference voltage are different from each other. Examples of the third reference supply voltage include corresponding Figure 2 、 3A Reference voltage TVDD, reference voltage VVDD, and reference voltage VSS, etc., in 3D, 4A to 4B, 5A to 5B, 6A to 6B, 7A to 7B, 8A to 8B, 9, 10A to 10B, 11A to 11B, 12, 13A to 13B, and 14A to 14B.

[0166] Figure 18 is a flowchart 1800 of a method of fabricating a semiconductor device having a cell region according to some embodiments.

[0167] exist Figure 18 , flowchart 1800 is executed Figure 15 One embodiment of block 1504 in 15. Figure 18 , flowchart 1800 includes blocks 1802 to 1818.

[0168] At block 1802, a semiconductor substrate has first and second active regions of respective first and second conductivity types, the first and second active regions respectively extending in a first direction, with a front side defined above the semiconductor substrate and a back side defined below the semiconductor substrate. Examples of semiconductor substrates include Figure 10A 、 11A , the semiconductor substrate 308 in 13A and 14A, etc. Examples of the first active region and the second active region include Figure 10A 、 11A , active regions OD- 1 , OD- 2 in 13A and 14A, etc. Flow proceeds from block 1802 to block 1804 .

[0169] At block 1804, a first front side conductive line is formed on the front side. Examples of first front side conductive lines include Figure 10A and 11A The positive conductor 326, Figure 13A and 14AThe front side wires 330, 332, etc. in the circuit are connected to each other. The process proceeds from block 1804 to block 1806.

[0170] At block 1806, the first front side conductor is configured to receive an input or output signal. An example of an input or output signal is Figure 10A and 11A The input signal IN, Figure 13A and 13B The flow proceeds from block 1806 to block 1808.

[0171] At block 1808, a first front side power rail is formed. Examples of a first front side power rail include Figure 10A and 13A The positive power rail 628 in, etc. Flow proceeds from block 1808 to block 1810.

[0172] At block 1810, the positive power rail is configured to receive a first reference supply voltage. An example of a first reference supply voltage is Figure 10A and 13A TVDD in, etc. The process proceeds from block 1810 to block 1812.

[0173] At block 1812, a first back power rail is formed on the back side. Examples of the first back power rail include Figure 10B The back power rail 348', Figure 11B Back power rails 346, 348' in Figure 13B The back power rail 348', Figure 14B The back power rails 346, 348', etc. in the circuit. Flow proceeds from block 1812 to block 1814.

[0174] At block 1814, the first back power rail is configured to receive a second reference supply voltage. An example of a second reference supply voltage is Figure 10B and 13B VVDD in, etc. The process proceeds from block 1814 to block 1816.

[0175] At block 1816, a first gate electrode is formed on the front surface, the first gate electrode extending in a second direction substantially orthogonal to the first direction to define a first drain / source region and a second drain / source region in the first active region and a third drain / source region and a fourth drain / source region in the second active region. Examples of the first gate electrode include Figure 11A 、 12 , 13A, 14A of the gate electrodes PO-1, PO-2, PO-3, PO-4. Examples of the first drain / source region and the second drain / source region include Figure 10A The drain / source regions 1002, 1006, and 1010 in the Figure 13AExamples of the third drain / source region and the fourth drain / source region include Figure 10A The drain / source regions 1012, 1016, 1018 in the Figure 13A The flow proceeds from block 1816 to block 1818.

[0176] At block 1818, (1) the first gate electrode is connected to a first front side conductive line, (2) the first drain / source region or the second drain / source region is connected to a first front side power rail, and (3) the third drain / source region or the fourth drain / source region is connected to a first back side power rail. Examples of connections made by block 1818 include Figures 10A to 10B and the connections shown in 13A to 13B, etc.

[0177] Figure 19 is a block diagram of an electronic design automation (EDA) system 1900 according to some embodiments.

[0178] In some embodiments, the EDA system 1900 includes an APR system. According to some embodiments, the method described herein for designing a floorplan according to one or more embodiments may be implemented, for example, using the EDA system 1900 .

[0179] In some embodiments, EDA system 1900 is a general-purpose computing device that includes a hardware processor 1902 and a non-transitory computer-readable storage medium 1904. Storage medium 1904 is encoded with, i.e., stores, among other things, computer program code 1906, i.e., a set of executable instructions. Execution of instructions 1906 by hardware processor 1902 represents (at least in part) an EDA tool that implements some or all of the methods described herein, according to one or more embodiments (hereinafter, referred to as processes and / or methods).

[0180] The processor 1902 is electrically connected to the computer-readable storage medium 1904 via a bus 1908. The processor 1902 is also electrically connected to an I / O interface 1910 via the bus 1908. A network interface 1912 is also electrically connected to the processor 1902 via the bus 1908. The network interface 1912 is connected to a network 1914, enabling the processor 1902 and the computer-readable storage medium 1904 to connect to external components via the network 1914. The processor 1902 is configured to execute computer program code 1906 encoded in the computer-readable storage medium 1904 so that the system 1900 can be used to perform some or all of the described processes and / or methods. In one or more embodiments, the processor 1902 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0181] In one or more embodiments, the computer-readable storage medium 1904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1904 includes semiconductor or solid-state memory, magnetic tape, a removable computer disk, random access memory (RAM), read-only memory (ROM), a hard disk, and / or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 1904 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0182] In one or more embodiments, storage medium 1904 stores computer program code 1906 configured to enable system 1900 (where such execution represents (at least in part) an EDA tool) to perform some or all of the described processes and / or methods. In one or more embodiments, storage medium 1904 also stores information that facilitates the performance of some or all of the described processes and / or methods. In one or more embodiments, storage medium 1904 stores a library 1907 of standard cells that includes such standard cells as disclosed herein. In one or more embodiments, storage medium 1904 stores one or more layout drawings 1909 corresponding to one or more layouts disclosed herein.

[0183] EDA system 1900 includes an I / O interface 1910. I / O interface 1910 is connected to external circuitry. In one or more embodiments, I / O interface 1910 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor direction keys for transmitting information and commands to processor 1902.

[0184] EDA system 1900 also includes a network interface 1912 connected to processor 1902. Network interface 1912 allows system 1900 to communicate with a network 1914 to which one or more other computer systems are connected. Network interface 1912 includes a wireless network interface such as Bluetooth, WIFI, WIMAX, GPRS, WCDMA, or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods described are implemented in two or more systems 1900.

[0185] System 1900 is configured to receive information via I / O interface 1910. The information received via I / O interface 1910 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters to be processed by processor 1902. The information is transmitted to processor 1902 via bus 1908. EDA system 1900 is configured to receive information related to a user interface (UI) via I / O interface 1910. This information is stored in computer-readable medium 1904 as user interface (UI) 1942.

[0186] In some embodiments, some or all of the processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the processes and / or methods are implemented as a software application that is part of an add-on software application. In some embodiments, some or all of the processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the processes and / or methods are implemented as a software application used by EDA system 1900. In some embodiments, a system such as the one provided by CADENCE DESIGN SYSTEMS, Inc. is used. tool or other suitable layout generation tools to generate a layout diagram including standard cells.

[0187] In some embodiments, the process is implemented according to a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, for example, one or more optical disks such as DVDs, magnetic disks such as hard disks, semiconductor memories such as ROM, RAM, memory cards, etc.

[0188] Figure 20 is a block diagram of an integrated circuit (IC) manufacturing system 2000 and an IC manufacturing flow associated therewith, according to some embodiments.

[0189] In some embodiments, at least one of (A) one or more semiconductor masks and (B) at least one component in a semiconductor integrated circuit layer is fabricated using fabrication system 2000 based on the layout diagram.

[0190] exist Figure 20In the present invention, IC manufacturing system 2000 includes entities that interact with each other in the design, development and manufacturing cycle and / or in services related to manufacturing IC devices 2060, such as design room 2020, mask room 2030 and IC manufacturer / fab ("fab") 2050. The entities in system 2000 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of design room 2020, mask room 2030 and IC fab 2050 are owned by a single larger company. In some embodiments, two or more of design room 2020, mask room 2030 and IC fab 2050 coexist in a common facility and use common resources.

[0191] The design studio (or design team) 2020 generates an IC design layout diagram 2022. The IC design layout diagram 2022 includes various geometric patterns designed for the IC device 2060. The geometric patterns correspond to the patterns of the metal, oxide or semiconductor layers of the various components that constitute the IC device 2060 to be manufactured. Various layers are combined to form various IC components. For example, part of the IC design layout diagram 2022 includes various IC components, such as active areas, gate electrodes, source and drain electrodes, metal lines or through-holes for interlayer interconnection, and openings for pads to form various material layers in a semiconductor substrate (e.g., a silicon wafer) and arranged on the semiconductor substrate. The design studio 2020 implements an appropriate design program to form the IC design layout diagram 2022. The design program includes one or more of logic design, physical design, and layout and wiring. The IC design layout diagram 2022 is presented in one or more data files with geometric pattern information. For example, the IC design layout diagram 2022 can be expressed in a GDSII file format or a DFII file format.

[0192] The mask chamber 2030 includes data preparation 2032 and mask fabrication 2044. The mask chamber 2030 uses the IC design layout drawing 2022 to fabricate one or more masks 2045 for use in fabricating various layers of the IC device 2060 according to the IC design layout drawing 2022. The mask chamber 2030 performs mask data preparation 2032, wherein the IC design layout drawing 2022 is converted into a representative data file ("RDF"). The mask data preparation 2032 provides the RDF to the mask fabrication 2044. The mask fabrication 2044 includes a mask writer. The mask writer converts the RDF into an image on a substrate (e.g., a mask (reticle) 2045 or a semiconductor wafer 2053). The design layout drawing 2022 is manipulated by the mask data preparation 2032 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fabrication plant 2050. In Figure 20 , mask data preparation 2032 and mask fabrication 2044 are shown as separate elements. In some embodiments, mask data preparation 2032 and mask fabrication 2044 may be collectively referred to as mask data preparation.

[0193] In some embodiments, mask data preparation 2032 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 2022. In some embodiments, mask data preparation 2032 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary components, phase-shift masks, other suitable techniques, etc., or a combination thereof. In some embodiments, inverse lithography techniques (ILT), which treat OPC as an inverse imaging problem, are also used.

[0194] In some embodiments, mask data preparation 2032 includes a mask rule checker (MRC) that checks an IC design layout 2022 that has been subjected to a process in OPC with a set of mask creation rules that contain certain geometric and / or connection constraints to ensure sufficient margin to account for issues such as variability in semiconductor manufacturing processes. In some embodiments, the MRC modifies the IC design layout 2022 to compensate for the constraints during mask fabrication 2044, which can undo some of the modifications performed by the OPC to satisfy the mask creation rules.

[0195] In some embodiments, mask data preparation 2032 includes a lithography process check (LPC) that simulates a process to be performed by the IC fabrication facility 2050 to manufacture the IC device 2060. The LPC simulates the process based on the IC design layout drawing 2022 to create a simulated manufactured device, such as the IC device 2060. The process parameters in the LPC simulation may include parameters associated with various processes of the IC fabrication cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the fabrication process. The LPC considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, etc., or a combination thereof. In some embodiments, after the simulated manufactured device is created by the LPC, if the simulated device is not close enough in shape to meet the design rules, the OPC and / or MRC are repeated to further refine the IC design layout drawing 2022.

[0196] It should be understood that the above description of mask data preparation 2032 has been simplified for clarity. In some embodiments, mask data preparation 2032 includes additional features, such as modifying the logic operations (LOPs) of IC design layout 2022 according to manufacturing rules. Furthermore, the processes applied to IC design layout 2022 during mask data preparation 2032 can be performed in a variety of different orders.

[0197] After mask data preparation 2032 and during mask fabrication 2044, a mask 2045 or a set of masks 2045 are fabricated based on the modified IC design layout 2022. In some embodiments, mask fabrication 2044 includes performing one or more photolithographic exposures based on the IC design layout 2022. In some embodiments, a pattern is formed on a mask (photomask or reticle) 2045 using an electron beam (e-beam) or multiple electron beams based on the modified IC design layout 2022. The mask 2045 can be formed using various techniques. In some embodiments, the mask 2045 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of mask 2045 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 2045 is formed using phase shift technology. In a phase shift mask (PSM) version of mask 2045, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. Masks produced by mask manufacturing 2044 are used in a variety of processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 2053, in etching processes to form various etched regions in semiconductor wafer 2053, and / or in other suitable processes.

[0198] IC fabrication facility 2050 includes fabrication tools 2052 configured to perform various fabrication operations on semiconductor wafer 2053 to fabricate IC devices 2060 based on masks (e.g., mask 2045). In various embodiments, fabrication tools 2052 include one or more of a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, and other fabrication equipment capable of performing one or more suitable fabrication processes, as described herein.

[0199] IC fabrication facility 2050 uses mask 2045 manufactured by mask chamber 2030 to manufacture IC device 2060. Therefore, IC fabrication facility 2050 at least indirectly uses IC design layout 2022 to manufacture IC device 2060. In some embodiments, semiconductor wafer 2053 is manufactured by IC fabrication facility 2050 using mask 2045 to form IC device 2060. In some embodiments, IC fabrication includes performing one or more photolithographic exposures based at least indirectly on IC design layout 2022. Semiconductor wafer 2053 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer 2053 also includes one or more of various doped regions, dielectric components, multi-level interconnects, etc. (formed in subsequent fabrication steps).

[0200] In some embodiments, a semiconductor device includes: a semiconductor substrate including one or more active semiconductor components, wherein a front side is defined above the semiconductor substrate and a back side is defined below the semiconductor substrate; a first front side power rail located on the front side of the semiconductor substrate, the first front side power rail configured to receive a first reference supply voltage; and a first back side power rail and a second back side power rail located on the back side of the semiconductor substrate; the first back side power rail configured to receive a second reference supply voltage; the second back side power rail configured to receive a third reference supply voltage; wherein the first reference supply voltage, the second reference supply voltage, and the third reference supply voltage are different from each other.

[0201] In some embodiments, the semiconductor device further includes a first front metal layer on the front side, wherein the first front metal layer includes a first front power rail and a second front power rail. In some embodiments, the semiconductor device further includes a first back metal layer on the back side, wherein the first back metal layer includes a first back power rail and a second back power rail. In some embodiments, the semiconductor device further includes a third back power rail located on the back side; a fourth back power rail located on the back side; and a fifth back power rail located on the back side, wherein the first back power rail, the second back power rail, the third back power rail, the fourth back power rail, and the fifth back power rail each extend in a first direction. The third back power rail is configured to receive a third reference supply voltage; the fourth back power rail is configured to receive a first reference supply voltage; and the fourth back power rail is located between the second back power rail and the third back power rail relative to the first direction. In some embodiments, the semiconductor device further includes a fifth back power rail located on the back side, wherein the fifth back power rail is configured to receive a second reference supply voltage and extends in the first direction. The second back power rail, the third back power rail, and the fifth back power rail are located between the first back power rail and the fifth back power rail relative to a second direction substantially perpendicular to the first direction. In some embodiments, the first reference power supply voltage is true VDD (TVDD); the second reference power supply voltage is virtual VDD (VVDD); and the third reference power supply voltage is VSS. In some embodiments, the semiconductor device further comprises a first dual-mode cell region; a first single-mode cell region; wherein: each of the second back power rail, the third back power rail, and the fifth back power rail is at least partially aligned with respect to the second direction; a top portion of the first dual-mode cell region at least partially overlaps the first back power rail with respect to the second direction; a bottom portion of the first dual-mode cell region at least partially overlaps the second back power rail, the third back power rail, and the fifth back power rail with respect to the second direction; a top portion of the first single-mode cell region at least partially overlaps the second back power rail, the third back power rail, and the fifth back power rail with respect to the second direction; and a bottom portion of the first single-mode cell region at least partially overlaps the fifth back power rail with respect to the second direction. In some embodiments, the semiconductor device further comprises a first header cell region; wherein: a top portion of the first header cell region partially overlaps the first back power rail with respect to the second direction; and a bottom portion of the first header cell region partially overlaps the fifth back power rail with respect to the second direction.In some embodiments, the semiconductor device further includes a plurality of front power rails, the plurality of front power rails including a first back power rail; a front conductive line; wherein: each of the plurality of front power rails extends in a first direction; the front conductive line extends along the first direction; the front conductive line is configured to receive a control signal; some of the plurality of front power rails are configured to receive a first reference power supply voltage; and other of the plurality of front power rails are configured to receive a second reference power supply voltage; the front conductive line is aligned with the second, third, and fifth back power rails relative to a second direction; and the front conductive line is positioned between the first group of the plurality of front power rails and the second group of the plurality of front power rails relative to the second direction. In some embodiments, the semiconductor device further includes a third back power rail located on the back side; wherein: the third back power rail is configured to receive the second reference power supply voltage; the first, second, and third back power rails all extend in the first direction; and the third back power rail is positioned between the first and second back power rails relative to a second direction substantially perpendicular to the first direction. In some embodiments, the semiconductor device further includes cell areas adjacent to each other; a power filling area; a plurality of front power rails located on the front side extending above the cell areas and the power filling area; a first back power rail, a second back power rail, and a third back power rail all extending below the cell areas and the power filling area; wherein: the first group of cell areas extends relative to the second direction, so that the top of the first group of cell areas is partially aligned with the first back power rail relative to the second direction, and the bottom of the first group of cell areas is partially aligned with the second back power rail; the second group of cell areas extends relative to the second direction, so that the top of the second group of cell areas is partially aligned with the second back power rail relative to the second direction, and the bottom of the second group of cell areas is partially aligned with the third back power rail; and the plurality of front power rails are connected to the first back power rail, the second back power rail, and the third back power rail in the power filling area. In some embodiments, the semiconductor device further includes a first cell region extending relative to the second direction, such that a top portion of the first cell region extends relative to the second direction, such that a top portion of the first cell region is aligned with a first back power rail portion relative to the second direction, and a bottom portion of the first cell region is aligned with a second back power rail portion relative to the second direction; a second cell region extending relative to the second direction, such that a top portion of the second cell region is aligned with a second back power rail portion relative to the second direction, and a bottom portion of the second cell region is aligned with a third back power rail portion; a plurality of front power rails, including a first back power rail; and a front conductive line; wherein: each of the plurality of front power rails extends in the first direction; the front conductive line extends along the first direction; the front conductive line is configured to receive a control signal; some of the plurality of front power rails are configured to receive a first reference power supply voltage; some of the plurality of front power rails are configured to receive a second reference power supply voltage; and the front conductive line is aligned with the second back power rail, the third back power rail, and the fifth back power rail relative to the second direction.The front conductive line is located between a first group of the plurality of front power rails and a second group of the plurality of front power rails relative to the second direction. In some embodiments, the first reference power supply voltage is a true VDD (TVDD); the second reference power supply voltage is a virtual VDD (VVDD); and the third reference power supply voltage is VSS. In some embodiments, the first reference power supply voltage is a virtual VDD (VVDD); the second reference power supply voltage is a true VDD (TVDD); and the third reference power supply voltage is VSS.

[0202] In some embodiments, a semiconductor device includes: a semiconductor substrate including one or more active semiconductor components, wherein a front side is defined above the semiconductor substrate and a back side is defined below the semiconductor substrate; a first back side power rail, a second back side power rail, and a third back side power rail located on a back side of the semiconductor substrate; and wherein: the first back side power rail is configured to receive a first reference supply voltage; the second back side power rail is configured to receive a second reference supply voltage; and the third back side power rail is configured to receive a third reference supply voltage, wherein the first reference supply voltage, the second reference supply voltage, and the third reference supply voltage are different from each other. In some embodiments, the semiconductor device further includes: a first back side metal layer located on the back side, wherein the first back side metal layer includes the first back side power rail and the second back side power rail. In some embodiments, the second backside power rail is configured to receive a third reference supply voltage, and the semiconductor device further includes: a fourth backside power rail on the backside; a fifth backside power rail on the backside; the first backside power rail, the second backside power rail, the third backside power rail, the fourth backside power rail, and the fifth backside power rail all extend in a first direction; the third backside power rail is configured to receive the third reference supply voltage; the fourth backside power rail is configured to receive the first reference supply voltage; and the fourth backside power rail is located between the second backside power rail and the third backside power rail relative to the first direction. In some embodiments, the semiconductor device further includes: a fifth backside power rail on the backside, wherein the fifth backside power rail is configured to receive the second reference supply voltage and extends in the first direction; and the second backside power rail, the third backside power rail, and the fifth backside power rail are located between the first backside power rail and the fifth backside power rail relative to a second direction substantially perpendicular to the first direction.

[0203] In some embodiments, a method (of manufacturing a semiconductor device) includes: providing a semiconductor substrate having a first active region and a second active region extending respectively in a first direction; configuring the first active region to have a first conductivity; configuring the second active region to have a second conductivity; the front side is defined above the semiconductor substrate and the back side is defined below the semiconductor substrate; forming a first front side conductive line on the front side, configuring the first front side conductive line to receive an input signal or provide an output signal; forming a first front side power rail on the front side; configuring the first front side power rail to receive a first reference power supply voltage; forming a first back side power rail on the back side; configuring the first back side power rail to receive a second reference power supply voltage; forming a first gate electrode on the front side, the first gate electrode extending along a second direction substantially orthogonal to the first direction, the first gate electrode defining a first drain / source region and a second drain / source region in the first active region and a third drain / source region and a fourth drain / source region in the second active region; connecting the first gate electrode to the first front side conductive line; connecting the first drain / source region or the second drain / source region to the first front side power rail; connecting the third drain-source region or the fourth drain-source region to the first back side power rail. In some embodiments, the first reference power supply voltage is true VDD (TVDD); the second reference power supply voltage is virtual VDD (VVDD); and the third reference power supply voltage is VSS.

[0204] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may undergo various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device comprising: a semiconductor substrate comprising one or more active semiconductor components, wherein a front side is defined above the semiconductor substrate and a back side is defined below the semiconductor substrate; a first front side power rail located on the front side of the semiconductor substrate, the first front side power rail being configured to receive a first reference supply voltage; and a first back side power rail, a second back side power rail, a third back side power rail, and a fourth back side power rail, respectively extending along a first direction at the back side of the semiconductor substrate; the first backside power rail being configured to receive a second reference supply voltage; the second backside power rail being configured to receive a third reference supply voltage; Each of the third back power rail and the fourth back power rail is configured to receive the first reference supply voltage; and With respect to the first direction, the second back power rail is located between the third back power rail and the fourth back power rail; The first reference power supply voltage, the second reference power supply voltage and the third reference power supply voltage are different from each other.

2. The semiconductor device according to claim 1, further comprising: A first front metal layer on the front side, wherein the first front metal layer includes the first front power rail and the second front power rail.

3. The semiconductor device according to claim 1 , further comprising: A first back metal layer on the back side, wherein the first back metal layer includes the first back power rail and the second back power rail.

4. The semiconductor device according to claim 1 , further comprising: a fifth back side power rail located on the back side; in: The fifth back power rail correspondingly extends along the first direction.

5. The semiconductor device according to claim 4, wherein: The fifth back power rail is configured to receive the second reference power voltage, and the fifth back power rail extends along the first direction; as well as The second back side power rail, the third back side power rail, and the fourth back side power rail are located between the first back side power rail and the fifth back side power rail with respect to a second direction perpendicular to the first direction.

6. The semiconductor device according to claim 5, wherein: The first reference power supply voltage is true VDD; The second reference power supply voltage is a virtual VDD; and The third reference power supply voltage is VSS.

7. The semiconductor device according to claim 6, further comprising: a first dual-mode cell region; a first single-mode unit region; as well as in: each of the second back side power rail, the third back side power rail, and the fourth back side power rail being at least partially aligned with respect to the second direction; A top portion of the first dual-mode cell region at least partially overlaps the first back power rail relative to the second direction; a bottom of the first dual-mode cell region at least partially overlapping the second back power rail, the third back power rail, and the fourth back power rail relative to the second direction; a top portion of the first single mode cell region at least partially overlapping the second back side power rail, the third back side power rail, and the fourth back side power rail relative to the second direction; and A bottom of the first single mode cell region at least partially overlaps the fifth back power rail with respect to the second direction.

8. The semiconductor device according to claim 6, further comprising: first head unit region; as well as in: a top portion of the first header unit region partially overlapping the first back power rail relative to the second direction; and A bottom of the first header unit region partially overlaps with the fifth back power rail with respect to the second direction.

9. The semiconductor device according to claim 8, further comprising: a plurality of front power rails, including said first back power rail; Positive wire; as well as in: Each of the plurality of front power rails extends correspondingly along the first direction; The front conductive line extends along the first direction; The positive wire is configured to receive a control signal; some of the plurality of positive power rails are configured to receive the first reference supply voltage; some of the plurality of positive power rails are configured to receive the second reference supply voltage; the front conductive line is aligned with the second back power rail, the third back power rail, and the fourth back power rail relative to the second direction; and The front conductive line is located between a first group of the plurality of front power rails and a second group of the plurality of front power rails relative to the second direction.

10. The semiconductor device according to claim 1, wherein The second back side power rail, the third back side power rail, and the fourth back side power rail are disposed apart from each other along the first direction.

11. The semiconductor device according to claim 5, further comprising: Unit areas, adjacent to each other; Power fill area; a plurality of front power rails located on the front side and extending over the cell area and the power fill area; as well as The first back power rail, the fifth back power rail and the third back power rail all extend below the cell area and the power fill area; as well as in: The first group of cell regions extends relative to the second direction such that a top portion of the first group of cell regions is aligned with the first back power rail portion relative to the second direction, and a bottom portion of the first group of cell regions is aligned with the second back power rail portion; the second group of cell regions extending relative to the second direction such that a top portion of the second group of cell regions is aligned with the second back power rail portion relative to the second direction and a bottom portion of the second group of cell regions is aligned with the fifth back power rail portion; and The plurality of front side power rails are connected to the first back side power rail, the fifth back side power rail, and the third back side power rail in the power fill region.

12. The semiconductor device according to claim 1, further comprising: a first cell region extending relative to a second direction perpendicular to the first direction, such that a top portion of the first cell region extends relative to the second direction, such that a top portion of the first cell region is aligned with the first back power rail portion relative to the second direction, and a bottom portion of the first cell region is aligned with the second back power rail portion; a second cell region extending relative to the second direction such that a top portion of the second cell region is aligned with the second back power rail portion relative to the second direction and a bottom portion of the second cell region is aligned with the second back power rail portion; a plurality of front power rails, including said first back power rail; and Positive wire; as well as in: Each of the plurality of front power rails extends in the first direction; The front conductive line extends along the first direction; The positive wire is configured to receive a control signal; some of the plurality of positive power rails are configured to receive the first reference supply voltage; some of the plurality of positive power rails are configured to receive the second reference supply voltage; the front side conductor is aligned with the second back side power rail and the third back side power rail relative to the second direction; and The front conductive line is located between a first group of the plurality of front power rails and a second group of the plurality of front power rails relative to the second direction.

13. The semiconductor device according to claim 12, wherein: The first reference power supply voltage is true VDD; The second reference power supply voltage is a virtual VDD; and The third reference power supply voltage is VSS.

14. The semiconductor device according to claim 12, wherein: The first reference power supply voltage is a virtual VDD; The second reference power supply voltage is true VDD; and The third reference power supply voltage is VSS.

15. A semiconductor device comprising: a semiconductor substrate comprising one or more active semiconductor components, wherein a front side is defined above the semiconductor substrate and a back side is defined below the semiconductor substrate; a first back side power rail, a second back side power rail, a third back side power rail, and a fourth back side power rail, each of the first back side power rail, the second back side power rail, the third back side power rail, and the fourth back side power rail being located on the back side of the semiconductor substrate and extending along a first direction; and in: the first backside power rail being configured to receive a first reference supply voltage; The second back power rail is configured to receive a second reference supply voltage; and Each of the third back power rail and the fourth back power rail is configured to receive a third reference supply voltage, The second back power rail is located between the third back power rail and the fourth back power rail relative to the first direction, wherein the first reference supply voltage, the second reference supply voltage, and the third reference supply voltage are different from each other.

16. The semiconductor device according to claim 15, further comprising: A first back metal layer is located on the back side, wherein the first back metal layer includes the first back power rail and the second back power rail.

17. The semiconductor device according to claim 15, further comprising: a fifth back side power rail located on the back side; The fifth back power rail extends along the first direction.

18. The semiconductor device according to claim 17, wherein: The fifth back power rail is configured to receive the first reference supply voltage; and The second back side power rail, the third back side power rail, and the fourth back side power rail are located between the first back side power rail and the fifth back side power rail with respect to a second direction perpendicular to the first direction.

19. A method for manufacturing a semiconductor device, the method comprising: Providing a semiconductor substrate having a first active region and a second active region extending correspondingly along a first direction; configuring the first active region to have a first conductivity; configuring the second active region to have a second conductivity; A front surface is defined above the semiconductor substrate, and a back surface is defined below the semiconductor substrate; forming a first front side conductive line on the front side; configuring the first front conductive line to receive an input signal or provide an output signal; forming a first front side power rail on the front side; configuring the first positive power rail to receive a first reference supply voltage; forming a first back side power rail on the back side; configuring the first back power rail to receive a second reference supply voltage; as well as forming a first gate electrode on the front surface, wherein the first gate electrode extends along a second direction orthogonal to the first direction; The first gate electrode is provided to define a first drain / source region and a second drain / source region in the first active region, and a third drain / source region and a fourth drain / source region in the second active region; connecting the first gate electrode to the first front side wire; connecting the first drain / source region or the second drain / source region to the first positive power rail; as well as The third drain / source region or the fourth drain / source region is connected to the first back side power rail.

20. The method of claim 19, wherein: The first reference power supply voltage is true VDD; The second reference power supply voltage is a virtual VDD; and The method also includes forming a second backside power rail on the backside configured to receive a third reference power supply voltage, the third reference power supply voltage being VSS.

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