pixel array substrate

Abstract

A pixel array substrate includes a plurality of pixel structures, a plurality of scan lines, a plurality of data lines, and a plurality of adapter lines. The plurality of pixel structures are arranged into a plurality of pixel rows. The plurality of pixel rows are arranged in a first direction. The plurality of scan lines are arranged in a second direction and are electrically connected to the plurality of pixel structures. The plurality of adapter lines are arranged in the first direction and are electrically connected to the plurality of scan lines.

Description

Technical Field

[0001] The invention relates to a pixel array substrate. Background Art

[0002] With the advancement of display technology, people's demands for display devices are no longer satisfied with optical properties such as high resolution, high contrast, and wide viewing angle. People also expect display devices to have an elegant appearance. For example, people expect display devices to have narrow borders or even no borders.

[0003] Generally speaking, a display device includes a plurality of pixel structures arranged in a display area, a data driving circuit arranged below the display area, and a gate driving circuit arranged on the left side, right side, or both sides of the display area. In order to reduce the width of the left and right sides of the frame of the display device, the gate driving circuit and the data driving circuit can be arranged on the lower side of the display area. When the gate driving circuit is arranged on the lower side of the display area, the gate lines arranged in the vertical direction must be electrically connected to the gate driving circuit through the adapter wires arranged in the horizontal direction. However, the gate turn-on pulse signal of the adapter wire will affect the potential of other pixel structures that are still being charged, thereby causing display abnormalities (for example, diagonal bright lines). Summary of the Invention

[0004] The present invention provides a pixel array substrate. A display device using the pixel array substrate has good display quality.

[0005] The pixel array substrate of the present invention includes a substrate, a plurality of pixel structures, a plurality of scan lines, a plurality of data lines and a plurality of adapter lines. The plurality of pixel structures are disposed on the substrate and arranged into a plurality of pixel rows, wherein the plurality of pixel rows are arranged in a first direction. The plurality of scan lines are arranged in a second direction and electrically connected to the plurality of pixel structures, wherein the first direction and the second direction are staggered. The plurality of data lines are arranged in the first direction and electrically connected to the plurality of pixel rows. The plurality of adapter lines are arranged in the first direction and electrically connected to the plurality of scan lines. The plurality of scan lines include the xnth scan line to the xth scan line arranged in sequence in the second direction, where x is a positive integer greater than or equal to 2, n is a positive integer less than x, and the start time of the gate pulse signal of the xth scan line and the end time of the gate pulse signal of the xnth scan line overlap in timing. The plurality of adapter lines include the xnth adapter line and the xth adapter line, which are electrically connected to the xnth scan line and the xth scan line, respectively. The plurality of pixel rows include a k-1th pixel row, a kth pixel row, and a k+1th pixel row arranged in sequence in a first direction, where k is a positive integer greater than or equal to 2. The plurality of data lines include a k-1th data line, a kth data line, and a k+1th data line, which are electrically connected to the k-1th pixel row, the kth pixel row, and the k+1th pixel row, respectively. In a top view of the pixel array substrate, an xnth adapter line is disposed between the k-1th data line and the kth data line, and an xth adapter line is disposed between the kth data line and the k+1th data line. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0007] Figure 2 Show Figure 1 A plurality of gate pulse signals S of the xn-th scanning line HGx-n to the x+n-th scanning line HGx+n HGx-n ~S HGx+n .

[0008] Figure 3 FIG. 1 is a schematic top view of a layout of a pixel structure PX of a pixel array substrate 100 according to an embodiment of the present invention.

[0009] Figure 4 FIG. 1 is a cross-sectional diagram of a pixel array substrate 100 according to an embodiment of the present invention.

[0010] Figure 5 FIG. 1 is a schematic top view of a pixel array substrate 100 according to an embodiment of the present invention.

[0011] Figure 6 1 to 18th scanning lines HG18 according to an embodiment of the present invention.HG1 ~S HG18 .

[0012] Figure 7 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0013] Figure 8 Show Figure 7 A plurality of gate pulse signals S of the xn-th scanning line HGx-n to the x+n-th scanning line HGx+n HGx-n ~S HGx+n .

[0014] Figure 9 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0015] Figure 10 Show Figure 9 A plurality of gate pulse signals S of the xn-th scanning line HGx-n to the x+n-th scanning line HGx+n HGx-n ~S HGx+n .

[0016] Figure 11 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0017] Figure 12 Show Figure 11 A plurality of gate pulse signals S of the ynth scanning line HGy-n to the yth scanning line HGy HGy-n ~S HGy .

[0018] Figure 13 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0019] Figure 14 Show Figure 13 A plurality of gate pulse signals S of the ynth scanning line HGy-n to the yth scanning line HGy HGy-n ~S HGy .

[0020] Figure 15 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100A according to an embodiment of the present invention.

[0021] Figure 16 Show Figure 15 The gate pulse signals S of the first scanning line HG1 to the ninth scanning line HG9 are HG1 ~S HG9 .

[0022] Figure 17FIG. 1 is a schematic cross-sectional view of a pixel structure PX of a pixel array substrate 100 according to an embodiment of the present invention.

[0023] Figure 18 FIG. 1 is a schematic top view of a layout of a pixel structure PX of a pixel array substrate 100B according to an embodiment of the present invention.

[0024] Figure 19 FIG. 1 is a schematic cross-sectional view of a pixel structure PX of a pixel array substrate 100B according to an embodiment of the present invention.

[0025] Figure 20 FIG. 1 is a schematic top view of a layout of a pixel structure PX of a pixel array substrate 100C according to an embodiment of the present invention.

[0026] Figure 21 FIG. 1 is a schematic cross-sectional view of a pixel structure PX of a pixel array substrate 100C according to an embodiment of the present invention.

[0027] Figure 22 FIG. 1 is a schematic top view of a layout of a pixel structure PX of a pixel array substrate 100D according to an embodiment of the present invention.

[0028] Figure 23 FIG. 1 is a schematic cross-sectional view of a pixel structure PX of a pixel array substrate 100D according to an embodiment of the present invention.

[0029] Description of reference numerals:

[0030] 100, 100A, 100B, 100C, 100D: Pixel array substrates

[0031] 110: Base

[0032] 122: First common electrode

[0033] 122e, 124e, 126e, 142e, 142-1e, 162e, Tcs: Edge

[0034] 124: Second common electrode

[0035] 126: Third common electrode

[0036] 130: Insulation layer

[0037] 132: Contact window

[0038] 142: Conductive pattern

[0039] 142-1: Part 1

[0040] 142-2: Part 2

[0041] 142-3: Part 3

[0042] 142-4: Part 4

[0043] 142-5: Part 5

[0044] 150: First insulation layer

[0045] 152, 172, 162, 192: Opening

[0046] 160: Color filter pattern

[0047] 164: Sidewall

[0048] 170: Second insulation layer

[0049] 180: Transparent conductive layer

[0050] 190: Third insulation layer

[0051] 194: Pixel electrode

[0052] A: Area

[0053] DL, DLk-1, DLk, DLk+1, DLk+2, DLq-1, DLq, DLq+1, DLq+2, DL1~DL23: data lines

[0054] d1: first direction

[0055] d2: second direction

[0056] HG, HGm, HGp, HGx-n to HGx+n, HGy-n to HGy, HG1 to HG18: Scan lines

[0057] PX: Pixel structure

[0058] R, Rk-1, Rk, Rk+1, Rk+2, Rq-1, Rq, Rq+1, Rq+2, R1~R23: pixel rows

[0059] S HGx-n ~S HGx+n 、S HGy-n ~S HGy 、S HG1 ~S HG18 、S VGx-n 、S VGx 、S VGx+n 、S VG1 ~S VG18 : Gate pulse signal

[0060] T: Thin Film Transistor

[0061] Ta: Source

[0062] Tb: drain

[0063] Tc: Gate

[0064] Td: semiconductor pattern

[0065] Tp: pulse time length

[0066] t: length of time delay

[0067] tonx, tonx+n, tony, ton1, ton3, ton5, ton7, ton9, ton11, ton13, ton14, ton15, ton16, ton17, ton18: start time

[0068] toffx-n, toffx, toffy-n, toff1, toff3, toff5, toff6, toff7, toff8, toff9, toff10: end time

[0069] VG, VGp, VGm, VGx-n, VGx, VGx+n, VGy-n, VGy, VG1 to VG18: Adapter cables

[0070] VGa: At least part

[0071] Vgh: high potential

[0072] Vgl: low potential

[0073] VSS1, VSS1a, VSS1b, VSS1c, VSS1d: First common line

[0074] VSS2: Second common line

[0075] I-I', II-II', III-III', IV-IV', V-V': hatching line DETAILED DESCRIPTION

[0076] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0077] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or intermediate elements can also exist. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intermediate elements. As used herein, "connected" can refer to physical and / or electrical connections. Furthermore, "electrically connected" or "coupled" can mean the presence of other elements between two elements.

[0078] As used herein, "about," "approximately," or "substantially" includes the stated value and an average value that is within an acceptable deviation range of the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, or ±5%. Furthermore, as used herein, "about," "approximately," or "substantially" can be selected based on the optical property, etching property, or other property, and may not apply to all properties with a single standard deviation.

[0079] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and will not be interpreted as idealized or overly formal unless explicitly defined as such herein.

[0080] Figure 1 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0081] Figure 2 Show Figure 1 A plurality of gate pulse signals S of the xn-th scanning line HGx-n to the x+n-th scanning line HGx+n HGx-n ~S HGx+n .

[0082] Figure 3 FIG. 1 is a schematic top view of a layout of a pixel structure PX of a pixel array substrate 100 according to an embodiment of the present invention. Figure 3 correspond Figure 1 Area A.

[0083] Figure 4 FIG. 1 is a cross-sectional diagram of a pixel array substrate 100 according to an embodiment of the present invention. Figure 4 correspond Figure 3 Section line I-I'.

[0084] Please refer to Figure 1 and Figure 4 The pixel array substrate 100 includes a substrate 110. For example, in this embodiment, the substrate 110 may be made of glass. However, the present invention is not limited thereto. In other embodiments, the substrate 110 may be made of quartz, an organic polymer, an opaque / reflective material (e.g., a wafer, ceramic, etc.), or other suitable materials.

[0085] Please refer to Figure 1 The pixel array substrate 100 further includes a plurality of pixel structures PX disposed on a substrate 110. The plurality of pixel structures PX are arranged into a plurality of pixel rows R. The plurality of pixel rows R are arranged in a first direction d1.

[0086] Please refer to Figure 1 and Figure 3 Each pixel structure PX includes a thin film transistor T and a pixel electrode 194. The thin film transistor T has a source Ta, a drain Tb, a gate Tc and a semiconductor pattern Td. The insulating layer 130 (drawn on Figure 4 ) is sandwiched between the gate electrode Tc and the semiconductor pattern Td. The insulating layer 130 may also be referred to as a gate insulating layer. The source electrode Ta and the drain electrode Tb are electrically connected to two different regions of the semiconductor pattern Td, respectively, and the pixel electrode 194 is electrically connected to the drain electrode Tb.

[0087] For example, in this embodiment, the gate Tc of the thin film transistor T may belong to the first conductive layer, and the source Ta and the drain Tb of the thin film transistor T may belong to the second conductive layer, but the present invention is not limited thereto.

[0088] In this embodiment, the first conductive layer may be a first metal layer; that is, the material of the first conductive layer may be metal. However, the present invention is not limited thereto. In other embodiments, the material of the first conductive layer may be other conductive materials, such as an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or a stacked layer of a metal material and other conductive materials.

[0089] In this embodiment, the second conductive layer may be a second metal layer; that is, the material of the second conductive layer may be metal. However, the present invention is not limited thereto. In other embodiments, the material of the second conductive layer may also be other conductive materials, such as alloys, metal nitrides, metal oxides, metal oxynitrides, or stacked layers of metal and other conductive materials.

[0090] Please refer to Figure 1 and Figure 3 The pixel array substrate 100 further includes a plurality of scan lines HG arranged in a second direction d2, wherein the first direction d1 and the second direction d2 are interlaced. For example, in this embodiment, the first direction d1 and the second direction d2 may be perpendicular, but the present invention is not limited thereto. The plurality of scan lines HG are electrically connected to the plurality of pixel structures PX. Specifically, the plurality of scan lines HG are electrically connected to the plurality of gates Tc of the plurality of thin film transistors T of the plurality of pixel structures PX. In this embodiment, the scan lines HG may belong to the first conductive layer, but the present invention is not limited thereto.

[0091] Please refer to Figure 1and Figure 3 The pixel array substrate 100 further includes a plurality of data lines DL arranged in a first direction d1 and electrically connected to the plurality of pixel rows R. Specifically, in this embodiment, the plurality of data lines DL are electrically connected to the plurality of source electrodes Ta of the plurality of thin film transistors T in the plurality of pixel rows R, and the plurality of source electrodes Ta of the plurality of pixel structures PX in the same pixel row R are electrically connected to the same data line DL. In this embodiment, the data lines DL may belong to the second conductive layer, but the present invention is not limited thereto.

[0092] Please refer to Figure 1 and Figure 3 The pixel array substrate 100 further includes a plurality of transfer lines VG arranged in the first direction d1 and electrically connected to the plurality of scan lines HG. Figure 1 、 Figure 3 and Figure 4 For example, in this embodiment, the scan line HG belongs to the first conductive layer, and at least a portion VGa of the transition line VG (marked at Figure 4 ) belongs to the second conductive layer; the insulating layer 130 is disposed between the first conductive layer and the second conductive layer and has a contact window 132 (marked at Figure 4 ); at least a portion VGa of the transfer line VG is electrically connected to the scan line HG through the contact window 132 of the insulating layer 130.

[0093] Please refer to Figure 1 The plurality of scan lines HG include an xnth scan line HGx-n to an x+nth scan line HGx+n arranged in sequence in the second direction d2, where x is a positive integer greater than or equal to 2, and n is a positive integer less than x.

[0094] Please refer to Figure 1 and Figure 2 , the xn-th scanning line HGx-n to the x+n-th scanning line HGx+n respectively have gate pulse signals S HGx-n To gate pulse signal S HGx+n In detail, the xn-th scanning line HGx-n has a gate pulse signal S HGx-n , the x-n+1th scanning line HGx-n+1 has a gate pulse signal S HGx-n+1 , the x-n+2th scanning line HGx-n+2 has a gate pulse signal S HGx-n+2 , ..., the x-th scanning line HGx has a gate pulse signal S HGx , the x+1th scanning line HGx+1 has a gate pulse signal S HGx+1 , the x+2 scan line HGx+2 has a gate pulse signal S HGx+2 , ..., the x+nth scanning line HGx+n has a gate pulse signal S HGx+n.

[0095] Please refer to Figure 1 and Figure 2 In this embodiment, the xnth scanning line HGx-n to the x+nth scanning line HGx+n are sequentially turned on with a time delay, wherein the length of the time delay is t (shown in FIG. Figure 2 ), gate pulse signal S HGx-n To gate pulse signal S HGx+n The pulse time length of each is Tp (plotted on Figure 2 ), and n=Tp / t. The gate pulse signal S of the x-th scanning line HGx HGx The start time tonx and the gate pulse signal S of the xn-th scanning line HGx-n HGx-n The end time toffx-n of the x-th scanning line HGx overlaps in timing. HGx The period from the low potential Vgl to the high potential Vgh is related to the gate pulse signal S of the xn-th scanning line HGx-n. HGx-n The period of time from the high potential Vgh to the low potential Vgl at least partially overlaps in timing. HGx The end time toffx and the gate pulse signal S of the x+nth scanning line HGx+n HGx+n The start time tonx+n of the x-th scanning line HGx overlaps in timing. HGx The period from the high potential Vgh to the low potential Vgl and the gate pulse signal S of the x+nth scanning line HGx+n HGx+n The period during which the low potential Vgl rises to the high potential Vgh at least partially overlaps in timing.

[0096] Please refer to Figure 1 , the plurality of transfer lines VG include the xnth transfer line VGx-n, the xth transfer line VGx and the x+nth transfer line VGx+n, which are electrically connected to the xnth scan line HGx-n, the xth scan line HGx and the x+nth scan line HGx+n respectively. Figure 1 and Figure 2 , the xnth transfer line VGx-n, the xth transfer line VGx and the x+nth transfer line VGx+n respectively have gate pulse signals S VGx-n , gate pulse signal S VGx And gate pulse signal S VGx+n , where the gate pulse signal S of the xnth transfer line VGx-n VGx-n , the gate pulse signal S of the xth transfer line VGx VGx and the gate pulse signal S of the x+nth transfer line VGx+nVGx+n The gate pulse signal S of the xn-th scanning line HGx-n is respectively HGx-n , the gate pulse signal S of the x-th scanning line HGx HGx and the gate pulse signal S of the x+nth scanning line HGx+n HGx+n same.

[0097] Please refer to Figure 1 , multiple pixel rows R include the k-1th pixel row Rk-1, the kth pixel row Rk and the k+1th pixel row Rk+1 arranged in sequence in the first direction d1, k is a positive integer greater than or equal to 2; multiple data lines DL include the k-1th data line DLk-1, the kth data line DLk and the k+1th data line DLk+1, which are electrically connected to the k-1th pixel row Rk-1, the kth pixel row Rk and the k+1th pixel row Rk+1, respectively.

[0098] Please refer to Figure 1 It is worth noting that, in the top view of the pixel array substrate 100, the xnth transfer line VGx-n is disposed between the k-1th data line DLk-1 and the kth data line DLk, and the xth transfer line VGx is disposed between the kth data line DLk and the k+1th data line DLk+1. In other words, the xnth transfer line VGx-n and the xth transfer line VGx are adjacent to the same kth data line DLk, and are respectively located on the left and right sides of the same kth data line DLk. Please refer to Figure 1 and Figure 2 , especially, due to the gate pulse signal S of the xth transfer line VGx VGx The start time tonx and the gate pulse signal S of the xnth transfer line VGx-n VGx-n The end time toffx-n of the switching line VGx-n overlaps in timing. Therefore, the capacitive coupling effect between the xn-th switching line VGx-n and the k-th data line DLk and the capacitive coupling effect between the x-th switching line VGx and the k-th data line DLk can be offset, so that the pixel electrode 194 (drawn in FIG. 1 ) of the pixel structure PX located in the k-th pixel row Rk and electrically connected to the x-th scan line HGx Figure 3 ) is less likely to deviate significantly from its ideal potential due to the multiple transfer lines VG disposed on its left and right sides. Consequently, the pixel structure PX located in the k-th pixel row Rk and electrically connected to the x-th scan line HGx is less likely to exhibit abnormal brightness (e.g., excessive brightness), thereby alleviating the problem of diagonal bright lines described in the prior art. Specific examples are provided below with reference to other figures.

[0099] Figure 5 FIG. 1 is a schematic top view of a pixel array substrate 100 according to an embodiment of the present invention.

[0100] Figure 61 to 18th scanning lines HG18 according to an embodiment of the present invention. HG1 ~S HG18 .

[0101] Please refer to Figure 5 A plurality of pixel structures PX are disposed on a substrate 110 and arranged in a first pixel row R1 to a 23rd pixel row R23, wherein the first pixel row R1 to the 23rd pixel row R23 are arranged in a first direction d1. A plurality of scan lines HG include a first scan line HG1 to an 18th scan line HG18, which are sequentially arranged in a second direction d2. A plurality of data lines DL include a first data line DL1 to a 23rd data line DL23, which are electrically connected to the first pixel row R1 to the 23rd pixel row R23, respectively.

[0102] Please refer to Figure 5 and Figure 6 , the 1st scanning line HG1 to the 18th scanning line HG18 respectively have gate pulse signals S HG1 To gate pulse signal S HG18 In this embodiment, the first scanning line HG1 to the eighteenth scanning line HG18 are sequentially turned on with a time delay, wherein the length of the time delay is t (shown in FIG. Figure 6 ), gate pulse signal S HG1 To gate pulse signal S HG18 The pulse time length of each is Tp (plotted on Figure 6 ), n=Tp / t, n is 8, for example, but the present invention is not limited thereto.

[0103] Please refer to Figure 5 , the plurality of adapter wires VG include the first adapter wire VG1 to the eighteenth adapter wire VG18, which are electrically connected to the first scan line HG1 to the eighteenth scan line HG18 respectively. Figure 5 and Figure 6 , the 1st adapter wire VG1 to the 18th adapter wire VG18 respectively have gate pulse signals S VG1 To gate pulse signal S VG18 , where the gate pulse signal S of the first transfer line VG1 VG1 Gate pulse signal S to the 18th adapter VG18 VG18 The gate pulse signal S of the first scanning line HG1 is respectively HG1 The gate pulse signal S to the 18th scanning line HG18 HG18 same.

[0104] Please refer to Figure 1 and Figure 2The plurality of scan lines HG include the xnth scan line HGx-n to the x+nth scan line HGx+n sequentially arranged in the second direction d2, where x is a positive integer greater than or equal to 2, and n is a positive integer less than x; the gate pulse signal S of the xth scan line HGx is HGx The start time tonx and the gate pulse signal S of the xn-th scanning line HG HGx-n The end time toffx-n overlaps in timing; the gate pulse signal S of the x-th scanning line HG HGx The end time toffx and the gate pulse signal S of the x+n scanning line HG HGx+n The start times tonx+n overlap in timing; a plurality of transfer lines VG include an xn-th transfer line VGx-n, an x-th transfer line VGx, and an x+n-th transfer line VGx+n, which are electrically connected to the xn-th scan line HGx-n, the x-th scan line HGx, and the x+n-th scan line HGx+n, respectively; a plurality of pixel rows R include a k-1-th pixel row Rk-1, a k-th pixel row Rk, and a k+1-th pixel row Rk+1 arranged in sequence in a first direction d1, where k is a positive integer greater than or equal to 2; a plurality of data lines DL include a k-1-th data line DLk-1, a k-th data line DLk, and a k+1-th data line DLk+1, which are electrically connected to the k-1-th pixel row Rk-1, the k-th pixel row Rk, and the k+1-th pixel row Rk+1, respectively. In the top view of the pixel array substrate 100, the xnth transfer line VGx-n is disposed between the k-1th data line DLk-1 and the kth data line DLk, and the xth transfer line VGx is disposed between the kth data line DLk and the k+1th data line DLk+1; Figure 5 and Figure 6 Take this as an example.

[0105] Please refer to Figure 5 and Figure 6 In one location of the pixel array substrate 100 of this embodiment, n, x, and k mentioned in the previous paragraph can be regarded as 8, 9, and 2 respectively (ie, n=8, x=9, k=2). Figure 5 and Figure 6 In one portion of the pixel array substrate 100 of this embodiment, the plurality of scan lines HG include the first scan line HG1 to the seventeenth scan line HG17 sequentially arranged in the second direction d2; the gate pulse signal S of the ninth scan line HG9 is HG9 The start time ton9 is related to the gate pulse signal S of the first scanning line HG1. HG1 The end time toff1 overlaps in timing; the gate pulse signal S of the 9th scanning line HG9 HG9 The end time toff9 is related to the gate pulse signal S of the 17th scanning line HG17. HG17The start times ton17 of the switching operations overlap in timing. The plurality of adapter lines VG include a first adapter line VG1, a ninth adapter line VG9, and a seventeenth adapter line VG17, which are electrically connected to the first scan line HG1, the ninth scan line HG9, and the seventeenth scan line HG17, respectively. The plurality of pixel rows R include a first pixel row R1, a second pixel row R2, and a third pixel row R3, sequentially arranged in a first direction d1. The plurality of data lines DL include a first data line DL1, a second data line DL2, and a third data line DL3, which are electrically connected to the first pixel row R1, the second pixel row R2, and the third pixel row R3, respectively. In a top view of the pixel array substrate 100, the first adapter line VG1 is disposed between the first data line DL1 and the second data line DL2, and the ninth adapter line VG is disposed between the second data line DL2 and the third data line DL3.

[0106] Please refer to Figure 5 In other words, the first adapter line VG1 and the ninth adapter line VG9 are adjacent to the second data line DL2 and are located on the left and right sides of the second data line DL2, respectively. Figure 5 and Figure 6 , especially, due to the gate pulse signal S of the 9th transfer line VG9 VG9 The start time ton9 and the gate pulse signal S of the first transfer line VG1 VG1 The end time toff1 of the switching line VG1 overlaps in timing, so the capacitive coupling effect between the first switching line VG1 and the second data line DL2 and the capacitive coupling effect between the ninth switching line VG9 and the second data line DL2 can be offset, so that the pixel electrode 194 (drawn in FIG. 1 ) of the pixel structure PX located in the second pixel row R2 and electrically connected to the ninth scan line HG9 Figure 3 ) is less likely to deviate significantly from its ideal potential due to the multiple transfer lines VG disposed on its left and right sides. Therefore, the pixel structure PX located in the second pixel row R2 and electrically connected to the ninth scan line HG9 is less likely to exhibit abnormal brightness (e.g., too bright), thereby alleviating the problem of diagonal bright lines described in the prior art.

[0107] Please refer to Figure 1 and Figure 2 The plurality of scan lines HG include the xnth scan line HGx-n to the x+nth scan line HGx+n sequentially arranged in the second direction d2, and the gate pulse signal S of the xth scan line HGx is HGx The end time toffx and the gate pulse signal S of the x+nth scanning line HGx+n HGx+nThe start times tonx+n of the switching lines VG and the start times tonx+n overlap in timing; the plurality of switching lines VG further include an x+nth switching line VGx+n, which is electrically connected to the x+nth scan line HGx+n; the plurality of pixel rows R further include a k+2th pixel row Rk+2, and the k-1th pixel row Rk-1, the kth pixel row Rk, the k+1th pixel row Rk+1, and the k+2th pixel row Rk+2 are arranged in sequence in the first direction d1; the plurality of data lines DL further include a k+2th data line DLk+2, which is electrically connected to the k+2th pixel row Rk+2; in the top view of the pixel array substrate 100, the x+nth switching line VGx+n is disposed between the k+1th data line DLk+1 and the k+2th data line DLk+2; Figure 5 and Figure 6 Take this as an example.

[0108] Please refer to Figure 5 and Figure 6 In one location of the pixel array substrate 100 of this embodiment, n, x, and k mentioned in the previous paragraph can be regarded as 8, 9, and 2 respectively (ie, n=8, x=9, k=2). Figure 5 and Figure 6 In one portion of the pixel array substrate 100 of this embodiment, the plurality of scan lines HG include the first scan line HG1 to the seventeenth scan line HG17 sequentially arranged in the second direction d2, and the gate pulse signal S of the ninth scan line HG9 is HG9 The end time toff9 is related to the gate pulse signal S of the 17th scanning line HG17. HG17 The start time ton17 overlaps in timing; the multiple transfer lines VG also include the 17th transfer line VG17, which is electrically connected to the 17th scan line HG17; the multiple pixel rows R also include the 4th pixel row R4, and the 1st pixel row R1, the 2nd pixel row R2, the 3rd pixel row R3 and the 4th pixel row R4 are arranged in sequence in the first direction d1; the multiple data lines DL also include the 4th data line DL4, which is electrically connected to the 4th pixel row R4; in the top view of the pixel array substrate 100, the 17th transfer line VG17 is arranged between the 3rd data line DL3 and the 4th data line DL4.

[0109] Please refer to Figure 5 In other words, the 9th adapter line VG9 and the 17th adapter line VG17 are adjacent to the 3rd data line DL3 and are located on the left and right sides of the 3rd data line DL3 respectively. Figure 5 and Figure 6 Similarly, due to the gate pulse signal S of the 9th adapter line VG9 VG9 The end time toff9 and the gate pulse signal S of the 17th adapter line VG17 VG17The start time ton17 of the switching line 9 overlaps in timing, so the capacitive coupling effect between the 9th switching line VG9 and the 3rd data line DL3 and the capacitive coupling effect between the 17th switching line VG9 and the 3rd data line DL3 can be offset, so that the pixel electrode 194 (drawn in FIG. 194 ) of the pixel structure PX located in the 3rd pixel row R3 and electrically connected to the 17th scan line HG17 Figure 3 ) is less likely to deviate significantly from its ideal potential due to the multiple transfer lines VG disposed on its left and right sides. Therefore, the pixel structure PX located in the third pixel row R3 and electrically connected to the 17th scan line HG17 is less likely to exhibit abnormal brightness (e.g., too bright), thereby alleviating the problem of diagonal bright lines described in the prior art.

[0110] Figure 7 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0111] Figure 8 Show Figure 7 A plurality of gate pulse signals S of the xn-th scanning line HGx-n to the x+n-th scanning line HGx+n HGx-n ~S HGx+n .

[0112] Please refer to Figure 7 and Figure 8 The plurality of scan lines HG include the xnth scan line HGx-n to the xth scan line HGx arranged in sequence in the second direction d2, where x is a positive integer greater than or equal to 2, n is a positive integer less than x, and the gate pulse signal S of the xth scan line HGx is HGx The start time tonx and the gate pulse signal S of the xn-th scanning line HGx-n HGx-nThe end times toffx-n overlap in timing; the plurality of transfer lines VG include an xn-th transfer line VGx-n and an x-th transfer line VGx, which are electrically connected to the xn-th scan line HGx-n and the x-th scan line HGx, respectively; the plurality of pixel rows R include a k-1-th pixel row Rk-1, a k-th pixel row Rk, a k+1-th pixel row Rk+1, and a k+2-th pixel row Rk+2 arranged in sequence in the first direction d1, where k is a positive integer greater than or equal to 2; the plurality of data lines DL include a k-1-th data line DLk-1, a k-th data line DLk, a k+1-th data line DLk+1, and a k+2-th data line DL k+2, are electrically connected to the k-1th pixel row Rk-1, the kth pixel row Rk, the k+1th pixel row Rk+1 and the k+2th pixel row Rk+2 respectively; the pixel array substrate 100 further includes a first common line VSS1; in a top view of the pixel array substrate 100, the xnth transfer line VGx-n is arranged between the k-1th data line DLk-1 and the kth data line DLk, the xth transfer line VGx is arranged between the kth data line DLk and the k+1th data line DLk+1, and the first common line VSS1 is arranged between the k+1th data line DLk+1 and the k+2th data line DLk+2; Figure 5 and Figure 6 Take this as an example.

[0113] Please refer to Figure 5 and Figure 6 In one location of the pixel array substrate 100 of this embodiment, n, x, and k mentioned in the previous paragraph can be regarded as 8, 17, and 3 respectively (ie, n=8, x=17, k=3). Figure 5 and Figure 6 The plurality of scan lines HG include the 9th scan line HG9 to the 17th scan line HG17 sequentially arranged in the second direction d2, and the gate pulse signal S of the 17th scan line HG17 is HG17 The start time ton17 is the same as the gate pulse signal S of the 9th scanning line HG9. HG9The end time toff9 overlaps in timing; the plurality of adapter lines VG include a 9th adapter line VG9 and a 17th adapter line VG17, which are electrically connected to the 9th scan line HG9 and the 17th scan line HG17 respectively; the plurality of pixel rows R include a 2nd pixel row R2, a 3rd pixel row R3, a 4th pixel row R4 and a 5th pixel row R5 arranged in sequence in the first direction d1; the plurality of data lines DL include a 2nd data line DL2, a 3rd data line DL3, a 4th data line DL4 and a 5th data line DL5, The 9th transfer line VG9 is arranged between the 2nd data line DL2 and the 3rd data line DL3, the 17th transfer line VG17 is arranged between the 3rd data line DL3 and the 4th data line DL4, and the first common line VSS1a is arranged between the 4th data line DL4 and the 5th data line DL5.

[0114] Please refer to Figure 5 and Figure 6 In another part of the pixel array substrate 100 of this embodiment, n, x, and k mentioned in the previous two paragraphs can also be regarded as 8, 11, and 11 respectively (ie, n=8, x=11, k=11). Figure 5 and Figure 6 The plurality of scan lines HG include the third scan line HG3 to the eleventh scan line HG11 sequentially arranged in the second direction d2, and the gate pulse signal S of the eleventh scan line HG11 is HG11 The start time ton11 and the gate pulse signal S of the third scanning line HG3 HG3The end time toff3 overlaps in timing; the plurality of transfer lines VG include a third transfer line VG3 and an eleventh transfer line VG11, which are electrically connected to the third scan line HG3 and the eleventh scan line HG11, respectively; the plurality of pixel rows R include a tenth pixel row R10, an eleventh pixel row R11, a twelfth pixel row R12, and a thirteenth pixel row R13 arranged in sequence in the first direction d1; the plurality of data lines DL include a tenth data line DL10, an eleventh data line DL11, a twelfth data line DL12, and a thirteenth data line DL13, which are electrically connected to the third scan line HG3 and the eleventh scan line HG11, respectively; The third data line VG3 is arranged between the tenth data line DL10 and the eleventh data line DL11, the eleventh data line VG11 is arranged between the eleventh data line DL11 and the twelfth data line DL12, and the first common line VSS1b is arranged between the 12th data line DL12 and the 13th data line DL13.

[0115] Please refer to Figure 5 and Figure 6 In another part of the pixel array substrate 100 of this embodiment, n, x, and k mentioned in the first three paragraphs can also be regarded as 8, 18, and 15 respectively (ie, n=8, x=18, k=15). Figure 5 and Figure 6 The plurality of scan lines HG include the tenth scan line HG10 to the eighteenth scan line HG18 sequentially arranged in the second direction d2, and the gate pulse signal S of the eighteenth scan line HG18 is HG18 The start time ton18 is the same as the gate pulse signal S of the 10th scanning line HG10. HG10The end time toff10 overlaps in timing; the plurality of transfer lines VG include a 10th transfer line VG10 and an 18th transfer line VG18, which are electrically connected to the 10th scan line HG10 and the 18th scan line HG18, respectively; the plurality of pixel rows R include a 14th pixel row R14, a 15th pixel row R15, a 16th pixel row R16, and a 17th pixel row R17 arranged in sequence in the first direction d1; the plurality of data lines DL include a 14th data line DL14, a 15th data line DL15, a 16th data line DL16, and a 17th data line DL17, respectively Electrically connected to the 14th pixel row R14, the 15th pixel row R15, the 16th pixel row R16 and the 17th pixel row R17; the pixel array substrate 100 also includes a first common line VSS1c; in the top view of the pixel array substrate 100, the 10th adapter line VG10 is arranged between the 14th data line DL14 and the 15th data line DL15, the 18th adapter line VG18 is arranged between the 15th data line DL15 and the 16th data line DL16, and the first common line VSS1c is arranged between the 16th data line DL16 and the 17th data line DL17.

[0116] Please refer to Figure 5 and Figure 6 In another part of the pixel array substrate 100 of this embodiment, n, x, and k mentioned in the first four paragraphs can also be regarded as 8, 14, and 18 respectively (ie, n=8, x=14, k=18). Figure 5 and Figure 6 The plurality of scan lines HG include the sixth scan line HG6 to the fourteenth scan line HG14 sequentially arranged in the second direction d2, and the gate pulse signal S of the fourteenth scan line HG14 is HG14 The start time ton14 is related to the gate pulse signal S of the sixth scanning line HG6. HG6The end time toff6 overlaps in timing; the plurality of transfer lines VG include a 6th transfer line VG6 and a 14th transfer line VG14, which are electrically connected to the 6th scan line HG6 and the 14th scan line HG14 respectively; the plurality of pixel rows R include a 17th pixel row R17, an 18th pixel row R18, a 19th pixel row R19 and a 20th pixel row R20 arranged in sequence in the first direction d1; the plurality of data lines DL include a 17th data line DL17, an 18th data line DL18, a 19th data line DL19 and a 20th data line DL20, which are electrically connected to the 6th scan line HG6 and the 14th scan line HG14 respectively. The 6th data line VG6 is arranged between the 17th data line DL17 and the 18th data line DL18, the 14th data line VG14 is arranged between the 18th data line DL18 and the 19th data line DL19, and the first common line VSS1d is arranged between the 19th data line DL19 and the 20th data line DL20.

[0117] Figure 9 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0118] Figure 10 Show Figure 9 A plurality of gate pulse signals S of the xn-th scanning line HGx-n to the x+n-th scanning line HGx+n HGx-n ~S HGx+n .

[0119] Please refer to Figure 9 and Figure 10 The plurality of scan lines HG include the xnth scan line HGx-n to the xth scan line HGx arranged in sequence in the second direction d2, where x is a positive integer greater than or equal to 2, n is a positive integer less than x, and the gate pulse signal S of the xth scan line HGx is HGx The start time tonx and the gate pulse signal S of the xn-th scanning line HGx-n HGx-nThe end times toffx-n overlap in timing; the plurality of scan lines HG further include an m-th scan line HGm, where m is a positive integer greater than 2, and |xm| is not equal to n; the plurality of transfer lines VG include an xn-th transfer line VGx-n, an x-th transfer line VGx, and an m-th transfer line VGm, which are electrically connected to the xn-th scan line HGx-n, the x-th scan line HGx, and the m-th scan line HGm, respectively; the plurality of pixel rows R include a k-1-th pixel row Rk-1, a k-th pixel row Rk, a k+1-th pixel row Rk+1, and a k+2-th pixel row Rk+2 arranged in sequence in the first direction d1, where k is a positive integer greater than or equal to 2; the plurality of data lines DL include a k- 1 data line DLk-1, the kth data line DLk, the k+1th data line DLk+1 and the k+2th data line DLk+2 are electrically connected to the k-1th pixel row Rk-1, the kth pixel row Rk, the k+1th pixel row Rk+1 and the k+2th pixel row Rk+2, respectively; in the top view of the pixel array substrate 100, the xnth connecting line VGx-n is arranged between the k-1th data line DLk-1 and the kth data line DLk, the xth connecting line VGx is arranged between the kth data line DLk and the k+1th data line DLk+1, and the mth connecting line VGm is arranged between the k+1th data line DLk+1 and the k+2th data line DLk+2; Figure 5 and Figure 6 Take this as an example.

[0120] Please refer to Figure 5 and Figure 6 In one location of the pixel array substrate 100 of this embodiment, the n, x, k, and m mentioned in the previous paragraph can be regarded as 8, 16, 21, and 4, respectively (i.e., n=8, x=16, k=21, and m=4). Figure 5 and Figure 6 The plurality of scan lines HG include the eighth scan line HG8 to the sixteenth scan line HG16 sequentially arranged in the second direction d2, and the gate pulse signal S of the sixteenth scan line HG16 is HG16 The start time ton16 is the same as the gate pulse signal S of the eighth scanning line HG8. HG8The end time toff8 overlaps in timing; the plurality of scan lines HG further includes a fourth scan line HG4, 4 is a positive integer greater than 2, and |16-4| is not equal to 8; the plurality of adapter lines VG include an eighth adapter line VG8, a sixteenth adapter line VG16, and a fourth adapter line VG4, which are electrically connected to the eighth scan line HG8, the sixteenth scan line HG16, and the fourth scan line HG4, respectively; the plurality of pixel rows R include a 20th pixel row R20, a 21st pixel row R21, a 22nd pixel row R22, and a 23rd pixel row R23 arranged in sequence in the first direction d1; the plurality of data lines DL include a 20th data line The 8th data line DL20, the 21st data line DL21, the 22nd data line DL22 and the 23rd data line DL23 are electrically connected to the 20th pixel row R20, the 21st pixel row R21, the 22nd pixel row R22 and the 23rd pixel row R23, respectively; in the top view of the pixel array substrate 100, the 8th adapter line VG8 is arranged between the 20th data line DL20 and the 21st data line DL21, the 16th adapter line VG16 is arranged between the 21st data line DL21 and the 22nd data line DL22, and the 4th adapter line VG4 is arranged between the 22nd data line DL22 and the 23rd data line DL23.

[0121] That is, in this embodiment, at one location of the pixel array substrate 100, the gate pulse signals (e.g., S ) of the plurality of adapter wires VG (e.g., the 8th adapter wire VG8 and the 16th adapter wire VG16) located on the left and right sides of the same data line DL (e.g., the 21st data line DL21) are VG8 、S VG16 ) can differ by n time lengths t of the time delay (e.g., 8 t); however, at another location on the pixel array substrate 100, the gate pulse signals (e.g., S t ) of the plurality of adapter wires VG (e.g., the 16th adapter wire VG16 and the 4th adapter wire VG4) on the left and right sides of the same data line DL (e.g., the 22nd data line DL22) are VG16 、S VG4 )’s start time (e.g. ton16, ton4) may not differ by n t’s (e.g. 12 t’s).

[0122] Figure 11 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0123] Figure 12 Show Figure 11 A plurality of gate pulse signals S of the ynth scanning line HGy-n to the yth scanning line HGy HGy-n ~S HGy .

[0124] Please refer to Figure 11 The plurality of scan lines HG include a ynth scan line HGy-n to a yth scan line HGy arranged in sequence in the second direction d2, where y is a positive integer greater than or equal to 2, and n is a positive integer less than y.

[0125] Please refer to Figure 11 and Figure 12 , the ynth scanning line HGy-n to the yth scanning line HGy respectively have gate pulse signals S HGy-n To gate pulse signal S HGy In detail, the ynth scanning line HGy-n has a gate pulse signal S HGy-n , the y-n+1th scanning line HGy-n+1 has a gate pulse signal S HGy-n+1 , the y-n+2th scanning line HGy-n+2 has a gate pulse signal S HGy-n+2 , ..., the y-th scanning line HGy has a gate pulse signal S HGy .

[0126] Please refer to Figure 11 and Figure 12 , sequentially turning on the ynth scanning line HGy-n to the yth scanning line HGy with a time delay, wherein the length of the time delay is t (plotted on Figure 12 ), gate pulse signal S HGy-n To gate pulse signal S HGy The pulse time length of each is Tp (plotted on Figure 12 ), and n=Tp / t. The gate pulse signal S of the y-th scanning line HGy HGy The start time tony and the gate pulse signal S of the ynth scanning line HGy-n HGy-n The end time toffy-n overlaps in time sequence.

[0127] Please refer to Figure 11 The plurality of transfer lines VG include the ynth transfer line VGy-n and the yth transfer line VGy, which are electrically connected to the ynth scan line HGy-n and the yth scan line HGy, respectively. Figure 11 and Figure 12 The ynth transfer line VGy-n and the yth transfer line VGy respectively have gate pulse signals S VGy-n And gate pulse signal S VGy , where the gate pulse signal S of the ynth transfer line VGy-n VGy-n And the gate pulse signal S of the y-th transfer line VGy VGy The gate pulse signal S of the ynth scanning line HGy-n is respectively HGy-n and the gate pulse signal S of the y-th scanning line HGy HGy same.

[0128] Please refer to Figure 11 , multiple pixel rows R include the q-1th pixel row Rq-1, the qth pixel row Rq, the q+1th pixel row Rq+1 and the q+2th pixel row Rq+2 arranged in sequence in the first direction d1, q is a positive integer greater than or equal to 2; multiple data lines DL include the q-1th data line DLq-1, the qth data line DLq, the q+1th data line DLq+1 and the q+2th data line DLq+2, which are electrically connected to the q-1th pixel row Rq-1, the qth pixel row Rq, the q+1th pixel row Rq+1 and the q+2th pixel row Rq+2, respectively, and q is a positive integer greater than or equal to 2.

[0129] Please refer to Figure 11 It is worth noting that, in the top view of the pixel array substrate 100, the y-th transfer line VGy is disposed between the q-1-th data line DLq-1 and the q-th data line DLq, and the yn-th transfer line VGy-n is disposed between the q-th data line DLq and the q+1-th data line DLq+1; Figure 5 and Figure 6 Take this as an example.

[0130] Please refer to Figure 5 and Figure 6 In one part of the pixel array substrate 100 of this embodiment, the corresponding Figure 11 and Figure 12 The n, y, and q are considered to be 8, 13, and 6 respectively (i.e., n=8, y=13, q=6). Figure 5 and Figure 6 In one portion of the pixel array substrate 100 of this embodiment, the plurality of scan lines HG include the fifth scan line HG5 to the thirteenth scan line HG13 sequentially arranged in the second direction d2; the gate pulse signal S of the thirteenth scan line HG13 HG13 The start time ton13 and the gate pulse signal S of the fifth scanning line HG5 HG5 The end time toff5 of the plurality of adapter lines VG includes the fifth adapter line VG5 and the thirteenth adapter line VG13, which are electrically connected to the fifth scan line HG5 and the thirteenth scan line HG13 respectively. The fifth adapter line VG5 and the thirteenth adapter line VG13 respectively have gate pulse signals S VG5 And gate pulse signal S VG13 , where the gate pulse signal S of the 5th adapter VG5 VG5 And the gate pulse signal S of the 13th adapter VG13 VG13 The gate pulse signal S of the fifth scanning line HG5 is respectively HG5 and the gate pulse signal S of the 13th scanning line HG13HG13 The plurality of pixel rows R include a fifth pixel row R5, a sixth pixel row R6, a seventh pixel row R7, and an eighth pixel row R8 sequentially arranged in the first direction d1; the plurality of data lines DL include a fifth data line DL5, a sixth data line DL6, a seventh data line DL7, and an eighth data line DL8, which are electrically connected to the fifth pixel row R5, the sixth pixel row R6, the seventh pixel row R7, and the eighth pixel row R8, respectively.

[0131] Please refer to Figure 5 It is worth noting that, in the top view of the pixel array substrate 100, the 13th adapter line VG13 is disposed between the 5th data line DL5 and the 6th data line DL6, and the 5th adapter line VG5 is disposed between the 6th data line DL6 and the 7th data line DL7. Similarly, the 13th adapter line VG13 and the 5th adapter line VG5 are adjacent to the 6th data line DL6 and are located on the left and right sides of the 6th data line DL6, respectively. Please refer to Figure 5 and Figure 6 Similarly, due to the gate pulse signal S of the fifth transfer line VG5 VG5 The end time toff5 and the gate pulse signal S of the 13th adapter line VG13 VG13 The start time ton13 of the switching line VG13 overlaps in timing, so the capacitive coupling effect between the 13th switching line VG13 and the 6th data line DL6 and the capacitive coupling effect between the 5th switching line VG5 and the 6th data line DL6 can be offset, so that the pixel electrode 194 (drawn in FIG. 194 ) of the pixel structure PX located in the 6th pixel row R6 and electrically connected to the 13th scan line HG13 Figure 3 ) is less likely to deviate significantly from its ideal potential due to the multiple transfer lines VG disposed on its left and right sides. Therefore, the pixel structure PX located in the sixth pixel row R6 and electrically connected to the thirteenth scan line HG13 is less likely to exhibit abnormal brightness (e.g., too bright), thereby alleviating the problem of diagonal bright lines described in the prior art.

[0132] It should be noted that the two adapter lines VG located on the left and right sides of the same data line DL and arranged in sequence in the first direction d1 can offset the multiple capacitance effects of the same data line DL; however, the present invention does not limit the start time of the gate pulse signal of one of the adapter lines VG arranged first in the first direction d1 to be earlier than the start time of the gate pulse signal of the other adapter line VG arranged later; the present invention also does not limit the start time of the gate pulse signal of one of the adapter lines VG arranged first in the first direction d1 to be later than the start time of the gate pulse signal of the other adapter line VG arranged later.

[0133] For example, in Figure 5In one portion of the pixel array substrate 100, two transfer lines (for example, a first transfer line VG1 and a ninth transfer line VG9) are arranged on the left and right sides of the same data line (for example, the second data line DL2) and arranged in sequence in the first direction d1. Multiple capacitance effects of the two transfer lines and the same data line (for example, the second data line DL2) can be offset. The start time of the gate pulse signal of one of the transfer lines VG arranged first in the first direction d1 can be earlier than the start time of the gate pulse signal of the other transfer line VG arranged later (for example, the gate pulse signal S of the first transfer line VG1 arranged first in the first direction d1 is 0). VG1 The start time ton1 can be earlier than the gate pulse signal S of the 9th transfer line VG9 arranged later. VG9 The start time ton9); but Figure 5 At another location of the pixel array substrate 100, a plurality of adapter lines (for example, the 13th adapter line VG13 and the 5th adapter line VG5) are arranged on the left and right sides of the same data line (for example, the 6th data line DL6) and arranged in sequence in the first direction d1. The plurality of capacitance effects of the adapter lines and the same data line (for example, the 6th data line DL6) can offset each other, and the start time of the gate pulse signal of the adapter line VG arranged first in the first direction d1 can be later than the start time of the gate pulse signal of the other adapter line VG arranged later (for example, the gate pulse signal S of the 13th adapter line VG13 arranged first in the first direction d1). VG13 The start time ton13 may be later than the gate pulse signal S of the fifth transfer line VG5 arranged later. VG5 The start time ton5).

[0134] Please refer to Figure 11 and Figure 12 , the pixel array substrate 100 further includes a second common line VSS2; in a top view of the pixel array substrate 100, the y-th transfer line VGy is disposed between the q-1-th data line DLq-1 and the q-th data line DLq, the yn-th transfer line VGy-n is disposed between the q-th data line DLq and the q+1-th data line DLq+1, and the second common line VSS2 is disposed between the q+1-th data line DLq+1 and the q+2-th data line DLq+2; Figure 5 and Figure 6 Take this as an example.

[0135] Please refer to Figure 5 In one part of the pixel array substrate 100 of this embodiment, the corresponding Figure 11 and Figure 12 The n, y, and q are considered to be 8, 13, and 6 respectively (i.e., n=8, y=13, q=6). Figure 5In the top view of the pixel array substrate 100, the 13th adapter line VG13 is arranged between the 5th data line DL5 and the 6th data line DL6, the 5th adapter line VG5 is arranged between the 6th data line DL6 and the 7th data line DL7, and the second common line VSS2 is arranged between the 7th data line DL7 and the 8th data line DL8.

[0136] Figure 13 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100 according to an embodiment of the present invention.

[0137] Figure 14 Show Figure 13 A plurality of gate pulse signals S of the ynth scanning line HGy-n to the yth scanning line HGy HGy-n ~S HGy .

[0138] Please refer to Figure 13 and Figure 14 The plurality of scan lines HG include the ynth scan line HGy-n to the yth scan line HGy arranged in sequence in the second direction d2, y is a positive integer greater than or equal to 2, n is a positive integer less than y, and the gate pulse signal S of the yth scan line HGy is HGy The start time tony and the gate pulse signal S of the ynth scanning line HGy-n HGy-n The end times toffy-n overlap in timing; the plurality of scan lines HG further include a p-th scan line HGp; the plurality of adapter lines VG include a yn-th adapter line VGy-n and a y-th adapter line VGy, which are electrically connected to the yn-th scan line HGy-n and the y-th scan line HGy, respectively; the plurality of adapter lines VG further include a p-th adapter line VGp, which is electrically connected to the p-th scan line HGp; the plurality of pixel rows R include a q-1-th pixel row Rq-1, a q-th pixel row Rq, a q+1-th pixel row Rq+1, and a q+2-th pixel row Rq+2 arranged in sequence in the first direction d1, where q is a positive integer greater than or equal to 2; the plurality of data lines DL include a q-1-th data line DLq-1, a q-th data line DLq-2, a q-th data line DLq-3, a q-th data line DLq-4, a q-th data line DLq-5, a q-th data line DLq-6, a q-th data line DLq-7, a q-th data line DLq-8, a q-th data line DLq-9, a q-th data line DLq-11, a q-th data line DLq-12, a q-th data line DLq-13, a q-th data line DLq-14, a q-th data line DLq The q+1 data line DLq, the q+1 data line DLq+1 and the q+2 data line DLq+2 are electrically connected to the q-1 pixel row Rq-1, the q pixel row Rq, the q+1 pixel row Rq+1 and the q+2 pixel row Rq+2, respectively; in the top view of the pixel array substrate 100, the y-th transfer line VGy is arranged between the q-1 data line DLq-1 and the q data line DLq, the yn-th transfer line VGy-n is arranged between the q data line DLq and the q+1 data line DLq+1, and the p-th transfer line VGp is ​​arranged between the q+1 data line DLq+1 and the q+2 data line DLq+2; in particular, p is a positive integer greater than 2, and |yp| is not equal to n; the following is Figure 5 and Figure 6 Take this as an example.

[0139] Please refer to Figure 5 and Figure 6 In one part of the pixel array substrate 100 of this embodiment, the corresponding Figure 13 and Figure 14 The n, y, q, and p of are considered to be 8, 13, and 6 respectively (i.e., n=8, y=15, q=9, and p=3). Figure 5 and Figure 6 In the top view of the pixel array substrate 100, the plurality of scan lines HG include the 7th scan line HG7 to the 15th scan line HG15 sequentially arranged in the second direction d2, and the gate pulse signal S of the 15th scan line HG15 is HG15 The start time ton15 is the same as the gate pulse signal S of the 7th scanning line HG7. HG7 The end time toff7 overlaps in timing; the plurality of scan lines HG further includes a third scan line HG3; the plurality of adapter lines VG include a seventh adapter line VG7 and a fifteenth adapter line VG15, which are electrically connected to the seventh scan line HG7 and the fifteenth scan line HG15, respectively; the plurality of adapter lines VG further include a third adapter line VG3, which is electrically connected to the third scan line HG3; the plurality of pixel rows R include an eighth pixel row R8, a ninth pixel row R9, a tenth pixel row R10, and an eleventh pixel row R11 arranged in sequence in the first direction d1; the plurality of data lines DL include an eighth data line DL8, a ninth data line D10, and a tenth pixel row R11. L9, the 10th data line DL10 and the 11th data line DL11 are electrically connected to the 8th pixel row R8, the 9th pixel row R9, the 10th pixel row R10 and the 11th pixel row R11, respectively; in the top view of the pixel array substrate 100, the 15th adapter line VG15 is arranged between the 8th data line DL8 and the 9th data line DL9, the 7th adapter line VG7 is arranged between the 9th data line DL9 and the 10th data line DL10, and the 3rd adapter line VG3 is arranged between the 10th data line DL10 and the 11th data line DL11; in particular, 3 is a positive integer greater than 2, and |15-3| is not equal to 8.

[0140] That is, in this embodiment, at one location of the pixel array substrate 100, the gate pulse signals (e.g., S ) of the two connecting wires VG (e.g., the 15th connecting wire VG15 and the 7th connecting wire VG7) located on the left and right sides of the same data line DL (e.g., the 9th data line DL9) are VG15 、S VG7) may differ by n time lengths t of the time delay (e.g., 8 t; however, at another location on the pixel array substrate 100, the gate pulse signals (e.g., S t ) of the plurality of adapter wires VG (e.g., the 7th adapter wire VG7 and the 3rd adapter wire VG3) located on the left and right sides of the same data line DL (e.g., the 10th data line DL10) may differ by n time lengths t of the time delay (e.g., 8 t; however, at another location on the pixel array substrate 100, the gate pulse signals (e.g., S t ) of the plurality of adapter wires VG (e.g., the 7th adapter wire VG7 and the 3rd adapter wire VG3) may differ by n time lengths t of the time delay (e.g., 8 t; VG7 、S VG3 )'s start time (e.g., ton7, ton3) may also not differ by n t's (e.g., by 4 t's).

[0141] In the above description, Tp / t=n=8 is used as an example. However, the present invention is not limited thereto. In other embodiments, Tp / t=n, and n can also be a positive integer other than 8. Figure 15 and Figure 16 Give an example.

[0142] Figure 15 FIG. 1 is a schematic top view of a portion of a pixel array substrate 100A according to an embodiment of the present invention.

[0143] Figure 16 Show Figure 15 The gate pulse signals S of the first scanning line HG1 to the ninth scanning line HG9 are HG1 ~S HG9 .

[0144] Please refer to Figure 1 and Figure 2 The plurality of scan lines HG include the xnth scan line HGx-n to the x+nth scan line HGx+n sequentially arranged in the second direction d2, where x is a positive integer greater than or equal to 2, and n is a positive integer less than x; the gate pulse signal S of the xth scan line HGx is HGx The start time tonx and the gate pulse signal S of the xn-th scanning line HG HGx-n The end time toffx-n overlaps in timing; the gate pulse signal S of the x-th scanning line HGx HGx The end time toffx and the gate pulse signal S of the x+nth scanning line HGx+n HGx+nThe start times tonx+n of the switching lines VG overlap in timing; the plurality of adapter lines VG include the xnth adapter line VGx-n, the xth adapter line VGx, and the x+nth adapter line VGx+n, which are electrically connected to the xnth scan line HGx-n, the xth scan line HGx, and the x+nth scan line HGx+n, respectively; the plurality of pixel rows R include the k-1th pixel row Rk-1, the kth pixel row Rk, the xth pixel row Rk-1, and the x+nth pixel row Rk-2 arranged in sequence in the first direction d1. k+1 pixel rows Rk+1 and k+2 pixel rows Rk+2, where k is a positive integer greater than or equal to 2; a plurality of data lines DL include the k-1th data line DLk-1, the kth data line DLk, the k+1th data line DLk+1, and the k+2th data line DLk+2, which are electrically connected to the k-1th pixel row Rk-1, the kth pixel row Rk, the k+1th pixel row Rk+1, and the k+2th pixel row Rk+2, respectively. In a top view of the pixel array substrate 100, the xnth transfer line VGx-n is disposed between the k-1th data line DLk-1 and the kth data line DLk, the xth transfer line VGx is disposed between the kth data line DLk and the k+1th data line DLk+1, and the x+nth transfer line VGx+n is disposed between the k+1th data line DLk+1 and the k+2th data line DLk+2; Figure 15 and Figure 16 Take this as an example.

[0145] In one location of the pixel array substrate 100A of this embodiment, n, x, and k mentioned in the previous paragraph can be regarded as 4, 5, and 2, respectively (ie, n=4, x=5, k=2). Figure 15 and Figure 16 The plurality of scan lines HG include the first scan line HG1 to the ninth scan line HG9 sequentially arranged in the second direction d2; the gate pulse signal S of the fifth scan line HG5 HG5 The start time ton5 is related to the gate pulse signal S of the first scanning line HG. HG1 The end time toff1 overlaps in timing; the gate pulse signal S of the fifth scanning line HG5 HG5 The end time toff5 is related to the gate pulse signal S of the ninth scanning line HG9. HG9The start time ton9 overlaps in timing; the plurality of adapter lines VG include the 1st adapter line VG1, the 5th adapter line VG5 and the 9th adapter line VG9, which are electrically connected to the 1st scan line HG1, the 5th scan line HG5 and the 9th scan line HG9, respectively; the plurality of pixel rows R include the 1st pixel row R1, the 2nd pixel row R2, the 3rd pixel row R3 and the 4th pixel row R4 arranged in sequence in the first direction d1; the plurality of data lines DL include the 1st data line DL1, the 2nd data line DL2, the 3rd data line DL3 and the 4th data line DL4, which are electrically connected to the 1st pixel row R1, the 2nd pixel row R2, the 3rd pixel row R3 and the 4th pixel row R4, respectively. In the top view of the pixel array substrate 100, the first adapter line VG1 is arranged between the first data line DL1 and the second data line DL2, the fifth adapter line VG5 is arranged between the second data line DL2 and the third data line DL3, and the ninth adapter line VG9 is arranged between the third data line DL3 and the fourth data line DL4.

[0146] Figure 17 FIG. 1 is a schematic cross-sectional view of a pixel structure PX of a pixel array substrate 100 according to an embodiment of the present invention. Figure 17 correspond Figure 3 Section line II-II'.

[0147] The following combination Figure 3 and Figure 17 The specific structure of the pixel structure PX according to an embodiment of the present invention is described by way of example. The pixel structure PX can be selectively applied to the aforementioned pixel array substrate 100 or 100A.

[0148] Please refer to Figure 3 and Figure 17 In addition to the aforementioned thin film transistor T and the pixel electrode 194 electrically connected to the thin film transistor T, the pixel structure PX further includes a first common electrode 122. The first common electrode 122 partially overlaps with the pixel electrode 194 to form a storage capacitor.

[0149] In this embodiment, the pixel structure PX may selectively include a second common electrode 124 separated from the first common electrode 122. Figure 3 In a top view of the pixel array substrate 100 , the first common electrode 122 , the second common electrode 124 and the scan line HG are arranged in the second direction d2 and are separated from each other.

[0150] For example, in this embodiment, the first common electrode 122, the second common electrode 124 and the scan line HG may belong to the first conductive layer and be separated from each other, the gate Tc of the thin film transistor T may belong to the first conductive layer, and the gate Tc of the thin film transistor T may be directly connected to the scan line HG; the source Ta and the drain Tb of the thin film transistor T may belong to the second conductive layer and be separated from each other, the data line DL may belong to the second conductive layer, and the data line DL may be directly connected to the source Ta of the thin film transistor T; however, the present invention is not limited to this.

[0151] Please refer to Figure 3 and Figure 17 The pixel structure PX further includes a conductive pattern 142 electrically connected to the thin film transistor T. Specifically, the conductive pattern 142 is electrically connected to the drain electrode Tb of the thin film transistor T. For example, in this embodiment, the conductive pattern 142 and the drain electrode Tb of the thin film transistor T may belong to the same second conductive layer and may be directly connected, but the present invention is not limited thereto.

[0152] The conductive pattern 142 has a first portion 142-1 disposed on the first common electrode 122. Specifically, the conductive pattern 142 is disposed on the insulating layer 130, and the first portion 142-1 of the conductive pattern 142 overlaps the first common electrode 122. In this embodiment, the conductive pattern 142 further has a second portion 142-2 disposed on the second common electrode 124. Specifically, the conductive pattern 142 is disposed on the insulating layer 130, and the second portion 142-2 of the conductive pattern 142 overlaps the second common electrode 124. In this embodiment, the conductive pattern 142 further has a third portion 142-3 connected between the first portion 142-1 and the second portion 142-2. In a top view of the pixel array substrate 100, the third portion 142-3 of the conductive pattern 142 is located between the first common electrode 122 and the second common electrode 124, and does not overlap with the first common electrode 122 or the second common electrode 124.

[0153] Please refer to Figure 3 and Figure 17 The pixel structure PX further includes a first insulating layer 150 disposed on the conductive pattern 142 and having an opening 152 that overlaps with the conductive pattern 142. In this embodiment, the opening 152 of the first insulating layer 150 may overlap with the third portion 142-3 of the conductive pattern 142. For example, in this embodiment, the first insulating layer 150 may be made of an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of these materials), an organic material, or a combination thereof.

[0154] Please refer to Figure 3 and Figure 17The pixel structure PX further includes a color filter pattern 160 disposed on the first insulating layer 150 and having an opening 162 overlapping with the conductive pattern 142. Figure 3 For example, in a top view of the pixel array substrate 100 , the opening 152 of the first insulating layer 150 may be located within the opening 162 of the color filter pattern 160 .

[0155] Please refer to Figure 3 and Figure 17 The pixel structure PX further includes a second insulating layer 170 disposed on the color filter pattern 160 and having an opening 172 overlapping the conductive pattern 142. For example, in this embodiment, the second insulating layer 170 may be made of an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of these materials), an organic material, or a combination thereof.

[0156] In this embodiment, the pixel array substrate 100 may optionally include a transparent conductive layer 180 disposed on the second insulating layer 170. The transparent conductive layer 180 is disposed between the film layer to which the switching line VG belongs and the film layer to which the pixel electrode 194 belongs to shield the pixel electrode 194, thereby making the potential of the pixel electrode 194 less susceptible to the influence of the switching line VG. For example, in this embodiment, the material of the transparent conductive layer 180 may include a metal oxide, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or a stacked layer of at least two of the above, but the present invention is not limited thereto.

[0157] The pixel electrode 194 is disposed on the second insulating layer 170 and is electrically connected to the conductive pattern 142 through the opening 152 in the first insulating layer 150 and the opening 172 in the second insulating layer 170. For example, in this embodiment, the pixel structure PX may optionally include a third insulating layer 190 disposed on the second insulating layer 170 and covering the transparent conductive layer 180; the third insulating layer 190 has an opening 192 that overlaps the conductive pattern 142; the pixel electrode 194 may be disposed on the third insulating layer 190 and electrically contact the third portion 142-3 of the conductive pattern 142 through the opening 192 in the third insulating layer 190, the opening 172 in the second insulating layer 170, and the opening 152 in the first insulating layer 150, but the present invention is not limited thereto.

[0158] In this embodiment, the opening 192 of the third insulating layer 190, the opening 172 of the second insulating layer 170, and the opening 152 of the first insulating layer 150 may be located on the third portion 142-3 of the conductive pattern 142; the opening 192 of the third insulating layer 190, the opening 172 of the second insulating layer 170, and the opening 152 of the first insulating layer 150 may be substantially aligned; however, the present invention is not limited thereto.

[0159] In this embodiment, in a top view of the pixel array substrate 100 , the opening 152 of the first insulating layer 150 and the opening 172 of the second insulating layer 170 may be located between the first common electrode 122 and the second common electrode 124 and do not overlap with the first common electrode 122 and the second common electrode 124 .

[0160] Please refer to Figure 3 It is worth noting that, in the top view of the pixel array substrate 100, the first portion 142-1 of the conductive pattern 142 covers all edges 122e of the first common electrode 122 located within the opening 162 of the color filter pattern 160. Figure 3 and Figure 17 That is, within the openings 162 of the color filter pattern 160, there is no overlap or intersection between the edge 142e of the conductive pattern 142 and the edge 122e of the first common electrode 122. As a result, the first common electrode 122, the conductive pattern 142, and the insulating layer 130 interposed therebetween are unlikely to form a stacked structure with steep sidewalls. Near the edge 122e of the first common electrode 122, the second insulating layer 170 does not need to be formed on the stacked structure with steep sidewalls, but can instead be well-positioned on the first insulating layer 150. Therefore, the second insulating layer 170 effectively covers the color filter pattern 160 and its sidewalls 164, making it less likely that gas within the color filter pattern 160 will pass through the second insulating layer 170 and leak outside the pixel array substrate 100, potentially causing air bubbles in the display panel.

[0161] Please refer to Figure 3 In this embodiment, in the top view of the pixel array substrate 100, the second portion 142-2 of the conductive pattern 142 covers all edges 124e of the second common electrode 124 located within the opening 162 of the color filter pattern 160. Figure 3 and Figure 17 That is, within the opening 162 of the color filter pattern 160, there is no overlap or intersection between the edge 142e of the conductive pattern 142 and the edge 124e of the second common electrode 124. As a result, the second common electrode 124, the conductive pattern 142, and the insulating layer 130 interposed therebetween are unlikely to form a stacked structure with steep sidewalls. Near the edge 124e of the second common electrode 124, the second insulating layer 170 does not need to be formed on the stacked structure with steep sidewalls, but can instead be well-positioned on the first insulating layer 150. Therefore, the second insulating layer 170 effectively covers the color filter pattern 160 and its sidewalls 164, making it less likely that gas within the color filter pattern 160 will pass through the second insulating layer 170 and leak outside the pixel array substrate 100, potentially causing air bubbles in the display panel.

[0162] Figure 18FIG. 1 is a schematic top view of a layout of a pixel structure PX of a pixel array substrate 100B according to an embodiment of the present invention.

[0163] Figure 19 FIG. 1 is a schematic cross-sectional view of a pixel structure PX of a pixel array substrate 100B according to an embodiment of the present invention. Figure 19 correspond Figure 18 Section line III-III'.

[0164] Figure 18 and Figure 19 The pixel structure PX can also be selectively applied to the aforementioned pixel array substrate 100 or 100A.

[0165] Figure 18 and Figure 19 The pixel structure PX and Figure 3 and Figure 17 The pixel structure PX of is similar to that of and is denoted by the same or similar reference numerals. The differences between the two are described below. For the same or similar points between the two, please refer to the above description and will not be repeated here.

[0166] Please refer to Figure 18 and Figure 19 In this embodiment, the pixel structure PX may not include Figure 3 and Figure 17 In addition, the pixel structure PX may not include the second common electrode 124 of the embodiment. Figure 3 and Figure 17 The third insulating layer 190 and the transparent conductive layer 180 of the embodiment.

[0167] Please refer to Figure 18 and Figure 19 In this embodiment, the second portion 142-2 of the conductive pattern 142 may be disposed on the gate electrode Tc of the thin film transistor T. Figure 18 In the top view of the pixel array substrate 100B, the second portion 142 - 2 of the conductive pattern 142 may cover all edges Tcs of the gate Tc located within the opening 162 of the color filter pattern 160 .

[0168] In the top view of the pixel array substrate 100B, the third portion 142-3 of the conductive pattern 142 is located between the first common electrode 122 and the gate Tc, the opening 152 of the first insulating layer 150 and the opening 172 of the second insulating layer 170 are located on the third portion 142-3 of the conductive pattern 142, and the opening 152 of the first insulating layer 150 and the opening 172 of the second insulating layer 170 do not overlap with the first common electrode 122 and the gate Tc.

[0169] Figure 20FIG. 1 is a schematic top view of a layout of a pixel structure PX of a pixel array substrate 100C according to an embodiment of the present invention.

[0170] Figure 21 FIG. 1 is a schematic cross-sectional view of a pixel structure PX of a pixel array substrate 100C according to an embodiment of the present invention. Figure 21 correspond Figure 20 Section line IV-IV'.

[0171] Figure 20 and Figure 21 The pixel structure PX can also be selectively applied to the aforementioned pixel array substrate 100 or 100A.

[0172] Figure 20 and Figure 21 The pixel structure PX and Figure 3 and Figure 17 The pixel structure PX of is similar to that of and is denoted by the same or similar reference numerals. The differences between the two are described below. For the same or similar points between the two, please refer to the above description and will not be repeated here.

[0173] and Figure 3 and Figure 17 The pixel structure PX is different in that Figure 20 and Figure 21 In the embodiment of the present invention, the pixel structure PX further includes a third common electrode 126, which is separated from the first common electrode 122 and the second common electrode 124. In this embodiment, the third common electrode 126 may belong to the first conductive layer. Figure 20 The conductive pattern 142 further includes a fourth portion 142-4 disposed on the third common electrode 126. In the top view of the pixel array substrate 100C, the fourth portion 142-4 of the conductive pattern 142 covers all edges 126e of the third common electrode 126 located within the opening 162 of the color filter pattern 160.

[0174] Figure 22 FIG. 1 is a schematic top view of a layout of a pixel structure PX of a pixel array substrate 100D according to an embodiment of the present invention.

[0175] Figure 23 FIG. 1 is a schematic cross-sectional view of a pixel structure PX of a pixel array substrate 100D according to an embodiment of the present invention. Figure 23 correspond Figure 22 Section line V-V'.

[0176] Figure 22 and Figure 23 The pixel structure PX can also be selectively applied to the aforementioned pixel array substrate 100 or 100A.

[0177] Figure 22 and Figure 23 The pixel structure PX and Figure 3 and Figure 17 The pixel structure PX of is similar to that of and is denoted by the same or similar reference numerals. The differences between the two are described below. For the same or similar points between the two, please refer to the above description and will not be repeated here.

[0178] exist Figure 3 and Figure 17 In the embodiment of the present invention, an edge 142-1e (marked at Figure 3 ) and an edge 162e (marked at Figure 3 ) are substantially cut flush. That is, Figure 3 and Figure 17 In the embodiment, the first portion 142 - 1 of the conductive pattern 142 does not extend beyond the opening 162 of the color filter pattern 160 .

[0179] exist Figure 22 and Figure 23 In the embodiment, the conductive pattern 142 further has a fifth portion 142-5; in the top view of the pixel array substrate 100D, the fifth portion 142-5 of the conductive pattern 142 overlaps with the first common electrode 122 and is located outside the opening 162 of the color filter pattern 160. In other words, Figure 22 and Figure 23 In the embodiment, the conductive pattern 142 may extend beyond the opening 162 of the color filter pattern 160 .

Claims

1. A pixel array substrate, comprising: a base; A plurality of pixel structures are disposed on the substrate and arranged into a plurality of pixel rows, wherein the pixel rows are arranged in a first direction; A plurality of scan lines are arranged in a second direction and electrically connected to the pixel structures, wherein the first direction is interlaced with the second direction; a plurality of data lines arranged in the first direction and electrically connected to the pixel rows; and A plurality of transfer lines are arranged in the first direction and electrically connected to the scan lines; The scan lines include an xn-th scan line to an x-th scan line sequentially arranged in the second direction, where x is a positive integer greater than or equal to 2, and n is a positive integer less than x, and a start time of a gate pulse signal of the x-th scan line and an end time of a gate pulse signal of the xn-th scan line overlap in timing; The adapter lines include an xn-th adapter line and an x-th adapter line, which are electrically connected to the xn-th scan line and the x-th scan line respectively; The pixel rows include a k-1th pixel row, a kth pixel row, and a k+1th pixel row sequentially arranged in the first direction, and k is a positive integer greater than or equal to 2; The data lines include a k-1th data line, a kth data line, and a k+1th data line, which are electrically connected to the k-1th pixel row, the kth pixel row, and the k+1th pixel row, respectively; In the top view of the pixel array substrate, the xnth adapter line is disposed between the k-1th data line and the kth data line, and the xth adapter line is disposed between the kth data line and the k+1th data line. The pixel structure further includes a conductive pattern electrically connected to the drain of the thin film transistor, the conductive pattern having a first portion, the first portion being disposed on the first common electrode, and the first portion of the conductive pattern overlapping the first common electrode. The pixel structure further includes: A first insulating layer is disposed on the conductive pattern; A color filter pattern is disposed on the first insulating layer; a second insulating layer disposed on the first portion of the conductive pattern and covering the color filter pattern and its sidewalls; The first insulating layer and the second insulating layer disposed on the first portion of the conductive pattern completely overlap.

2. The pixel array substrate of claim 1 , wherein the scan lines include the xnth scan line to the x+nth scan line arranged in sequence in the second direction, and an end time of the gate pulse signal of the xth scan line overlaps with a start time of a gate pulse signal of the x+nth scan line in timing; the adapters further include an x+nth adapter electrically connected to the x+nth scan line; the pixel rows further include a k+2th pixel row, and the k-1th pixel row, the kth pixel row, the k+1th pixel row, and the k+2th pixel row are arranged in sequence in the first direction; the data lines further include a k+2th data line electrically connected to the k+2th pixel row; in a top view of the pixel array substrate, the x+nth adapter is disposed between the k+1th data line and the k+2th data line.

3. The pixel array substrate of claim 1 , wherein the pixel rows further include a k+2th pixel row, the k-1th pixel row, the kth pixel row, the k+1th pixel row, and the k+2th pixel row are arranged in sequence in the first direction; the data lines further include a k+2th data line electrically connected to the k+2th pixel row; and the pixel array substrate further includes: A first common line is provided, wherein in a top view of the pixel array substrate, the first common line is provided between the k+1th data line and the k+2th data line.

4. The pixel array substrate as described in claim 1, wherein the pixel rows further include a k+2th pixel row, the k-1th pixel row, the kth pixel row, the k+1th pixel row and the k+2th pixel row are arranged in sequence in the first direction; the data lines further include a k+2th data line electrically connected to the k+2th pixel row; the scan lines include an mth scan line; the adapter lines further include an mth adapter line electrically connected to the mth scan line; m is a positive integer greater than 2, and |xm| is not equal to n; in a top view of the pixel array substrate, the mth adapter line is arranged between the k+1th data line and the k+2th data line.

5. The pixel array substrate as claimed in claim 1 , wherein the scan lines include a ynth scan line to a yth scan line sequentially arranged in the second direction, y is a positive integer greater than or equal to 2, n is a positive integer and less than y, and a start time of a gate pulse signal of the yth scan line and an end time of a gate pulse signal of the ynth scan line overlap in timing; the adapter lines include a ynth adapter line and a yth adapter line, electrically connected to the ynth scan line and the yth scan line, respectively; the pixel rows are included in the first A q-1th pixel row, a qth pixel row and a q+1th pixel row are arranged in sequence in a direction, q is a positive integer greater than or equal to 2; the data lines include a q-1th data line, a qth data line and a q+1th data line, which are electrically connected to the q-1th pixel row, the qth pixel row and the q+1th pixel row, respectively; in a top view of the pixel array substrate, the yth transfer line is arranged between the q-1th data line and the qth data line, and the ynth transfer line is arranged between the qth data line and the q+1th data line.

6. The pixel array substrate of claim 5 , wherein the pixel rows further include a q+2th pixel row, the q-1th pixel row, the qth pixel row, the q+1th pixel row, and the q+2th pixel row are arranged in sequence in the first direction; the data lines further include a q+2th data line electrically connected to the q+2th pixel row; and the pixel array substrate further includes: A second common line is provided, wherein in a top view of the pixel array substrate, the second common line is provided between the q+1th data line and the q+2th data line.

7. The pixel array substrate as described in claim 5, wherein the pixel rows further include a q+2th pixel row, the q-1th pixel row, the qth pixel row, the q+1th pixel row and the q+2th pixel row are arranged in sequence in the first direction; the data lines further include a q+2th data line electrically connected to the q+2th pixel row; the scan lines include a pth scan line; the transfer lines further include a pth transfer line electrically connected to the pth scan line; p is a positive integer greater than 2, and |yp| is not equal to n; in a top view of the pixel array substrate, the pth transfer line is arranged between the q+1th data line and the q+2th data line. The pixel array substrate according to claim 1 , wherein n=4. 9 . The pixel array substrate according to claim 1 , wherein n=8.

10. The pixel array substrate as described in claim 1, wherein the conductive pattern further has a second portion, the second portion is disposed on the second common electrode, the second portion of the conductive pattern overlaps with the second common electrode, and the conductive pattern further has a third portion, the third portion is connected between the first portion and the second portion, the third portion of the conductive pattern is located between the first common electrode and the second common electrode, and does not overlap with the first common electrode and the second common electrode.

Images