An overvoltage protection circuit

Abstract

The present invention discloses an overvoltage protection circuit, which includes a first current mirror unit, a second current mirror unit, a resistor voltage division unit, and a hysteresis comparator; the current input terminal of the first current mirror unit is connected to the circuit power ground through an NMOS transistor NM1, a resistor R2, and an NMOS transistor NM2, and the mirror current terminal of the first current mirror unit is connected to the circuit power ground through the resistor voltage division unit. The current input terminal of the second current mirror unit is connected to a reference current source I1, and the mirror current terminal of the second current mirror unit is connected to a sampling signal terminal V GS of the resistor voltage division unit. The other sampling signal terminal Va of the resistor voltage division unit is connected to the inverting input terminal of the hysteresis comparator. The non-inverting input terminal of the hysteresis comparator is connected to a reference voltage Vref, and the output terminal of the hysteresis comparator outputs an overvoltage protection signal. For the power supply voltage protection circuit of the present invention, the circuit area is small and the manufacturing cost is low. It is not only suitable for being built using discrete devices, but also easy to be integrated inside a chip.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly to an overvoltage protection circuit. Background Art

[0002] Electronic products all have their rated operating voltage ranges. Whether the power supply voltage is too high or too low, it will cause abnormal operation of the electronic products and even damage to the electrical products. Therefore, inside the electronic products, a power supply voltage protection circuit is generally designed. For example, in a switching power supply control chip, the overvoltage protection circuit is a very important circuit module. The function of the overvoltage protection circuit is to monitor the power supply voltage of the electronic product in real time during its operation. When the power supply voltage is too high, an overvoltage protection signal is output to stop the system from working, preventing the internal circuit of the chip from being damaged due to continuous operation under a too-high power supply voltage. After overvoltage protection occurs, if the power supply voltage continues to rise, the power supply clamping circuit in the overvoltage protection circuit is turned on to limit the power supply voltage of the chip within a safe range, preventing the chip from being damaged due to a too-high power supply voltage.

[0003] A common implementation scheme of an overvoltage protection circuit is as Figure 1 shown. Figure 1 In it, VDD_HV is a high-voltage power supply, VCC is a low-voltage power supply, vb1 and vb2 are the gate bias voltages of PMOS transistors PM1 and PM2 respectively, resistors R1, R2, R3, R4 and zener diodes D1, D2, D3, D4 form a VDD_HV detection circuit, and the high-voltage NMOS transistor NM4 is a power supply clamping device. The overvoltage protection working principle of this circuit is: when the system is working normally, the VDD_HV voltage is less than the overvoltage protection voltage VDD_OVP, the VDD_HV detection circuit is not conducting, so V GS is pulled down to a low level by resistor R4, making V GS less than the threshold voltage V TH,NM5 of the high-voltage NMOS transistor NM5, the switching transistor NM5 is turned off, the potential at point a is pulled up to a high level by PMOS transistors PM1 and PM2, and after passing through the inverter inv1 and the Schmitt trigger smit1, the overvoltage protection signal VDD_OVP_N is output as a high level. When VDD_HV rises and all the zener diodes D1 - D4 are reverse broken down, the VDD_HV detection circuit conducts, and current starts to flow through resistor R3 and resistor R4. As VDD_HV continues to rise, V GS also increases. When V GS is greater than V TH,NM5When NM5 is turned on, it pulls down the voltage at point a to a low level, the overvoltage protection signal VDD_OVP_N flips to a low level, the system enters the overvoltage protection state and stops working. NM4 and NM5 in the circuit are the same type of high-voltage NMOS transistors. When NM5 is turned on, the clamping device NM4 also starts to work, and at this time the power supply clamping function of the circuit is enabled.

[0004] Another common overvoltage protection circuit scheme is as Figure 2 shown. Figure 2 In it, resistors R1 and R2 form a resistor voltage division unit to monitor the power supply voltage VDD_HV in real time. Resistors R4, R5, and R6 form another resistor voltage division unit. NPN transistors VT1, VT2, and PMOS transistor PM1 are used as switching devices to control the opening and closing of the circuit.

[0005] The working principle of this overvoltage protection circuit is as follows: When the supply voltage is within the normal operating voltage range, the sampled voltage value at point A of the resistor voltage division unit is small and is not sufficient to turn on the NPN transistor VT1. At this time, the resistor voltage division unit composed of resistors R4, R5, and R6 generates a high potential at point B, causing the NPN transistor VT2 to turn on and pulling down the voltage at point C to a low level. Therefore, the switching transistor PM1 is normally turned on, and the output signal VDD = VDD_HV, connecting the power supply signal to the device to supply power to the electrical device normally. When the supply voltage rises above the normal operating voltage range, the voltage at point A increases to the turn-on voltage of the transistor VT1, causing VT1 to turn on and pulling down the voltage at point B to a low level. At this time, the transistor VT2 enters the off state, and the voltage at point C is pulled up to a high level by the resistor R7 from the low level during normal operation, causing the switching transistor PM1 to turn off, so that the electrical device is disconnected from the power supply to avoid damage to the device due to excessive external voltage.

[0006] The disadvantages of the power supply overvoltage protection and clamping circuit in the above Scheme 1 are as follows:

[0007] (1) This scheme needs to use a relatively large number of zener diodes in series to achieve, occupying a large circuit area. The above circuit mainly uses the reverse breakdown characteristic of the zener diode to achieve the overvoltage protection function. The higher the overvoltage protection voltage, the more zener diodes are required. For example, if the overvoltage protection voltage is designed to be 30V, and the reverse breakdown voltage of the zener diode is generally between 5 and 7V, at least 4 zener diodes are required. The circuit area of the zener diode is large, and the increase in its number will significantly increase the circuit area.

[0008] (2) This solution cannot flexibly design the overvoltage protection voltage. As described in (1), this solution mainly uses the series connection of the reverse breakdown voltages of zener diodes to obtain the overvoltage protection voltage value, which greatly limits the flexibility of the VDD_OVP value. Because in this case, VDD_OVP can only be designed as an integer multiple of the reverse breakdown voltage of the zener diode, which makes it difficult to adjust the design of VDD_OVP and unable to flexibly design the overvoltage protection voltage.

[0009] (3) The overvoltage protection signal output by this solution is prone to false flipping. The overvoltage protection flip threshold and the flip threshold for overvoltage protection release of the above circuit are the same. When the system undergoes overvoltage protection, if the power supply voltage fluctuates due to external factors, causing the V GS voltage to fluctuate up and down near the NM5 threshold voltage V TH,NM5 , it will cause NM5 to turn on and off repeatedly, resulting in false flipping of the overvoltage protection signal VDD_OVP_N and making the circuit unable to work properly.

[0010] The disadvantages of the power supply overvoltage protection circuit in Solution 2 above are as follows:

[0011] (1) The overvoltage protection circuit described in this solution uses many types of devices. If this solution is designed as a circuit module inside an integrated circuit, it will make the manufacturing process of the chip complex and increase the wafer manufacturing cost. This solution uses a resistor as the sampling circuit and also uses a triode and a MOS transistor as switching devices to control the operation of the circuit, and the circuit also includes a capacitor element. The more types of devices in the circuit, the more mask layers need to be fabricated during wafer manufacturing, and at the same time, the number of photolithography operations in production increases, which will significantly increase the wafer manufacturing cost.

[0012] (2) The overvoltage protection circuit of this solution is easily affected by power supply voltage fluctuations and has unstable operation. If the power supply voltage fluctuates around the minimum operating voltage, it will cause the voltage at point B to be unstable, causing the switching transistors VT2 and PM1 to turn on and off repeatedly, so that the external power supply cannot be supplied normally, and thus the electrical product cannot work. When the power supply voltage fluctuates near the overvoltage protection voltage, it is very easy to cause the voltage at point A to fluctuate, resulting in the transistor VT1 turning on and off repeatedly, and thus causing the switching transistor PM1 to turn on and off repeatedly, making the circuit unable to work properly.

[0013] (3) The overvoltage protection circuit of this solution has a relatively large static power consumption. The triodes VT1 and VT2 are used as switching devices in the circuit. Since the triode is turned on by current drive, the switching transistors VT1 and VT2 will consume a certain base current when conducting, increasing the static power consumption. Summary of the Invention

[0014] Therefore, it is necessary to provide an overvoltage protection circuit to solve the problems existing in the overvoltage protection circuit in the background art.

[0015] To achieve the above object, the present invention provides an overvoltage protection circuit, including a first current mirror unit, a second current mirror unit, a resistor voltage division unit, and a hysteresis comparator;

[0016] The current input terminal of the first current mirror unit is connected to the circuit power ground through the NMOS transistor NM1, the resistor R2, and the NMOS transistor NM2. The mirror current terminal of the first current mirror unit is connected to the circuit power ground through the resistor voltage division unit. The current input terminal of the second current mirror unit is connected to the reference current source I1, and the mirror current terminal of the second current mirror unit is connected to a sampling signal terminal V of the resistor voltage division unit GS is connected. The other sampling signal terminal Va of the resistor voltage division unit is connected to the inverting input terminal of the hysteresis comparator. The non-inverting input terminal of the hysteresis comparator is connected to the reference voltage Vref. The output terminal of the hysteresis comparator outputs an overvoltage protection signal.

[0017] Further, the first current mirror unit includes a PMOS transistor PM1 and a PMOS transistor PM2. The source electrodes of the PMOS transistor PM1 and the PMOS transistor PM2 are connected to the positive circuit power supply. The gate electrode of the PMOS transistor PM1 and the drain electrode of the PMOS transistor PM1 are connected to the gate electrode of the PMOS transistor PM2 and the drain electrode of the NMOS transistor NM1. The drain electrode of the PMOS transistor PM2 is connected to the resistor voltage division unit.

[0018] Further, the second current mirror unit includes an NMOS transistor NM3, an NMOS transistor NM4, and an NMOS transistor NM5. The drain electrode of the NMOS transistor NM3 is connected to the gate electrode of the NMOS transistor NM3 and the reference current source I1. The source electrode of the NMOS transistor NM3 is connected to the drain electrode of the NMOS transistor NM4, the gate electrode of the NMOS transistor NM4, and the gate electrode of the NMOS transistor NM5. The source electrodes of the NMOS transistor NM4 and the NMOS transistor NM5 are grounded. The drain electrode of the NMOS transistor NM5 is connected to a sampling signal terminal V of the resistor voltage division unit GS is connected.

[0019] Further, it further includes an NMOS transistor NM2. The drain electrode of the NMOS transistor NM2 is connected to one end of the resistor R2. The other end of the resistor R2 is connected to the source stage of the NMOS transistor NM1. The gate electrode of the NMOS transistor NM2 is connected to the control signal UVLO_P. The source electrode of the NMOS transistor NM2 is grounded.

[0020] Furthermore, it further includes an NMOS transistor NM6. The drain of the NMOS transistor NM6 is connected to one end of a resistor R4. The other end of the resistor R4 is connected to another sampling signal terminal Va of the resistor voltage division unit. The gate of the NMOS transistor NM6 is connected to a control signal UVLO_P. The source of the NMOS transistor NM6 is connected to a sampling signal terminal V GS of the resistor voltage division unit.

[0021] Furthermore, the resistor voltage division unit includes a resistor R3, a resistor R4, and a resistor R5 connected in sequence. Between the resistor R4 and the resistor R5 is another sampling signal terminal V GS of the resistor voltage division unit. Between the resistor R3 and the resistor R4 is another sampling signal terminal Va of the resistor voltage division unit.

[0022] Furthermore, it further includes an NMOS transistor NM1. The drain of the NMOS transistor NM1 is connected to the current input terminal of the first current mirror unit. The source of the NMOS transistor NM1 is connected to a resistor R2. The gate of the NMOS transistor NM1 is connected to one end of a resistor R1 and the cathode of a diode D1. The other end of the resistor R1 is connected to the positive electrode of the circuit power supply. The anode of the diode D1 is grounded.

[0023] Furthermore, it further includes an NMOS transistor NM7. The source of the NMOS transistor NM7 is grounded. The gate of the NMOS transistor NM7 is connected to a sampling signal terminal V GS of the resistor voltage division unit. The drain of the NMOS transistor NM7 is connected to the positive electrode of the circuit power supply.

[0024] Further, the hysteresis comparator includes a PMOS transistor PM3. The source of the PMOS transistor PM3 is connected to the comparator power supply VCCA, the sources of the PMOS transistors PM4, PM5, PM6, and PM7. The gate of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM3, the drain of the NMOS transistor NM8, the gates of the PMOS transistors PM4, PM5, PM6, and PM7. The gate of the NMOS transistor NM8 is connected to the bias voltage Vb1. The source of the NMOS transistor NM8 is connected to the drain of the NMOS transistor NM9. The drain of the PMOS transistor PM4 is connected to the gate of the PMOS transistor PM8 and the source of the PMOS transistor PM10. The drain of the PMOS transistor PM10 is connected to the drain and the gate of the NMOS transistor NM10. The gate of the PMOS transistor PM10, Vinp, is the non-inverting input terminal of the hysteresis comparator. The source of the PMOS transistor PM8 is connected to the drain of the PMOS transistor PM5 and the source of the PMOS transistor PM9. The drain of the PMOS transistor PM8 is connected to the drain, the gate of the NMOS transistor NM11, and the gates of the NMOS transistors NM12. The drain of the PMOS transistor PM9 is connected to the drain of the NMOS transistor NM12 and the gate of the NMOS transistor NM15. The gate of the PMOS transistor PM9 is connected to the drain of the PMOS transistor PM6, the sources of the PMOS transistors PM11 and PM12. The drain of the PMOS transistor PM11 is connected to the source of the NMOS transistor NM14, the drain, and the gate of the NMOS transistor NM13. The gate of the PMOS transistor PM11, Vinm, is the inverting input terminal of the hysteresis comparator. The drain of the PMOS transistor PM12 is connected to the drain of the NMOS transistor NM14. The drain of the NMOS transistor NM15 is connected to the drain of the PMOS transistor PM7 and the input terminal of the inverter. The output terminal of the inverter is connected to the gate of the NMOS transistor NM14 as the output terminal of the hysteresis comparator. The sources of the NMOS transistors NM9, NM10, NM11, NM12, NM13, and NM15 are grounded.

[0025] Further, the grounding of the source of the NMOS transistor NM9 includes: the source of the NMOS transistor NM8 is connected to the drain of the NMOS transistor NM9, the gate of the NMOS transistor NM9 is connected to the bias voltage Vb2, and the source of the NMOS transistor NM9 is grounded;

[0026] Or: The source of NMOS transistor NM10 is grounded, which includes: the drain of PMOS transistor PM10 is connected to the drain and gate of NMOS transistor NM10, and the source of NMOS transistor NM10 is grounded;

[0027] Or: The source of NMOS transistor NM13 is grounded, which includes: the drain of PMOS transistor PM11 is connected to the drain and gate of NMOS transistor NM13, and the source of NMOS transistor NM13 is grounded.

[0028] Different from the prior art, the above technical solution has the following advantages over the prior art:

[0029] 1. For the power supply voltage protection circuit described in the present invention, the circuit area is small, the manufacturing cost is low, and it is easy to be integrated inside the chip. The circuit of the present invention adopts the form of a resistor voltage division unit plus a hysteresis comparator to implement the overvoltage protection function. Compared with the traditional implementation method using a zener diode, the circuit area is reduced and the manufacturing cost is lowered. Therefore, the circuit of the present invention is not only suitable for being built using discrete devices, but also very suitable for being integrated inside the chip.

[0030] 2. In an embodiment of the present invention, the overvoltage protection circuit has low power consumption. The overvoltage protection circuit of the present invention is controlled to start working by the start signal UVLO_P output by the internal undervoltage lockout circuit. Before the internal start signal is output, the overvoltage protection circuit is prohibited from working, ensuring that no static current is generated by the overvoltage protection circuit before the system officially starts working. After the overvoltage circuit starts working, the maximum working current of the resistor voltage division unit is limited by adjusting the current mirror bias ratio, effectively controlling the circuit current and reducing the circuit power consumption.

[0031] 3. The overvoltage protection value of the overvoltage protection circuit described in the present invention can be flexibly adjusted to meet the requirements of different system designs. The overvoltage protection of the present invention adopts the form of a resistor voltage division unit plus a comparator to implement the overvoltage protection function, and the structure is simple. From the circuit working principle, it can be seen that when the signal Va at the inverting input terminal of comparator COMP1 is greater than the reference voltage Vref at the non-inverting input terminal, the overvoltage protection signal is output. The sampling signal Va is determined by the resistance ratio of resistor R4 in this branch. By adjusting the resistance ratio, the overvoltage protection voltage value can be changed. Therefore, the overvoltage protection circuit in the form of resistor voltage division of the present invention can arbitrarily set the VDD_OVP parameter, which is more convenient and flexible than the traditional series form of zener diodes.

[0032] 4. The overvoltage protection circuit of the present invention outputs a stable overvoltage protection signal and is not prone to false inversion. The overvoltage protection comparator COMP1 in the circuit is a hysteresis comparator. The important function of the hysteresis comparator is to ensure that the signal rising flip point is not equal to the falling flip point, and there is a certain hysteresis amount between the two. Therefore, when the overvoltage protection circuit works, the overvoltage protection release voltage is less than the overvoltage protection voltage by a certain value. If the fluctuation amplitude of the voltage of the positive power supply terminal VDD_HV of the circuit is within the hysteresis range, the overvoltage protection signal will not be repeatedly inverted due to power supply fluctuations, effectively ensuring the normal operation of the overvoltage protection function of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is the circuit structure diagram of a power supply overvoltage protection and clamping circuit in the background art;

[0034] Figure 2 is the circuit structure diagram of another power supply overvoltage protection circuit in the background art;

[0035] Figure 3 is the circuit structure diagram of the overvoltage protection circuit described in the specific embodiment;

[0036] Figure 4 is the circuit diagram of the hysteresis comparator circuit structure described in the specific embodiment. SPECIFIC EMBODIMENT

[0037] In order to describe in detail the technical content, structural features, achieved objectives and effects of the technical solution, the following will be described in detail with specific embodiments in conjunction with the accompanying drawings.

[0038] Please refer to Figures 1 to 4 , the overvoltage protection circuit provided in this embodiment is as shown in Figure 3 : The high-voltage PMOS transistors PM1 and PM2 form a first current mirror unit. The reference current source I1 is the bias current generated by the internal reference current circuit of the system, and the current I2 is obtained through mirror processing by the second current mirror unit. The resistors R3, R4, and R5 form a resistor voltage division unit, and Va is the sampling voltage. By setting appropriate voltage division resistors, PM2 works in the linear region to ensure that Va changes linearly with VDD_HV. The high-voltage NMOS transistor NM7 is a clamping device to achieve the voltage clamping function. COMP1 is a hysteresis comparator. The high-voltage NMOS transistors NM2 and NM6 are switching devices, and their on and off are controlled by the UVLO_P signal. The UVLO_P signal is the circuit startup signal output by the internal undervoltage lockout circuit of the system. Before the system starts to work, UVLO_P is at a low level, and after the system starts to work, UVLO_P is at a high level.

[0039] The working principle of the power overvoltage protection circuit of the present invention is as follows: After the system starts to work, UVLO_P flips to a high level, NM2 and NM6 conduct, and the overvoltage protection circuit starts to work to monitor the power supply voltage VDD_HV. At this time, the zener diode D1 clamps the gate voltage of the high-voltage NMOS transistor NM1 at its zener voltage. At this time, NM1 conducts, and a current starts to be generated in the branch where NM1 is located, and the first current mirror unit biases to provide the working current for the resistor voltage division unit.

[0040] When the system is working normally, the sampled voltage Va on the resistor voltage division unit is less than the reference voltage Vref at the non-inverting input terminal of the hysteresis comparator COMP1, and the output signal VDD_OVP_N of COMP1 is at a high level. As VDD_HV gradually increases, the sampled voltage Va gradually increases. When VDD_HV rises to VDD_OVP, Va is greater than the reference voltage Vref, and the overvoltage protection signal VDD_OVP_N output by COMP1 flips to a low level, and the control system enters the overvoltage protection state. At this time, the voltage V GS across the resistor R5 is less than the threshold voltage V TH,NM7 of NM7, and the NM7 transistor remains in the cut-off state, and the circuit does not turn on the clamping function. When VDD_HV continues to increase, causing V GS to increase to equal V TH,NM7 , NM7 turns on, and the circuit enters the clamping protection state. Usually, the power supply voltage when the required clamping current is reached is called the clamping voltage VDD_CLAMP.

[0041] Then, according to the circuit principle, the VDD_OVP equation is as follows:

[0042]

[0043] When VDD_HV = VDD_OVP,

[0044]

[0045] When VDD_HV = VDD_CLAMP,

[0046]

[0047] In the above formula, V GS1 represents the V GS voltage when VDD_HV = VDD_OVP, and V GS2 represents the V GS voltage when VDD_HV = VDD_CLAMP. During the design process, by selecting appropriate resistance values of R3, R4, and R5, it is ensured that when VDD_HV = VDD_OVP, V GS1 < V TH,NM7, NM7 cannot be turned on. When VDD_HV is slightly greater than VDD_OVP, the circuit turns on the clamping function. When VDD_HV = VDD_CLAMP, V GS = V GS2 , and the current flowing through NM7 at this time is the clamping current required by the design.

[0048] The overvoltage protection voltage of the overvoltage protection circuit of the present invention is set by adjusting the resistance ratio. From the above circuit principle analysis, it can be seen that the magnitude of Va can be adjusted by changing the proportion of resistor R4 in the resistor voltage division unit. When the proportion of R4 decreases, the Va generated by the same VDD_HV decreases, and a larger VDD_HV is required to make the output signal of comparator COMP1 flip, that is, the overvoltage protection voltage increases. Similarly, when the proportion of R4 increases, only a smaller VDD_HV is required to make VDD_OVP_N flip, that is, the overvoltage protection voltage decreases.

[0049] The clamping device required by the power clamping circuit of the present invention has a small size. On a simple resistor voltage division unit, as VDD_HV increases, the V GS voltage changes relatively slowly. If a required clamping current is to be generated at the designed clamping voltage, a clamping device with a large size is required. The circuit of the present invention uses a current mirror structure composed of NM3, NM4, and NM5 to mirror the bias current I1 to obtain the current I2, so that V GS rapidly increases during the increase of VDD_HV. At this time, only a clamping device with a small size is required to reach the required clamping current at the designed clamping voltage. Therefore, compared with a simple resistor voltage division unit, the circuit of the present invention introduces a bias current I2, and a larger clamping current can be generated with a clamping device of a smaller size at the same clamping voltage, effectively reducing the size of the clamping device in the design, further reducing the area overhead, and reducing the manufacturing cost.

[0050] The comparator COMP1 used in the circuit of the present invention is a hysteresis comparator, which can, to a certain extent, solve the problem of false flipping of the output signal caused by voltage fluctuations, so that the overvoltage protection signal is not affected when the power supply voltage has a slight fluctuation, and the stability of the overvoltage protection signal is improved. The switching thresholds of an ordinary comparator are the same during the rising and falling processes of the input signal. When there is a slight interference in the input signal, it will cause corresponding fluctuations in the output signal. Specifically, the output signal of an ordinary comparator switches states when the two input voltages are equal. Therefore, when the two input signals are close to each other, the output of the comparator is uncertain. If there is interference noise in the input signal, it will cause the output signal of the comparator to switch states repeatedly, that is, the output has false flipping, resulting in the abnormal operation of the circuit. However, the hysteresis comparator has a hysteresis effect, providing different positive and negative switching thresholds for the sampled signal Va at the input end, so it has strong anti-interference ability. To avoid false flipping of the output signal of the overvoltage comparator caused by the voltage fluctuation of VDD_HV, a hysteresis comparator is used in the circuit of the present invention to ensure that there is a certain hysteresis amount between the overvoltage protection release voltage and the overvoltage protection voltage. When the power supply voltage fluctuation range is less than the hysteresis amount, it will not cause false flipping of the overvoltage protection signal. Ensure that the overvoltage protection signal output when the power supply VDD_HV signal fluctuates within the hysteresis amount remains stable, ensure that the circuit can correctly enter the protection state, and improve the reliability of the circuit.

[0051] The structure of the hysteresis comparator in the circuit of the present invention is as Figure 4 shown. Figure 4 Vb1 and Vb2 in the circuit are internal bias signals, providing bias voltages for the hysteresis comparator to generate the bias current required for operation. Vinp is the non-inverting input signal of the comparator, and Vinm is the inverting input signal of the comparator. Compared with an ordinary comparator, the two input signals of the hysteresis comparator are not directly transmitted to the gates of the comparator differential pair, but are respectively connected to the gates of the differential pair through PMOS transistors PM10, PM11, and PM12 for comparison. Among them, NM14 is a switching transistor, connected in series with PM12, and the opening and closing of NM14 are controlled by the output signal Vout of the comparator, so as to control whether PM12 is connected to the circuit, thereby changing the ratio of the aspect ratios of PM10, PM11, and PM12, and realizing the hysteresis function of the comparator.

[0052] The working principle of the hysteresis comparator is as follows: If Vinm is selected as the reference voltage input terminal and Vinp is the comparison signal input terminal. When Vinp gradually increases from a low level, when Vinp < Vinm, the comparator output Vout is at a low level. At this time, NM14 is turned off and PM12 is not connected to the circuit. When Vinp increases to make Vb = Vc, Vout flips to a high level. The flipping threshold voltage at this time is called the forward flipping voltage V+. When Vout becomes high, it controls NM14 to turn on and connects PM12 to the circuit. At this time, PM11 and PM12 are in parallel, so the size ratio of the MOS transistors at the two signal input terminals changes. Therefore, when Vinp changes in the reverse direction, the flipping threshold also changes. The flipping threshold voltage at this time is called the reverse flipping voltage V-, thus achieving the purpose of comparing hysteresis.

[0053] The equation for the comparator hysteresis amount can be described as:

[0054] V HYS =(V+)-(V-) (4)

[0055] According to the principle of the comparator circuit:

[0056] V+ = Vinm + V GS,PM11 -V GS,PM10 ;

[0057] V- = Vinm + V GS,PM11 '-V GS,PM10 .

[0058] Therefore, there is:

[0059] V HYS = V GS,PM11 -V GS,PM11 ' (5)

[0060] During forward comparison, the gate-source voltage of PM11:

[0061]

[0062] During reverse comparison, the gate-source voltage of PM11:

[0063]

[0064] Combining equations (4), (5), (6), and (7) gives:

[0065]

[0066] In the above formula, I PM6 is the current of PM6 transistor, and its current magnitude is related to the current mirror ratio formed by PM3. K P is the process parameter of PMOS transistor, (W / L) PM11is the aspect ratio of PM11 transistor, (W / L) PM12 is the aspect ratio of PM12 transistor. The above formula (8) proves that the hysteresis of the comparator can be adjusted by adjusting the sizes of PM11 and PM12 and the current I PM6 of PM6 transistor for control.

[0067] In the above embodiments, the first current mirror unit, the second current mirror unit, the resistor voltage division unit, and the hysteresis comparator are not limited to the structures listed in the above embodiments, and may also be other structures that can achieve the same functions. Among them, NMOS transistor NM2 and NMOS transistor NM6 can realize the turn-on and turn-off of the circuit, and can be omitted in some embodiments so that the circuit is always in the on state. NMOS transistor NM7 realizes voltage clamping and can also be omitted in non-essential embodiments.

[0068] It should be noted that although the above embodiments have been described in this article, the patent protection scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, any changes and modifications made to the embodiments described in this article, or equivalent structural or equivalent process transformations made using the content of the specification and drawings of the present invention, and directly or indirectly applying the above technical solutions to other related technical fields are all included in the patent protection scope of the present invention.

Claims

1. An overvoltage protection circuit, characterized in that: It includes a first current mirror unit, a second current mirror unit, a resistor voltage dividing unit, and a hysteresis comparator; The current input terminal of the first current mirror unit is connected to the circuit ground through the NMOS transistor NM1, the resistor R2, and the NMOS transistor NM2. The mirror current terminal of the first current mirror unit is connected to the circuit ground through the resistor voltage division unit. The current input terminal of the second current mirror unit is connected to the reference current source I1. The mirror current terminal of the second current mirror unit is connected to a sampling signal terminal V GS of the resistor voltage division unit. The other sampling signal terminal Va of the resistor voltage division unit is connected to the inverting input terminal of the hysteresis comparator. The non-inverting input terminal of the hysteresis comparator is connected to the reference voltage Vref. The output terminal of the hysteresis comparator outputs an overvoltage protection signal; The hysteresis comparator includes PMOS transistor PM3. The source of PMOS transistor PM3 is connected to the comparator power supply VCCA, the sources of PMOS transistors PM4, PM5, PM6, and PM7. The gate of PMOS transistor PM3 is connected to the drain of PMOS transistor PM3, the drain of NMOS transistor NM8, and the gates of PMOS transistors PM4, PM5, PM6, and PM7. The gate of NMOS transistor NM8 is connected to the bias voltage Vb1. The source of NMOS transistor NM8 is connected to the drain of NMOS transistor NM9. The drain of PMOS transistor PM4 is connected to the gate of PMOS transistor PM8 and the source of PMOS transistor PM10. The drain of PMOS transistor PM10 is connected to the drain and gate of NMOS transistor NM10. The gate Vinp of PMOS transistor PM10 is the non-inverting input terminal of the hysteresis comparator. The source of PMOS transistor PM8 is connected to the drain of PMOS transistor PM5 and the source of PMOS transistor PM9. The drain of PMOS transistor PM8 is connected to the drain and gates of NMOS transistors NM11 and NM12. The drain of PMOS transistor PM9 is connected to the drain of NMOS transistor NM12 and the gate of NMOS transistor NM15. The gate of PMOS transistor PM9 is connected to the drain of PMOS transistor PM6 and the sources of PMOS transistors PM11 and PM12. The drain of PMOS transistor PM11 is connected to the source of NMOS transistor NM14, the drain and gate of NMOS transistor NM13. The gate of PMOS transistor PM11 and the gate Vinm of PMOS transistor PM12 are the inverting input terminal of the hysteresis comparator. The drain of PMOS transistor PM12 is connected to the drain of NMOS transistor NM14. The drain of NMOS transistor NM15 is connected to the drain of PMOS transistor PM7 and the input terminal of the inverter. The output terminal of the inverter is connected to the gate of NMOS transistor NM14 as the output terminal of the hysteresis comparator. The sources of NMOS transistors NM9, NM10, NM11, NM12, NM13, and NM15 are grounded; the gate of NMOS transistor NM9 is connected to the bias voltage Vb2.

2. The overvoltage protection circuit according to claim 1, wherein: The first current mirror unit includes PMOS transistors PM1 and PM2. The sources of PMOS transistors PM1 and PM2 are connected to the positive pole of the circuit power supply. The gates and drains of PMOS transistor PM1 are connected to the gates of PMOS transistor PM2 and the drain of NMOS transistor NM1. The drain of PMOS transistor PM2 is connected to the resistor voltage dividing unit.

3. The overvoltage protection circuit according to claim 1, wherein: The second current mirror unit includes NMOS transistor NM3, NMOS transistor NM4, and NMOS transistor NM5. The drain of NMOS transistor NM3 is connected to the gate of NMOS transistor NM3 and the reference current source I1. The source of NMOS transistor NM3 is connected to the drain of NMOS transistor NM4, the gate of NMOS transistor NM4, and the gate of NMOS transistor NM5. The sources of NMOS transistor NM4 and NMOS transistor NM5 are grounded. The drain of NMOS transistor NM5 is connected to a sampling signal terminal V GS of the resistor voltage division unit.

4. An overvoltage protection circuit according to claim 1, characterized in that: It further includes an NMOS transistor NM2. The drain of the NMOS transistor NM2 is connected to one end of a resistor R2, the other end of the resistor R2 is connected to the source of the NMOS transistor NM1, the gate of the NMOS transistor NM2 is connected to a control signal UVLO_P, and the source of the NMOS transistor NM2 is grounded.

5. The overvoltage protection circuit according to claim 1, characterized in that: It further includes an NMOS transistor NM6. The drain of the NMOS transistor NM6 is connected to one end of a resistor R4. The other end of the resistor R4 is connected to another sampling signal terminal Va of the resistor voltage division unit. The gate of the NMOS transistor NM6 is connected to a control signal UVLO_P. The source of the NMOS transistor NM6 is connected to a sampling signal terminal V GS connection.

6. The overvoltage protection circuit according to claim 1, characterized in that: The resistor voltage dividing unit includes a resistor R3, a resistor R4, and a resistor R5 connected in sequence. Another sampling voltage V of the resistor voltage dividing unit is between the resistor R4 and the resistor R5 GS , and another sampling voltage Va of the resistor voltage dividing unit is between the resistor R3 and the resistor R4.

7. An overvoltage protection circuit according to claim 1, characterized in that: It further includes an NMOS transistor NM1. The drain of the NMOS transistor NM1 is connected to the current input terminal of the first current mirror unit, the source of the NMOS transistor NM1 is connected to the resistor R2, the gate of the NMOS transistor NM1 is connected to one end of a resistor R1 and the cathode of a zener diode D1, the other end of the resistor R1 is connected to the positive pole of the circuit power supply, and the anode of the zener diode D1 is grounded.

8. The overvoltage protection circuit according to claim 1, wherein: It further includes an NMOS transistor NM7. The source of the NMOS transistor NM7 is grounded, and the gate of the NMOS transistor NM7 is connected to a sampling voltage V of the resistor voltage dividing unit. GS The drain of the NMOS transistor NM7 is connected to the positive pole of the circuit power supply.

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