In-memory operation method and device, memory and storage medium

Abstract

An in-memory operation method and device, a memory and a storage medium. The memory includes an array having a plurality of storage units, the array including a plurality of rows and columns. The in-memory operation method includes: selecting, in the plurality of storage units, a first storage unit storing a first numerical value for operation and a second storage unit storing a second numerical value for operation to perform a read operation, obtaining an overlapping signal corresponding to the first numerical value and the second numerical value, and obtaining an operation result of the operation using the overlapping signal in the memory. The method reads the numerical values in the storage units that need to be operated in the memory and completes the logical operation, which not only effectively shortens the logical operation time, but also does not require additional external storage devices, thereby reducing the chip area and power consumption.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a method and apparatus for in-memory operation, a memory and a storage medium. BACKGROUND

[0002] Static Random-Access Memory (SRAM) is a kind of random access memory. "Static" means that as long as the power is kept on, the stored data can be kept constant. SRAM includes a storage cell array, an address decoder (including a row decoder and a column decoder), a sense amplifier, a control circuit and a buffer / drive circuit. Each storage cell in the storage array shares electrical connections with other cells in rows and columns, where the horizontal connection is called "word line (WL)", and the vertical connection of data flowing into and out of the storage cell is called "bit line". A specific word line and bit line can be selected by input address, and the intersection of the word line and the bit line is the selected storage cell, which is then read and written. SUMMARY

[0003] At least one embodiment of the present disclosure provides a method for in-memory operation, the memory includes an array having a plurality of storage cells, the array includes a plurality of rows and a plurality of columns, the method includes: selecting a first storage cell storing a first numerical value for the operation and a second storage cell storing a second numerical value for the operation in the plurality of storage cells for a read operation, obtaining an overlapping signal corresponding to the first numerical value and the second numerical value, and obtaining an operation result of the operation using the overlapping signal in the memory.

[0004] For example, in the method for in-memory operation provided by some embodiments of the present disclosure, the array includes a plurality of word lines, a plurality of first bit lines, and a plurality of second bit lines, each of the storage cells includes a first readout port controlled by a corresponding word line, the first readout port is connected to a corresponding first bit line, the first bit line of the first storage cell and the first bit line of the second storage cell are the same first bit line,

[0005] The obtaining of the overlapping signal corresponding to the first numerical value and the second numerical value includes: obtaining a first overlapping signal corresponding to the first numerical value and the second numerical value through the same first bit line, wherein the first overlapping signal is used to obtain the overlapping signal.

[0006] For example, in the method for in-memory operation provided by some embodiments of the present disclosure, each of the storage cells further includes a second readout port controlled by a corresponding word line, the second readout port is connected to a corresponding second bit line, the second bit line of the first storage cell and the second bit line of the second storage cell are the same second bit line,

[0007] The obtaining the superimposed signal corresponding to the first value and the second value comprises: obtaining, through the same second bit line, a second superimposed sub-signal corresponding to the first value and the second value; and combining the first superimposed sub-signal and the second superimposed sub-signal to obtain the superimposed signal.

[0008] For example, in the in-memory operation method provided by some embodiments of the present disclosure, the first storage unit and the second storage unit are selected synchronously to obtain the superimposed signal corresponding to the first value and the second value.

[0009] For example, in the in-memory operation method provided by some embodiments of the present disclosure, the first storage unit and the second storage unit are selected, the superimposed signal is obtained, and the operation result is obtained in the same operation cycle.

[0010] For example, in the in-memory operation method provided by some embodiments of the present disclosure, the first superimposed signal output by the same first bit line and the second superimposed signal output by the same second bit line are read out through a sense amplifier.

[0011] For example, in the in-memory operation method provided by some embodiments of the present disclosure, the superimposed signal obtained by combining the first superimposed signal and the second superimposed signal is operated through an operation module to obtain the operation result.

[0012] For example, in the in-memory operation method provided by some embodiments of the present disclosure, the operation comprises a logical operation.

[0013] For example, in the in-memory operation method provided by some embodiments of the present disclosure, the operation module comprises an NAND gate.

[0014] For example, the in-memory operation method provided by some embodiments of the present disclosure further comprises: setting the value read out by the readout circuit to 0 or 1.

[0015] For example, the in-memory operation method provided by some embodiments of the present disclosure further comprises: obtaining a first storage address of the first storage unit and a second storage address of the second storage unit, decoding the first storage address and the second storage address to select a word line corresponding to the first storage unit and a bit line corresponding to the first storage unit, and select a word line corresponding to the second storage unit and a bit line corresponding to the second storage unit.

[0016] The at least one embodiment of the present disclosure further provides a memory-in- compute device. The memory includes an array of a plurality of memory cells. The array includes a plurality of rows and a plurality of columns. The memory-in-compute device includes a control module and a compute module. The control module and the compute module are coupled to the array, respectively. The control module is configured to select, in the plurality of memory cells, a first memory cell storing a first value for a computation and a second memory cell storing a second value for the computation for a read operation. The first memory cell and the second memory cell are configured to output a first superposition signal corresponding to the first value and the second value. The compute module is configured to obtain, in the memory-in-compute device, a computation result of the computation using the first superposition signal.

[0017] The at least one embodiment of the present disclosure further provides a memory-in- compute device. The array includes a plurality of word lines, a plurality of first bit lines, and a plurality of second bit lines. Each of the memory cells includes a first readout port controlled by a corresponding word line. The first readout port is connected to a corresponding first bit line. A first bit line of the first memory cell and a first bit line of the second memory cell are a same first bit line. The first memory cell and the second memory cell are configured to output, through the same first bit line, a first superposition signal corresponding to the first value and the second value. The first superposition signal is used to obtain the superposition signal.

[0018] For example, the at least one embodiment of the present disclosure further provides a memory-in-compute device. Each of the memory cells further includes a second readout port controlled by a corresponding word line. The second readout port is connected to a corresponding second bit line. A second bit line of the first memory cell and a second bit line of the second memory cell are a same second bit line. The first memory cell and the second memory cell are further configured to obtain, through the same second bit line, a second superposition signal corresponding to the first value and the second value. The first superposition signal and the second superposition signal are combined to obtain the superposition signal.

[0019] For example, the at least one embodiment of the present disclosure further provides a memory-in-compute device. The control module is further configured to synchronously select the first memory cell and the second memory cell. The compute module is configured to obtain the superposition signal corresponding to the first value and the second value.

[0020] For example, the at least one embodiment of the present disclosure further provides a memory-in-compute device. The control module is further configured to select, in a same operation cycle, the first memory cell and the second memory cell, and obtain the superposition signal. The compute module is further configured to obtain, in the same operation cycle, the computation result.

[0021] For example, the at least one embodiment of the present disclosure further provides a memory-in computing device, wherein the operation module comprises an AND gate.

[0022] For example, the at least one embodiment of the present disclosure further provides a memory-in computing device, wherein the operation module comprises an AND gate.

[0023] For example, the at least one embodiment of the present disclosure further provides a memory-in computing device, wherein the readout circuit is further configured to set the value read by the readout circuit to 0 or 1.

[0024] For example, the at least one embodiment of the present disclosure further provides a memory-in computing device, wherein the control module is further configured to obtain a first storage address of the first storage unit and a second storage address of the second storage unit, and the device further comprises an address decoding module configured to decode the first storage address and the second storage address, so as to select the word line and the bit line corresponding to the first storage unit and the word line and the bit line corresponding to the second storage unit.

[0025] For example, the at least one embodiment of the present disclosure further provides a memory, comprising the memory-in computing device provided in any of the above embodiments and an array having a plurality of storage units.

[0026] The at least one embodiment of the present disclosure further provides a memory-in computing device, comprising: a storage unit configured to non-transiently store computer executable instructions; and a processing unit configured to run the computer executable instructions, wherein the computer executable instructions are run by the processing unit to perform the memory-in computing method provided in any of the embodiments of the present disclosure.

[0027] The at least one embodiment of the present disclosure further provides a non-transient storage medium configured to non-transiently store computer executable instructions, wherein the computer executable instructions are executed by a computer to perform the memory-in computing method provided in any of the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some of the embodiments of the present disclosure, but not limit the present disclosure.

[0029] Figure 1A circuit schematic diagram of a 6T type static random access memory (SRAM) memory cell;

[0030] Figure 2 A circuit schematic diagram of a 6T type static random access memory (SRAM) memory cell; Figure 1 A voltage waveform schematic diagram when a read operation is performed on the 6T type SRAM memory cell shown in FIG. 1;

[0031] Figure 3 A voltage waveform schematic diagram when a write operation is performed on the 6T type SRAM memory cell shown in FIG. 1; Figure 1

[0032] Figure 4 A structural block diagram of a memory provided by an embodiment of the present disclosure;

[0033] Figure 5 A circuit schematic diagram of a 6T type SRAM memory cell provided by an embodiment of the present disclosure;

[0034] Figure 6A A circuit schematic diagram of a 6T type SRAM memory cell provided by an embodiment of the present disclosure; Figure 5 A circuit diagram of a driving circuit (sensitive amplifier) connected in the 6T type SRAM memory cell shown in FIG. 1;

[0035] Figure 6B An exemplary structural circuit diagram of a sensitive amplifier; Figure 6A

[0036] A flow schematic diagram of an in-memory operation method provided by an embodiment of the present disclosure; Figure 7

[0037] A structural block diagram of a first memory cell and a second memory cell connected with an operation module corresponding to the method shown in FIG. 2; Figure 8 Figure 7 A partial circuit design diagram of a memory provided by an embodiment of the present disclosure;

[0038] Figure 9 A signal flow schematic diagram of an exclusive-OR operation on word lines and bit lines of a first memory cell and a second memory cell provided by an embodiment of the present disclosure;

[0039] Figure 10 Another signal flow schematic diagram of an exclusive-OR operation on word lines and bit lines of a first memory cell and a second memory cell provided by an embodiment of the present disclosure;

[0040] Figure 11 A structural schematic diagram of a memory provided by an embodiment of the present disclosure;

[0041] Figure 12

[0042] Figure 13 ​​​A schematic block diagram of an in-memory operation device provided by an embodiment of the present disclosure is shown in FIG. 1.

[0043] Figure 14 A schematic block diagram of another in-memory operation device provided by an embodiment of the present disclosure is shown in FIG. 2.

[0044] Figure 15 A schematic diagram of a non-transitory storage medium provided by some embodiments of the present disclosure is shown in FIG. 3. DETAILED DESCRIPTION

[0045] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present disclosure.

[0046] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the common meaning in the field of the present disclosure to those of ordinary skill. The terms "first", "second", and similar terms used in the present disclosure do not indicate any order, number, or importance, but are only used to distinguish different components. Similarly, the terms "one", "an", or "the" and similar terms do not indicate a quantity limitation, but indicate the presence of at least one. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "up", "down", "left", "right", and the like only indicate relative positional relationships, which can change accordingly when the absolute positions of the described objects change.

[0047] The present disclosure will be described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of known functions and known components. When any component of the embodiments of the present disclosure appears in more than one figure, the component is denoted by the same or similar reference numeral in each figure.

[0048] For example, in current integrated circuit design, the circuit needs to perform various mathematical operations, and most of the mathematical operations need the values stored in the memory in the chip to participate in the operation. For example, the following corresponds to or, and, and exclusive or operations, respectively.

[0049] • Operation result 1 = storage value of address 1 or storage value of address 2;

[0050] • Operation result 2 = address 1's stored value and address 2's stored value;

[0051] • Operation result 3 = address 1's stored value xor address 2's stored value.

[0052] For example, in the operation, the stored value of address 1 is read from the memory of the chip for the first time, stored in the external storage device DFF (sequential circuit), the stored value of address 2 is read from the memory for the second time, and the stored values read twice are logically operated. The twice reading of the stored values results in a long logical operation time, and the first read stored value needs to be stored in the external storage device, resulting in an increase in chip area and power consumption.

[0053] Some embodiments of the present disclosure provide an in-memory operation (which can be referred to as "in-memory operation" for short) method, the memory comprising an array having a plurality of storage units, the array comprising a plurality of rows and a plurality of columns, the in-memory operation method comprising: selecting a first storage unit storing a first numerical value for operation and a second storage unit storing a second numerical value for operation in the plurality of storage units for a read operation, obtaining an overlay signal corresponding to the first numerical value and the second numerical value, and obtaining an operation result of the operation using the overlay signal in the memory.

[0054] Some embodiments of the present disclosure also provide an in-memory operation device corresponding to the in-memory operation method, the memory comprising an array having a plurality of storage units, the array comprising a plurality of rows and a plurality of columns, the in-memory operation device comprising a control module and an operation module, the control module and the operation module being coupled to the array respectively, the control module being configured to select a first storage unit storing a first numerical value for operation and a second storage unit storing a second numerical value for operation in the plurality of storage units for a read operation, the first storage unit and the second storage unit being configured to output an overlay signal corresponding to the first numerical value and the second numerical value, and the operation module being configured to obtain an operation result of the operation using the overlay signal in the memory.

[0055] Some embodiments of the present disclosure also provide a memory comprising the above-mentioned in-memory operation device.

[0056] Some embodiments of the present disclosure also provide a non-transitory storage medium corresponding to the above-mentioned in-memory operation method, the storage medium non-transitorily storing computer readable instructions, wherein when the computer readable instructions are executed by a computer, the above-mentioned in-memory operation method provided by the embodiments of the present disclosure is executed.

[0057] The in-memory operation method provided by the above embodiments of the present disclosure includes: selecting a first storage unit and a second storage unit from a plurality of storage units in a memory for a read operation; obtaining a superposition signal of a first value and a second value in the first storage unit; and obtaining an operation result using the superposition signal in the memory. The method reads values in storage units that need to be operated in the memory and completes a logical operation, which not only effectively shortens the logical operation time, but also does not require additional external storage devices, thereby reducing the chip area and power consumption.

[0058] Some embodiments of the present disclosure and examples thereof will be described in detail below with reference to the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0059] Figure 1 A common 6-transistor (6T) type random static memory storage unit is shown. The 6T storage unit includes 6 transistors for storing data and read-write operations, such as PU transistor, PD transistor, PU_X transistor, PD_X transistor, PG transistor, and PG_X transistor. This structure has a word line (WL) and a pair of bit lines (BL / BLB) for writing data. Data is read from the read port, and data is written from the write port. When writing, BL and BLB are complementary. PU transistor and PD transistor, PU_X transistor and PD_X transistor form two inverters connected in series, that is, the output of one inverter is connected to the input of the other inverter, and vice versa. Due to the connection of the two inverters in series, a latch is formed, and the Q storage node and the QB storage node can very stably store data without external influence. They are complementary, for example, Q=0, QB=1 (i.e., the stored value is "0"). Assuming Q=0, before the read operation, WL=0, BL=BLB=Float 1 (that is, after charging to 1, turn off the charging circuit, and make it float at 1).

[0060] During the read operation, the word line WL is high (WL=1) to control the PG transistor and the PG_X transistor to be in the on state. Q=0 will pull down BL=Float 1 (float at 1) through the PG transistor to read out the data. For example, Figure 2 A waveform diagram of the actual read operation of the 6T type storage unit is shown. Q=0 will pull down the level of the bit line BL through the PG transistor, and the bit line BLB will still maintain the previous potential, which causes a voltage difference (Delta V) between the bit line BL and the bit line BLB. The voltage difference is amplified by, for example, a sensitive amplifier circuit to read out the data.

[0061] In writing data, a pair of complementary signals is formed between the bit line BL and the bit line BLB through a write circuit not shown. When the WL is high (WL = 1) to control the PG transistor and the PG_X transistor to be in the on state, if the data stored in Q and QB is different from the data to be written, the signals on the bit line BL and the bit line BLB will be forcibly driven, changed and flipped to change the data stored in Q and QB. For example, assuming that before the write operation, QB = 1 and Q = 0, in the write operation of writing 1 to the storage unit (i.e. to set Q to 1), the bit line BLB = 0 and QB = 1 will be inconsistent, and the potential corresponding to 0 applied to BLB must be forcibly driven, changed and flipped to QB = 0 to ensure the writing of data. Similarly, for the inconsistent bit line BL = 1 and Q = 0, the potential corresponding to 1 applied to BL must be forcibly driven, changed and flipped to Q = 1 to ensure the writing of data. Figure 3 The waveform diagram in the actual write operation of the 6T type storage unit is shown. When the WL is high (WL = 1) to control the PG transistor and the PG_X transistor to be in the on state, the 0 of BLB will be filled into QB through PG_X, and the 1 of BL will be filled into Q through PG, finally making Q flip from 0 to 1 and QB flip from 1 to 0.

[0062] Figure 4 A structural block diagram of a memory is provided for some embodiments of the present disclosure.

[0063] As shown in Figure 4 The memory includes an in-memory operation device and an array (storage array) 200 having a plurality of rows and a plurality of columns of storage units. The in-memory operation device includes a control module 110 coupled to the storage array, an operation module 120, a readout circuit 130, an address decoding module (XDEC) 140, and a write module (not shown), etc. For example, the control module 110 is used to control the enablement of the entire memory circuit, logic control, such as read, write, and logic operation.

[0064] For example, when performing a logic operation, the control module 110 obtains the storage addresses of a plurality of values used for operation, and provides the storage addresses to the address decoding module 140. The address decoding module 140 decodes the obtained storage addresses, obtains the storage units in the storage array 200 corresponding to the storage addresses where the values are stored, and is used to select the word lines and bit lines in the storage array 200 accordingly, so as to drive the storage units where the values are stored. The operation module 120 obtains the signals output by the storage units through the corresponding bit lines under the control of the control module 110, and performs corresponding operations, such as XOR and XNOR logic operations. The operation module 120 outputs the operation result, or the operation result can also be output outside the memory through the readout circuit 130.

[0065] For example, during a read operation, the control module 110 obtains the storage address of the data to be read and provides this storage address to the address decoding module 140. The address decoding module 140 decodes the storage address to select the word line and bit line of the storage cell containing the data to be read, thereby driving the storage cell containing the value to be read. Under the control of the control module 110, the read circuit 130 obtains the signal output by the storage cell through the corresponding bit line and outputs the read result outside the memory.

[0066] For example, during a write operation, the control module 110 obtains the storage address of the target storage cell for the data to be written and provides this storage address to the address decoding module 140. The address decoding module 140 decodes the storage address to select the word line and bit line of the target storage cell for storing the data to be written, thereby driving the target storage cell for storing the value to be written. Under the control of the control module 110, the write module (not shown) writes data into the target storage cell through the corresponding bit lines.

[0067] For example, the storage cells of the storage array in some embodiments of this disclosure can be based on, for example... Figure 1 The 6T type memory cell shown, or other improved 6T type memory cells, each memory cell has two read ports controlled by word lines and connected to two bit lines of the same type. These two read ports can be used for read operations. For example, this improved 6T type memory cell can be an 8T Dual Port (8 transistors, dual-port) SRAM memory cell, which... Figure 1 Based on the above, it also includes a pair of control transistors and a pair of bit lines ABL / ABLB. For example, bit lines BL / BLB define a pair of read ports for reading data stored in the memory cell, while bit lines ABL / ABLB define a pair of write ports for writing data to the memory cell.

[0068] For example, each memory cell can be a 6T memory cell or a modified 6T memory cell. Multiple memory cells are arranged in a multi-row, multi-column array, which also includes multiple word lines and multiple bit lines for the aforementioned multiple memory cells.

[0069] Figure 5 A circuit diagram of a 6T type memory cell is provided as an embodiment of the present disclosure, which is based on... Figure 1 The 6T type storage unit shown.

[0070] like Figure 5As shown, this 6T type memory cell includes a first read port and a second read port controlled by corresponding word lines. The first read port is connected to the corresponding first bit line, and the second read port is connected to the second bit line. For example, the word line can be WL, the first bit line can be BL to provide the first read port, and the second bit line can be BLB to provide the second read port. Figure 1 Compared to the 6T-type memory cell shown, the 6T-type memory cell in this embodiment can still perform read operations using the word line WL and the first bit line BL and the second bit line BLB through the driving circuit. It can also cooperate with other memory cells and perform in-memory operations through the driving circuit. The signal read by the driving circuit can be output through the readout circuit 130, or the driving circuit can output a superimposed signal for operation. This driving circuit is, for example, a sensitive amplifier, which can be shared by a row of memory cells; specific operations will be described later. As described above, the 6T-type memory cell in this embodiment can also perform operations on the first and second values. The superimposed signal output by the driving circuit for operation is input to the operation module 120, and after operation by the operation unit, the operation result is output.

[0071] As described above, the in-memory computing device 100 provided in the embodiments of this disclosure further includes at least one driving circuit for reading data from the memory cell, the driving circuit being, for example, a sensitive amplifier.

[0072] Figure 6A This diagram illustrates the structure of connecting the first and second bit lines of each 6T-type memory cell in the memory array to a driving circuit (e.g., a sensitive amplifier). Figure 5 Take the 6T type storage unit shown as an example.

[0073] As shown in the figure, this 6T type memory cell contains six transistors (6T) (six MOS transistors: PU0 / 1, NG0 / 1, and ND0 / 1) for storing data. These memory cells are connected to a driving circuit (e.g., a sensitive amplifier) ​​via a first bit line BL and a second bit line BLB. More specifically, the first bit line BL and the second bit line BLB are each connected to the driving circuit via corresponding switching elements, such as transistors. As shown in the figure, transistors PMX0 and PMX1 are used to connect the first bit line BL and the second bit line BLB to the driving circuit, and both are controlled by the control line YMUX. The word line WL controls whether the memory cell outputs a signal corresponding to the stored data on the first bit line BL and the second bit line BLB. When transistors PMX0 and PMX1 are turned on by the control line YMUX, the signals output on the first bit line BL and the second bit line BLB are input to the sensitive amplifier. The sensitive amplifier amplifies and reads the signals output from the first bit line BL and the second bit line BLB, and inputs them to the arithmetic module 120 for processing. For example, the processing result is output directly from the DO output terminal without going through the readout circuit 130.

[0074] Figure 6B A schematic diagram of an exemplary structure of a sensitive amplifier is shown. When WL is high, the data stored at nodes Q and QB is output as signals on the first bit line BL and the second bit line BLB. After an enable signal is applied to the control line YMUX, the signal output from the first bit line BL is input to the SATI circuit of the sensitive amplifier through transistor PMX0, and the signal output from the second bit line BLB is input to the SACI circuit of the sensitive amplifier through transistor PMX1. When a voltage difference is generated between the first bit line BL and the second bit line BLB, the same voltage difference is generated between the SATI circuit and the SACI circuit. Therefore, after the switch SAEN controlling the sensitive amplifier is turned on, the sensitive amplifier amplifies the signals output from the first bit line BL and the second bit line BLB. For example, the operating state waveform of the sensitive amplifier is as follows: Figure 6B As shown in the diagram on the right.

[0075] Figure 7 A flowchart illustrating an in-memory operation method provided for some embodiments of this disclosure; Figure 8 For corresponding Figure 7 The diagram shows the structural block diagram of the connection between the first and second storage units and the arithmetic module in the method shown.

[0076] like Figure 7 As shown, the in-memory operation method includes the following steps S100 to S200.

[0077] Step S100: Select a first storage unit that stores a first value used for calculation and a second storage unit that stores a second value used for calculation from among the multiple storage units, and perform a read operation to obtain the superimposed signal corresponding to the first value and the second value.

[0078] Step S200: Obtain the operation result using superimposed signals in the memory.

[0079] like Figure 8 As shown, the superimposed signal of the first value and the second value output from the first storage unit and the second storage unit is processed by the arithmetic module 120 to obtain the calculation result, which is then output.

[0080] The following will further combine Figure 4 as well as Figure 5 The embodiments shown are illustrated, but the embodiments disclosed herein are not limited thereto.

[0081] First, the control module 110 obtains the first storage address of the first value m and the second storage address of the second value n. Then, the address decoding module 140 selects the first storage unit to store the first value m from multiple storage units according to the first storage address, and selects the second storage unit to store the second value n from multiple storage units according to the second storage address, so as to perform read operations on the first value and the second value.

[0082] Specifically, the address decoding module 140 decodes the first and second storage addresses sent by the control module 110 to select the word line (WL[m]), first bit line (BL[m]), and second bit line (BLB[m]) corresponding to the first storage unit, and to select the word line (WL[n]), first bit line (BL[n]), and second bit line (BLB[n]) corresponding to the second storage unit. For example, if the first and second storage units are in the same column, the first bit line (BL[m]) of the first storage unit and the first bit line (BL[n]) of the second storage unit are the same first bit line BL, and the second bit line (BLB[m]) of the first storage unit and the second bit line (BLB[n]) of the second storage unit are the same second bit line BLB.

[0083] Then, when reading the first value and the second value, the word line corresponding to the first storage unit controls (for example, applies an enable signal) the first storage unit, and outputs the signal of the first value on the corresponding first bit line BL through the first read port; the word line corresponding to the second storage unit controls (for example, applies an enable signal) the second storage unit, and outputs the signal of the second value on the corresponding same first bit line BL through the first read port; and the signal of the first value and the signal of the second value output on the same first bit line BL are combined to obtain a first superimposed signal. Similarly, the word line corresponding to the first storage unit controls (for example, applies an enable signal) the first storage unit, and outputs the signal of the first value on the corresponding second bit line BLB through the second read port; the word line corresponding to the second storage unit controls (for example, applies an enable signal) the second storage unit, and outputs the signal of the second value on the corresponding same second bit line BLB through the second read port; and the signal of the first value and the signal of the second value output on the same second bit line BLB are combined to obtain a second superimposed signal. The first superimposed signal and the second superimposed signal are combined to obtain a pair of superimposed signals. The read port of each storage unit is connected to the operation module 120 through the corresponding bit line, and the pair of superimposed signals are processed through the operation module 120 to obtain an operation result.

[0084] It should be noted that, here, the "first storage unit" or the "second storage unit" is used to refer to any storage unit in the plurality of storage units as an operation object, and the "first bit line" and the "second bit line" are the bit lines corresponding to the storage unit (for example, the first storage unit or the second storage unit) as a description object.

[0085] Here, the operation performed includes a logical operation, which can be an exclusive or (xor) operation or an exclusive nor (xnor) operation. In at least one embodiment of the present disclosure, in order to be able to implement the two kinds of storage operations, the operation module 120 can include a NAND gate, and the operation result is output through the NAND gate, and the operation result is obtained, for example, the "exclusive nor" operation result or the "exclusive or" operation result.

[0086] For example, the output end of the operation module 120 can also be connected to a latch circuit, which is used to latch the signal output by the operation module (for example, the signal output by the match output end in the subsequent embodiment), to prevent the line SATI / SACI in the sensitive amplifier from returning to the initial value after the reset operation and causing the loss of the operation result signal output by the operation module.

[0087] Alternatively, for example, the superposition signal of the first value stored in the first storage unit and the second value stored in the second storage unit can be read out through the readout circuit 130, which reads out the first and second values. Since the data read out by the readout circuit 130 may be updated to the first and second values ​​of the current operation during an XOR or XNOR operation, or the read data may not be updated and may remain as the first and second values ​​of the previous operation (described in detail in subsequent embodiments), the data read out by the readout circuit 130 is uncertain. To ensure that the data read out by the readout circuit 130 is definite, the superposition signal of the first and second values ​​is set to 0 or 1 by the value read out by the readout circuit 130, thereby locking the output state in the operation phase (but not for actual use). Then, in the data reading phase (not the operation phase), the readout circuit 130 will output the actual value according to the output of the sensitive amplifier.

[0088] For example, the control module 110 can simultaneously select the first storage unit and the second storage unit. The first superimposed signal output by the first storage unit and the second superimposed signal output by the second storage unit on the first bit line are combined with each other to obtain a superimposed signal. The superimposed signal is input into the arithmetic module 120 for calculation, which can effectively speed up the calculation speed of the whole process and shorten the calculation cycle.

[0089] For example, within the same operation cycle (clock cycle or machine cycle), the first and second memory cells are selected, the superimposed signal is acquired, and the calculation result is obtained. By concentrating the calculation cycles for the first and second values ​​within the memory into the same operation cycle, the computation cycle is effectively shortened.

[0090] like Figure 9 As shown, Figure 9 The circuit section is for illustrative purposes only, and is based on... Figure 5 The illustrated embodiment is an example; the actual circuit design can be adapted to suit specific circumstances, and the embodiments disclosed herein do not impose limitations on this. Figure 9 In the IO[0] section, the input / output channel is represented, which may correspond to a column in a storage array, for example.

[0091] The following describes in detail the specific process of signal transmission when the in-memory operation method of the present disclosure is executed in the storage unit, taking the logical operation "XNOR" as an example. This specific process can also be applied to other types of operations.

[0092] For example, Figure 10 This diagram illustrates the signal flow of an XOR operation on the word lines and bit lines of a first and second memory cell.

[0093] In one example, assume that the first value stored in the first storage cell and the second value stored in the second storage cell are the same, for example, the first value Q[m] and the second value Q[n] stored in the nodes Q and QB are both 1 or 0. In the case of Q[m] = Q[n] = 0, when the word line WL[m] of the first storage cell and the word line WL[n] of the second storage cell are high, the first value Q[m] and the second value Q[n] stored in the nodes Q and QB output signals on the first bit line BL and the second bit line BLB. Since Q[m] = Q[n] = 0, the Q[m] node and the Q[n] node pull down the voltage of the first bit line BL, and since both nodes of the two storage cells pull down the voltage of the first bit line BL, the first bit line BL is pulled down to 0 (or close to 0) at a speed twice as fast as a single storage cell pulling down the voltage of the first bit line BL (as shown by the dashed arrow showing the discharge path of the first bit line BL being pulled down to 0); and both nodes of the two storage cells do not change the voltage of the second bit line BLB, which remains in a floating (i.e., 1) state. The function of the control line Write / Match YMUX is to select the first bit line BL and the second bit line BLB in a certain column from the plurality of columns of storage cells to be connected to the subsequent sense amplifier. Then, after an opening signal is applied to the control line Write / Match YMUX, the two MOS transistors (T1 transistor and T2 transistor) open the path connecting the first bit line BL and the second bit line BLB to the sense amplifier, so that the signal output by the first bit line BL (BL = 0) is input to the SAT line of the sense amplifier, and the signal output by the second bit line BLB (BLB = 1) is input to the SAC line of the sense amplifier. The input end switch line Match_PG (Pass_Gate) of the sense amplifier controls the opening of the two MOS transistors (T3 transistor and T4 transistor) to be opened, so that SAT and SATI are connected, and SAC and SACI are connected. SAT and SATI are connected through Match_PG, and similarly, SAC and SACI are connected through Match_PG, so that the signal on the SAT line (SAT = 0) enters the sense amplifier through the input end line SATI, and the signal on the SAC line (SAC = 0) enters the sense amplifier through the input end line SACI. After the two signals output by the sense amplifier are operated by the NAND gate, the operation result "1" is output, i.e., Match = 1, which indicates that the first value Q[m] and the second value Q[n] are the same (both 0 or both 1). Similarly, in the case of Q[m] = Q[n] = 1, the NAND gate also outputs the operation result "1", i.e., Match = 1. Figure 11

[0094] For example, Figure 11 ​A signal flow diagram showing the XNOR operation on the word lines and bit lines of the first memory cell and the second memory cell.

[0095] In one example, it is assumed that the first value stored in the first memory cell and the second value stored in the second memory cell are different, for example, one of the first value Q[m] and the second value Q[n] stored in the nodes Q and QB is 1 and the other is 0. In the case of Q[m] = 1 and Q[n] = 0, when the word line WL[m] of the first memory cell and the word line WL[n] of the second memory cell are high, the first value Q[m] and the second value Q[n] stored in the nodes Q and QB output signals on the first bit line BL and the second bit line BLB. Since Q[m] = 0, the Q[m] node pulls down the voltage of the first bit line BL common to the first memory cell and the second memory cell. Since Q[n] = 1, when the first bit line BL is pulled down to a voltage value of VDD-Vth (because the NMOS on the path loses one Vth when transmitting VDD), Q[n] continuously supplies current to the first bit line BL, and the voltage of the first bit line BL stays at a value close to VDD-Vth (the thick dashed line is the discharge path of BL pulled down to 0, and the thin dashed line is the path of Q / QB charging BL). Similarly, the voltage of the second bit line BLB also stays at a value of VDD-Vth. Then, after applying an opening signal to the control line Write / Match YMUX, the two MOS transistors (T1 transistor and T2 transistor) open the path connecting the first bit line BL and the second bit line BLB to the sensitive amplifier, so that the signal output by the first bit line (BL = VDD-Vth) is input to the SAT line of the sensitive amplifier, and the signal output by the second bit line BLB (BLB = 1) is input to the SAC line of the sensitive amplifier. The input end switch line Match_PG of the sensitive amplifier controls the opening of the two MOS transistors (T3 transistor and T4 transistor) to open, so that SAT and SATI are connected, and SAC and SACI are connected. SAT and SATI are connected through Match_PG, and similarly, SAC and SACI are connected through Match_PG, so that the signal on the SAT line (SAT = VDD-Vth) enters the sensitive amplifier through the input end line SATI, and the signal on the SAC line (SAC = VDD-Vth) enters the sensitive amplifier through the input end line SACI. After the two signals output by the sensitive amplifier are operated by the NAND gate, the operation result "0" is output, i.e. Match = 0, which indicates that the first value Q[m] and the second value Q[n] are different. Similarly, in the case of Q[m] = 0 and Q[n] = 1, the NAND gate also outputs the operation result "0", i.e. Match = 0.

[0096] As can be seen from the above, on the one hand, when Q[m] is the same as Q[n], the NAND outputs "1"; on the other hand, when Q[m] is different from Q[n], the NAND outputs "0", i.e. Match=0. Thus, the "XOR" operation (same as true, different as false) is realized.

[0097] For example, Figure 12 A structure diagram of a memory is shown, based on which the specific process of signal transmission when the memory-in operation method of the embodiment of the present disclosure is executed in a memory cell is described in detail, and the conventional read and write operation process of the memory is described.

[0098] In an example, referring to the embodiment of the "XOR" operation on the word line and the bit line of the first memory cell and the second memory cell described above, the first value Q[m] stored in the first memory cell and the second value Q[n] stored in the second memory cell are outputted from the Match terminal after the operation in the memory, and the first value Q[m] and the second value Q[n] can be outputted from the port DO through the readout circuit 130. The output of the Match output port and the DO output port can have various setting modes, for example, when Match=1, the first value Q[m] and the second value Q[n] currently used for operation are outputted from the DO output terminal, and when Match=0, the data outputted from the DO is set to 0 or 1. The reason is that when one of SATI and SACI is 0, Match=1 is outputted through the NAND, and the data outputted from D0 is updated to the currently stored data Q, and when SATI and SACI are both 1, Match=0 is outputted through the NAND, and the data outputted from D0 is not updated, and the previously stored data Q-1 is still outputted, so the data outputted from DO is in an uncertain state, in order to ensure that the data outputted from D0 is in a certain state, the data outputted from D0 is set to 0 or 1. Of course, when the "XOR" operation is performed, the Match output terminal outputs the operation result, and the data outputted from DO can be set to 0 or 1, which is not limited in the embodiment.

[0099] For example, in the case of reading the first value Q[m] stored in the first memory cell or the second value Q[n] stored in the second memory cell, when the word line WL[m] of the first memory cell or the word line WL[n] of the second memory cell is high, the first value Q[m] or the second value Q[n] stored in the nodes Q and QB outputs a signal on the first bit line BL and a signal on the second bit line BLB. Then, after applying an opening signal to the control line Read YMUX (Write / Match YMUX is in the closed state), the two MOS transistors (PUX0 transistor and PUX1 transistor) open the path connecting the first bit line BL and the second bit line BLB to the sense amplifier, so that the signal output by the first bit line is input to the SAT line of the sense amplifier, or the signal output by the second bit line BLB is input to the SAC line of the sense amplifier. After the input end switch line Match_PG of the sense amplifier controls the closing of the two MOS transistors (T3 transistor and T4 transistor), and the switch SAEN of the sense amplifier is opened, the signal on the SAT line does not pass through the input end line SATI, and similarly, the signal on the SAC line does not pass through the input end line SAC. The signal on the SAT line or the signal on the SAC line passes through the readout circuit 130, and the first value Q[m] or the second value [n] is output at the DO output end.

[0100] For example, in the case of writing the first value Q[m] stored in the first memory cell or the second value Q[n] stored in the second memory cell by the write circuit (not shown), when the word line WL[m] of the first memory cell or the word line WL[n] of the second memory cell is high, the first value Q[m] or the second value Q[n] stored in the nodes Q and QB outputs a signal on the first bit line BL and a signal on the second bit line BLB. Then, after applying an opening signal to the control line Write / Match YMUX (Read YMUX is in the closed state), the two MOS transistors (PUX0 transistor and PUX1 transistor) open the path connecting the first bit line BL and the second bit line BLB to the sense amplifier, but since the input end switch line Match_PG of the sense amplifier controls the closing of the two MOS transistors (T3 transistor and T4 transistor), and the switch SAEN of the sense amplifier is also closed, data can be written at this time.

[0101] The operation process, read and write operations, and the opening or closing of each control line in the memory, as well as the Match output end and the DO output end in each of the above embodiments, are shown in Table 1 below, where Q-1 represents the last read data; Q represents the current read data. Table 1 is only a partial example, and the type of operation can also be various, without being specifically limited.

[0102] Table 1

[0103]

[0104] Figure 13 A memory 10 is provided for some embodiments of the present disclosure, the memory 10 comprises an in-memory computing device 100 and an array 200 (storage array) having a plurality of storage units, the array 200 comprises a plurality of rows and columns of storage units. The in-memory computing device 100 comprises a control module 110 and a computing module 120, the control module 110 and the computing module 120 are coupled with the array 200 respectively.

[0105] The control module 110 is configured to select a first storage unit storing a first numerical value for computation and a second storage unit storing a second numerical value for computation in the plurality of storage units for a read operation, and obtain an overlay signal corresponding to the first numerical value and the second numerical value; the computing module 120 is configured to obtain a computation result of the computation using the overlay signal in the memory 10.

[0106] For example, the array 200 comprises a plurality of word lines, a plurality of first bit lines, and a plurality of second bit lines, each storage unit comprises a first readout port controlled by a corresponding word line, the first readout port is connected to a corresponding first bit line, and the first bit line of the first storage unit and the first bit line of the second storage unit are the same first bit line. The first storage unit and the second storage unit are configured to output a first overlay signal corresponding to the first numerical value and the second numerical value through the same first bit line, wherein the first overlay signal is used to obtain the overlay signal.

[0107] For example, each storage unit further comprises a second readout port controlled by a corresponding word line, the second readout port is connected to a corresponding second bit line, and the second bit line of the first storage unit and the second bit line of the second storage unit are the same second bit line. The first storage unit and the second storage unit are further configured to obtain a second overlay sub-signal corresponding to the first numerical value and the second numerical value through the same second bit line; and combine the first overlay sub-signal and the second overlay sub-signal to obtain the overlay signal.

[0108] For example, each storage unit further comprises a second readout port controlled by a corresponding word line, the second readout port is connected to a corresponding second bit line, and the second bit line of the first storage unit and the second bit line of the second storage unit are the same second bit line. The first storage unit and the second storage unit are further configured to obtain a second overlay sub-signal corresponding to the first numerical value and the second numerical value through the same second bit line; and combine the first overlay sub-signal and the second overlay sub-signal to obtain the overlay signal.

[0109] For example, the control module 110 is further configured to synchronously select the first storage unit and the second storage unit, and the computing module 120 is configured to obtain the overlay signal corresponding to the first numerical value and the second numerical value.

[0110] For example, the control module 110 is also configured to select the first storage unit and the second storage unit and acquire the superimposed signal within the same operation cycle, and the calculation module 120 is also configured to obtain the calculation result within the same operation cycle.

[0111] For example, the in-memory processing device also includes a sensitive amplifier configured to read out a first superimposed signal output from the same first bit line and a second superimposed signal output from the same second bit line.

[0112] For example, the arithmetic module 120 includes NAND gates.

[0113] For example, the in-memory processing device also includes a readout circuit 130, which is configured to read out a first value and a second value.

[0114] For example, the readout circuit 130 is also configured to set the value read out by the readout circuit to 0 or 1.

[0115] For example, the control module 110 is also configured to obtain the first storage address of the first storage unit and the second storage address of the second storage unit.

[0116] The in-memory arithmetic unit also includes an address decoding module 140, which is configured to decode the first memory address and the second memory address, and to select the word line and the corresponding bit line corresponding to the first memory cell, and to select the word line and the corresponding bit line corresponding to the second memory cell.

[0117] Figure 14 This is a schematic block diagram of another in-memory computing device provided for some embodiments of this disclosure.

[0118] For example, such as Figure 14 As shown, the in-memory computing device 500 includes a storage unit 510 and a processing unit 520. For example, the storage unit 510 is used to non-temporarily store computer-executable instructions, and the processing unit 520 is used to run the computer-executable instructions. The computer-executable instructions are executed by the processing unit 520 to perform the in-memory computing method provided in any embodiment of this disclosure.

[0119] For example, the storage unit 510 and the processing unit 520 can communicate with each other directly or indirectly. For example, in some examples, such as... Figure 14As shown, the in-memory computing device 500 can further include a system bus 530 through which the storage unit 510 and the processing unit 520 can communicate with each other, e.g., the processing unit 520 can access the storage unit 510 through the system bus 1006. In other examples, the components such as the storage unit 510 and the processing unit 520 can communicate through a network-on-chip (NOC) connection.

[0120] For example, the processing unit 520 can control other components in the in-memory computing device to perform desired functions. The processing unit 520 can be a central processing unit (CPU), a tensor processing unit (TPU), a network processing unit (NP), or a graphics processing unit (GPU), etc., which has data processing capability and / or program execution capability, and can also be a digital signal processing unit (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, etc.

[0121] For example, the storage unit 510 can include one or more combinations of various forms of computer-readable storage media, e.g., volatile storage unit and / or non-volatile storage unit. For example, the volatile storage unit can include random access memory (RAM), cache, etc. For example, the non-volatile storage unit can include read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), compact disc read-only memory (CD-ROM), USB storage unit, flash memory, etc.

[0122] For example, one or more computer instructions can be stored on the storage unit 510, and the processing unit 520 can execute the computer instructions to implement various functions. Various application programs and various data, e.g., instruction processing code and various data used and / or generated by the application programs, etc., can also be stored in the computer-readable storage medium.

[0123] For example, some computer instructions stored in the storage unit 510 can be executed by the processing unit 520 to perform one or more steps in the in-memory computing method according to the above.

[0124] For example, as shown in FIG. 5, the in-memory computing device 500 can further include a system bus 530 through which the storage unit 510 and the processing unit 520 can communicate with each other, e.g., the processing unit 520 can access the storage unit 510 through the system bus 1006. In other examples, the components such as the storage unit 510 and the processing unit 520 can communicate through a network-on-chip (NOC) connection. Figure 14As shown, the in-memory processing unit 500 may further include an input interface 540 that allows external devices to communicate with the in-memory processing unit 500. For example, the input interface 540 may be used to receive instructions from external computer devices, users, etc. The in-memory processing unit 500 may also include an output interface 550 that enables interconnection between the in-memory processing unit 500 and one or more external devices. For example, the in-memory processing unit 500 can communicate via the output interface 550, etc.

[0125] For example, a detailed description of the processing procedure of the in-memory arithmetic method can be found in the relevant descriptions in the embodiments of the above-described in-memory arithmetic method, and repeated details will not be repeated here.

[0126] It should be noted that the in-memory computing device provided in the embodiments of this disclosure is exemplary and not restrictive. Depending on the actual application needs, the in-memory computing device may also include other conventional components or structures. For example, in order to realize the necessary functions of the in-memory computing device, those skilled in the art can set other conventional components or structures according to the specific application scenario. The embodiments of this disclosure do not limit this.

[0127] At least some embodiments of this disclosure also provide a memory, including a memory array comprising multiple memory cells and an in-memory computing device as described in any of the foregoing embodiments, the memory array comprising multiple rows and columns of memory cells. For example, the memory may be SRAM (Static Random Access Memory), etc.

[0128] At least some embodiments of this disclosure also provide a non-transitory storage medium. Figure 15 This is a schematic diagram of a non-transitory storage medium provided for some embodiments of this disclosure.

[0129] For example, such as Figure 15 As shown, the storage medium 600 non-transitory stores computer-executable instructions 610, which can execute in-memory arithmetic methods provided in any embodiment of this disclosure when executed by a computer (including a processor).

[0130] For example, one or more computer instructions may be stored on the storage medium 600. Some of the computer instructions stored on the storage medium 600 may be, for example, instructions for implementing one or more steps in the above-described in-memory operation method.

[0131] The storage medium can include, for example, a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read only memory (ROM), an erasable programmable read only memory (EPROM), a compact disk read only memory (CD-ROM), a flash memory, or any combination of the above storage media, and can also be other applicable storage medium. For example, the storage medium 600 can include the storage unit 510 in the aforementioned in-memory computing device 500.

[0132] The technical effects of the storage medium provided by the embodiments of the present disclosure can refer to the corresponding descriptions of the in-memory computing method in the above embodiments, which will not be repeated here.

[0133] For the present disclosure, the following points need to be explained:

[0134] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the usual design.

[0135] (2) In the case of no conflict, the features in the same and different embodiments of the present disclosure can be combined with each other.

[0136] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for in-memory operation, the memory comprising an array of a plurality of memory cells, the array comprising a plurality of rows and a plurality of columns, the method comprising: selecting a first memory cell storing a first value for the operation and a second memory cell storing a second value for the operation in the plurality of memory cells for a read operation, obtaining a superposition signal corresponding to the first value and the second value, obtaining an operation result of the operation using the superposition signal in the memory, wherein the obtaining the operation result of the operation using the superposition signal comprises: operating the superposition signal by an operation module to obtain the operation result, wherein the operation module comprises an NAND gate, and the operation comprises an XOR logical operation or an XNOR logical operation, and the method further comprising: outputting the superposition signal by a readout circuit, and locking the output state in the operation stage by setting the value of the superposition signal read out by the readout circuit to 0 or 1.

2. The operation method according to claim 1, wherein the array comprises a plurality of word lines, a plurality of first bit lines, and a plurality of second bit lines, each of the memory cells comprises a first readout port controlled by a corresponding word line, the first readout port being connected to a corresponding first bit line, the first bit line of the first memory cell and the first bit line of the second memory cell are the same first bit line, the obtaining the superposition signal corresponding to the first value and the second value comprises: obtaining a first superposition sub-signal corresponding to the first value and the second value by the same first bit line, wherein the first superposition sub-signal is used to obtain the superposition signal.

3. The operation method according to claim 2, wherein each of the memory cells further comprises a second readout port controlled by a corresponding word line, the second readout port being connected to a corresponding second bit line, the second bit line of the first memory cell and the second bit line of the second memory cell are the same second bit line, the obtaining the superposition signal corresponding to the first value and the second value comprises: obtaining a second superposition sub-signal corresponding to the first value and the second value by the same second bit line; combining the first superposition sub-signal and the second superposition sub-signal to obtain the superposition signal.

4. The operation method according to claim 3, wherein the first memory cell and the second memory cell are selected synchronously to obtain the superposition signal corresponding to the first value and the second value.

5. The operation method according to claim 3, wherein in the same operation cycle, the first memory cell and the second memory cell are selected, the superposition signal is obtained, and the operation result is obtained.

6. The operation method according to claim 3, wherein the first superposition signal output by the same first bit line and the second superposition signal output by the same second bit line are read out by a sense amplifier.

7. The operation method according to claim 6, wherein the superposition signal obtained by combining the first superposition signal and the second superposition signal is operated by the operation module to obtain the operation result.

8. The method of claim 3, the method further comprising: obtaining a first memory address of the first memory cell and a second memory address of the second memory cell, The first storage address and the second storage address are decoded to select a word line and a bit line corresponding to the first storage unit and a word line and a bit line corresponding to the second storage unit.

9. An in-memory operation apparatus, the memory comprising an array of a plurality of storage units, the array comprising a plurality of rows and a plurality of columns, the operation apparatus comprising a control module and an operation module, the control module and the operation module being coupled to the array respectively, the control module being configured to select a first storage unit storing a first value for the operation and a second storage unit storing a second value for the operation in the plurality of storage units for a read operation, the first storage unit and the second storage unit being configured to output a superposition signal corresponding to the first value and the second value, The operation module is configured to obtain an operation result of the operation using the superimposed signal in the memory, wherein the operation module comprising an XNOR gate, the operation comprising an XOR logical operation or an XNOR logical operation, and the operation apparatus further comprising a readout circuit configured to output the superposition signal and to lock the output state in the operation stage by setting the value read out by the readout circuit to 0 or 1.

10. The operation device according to claim 9, wherein the array comprising a plurality of word lines, a plurality of first bit lines, and a plurality of second bit lines, each of the storage units comprising a first readout port controlled by a corresponding word line, the first readout port being connected to a corresponding first bit line, the first bit line of the first storage unit and the first bit line of the second storage unit being a same first bit line, the first storage unit and the second storage unit being configured to output a first superposition sub-signal corresponding to the first value and the second value through the same first bit line, wherein the first superposition sub-signal is used to obtain the superposition signal.

11. The operation device according to claim 10, wherein each of the storage units further comprising a second readout port controlled by a corresponding word line, the second readout port being connected to a corresponding second bit line, the second bit line of the first storage unit and the second bit line of the second storage unit being a same second bit line, the first storage unit and the second storage unit being further configured to obtain a second superposition sub-signal corresponding to the first value and the second value through the same second bit line, and to combine the first superposition sub-signal and the second superposition sub-signal to obtain the superposition signal.

12. The operation device according to claim 11, wherein the control module being further configured to select the first storage unit and the second storage unit synchronously, and the operation module being configured to obtain the superposition signal corresponding to the first value and the second value.

13. The operation device according to claim 11, wherein the control module being further configured to select the first storage unit and the second storage unit, to obtain the superposition signal, and to lock the output state in the operation stage in a same operation cycle, and the operation module being further configured to obtain the operation result in the same operation cycle.

14. The operation apparatus of claim 11, further comprising a sense amplifier, wherein the sense amplifier being configured to read out the first superposition signal output by the same first bit line and the second superposition signal output by the same second bit line.

15. The arithmetic device according to claim 9, wherein the readout circuit being further configured to read out the first value and the second value.

16. The arithmetic device according to claim 11, wherein The control module is further configured to obtain a first storage address of the first storage unit and a second storage address of the second storage unit, The device further comprises an address decoding module configured to decode the first storage address and the second storage address, for selecting a word line and a bit line corresponding to the first storage unit, and selecting a word line and a bit line corresponding to the second storage unit.

17. A memory, comprising: The in-memory computing device according to any one of claims 9-16; and The array.

18. An in-memory computing device, comprising: a memory for non-transitorily storing computer executable instructions; and a processor for running the computer executable instructions, wherein the computer executable instructions, when executed by the processor, perform the in-memory computing method according to any one of claims 1-8.

19. A non-transitory storage medium non-transitorily storing computer- executable instructions, wherein, A computer program product, comprising a computer readable medium storing computer executable instructions, the computer executable instructions, when executed by a computer, perform the in-memory computing method according to any one of claims 1-8.

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