Information processing system

Abstract

The present invention provides an information processing system. It rapidly calculates the solution to an optimization problem. The information processing system according to the embodiment solves an optimization problem. In the information processing system, in a search process including an Ising machine and a host unit, the Ising machine alternately repeats, for each of a plurality of Ising spins, an auxiliary variable update process of updating an auxiliary variable by a main variable and a main variable update process of updating the main variable by the auxiliary variable a plurality of times. Before the search process, the host unit sends the initial value of the auxiliary variable corresponding to each of the plurality of Ising spins to the Ising machine.

Description

Technical Field

[0001] Embodiments of the present invention relate to an information processing system. Background Art

[0002] In most cases, the optimization of complex systems in various application fields such as finance, logistics, control, and chemistry is reduced to a mathematical combinatorial optimization problem. The combinatorial optimization problem is a problem of finding a combination of discrete values that minimizes a function of discrete variables called a cost function.

[0003] In recent years, a specific-purpose device called an Ising machine, which performs a search process for the ground state of an Ising model, has attracted attention. The problem of searching for the ground state of the Ising model is called the Ising problem. The Ising problem is a combinatorial optimization problem that minimizes a cost function provided by a quadratic function of binary variables (Ising spins). The cost function is called the Ising energy. A large number of practical combinatorial optimization problems can be transformed into the Ising problem. Therefore, a system for solving a combinatorial optimization problem can solve the target combinatorial optimization problem by using an Ising machine.

[0004] A system for solving a combinatorial optimization problem includes: an Ising machine that performs a search process for the ground state of an Ising model; and a host unit that performs processes other than the search process. In addition, the Ising problem is defined by a coupling coefficient group (J matrix) and an external magnetic field coefficient group (h vector).

[0005] In a system for solving such a combinatorial optimization problem, the host unit sends the J matrix and the h vector to the Ising machine and receives the values of the optimized Ising spins from the Ising machine. In addition, the Ising machine receives the J matrix and the h vector from the host unit and sends back the values of the optimized Ising spins in such a way that the Ising energy is minimized. A system for solving such a combinatorial optimization problem is required to efficiently send and receive information between the host unit and the Ising machine and shorten the time from the start of the computational process of the combinatorial optimization problem to the output of the solution. Summary of the Invention

[0006] The problem to be solved by the present invention is to calculate the solution of a combinatorial optimization problem at high speed.

[0007] The information processing system according to the embodiment solves a combinatorial optimization problem. The information processing system includes an Ising machine and a host unit. The Ising machine is hardware that executes a search process for searching for a ground state of an Ising model representing the combinatorial optimization problem. The host unit is hardware that is connected to the Ising machine via an interface and controls the Ising machine. In the search process, the Ising machine stores the main variables and auxiliary variables corresponding to each of the plurality of Ising spins included in the Ising model. For each of the plurality of Ising spins, the auxiliary variable update process of updating the auxiliary variable by the main variable and the main variable update process of updating the main variable by the auxiliary variable are alternately repeated multiple times. The value of the main variable corresponding to each of the plurality of Ising spins after alternately executing the main variable update process and the auxiliary variable update process multiple times is output as a search result. Before the search process, the host unit sends the initial value of the auxiliary variable corresponding to each of the plurality of Ising spins to the Ising machine. After the search process, the host unit receives the search result from the Ising machine and outputs the solution of the combinatorial optimization problem based on the received search result. According to the above information processing system, the solution of the combinatorial optimization problem can be calculated at high speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. is a diagram showing the functional configuration of the information processing system according to the first embodiment.

[0009] Figure 2 FIG. is a diagram showing a graph representing an Ising model.

[0010] Figure 3 FIG. is a diagram showing the variables stored in the Ising machine.

[0011] Figure 4 FIG. is a flowchart showing the flow of the search process using the Ising machine.

[0012] Figure 5 FIG. is a diagram showing the hardware configuration of the information processing system.

[0013] Figure 6 FIG. is a sequence diagram showing the flow of the processing of the information processing system.

[0014] Figure 7 FIG. is a diagram showing the hardware configuration of the information processing system according to the second embodiment.

[0015] Figure 8 FIG. is a flowchart of the first example of the second embodiment.

[0016] Figure 9 FIG. is a timing chart of the first example of the second embodiment.

[0017] Figure 10 It is a flowchart of the second example of the second embodiment.

[0018] Figure 11 It is a flowchart showing the process of preprocessing.

[0019] Figure 12 It is a timing chart of the second example of the second embodiment.

[0020] Figure 13 It is a diagram showing the functional structure of the information processing system related to the third embodiment.

[0021] Figure 14 It is a flowchart of the third embodiment.

[0022] Figure 15 It is a flowchart of the timer interrupt of the third embodiment.

[0023] Figure 16 It is a timing chart of the third embodiment.

[0024] Figure 17 It is a flowchart of the timer interrupt of the fourth embodiment.

[0025] Figure 18 It is a timing chart of the fourth embodiment.

[0026] Figure 19 It is a diagram showing the processing time in the case of non - reconstruction and the case of reconstruction.

[0027] Figure 20 It is a diagram showing coupling information including a coupling coefficient.

[0028] (Reference Signs)

[0029] 10: Information processing system; 12: Ising machine; 14: Host unit; 32: FPGA; 34: CPU; 36: Main storage device; 38: Circuit information storage device; 40: Input device; 42: Display device; 44: Bus; 51: First flag storage circuit; 52: Second flag storage circuit. Detailed Embodiments

[0030] (First Embodiment)

[0031] Figure 1 It is a diagram showing the functional structure of the information processing system 10 related to the first embodiment.

[0032] The information processing system 10 is a device for solving combinatorial optimization problems. The information processing system 10 related to the first embodiment includes an Ising machine 12 and a host unit 14.

[0033] The Ising machine 12 is hardware that performs a search process for searching for the ground state of an Ising model representing a combinatorial optimization problem. The Ising machine 12 is, for example, a reconfigurable semiconductor device such as an FPGA (Field Programmable Gate Array). In addition, in the first embodiment, the Ising machine 12 may not be a reconfigurable semiconductor device. In the first embodiment, the Ising machine 12 may be, for example, a non-reconfigurable semiconductor device or a processing circuit that executes information processing according to a program.

[0034] The host unit 14 is hardware that is connected to the Ising machine 12 via a physical interface and controls the Ising machine 12. The host unit 14 is a processing circuit that executes information processing according to a program. The host unit 14 executes processing other than the search processing executed by the Ising machine 12 in a series of processes for solving a combinatorial optimization problem.

[0035] When searching for the ground state of an Ising model representing a combinatorial optimization problem to be solved, the host unit 14 transmits, via the interface, the J matrix and h vector, which are definition information defining the Ising model, control parameters for controlling the search process executed by the Ising machine 12, and initial values of a plurality of auxiliary variables (p1, p2, p3,...) (described in detail later). In addition, the host unit 14 may further transmit, via the interface, the initial values of a plurality of main variables (x1, x2, x3,...) (described in detail later) to the Ising machine 12.

[0036] The Ising machine 12 executes a search process for searching for the ground state of the Ising model defined by the search J matrix and h vector. At the start of the search process, the Ising machine 12 substitutes the initial values received from the host unit 14 into each of the plurality of auxiliary variables (p1, p2, p3,...). Further, at the start of the search process, the Ising machine 12 substitutes, as initial values, predetermined values such as 0 into each of the plurality of main variables (x1, x2, x3,...). The Ising machine 12 may also generate values based on random numbers or the like in each of the plurality of main variables (x1, x2, x3,...) and substitute the generated values as initial values. In addition, when the Ising machine 12 receives the initial values of the plurality of main variables (x1, x2, x3,...) from the host unit 14, it substitutes the received values into each of the plurality of main variables (x1, x2, x3,...). Then, after substituting the initial values into each of the plurality of main variables (x1, x2, x3,...) and each of the plurality of auxiliary variables (p1, p2, p3,...), the Ising machine 12 starts the search.

[0037] The Ising machine 12 can calculate the values of a plurality of main variables (x1, x2, x3, …) that minimize the Ising energy in the Ising model by performing a search process. Then, the Ising machine 12 transmits, as a search result, the values of N Ising spins (s1, s2, s3, …) obtained by binarizing each of the values of the plurality of main variables (x1, x2, x3, …) after the search process to the host unit 14 via an interface. The Ising machine 12 may also transmit, as a search result, the values of the plurality of main variables (x1, x2, x3, …) after the search process to the host unit 14. Then, the host unit 14 outputs the values of the plurality of Ising spins (s1, s2, s3, …) as a solution to the combinatorial optimization problem.

[0038] Figure 2 FIG. is a diagram showing a graph representing an Ising model. The energy (E(s)) of the Ising model including N Ising spins is represented by the following equation (1).

[0039]

Equation 1

[0040]

[0041] N is the number of Ising spins included in the Ising model and is an integer of 3 or more. i and j represent indices of Ising spins and are integers of 1 or more and N or less. s i represents the i-th Ising spin. s j represents the j-th Ising spin. s i and s j represent either -1 or +1. In addition, there is a case where the N Ising spins are collectively referred to as an s vector (s1, s2, …, s N ). The s vector represents the configuration of -1 or +1 in the N Ising spins.

[0042] J ij is the element in the i-th row and j-th column of the J matrix. The J matrix is a square matrix of N rows and N columns with the same elements in the symmetric components (J ij = J ji ). The Ising model defines a coupling coefficient for each group of all two Ising spins included in the N Ising spins. J ij represents the coupling coefficient representing the interaction between the i-th Ising spin and the j-th Ising spin.

[0043] h i is the i-th element in the h vector. The Ising model defines an external magnetic field coefficient representing an external magnetic field that individually affects each of the N Ising spins. h i represents the external magnetic field coefficient that affects the i-th Ising spin.

[0044] The N - dimensional Ising problem refers to the problem of calculating the spin configuration that minimizes the Ising energy for an Ising model consisting of N Ising spins. The spin configuration (S vector) that minimizes the energy is called the ground state.

[0045] In Figure 2 , a diagram showing an Ising model for the case of N = 6 is presented. The vertices of the diagram correspond to the Ising spins. The edges of the diagram correspond to the coupling coefficient J ij between the Ising spins. The external magnetic field coefficient h i is assigned to the vertices of the diagram.

[0046] A general combinatorial optimization problem is represented as an Ising problem defined by a J matrix and an h vector. The Ising machine 12 accepts the J matrix and the h vector as the problem to be solved, searches internally for a spin configuration with a lower Ising energy, and outputs this optimized spin configuration as the solution.

[0047] The spin configuration with the minimum Ising energy corresponds to the exact solution. The spin configuration with an Ising energy close to the minimum corresponds to an approximate solution. Generally, the performance of the Ising machine 12 is represented by the time until the solution is output and the accuracy of the solution (the accuracy of the solution is high at lower energies). The Ising machine 12 can also output not only the exact solution but also an approximate solution as the solution. In addition, the search process for searching the ground state using the Ising machine 12 includes not only the process of searching for the exact solution but also the process of searching for an approximate solution.

[0048] In addition, the Ising machine 12 that can solve the N - dimensional Ising problem can also solve an Ising problem smaller than the N - dimension. For example, the Ising machine 12 can search for an Ising problem smaller than the N - dimension as an N - dimensional Ising problem by setting the coupling coefficients and external magnetic field coefficients of the elements where there are no Ising spins in the J matrix and the h matrix to 0.

[0049] As a solution method for the Ising problem, the simulated annealing (SA) method has been known in the past. A device that performs the search process for the ground state of the Ising model according to the SA method is also called an SA - based Ising machine.

[0050] In addition, as a solution method for solving the Ising problem, the simulated bifurcation (SB) method is known. In addition, the Ising machine 12 performs the search process for the ground state of the Ising model by the simulated bifurcation method. For example, in Non - Patent Document 1 and Patent Documents 2 - 7, etc., the simulated bifurcation method is proposed. The simulated bifurcation method is an algorithm that transforms the equation of motion in the optimization algorithm based on adiabatic change in classical mechanics into a form suitable for high - speed simulation. The Ising machine 12 uses such a simulated bifurcation method to perform the search process for the ground state of the Ising model.

[0051] In the simulated bifurcation method, two main variables (xi ) and auxiliary variables (p i ). The N particles correspond to N Ising spins. In the simulation branching method, the main variable (x i ) represents the position of the i-th particle among the N particles (i = 1, 2, …, N). In the simulation branching method, the auxiliary variable (p i ) represents the momentum of the i-th particle. Each of the N main variables (x i ) and each of the N auxiliary variables (p i ) are continuous variables represented by real numbers.

[0052] Then, in the simulation branching method, for each of the N virtual particles, the following simultaneous ordinary differential equations of Equation (2) and Equation (3) are numerically solved.

[0053]

Equation 2

[0054]

[0055]

[0056] Here, H is the Hamiltonian of the following Equation (4).

[0057]

Equation 3

[0058]

[0059] c is a predetermined coefficient. D is a predetermined coefficient corresponding to detuning. K is a coefficient corresponding to the positive Kerr coefficient. t is a variable representing time. p(t) corresponds to the pumping amplitude and is a function that monotonically increases in value according to the number of update times during the calculation of the simulation branching method. The initial value of p(t) can also be set to 0. α(t) is a function that monotonically increases together with p(t).

[0060] Here, when using the symplectic Euler method, the differential equations provided by Equation (2) and (3) can be solved. As shown in the following Equation (5) and Equation (6), when using the symplectic Euler method, the differential equations are rewritten as discrete recurrence formulas.

[0061]

Equation 4

[0062] x i = x i + Dp i Δt …(5)

[0063]

[0064] Δt is the time step (unit time, time increment).

[0065] Therefore, while successively increasing t by Δt, the Ising machine 12 alternately executes the operations of Expression (5) and Expression (6) until t reaches a predetermined end time (T). Then, the Ising machine 12 outputs, as search results, the values of the N Ising spins (s i ) obtained by binarizing each of the finally obtained N main variables (x i ), or the values of the N main variables (x i ).

[0066] In addition, as long as the Ising machine 12 uses an algorithm of the analog branching method, it can also execute algorithms other than Expression (3) and Expression (4). For example, the Ising machine 12 can also execute an algorithm of an expression obtained by transforming Expression (3) and Expression (4). Additionally, for example, the Ising machine 12 can also execute an algorithm for performing predetermined control processing in addition to the operations of Expression (3) and Expression (4) or the operations of an expression obtained by transforming Expression (3) and Expression (4).

[0067] When the Ising machine 12 changes the executed algorithm, there are cases where performance indicators such as the convergence speed and the solution accuracy change. Therefore, the algorithm applied to the Ising machine 12 can also vary depending on the Ising problem to be solved and the purpose (emphasis on convergence speed, emphasis on accuracy, etc.). The Ising machine 12 can also execute a search process using an algorithm selected by the user from among a plurality of pre-set algorithms. For example, in the case where the Ising machine 12 is a semiconductor device capable of being reconfigured, the host unit 14 reconstructs the semiconductor device based on circuit information indicating a circuit for executing the algorithm selected by the user. Thereby, the Ising machine 12 can perform a search process for the ground state of the Ising model through a suitable circuit according to the Ising problem to be solved and the purpose.

[0068] Figure 3 is a diagram showing the variables stored in the Ising machine 12. The Ising machine 12 executes an algorithm using the analog branching method through a hardware circuit. When performing a search process for the ground state of an Ising model including N Ising spins, the Ising machine 12 stores N main variables (x i ) and N auxiliary variables (p i ) in an internal memory or register.

[0069] In this way, the Ising machine 12 stores 2×N variables internally. Therefore, the structure of the Ising machine 12 is different from that of the SA-based Ising machine that stores N variables. In addition, the main variables (x i ) are transformed into Ising spins (s i ) through binarization processing. In contrast, the auxiliary variables (p i ) cannot be used to transform into Ising spins (si ) transformation

[0070] In addition, each of the N main variables (x i ) and each of the N auxiliary variables (p i ) are initialized at the start of the search process. Even for the problem where the J matrix and h vector are the same in the Ising machine 12, there are cases where different solutions (approximate) are output when the initial values of the auxiliary variables (p i ) are different. Therefore, by changing the initial values of the auxiliary variables (p i ) and performing the search process for the problem with the same J matrix and h vector, the Ising machine 12 can obtain a solution with higher accuracy.

[0071] Figure 4 is a flowchart showing the flow of the search process using the Ising machine 12. The Ising machine 12 performs the search process according to the Figure 4 shown flow.

[0072] First, in S111, the Ising machine 12 performs setting processing. Specifically, the Ising machine 12 sets, for example, the coefficients of K and D, functions such as p(t) and α(t), and the number of repetitions. Further, the Ising machine 12 sets the J matrix and h vector according to the definition information received from the host unit 14.

[0073] Next, in S112, the Ising machine 12 initializes the values of each of the N main variables (x1 to x N ) and the values of each of the N auxiliary variables (p1 to p N ). For example, the Ising machine 12 sets the values of each of the N main variables (x1 to x N ) to 0, a predetermined value, or a value determined by a random number within a predetermined range. In addition, when the Ising machine 12 receives the initial values of each of the N main variables (x1 to x N ) from the host unit 14, it sets the values of each of the N main variables (x1 to x N ) to the initial values received from the host unit 14. Further, the Ising machine 12 sets the values of each of the N auxiliary variables (p1 to p N ) to the initial values received from the host unit 14.

[0074] Next, the Ising machine 12 repeats the loop process from S113 to S120 for the set number of times.

[0075] In S114 to S116 within the loop, while incrementing i from i = 1 to i = N by 1 successively, the Ising machine 12 performs auxiliary variable update processing (S114, S115, S116). In the auxiliary variable update processing (S115) for updating the i-th auxiliary variable, the Ising machine 12 updates the i-th auxiliary variable (p N ) through N main variables (x1 to x i ), N coupling coefficients (J 1～i-1 , x i+1～N ) representing the interaction between the i-th main variable (x i，j ) and the other (N - 1) main variables (x j ), and the i-th external magnetic field coefficient (h i ).

[0076] Specifically, the Ising machine 12 calculates the i-th auxiliary variable (p i ) by computing the above formula (6).

[0077] In addition, the Ising machine 12 can also execute the processing of S115 in parallel. Thus, the Ising machine 12 can calculate N auxiliary variables (p1 to p N ) at high speed.

[0078] Next, in S117 to S119, while incrementing i from i = 1 to i = N by 1 successively, the Ising machine 12 performs main variable update processing (S117, S118, S119). In the main variable update processing (S118) for updating the i-th main variable, the Ising machine 12 updates the i-th main variable (x i ) through the i-th auxiliary variable (p i ).

[0079] Specifically, the Ising machine 12 calculates the i-th main variable (x i ) by computing the above formula (5).

[0080] In addition, the Ising machine 12 can also execute the processing of S118 in parallel. Thus, the Ising machine 12 can calculate N main variables (x1 to x N ) at high speed.

[0081] Then, when the Ising machine 12 executes the loop processing between S113 and S120 a set number of times, the processing proceeds to S121. In addition, the Ising machine 12 can also execute the processing of S117 to S119 first and then the processing of S114 to S116 within the loop processing from S113 to S120.

[0082] In S121, the Ising machine 12 outputs the search result to the host unit 14. For example, the Ising machine 12 outputs the values of N main variables (x1 to x NThe N Ising spins (s1 to s N ) obtained by binarizing each main variable of N ), or N main variables (x1 to x

[0083] ), are output to the host unit 14. Then, after finishing the processing of S121, the Ising machine 12 ends the search processing. N As described above, for each Ising spin of the N Ising spins (s1 to s

[0084] Figure 5 ), the Ising machine 12 alternately repeats the auxiliary variable update process (S115) of updating the auxiliary variable by the main variable and the main variable update process (S118) of updating the main variable by the auxiliary variable multiple times. Furthermore, the Ising machine 12 outputs the value of the main variable after alternately executing the auxiliary variable update process (S115) and the main variable update process (S118) multiple times as the search result. Thus, the Ising machine 12 can execute an algorithm using the simulated branch method and perform the search process for the ground state of the Ising model.

[0085] The FPGA 32 receives circuit information from the CPU 34 via the bus 44 and is configured as a predetermined circuit according to the received circuit information. Thus, the FPGA 32 functions as the Ising machine 12.

[0086] The FPGA 32 receives definition information and control parameters from the CPU 34 via the bus 44 and executes the search process according to the received definition information and control parameters. The definition information is information that defines the Ising model. Specifically, it is the J matrix and the h vector. The control parameters are information for controlling the search process. For example, the control parameters are coefficients (c, D, K), functions (α(t), p(t)), unit time (Δt), and the number of repetitions of the loop process, etc.

[0087] In addition, before the search process, the FPGA 32 receives from the CPU 34 via the bus 44 the initial values stored in the main storage device 36 of each of the N auxiliary variables (p i ) corresponding to the multiple Ising spins included in the Ising model. Furthermore, before the search process, the FPGA 32 may also receive from the CPU 34 via the bus 44 the initial values stored in the main storage device 36 of each of the N main variables (x i ) corresponding to the multiple Ising spins.

[0088] ​Then, after the search process is completed by FPGA 32, the search result is output to the host unit 14 via the bus 44. Specifically, in FPGA 32, as the search result, the Ising spins (s i ) obtained by binarizing each of the main variables corresponding to each of the multiple Ising spins (x i ), or the values of each of the multiple main variables (x i ) are output to the host unit 14.

[0089] CPU 34 operates according to the program stored in the main storage device 36. Thus, CPU 34 and the main storage device 36 function as the host unit 14.

[0090] CPU 34 executes preprocessing, parameter transmission processing, result reception processing, and main processing. In the preprocessing, CPU 34 generates definition information and control parameters. In addition, in the preprocessing, CPU 34 generates the initial values of each of the multiple auxiliary variables (p i ). CPU 34 may also generate the initial values of each of the multiple main variables (x i ) in the preprocessing.

[0091] In the parameter transmission processing, CPU 34 transmits the definition information, control parameters, and the initial values of each of the multiple auxiliary variables (p i ) to FPGA 32 via the bus 44. CPU 34 may further transmit the initial values of each of the multiple main variables (x i ) to FPGA 32 via the bus 44 in the parameter transmission processing.

[0092] In the result reception processing, CPU 34 receives the search result from FPGA 32 via the bus 44, and outputs the solution of the combinatorial optimization problem based on the received search result. In addition, CPU 34 executes the processing other than the preprocessing, parameter transmission processing, and result reception processing as the main processing.

[0093] The main storage device 36 is a RAM (Random Access Memory). The main storage device 36 is used as a work area for data processing by CPU 34.

[0094] The circuit information storage device 38 is a non-volatile storage device. The circuit information storage device 38 stores the circuit information for configuring FPGA 32 into a circuit for searching the ground state of the Ising model.

[0095] The circuit information storage device 38 can also store a plurality of circuit information. Each circuit information of the plurality of circuit information can also be, for example, information of a circuit having different maximum sizes of the Ising model that can be solved. In addition, each circuit information of the plurality of circuit information can also be, for example, information of a circuit that performs search processing with different execution algorithms. The CPU 34 selects the circuit information specified by the user from the plurality of circuit information, and reconfigures the FPGA 32 with the selected circuit information.

[0096] The input device 40 is a device for inputting instructions and the like from the user. The input device 40 is, for example, a mouse and a keyboard. The input device 40 receives a start instruction for processing from the user. The CPU 34 starts the calculation process of combining the solutions of the optimization problem when the input device 40 receives the start instruction input by the user.

[0097] The display device 42 is a device for displaying information to the user. The display device 42 displays the solution of the combinatorial optimization problem.

[0098] The bus 44 connects the FPGA 32, the CPU 34, the main storage device 36, the circuit information storage device 38, the input device 40, and the display device 42, and performs data transmission and reception. The bus 44 functions as an interface between the Ising machine 12 and the host unit 14.

[0099] Figure 6 is a sequence diagram showing the processing flow of the information processing system 10. When the information processing system 10 calculates the solution of the Ising model including N Ising spins in the FPGA 32, the processing is executed according to the Figure 6 shown flow.

[0100] First, in S11, the CPU 34 executes the main process. Next, in S12, the CPU 34 executes the preprocess. Specifically, in the preprocess, the CPU 34 generates definition information (J, h), control parameters, and initial values of N auxiliary variables (p1 to p N ) corresponding to the Ising machine 12 configured in the FPGA 32. Furthermore, the CPU 34 can also generate initial values of N main variables (x1 to x N ).

[0101] Next, in S13, the CPU 34 sends the definition information (J, h), control parameters, and initial values of N auxiliary variables (p1 to p N ) to the FPGA 32 via the bus 44. Furthermore, the CPU 34 can also send the initial values of N main variables (x1 to x N ) to the FPGA 32 via the bus 44.

[0102] Next, in S14, the FPGA 32 performs a search process. Specifically, for each of the N Ising spins of the FPGA 32, the FPGA 32 alternately repeats the auxiliary variable update process of updating the auxiliary variable (p i ) by the main variable (x i ), and the main variable update process of updating the main variable (x i ) by the auxiliary variable (p i ) multiple times. Specifically, the FPGA 32 executes the process shown in Figure 4 .

[0103] In addition, at the start of the search process, the FPGA 32 sets the initial values received from the CPU 34 in each of the N auxiliary variables (p i ). Further, at the start of the search process, the FPGA 32 sets a predetermined value such as 0 as the initial value in each of the N main variables (x i ). Alternatively, the FPGA 32 may generate a value corresponding to a random number or the like internally as the initial value in each of the N main variables (x i ) and set the generated value. In addition, when the FPGA 32 receives the initial values of the N main variables (x i ) from the CPU 34, the FPGA 32 sets the initial values received from the CPU 34 in each of the N main variables (x i ).

[0104] Next, in S14, the FPGA 32 sends the search result to the CPU 34. Specifically, the FPGA 32 sends the N Ising spins (s1 to s N ) obtained by binarizing each of the N main variables (x1 to x N ), or the N main variables (x1 to x N ) to the CPU 34 via the bus 44. Next, in S15, the CPU 34 receives the search result from the FPGA 32 via the bus 44.

[0105] As described above, the information processing system 10 according to the present embodiment sends, from the host unit 14 (CPU 34 and main storage device 36) to the Ising machine 12 (FPGA 32) via the interface (bus 44), in addition to the definition information (J, h) and control parameters defining the Ising model, the initial values of the respective multiple auxiliary variables (p i ). Even if the value of the main variable (x i ) of the Ising machine 12 (FPGA 32) is a fixed value, in the auxiliary variable (p iEven when the initial values of () are different, different approximate solutions can be output. That is, even if the host unit 14 (CPU 34) does not send the main variable (x i ) to the Ising machine 12 (FPGA 32), as long as the initial value of the auxiliary variable (p i ) is changed, the Ising machine 12 (FPGA 32) can be made to execute an appropriate search process. Therefore, the information processing system 10 according to the present embodiment can also omit the generation and transmission processes of the main variable (x i ), and can shorten the processing time and communication time. Thus, according to the information processing system 10 according to the present embodiment, the solution of the combinatorial optimization problem can be calculated at high speed.

[0106] (Second Embodiment)

[0107] Next, the information processing system 10 according to the second embodiment will be described. The structure of the information processing system 10 according to the second embodiment is substantially the same as that of the first embodiment. Therefore, in the description of the information processing system 10 according to the second embodiment, the same reference numerals are assigned to the components that are substantially the same as those in the first embodiment, and the detailed description thereof is omitted.

[0108] The information processing system 10 according to the second embodiment sequentially solves one of a plurality of combinatorial optimization problems one by one.

[0109] Figure 7 FIG. is a diagram showing the hardware structure of the information processing system 10 according to the second embodiment. The CPU 34 according to the second embodiment includes a first flag storage circuit 51. The first flag storage circuit 51 stores a first flag indicating whether the search process using the FPGA 32 has ended. The first flag storage circuit 51 is, for example, a flag register provided in the CPU 34. The first flag storage circuit 51 may also be provided outside the CPU 34 (for example, the main storage device 36).

[0110] The first flag storage circuit 51 can be written to and read from by the CPU 34 with the first flag. At the same time, in the first flag storage circuit 51, the first flag is set according to the operation status of the FPGA 32. For example, when the first flag is 0, it indicates that the search process using the FPGA 32 has not ended, and when it is 1, it indicates that the search process using the FPGA 32 has ended.

[0111] In addition, in the second embodiment, the CPU 34 can also execute the search process instead of the FPGA 32. In this case, the CPU 34 executes the search process by executing a predetermined search program.

[0112] Figure 8This is a flowchart showing the processing flow of the CPU 34 related to the first example of the second embodiment. In the first example, in the information processing system 10, the CPU 34 executes the search process instead of the FPGA 32. In the first example, the CPU 34 executes the process according to Figure 8 the flow shown.

[0113] In the first example, the CPU 34 executes the loop process between S21 and S24 L times. L represents the number of combinatorial optimization problems to be solved, which is a predetermined integer of 2 or more. In each loop process, the CPU 34 executes the main process (S22) and the search process (S23). In addition, the main process (S22) is the same as the process of Figure 6 S11 shown. Also, the search process (S23) is the same as the process of Figure 6 S14 shown. Then, when the CPU 34 executes the loop process L times, this process ends (S24).

[0114] Figure 9 This is a timing chart of the process executed by the information processing system 10 related to the first example of the second embodiment. m represents the index of the combinatorial optimization problem to be solved, which is an integer from 1 to L. The information processing system 10 sequentially solves the combinatorial optimization problems from the combinatorial optimization problem of m = 1 to the combinatorial optimization problem of m = L while incrementing m by 1 successively.

[0115] As Figure 9 shown, in the first example, the CPU 34 alternately repeats the main process and the search process. Thus, the information processing system 10 related to the first example of the second embodiment can sequentially solve multiple combinatorial optimization problems.

[0116] Figure 10 This is a flowchart showing the processing flow of the CPU 34 related to the second example of the second embodiment. In the second example, in the information processing system 10, the FPGA 32 executes the search process, and the CPU 34 executes the processes other than the search process. In the second example, the CPU 34 executes the process according to Figure 10 the flow shown.

[0117] In the second example, the CPU 34 executes the loop process between S31 and S41 L times. The CPU 34 executes the processes of S32 to S40 in each loop process.

[0118] In S32, the CPU 34 executes the main process. The main process (S32) is the same as the process of Figure 6 S11 shown. Next, in S33, the CPU 34 executes the preprocessing. Regarding the preprocessing of S33, refer to Figure 11 described later.

[0119] Next, in S34, the CPU 34 determines whether to perform reconfiguration of the FPGA 32. For example, the CPU 34 determines whether the circuit currently configured in the FPGA 32 corresponds to the Ising model representing the combinatorial optimization problem to be solved thereafter. Then, the CPU 34 determines that in the case of correspondence, reconfiguration is not performed, and in the case of non-correspondence, reconfiguration is performed. In the case where reconfiguration is not performed (the "No" of S34), the CPU 34 advances the process to S36. In the case where reconfiguration is performed (the "Yes" of S34), the CPU 34 advances the process to S35. In S35, the CPU 34 provides the circuit information corresponding to the Ising model representing the combinatorial optimization problem to be solved thereafter to the FPGA 32 to cause the FPGA 32 to perform reconfiguration.

[0120] Next, in S36, the CPU 34 sends the parameters generated in the preprocessing (S33) to the FPGA 32. Specifically, the CPU 34 sends the definition information (J, h), the control parameters, and the initial values of the N auxiliary variables (p1 to p N ) to the FPGA 32 via the bus 44. Furthermore, the CPU 34 may also send the initial values of the N main variables (x1 to x N ) to the FPGA 32 via the bus 44.

[0121] Next, in S37, the CPU 34 instructs the FPGA 32 to start the search process. In addition, before starting the search process, the FPGA 32 sets the first flag (bs_flag) to 0 as a value indicating that the search process has not ended. Also, when the search process ends, the FPGA 32 sets the first flag (bs_flag) to 1 as a value indicating that the search process has ended.

[0122] Next, in S38, the CPU 34 confirms whether the search process using the FPGA 32 has ended. Specifically, the CPU 34 acquires the first flag (bs_flag).

[0123] Next, in S39, the CPU 34 determines whether the search process has ended. In the case where the search process has ended, that is, when bs_flag == 1 (the "Yes" of S39), the process advances to S40. In the case where the search process has not ended, that is, when it is not bs_flag == 1 (the "No" of S39), the process returns to S38 and the processes of S38 and S39 are repeated. That is, from the start of instructing the search process to the end of the search process, the CPU 34 performs polling as a process of repeatedly confirming the first flag (bs_flag) in order to confirm the end of the search process.

[0124] In S40, the CPU 34 receives the search result from the FPGA 32. Then, the CPU 34 ends this process (S41) when the loop process is executed L times.

[0125] Figure 11 It is a flowchart showing the process of the preprocessing (S33). In the preprocessing (S32), the CPU 34 executes the processes of S51 to S54.

[0126] In S51, the CPU 34 generates the initial values of N auxiliary variables (p1 to p N ) respectively. In addition, the CPU 34 may also generate the initial values of N main variables (x i ) respectively.

[0127] Next, in S52, the CPU 34 generates the J matrix. Next, in S53, the CPU 34 generates the h vector. Next, in S54, the CPU 34 generates control parameters including coefficients (c, D, K), functions (α(t), p(t)), unit time (Δt), and the number of repetitions, etc. After the CPU 34 ends the process of S54, it returns the process to Figure 10 the process.

[0128] Figure 12 It is a timing chart of the process executed by the information processing system 10 according to the second example of the second embodiment. As Figure 12 shown, in the second example of the second embodiment, after the CPU 34 performs the main process, the preprocessing, and the parameter sending process, the FPGA 32 performs the search process. During the search process of the FPGA 32, the CPU 34 confirms whether the search process has ended by polling. After the search process ends, it performs the result receiving process. Then, after the result receiving process, the CPU 34 starts the main process of the next problem. In this way, in the information processing system 10 according to the second example of the second embodiment, the CPU 34 and the FPGA 32 execute the processes at exclusive timings. Thus, the information processing system 10 according to the second example of the second embodiment can sequentially solve multiple combinatorial optimization problems.

[0129] Here, the FPGA 32 can be configured to operate N main variables (x1 to x N ) and N auxiliary variables (p1 to p N)'s circuit. Therefore, the FPGA 32 can perform large-scale parallel operations. In contrast, generally, since the CPU 34 has limitations in the number of cores and the number of threads, it cannot perform large-scale parallel operation processing. Therefore, the information processing system 10 according to the second example adds preprocessing, parameter transmission processing, and result reception processing compared to the information processing system 10 according to the first example, but can significantly shorten the search processing. Therefore, the information processing system 10 according to the second example can increase the throughput as a whole.

[0130] (The third embodiment)

[0131] Next, the information processing system 10 according to the third embodiment will be described. The structure of the information processing system 10 according to the third embodiment is substantially the same as that of the second embodiment. Therefore, in the description of the information processing system 10 according to the third embodiment, the same reference numerals are attached to the constituent elements that are substantially the same as those of the second embodiment, and the detailed description is omitted.

[0132] The information processing system 10 according to the third embodiment sequentially solves one of a plurality of combinatorial optimization problems one by one, and executes the main processing using the CPU 34 and the search processing using the FPGA 32 in parallel.

[0133] Figure 13 FIG. is a diagram showing the functional structure of the information processing system 10 according to the third embodiment. The CPU 34 according to the third embodiment compared to Figure 7 The structure of the second embodiment shown further includes a second flag storage circuit 52. The second flag storage circuit 52 stores a second flag indicating whether the CPU 34 has received a search result from the FPGA 32. The second flag storage circuit 52 is, for example, a flag register built into the CPU 34. The second flag storage circuit 52 may also be provided outside the CPU 34 (for example, the main storage device 36).

[0134] Regarding the second flag storage circuit 52, the CPU 34 can perform writing and reading. For example, when the second flag is 0, it indicates that the CPU 34 has not received a search result, and when it is 1, it indicates that the CPU 34 has received a search result.

[0135] Figure 14 FIG. is a flowchart showing the processing flow of the CPU 34 according to the third embodiment. The CPU 34 according to the third embodiment executes processing according to the Figure 14 flow shown.

[0136] First, in S61, the CPU 34 sets the first flag (bs_flag) to 0, which represents that the search process has not ended. Further, the CPU 34 sets the second flag (rcv_flag) to 1, which represents that the search result has been received.

[0137] Next, the CPU 34 executes the loop process between S62 and S75 L times. In each loop process, the CPU 34 executes the processes of S63 to S74.

[0138] In S63, the CPU 34 enables the interruption of the timer. The timer generates a timer flag every predetermined time. When the interruption of the timer is enabled, the CPU 34 executes the process described below Figure 15 shown every time the timer flag occurs.

[0139] Next, in S64, the CPU 34 executes the main process. The main process (S64) is the same as the process of Figure 10 shown in S32.

[0140] Next, in S65, the CPU 34 executes the preprocess. The preprocess (S65) is the same as the process of Figure 10 shown in S33.

[0141] Next, in S66, the CPU 34 disables the interruption of the timer enabled in S63. Thereafter, until the interruption of the next timer is enabled, even if the timer flag occurs, the CPU 34 does not execute the process Figure 15 shown.

[0142] Next, in S67, the CPU 34 determines whether the second flag (rcv_flag) represents that the search result has not been received. When the second flag (rcv_flag) represents that the search result has been received, that is, when it is not the case that rcv_flag == 0 (the "No" in S67), the CPU 34 advances the process to S71. When the second flag (rcv_flag) represents that the search result has not been received, that is, when rcv_flag == 0 (the "Yes" in S67), the CPU 34 advances the process to S68.

[0143] Next, in S68, the CPU 34 confirms whether the search process using the FPGA 32 has ended. Specifically, the CPU 34 obtains the first flag (bs_flag).

[0144] Next, in S69, the CPU 34 determines whether the search process has ended. When the search process has ended, that is, when bs_flag == 1 (Yes in S69), the process proceeds to S70. When the search process has not ended, that is, when it is not the case that bs_flag == 1 (No in S69), the process returns to S68, and the processes of S68 and S69 are repeated. That is, the CPU 34 polls from the start of the instructed search process until the search process ends to confirm the end of the search process.

[0145] In S70, the CPU 34 receives the search result from the FPGA 32. Further, when the reception of the search result is completed, the CPU 34 sets the second flag (rcv_flag) to 1, which is a value indicating that the search result has been received.

[0146] Next, in S71, the CPU 34 determines whether to perform reconfiguration of the FPGA 32. When reconfiguration is not performed (No in S71), the CPU 34 causes the process to proceed to S73. When reconfiguration is performed (Yes in S71), the CPU 34 causes the process to proceed to S72. In S72, the CPU 34 provides circuit information corresponding to the Ising model representing the combinatorial optimization problem to be solved thereafter to the FPGA 32 to reconfigure the FPGA 32.

[0147] Next, in S73, the CPU 34 sends the parameters generated in the preprocessing (S65) to the FPGA 32. The parameter sending process (S73) is the same as the process of S36 Figure 10 shown.

[0148] Next, in S74, the CPU 34 instructs the start of the search process for the FPGA 32. Further, the CPU 34 sets the second flag (rcv_flag) to 0, which is a value indicating that the search result has not been received. Then, when the CPU 34 executes the loop process L times, this process ends (S75).

[0149] Figure 15 It is a flowchart showing the process when a timer interrupt occurs in the CPU 34 according to the third embodiment. When a timer interrupt occurs in the CPU 34 according to the third embodiment in a state where timer interrupts are permitted, the process is executed according to the Figure 15 flow shown.

[0150] First, in S81, the CPU 34 determines whether the second flag (rcv_flag) indicates that no search result has been received. In the case where the second flag (rcv_flag) indicates that a search result has been received, that is, when rcv_flag != 0 (the "No" in S81), the CPU 34 ends the timer interrupt process. In the case where the second flag (rcv_flag) indicates that no search result has been received, that is, when rcv_flag == 0 (the "Yes" in S81), the CPU 34 proceeds to S82.

[0151] In S82, the CPU 34 confirms whether the search process using the FPGA 32 has ended. Specifically, the CPU 34 obtains the first flag (bs_flag).

[0152] Next, in S83, the CPU 34 determines whether the search process has ended. In the case where the search process has ended, that is, when bs_flag == 1 (the "Yes" in S83), the process proceeds to S84. In the case where the search process has not ended, that is, when bs_flag != 1 (the "No" in S83), the CPU 34 ends the timer interrupt process.

[0153] In S84, the CPU 34 receives the search result from the FPGA 32. Furthermore, when the reception of the search result is completed, the CPU 34 sets the second flag (rcv_flag) to 1, which is a value indicating that a search result has been received. Then, after the processing in S84 is completed, the CPU 34 ends the timer interrupt process.

[0154] Figure 16 This is a timing diagram of the processing executed by the information processing system 10 according to the third embodiment. In the information processing system 10 according to the third embodiment, in the search process using the FPGA 32, the CPU 34 executes the main process in the combinatorial optimization problem to be solved next. For example, in the information processing system 10, when the second search process (m = 2) for searching the ground state of the second Ising model is executed after the first search process (m = 1) for searching the ground state of the first Ising model, the CPU 34 and the FPGA 32 perform processing as follows.

[0155] First, the CPU 34 executes the first main process for generating the information used in the execution of the first search process (m = 1), and then executes the preprocessing and parameter sending process for the first search process (m = 1). Next, after the CPU 34 executes the first main process, the FPGA 32 executes the first search process (m = 1).

[0156] Next, while the FPGA 32 is performing the first search process (m = 1), the CPU 34 performs a second main process for generating information used in the execution of the second search process (m = 2). When the first search process (m = 1) of the FPGA 32 ends during the execution of the second main process by the CPU 34, the CPU 34 temporarily interrupts the second main process and performs a result reception process for receiving the search result of the first search process (m = 1). Then, after the CPU 34 executes the second main process, the FPGA 32 performs the second search process (m = 2).

[0157] In this way, the information processing system 10 according to the third embodiment causes the CPU 34 and the FPGA 32 to operate in parallel. As a result, the information processing system 10 according to the third embodiment can shorten the overall processing time and increase the throughput as a whole.

[0158] (Fourth Embodiment)

[0159] Next, the information processing system 10 according to the fourth embodiment will be described. The structure of the information processing system 10 according to the fourth embodiment is the same as the structure of the information processing system 10 according to the third embodiment shown Figure 13 herein. In addition, the processing of the information processing system 10 according to the fourth embodiment is different from the processing of the information processing system 10 according to the third embodiment in the case of timer interrupt, and the other processing is the same. Therefore, in the description of the information processing system 10 according to the fourth embodiment, the same reference numerals are attached to the components that are substantially the same as those in the third embodiment, and the detailed description is omitted.

[0160] The information processing system 10 according to the fourth embodiment sequentially solves one by one a plurality of combinatorial optimization problems, and executes the main process using the CPU 34 and the search process using the FPGA 32 in parallel. Furthermore, in the main process of the CPU 34, the information processing system 10 according to the fourth embodiment executes the search process multiple times if possible.

[0161] Figure 17 is a flowchart showing the process flow in the case of timer interrupt in the CPU 34 according to the fourth embodiment. When the CPU 34 according to the fourth embodiment has a timer interrupt in the state where timer interrupt is permitted, it executes the process according to the Figure 17 flow shown herein.

[0162] First, in S91, the CPU 34 determines whether the second flag (rcv_flag) indicates that no search result has been received. In the case where the second flag (rcv_flag) indicates that a search result has been received, that is, when it is not the case that rcv_flag == 0 (the "No" in S91), the CPU 34 ends the process of the timer interrupt. In the case where the second flag (rcv_flag) indicates that no search result has been received, that is, when rcv_flag == 0 (the "Yes" in S91), the CPU 34 advances the process to S92.

[0163] In S92, the CPU 34 confirms whether the search process using the FPGA 32 has ended. Specifically, the CPU 34 acquires the first flag (bs_flag).

[0164] Next, in S93, the CPU 34 determines whether the search process has ended. In the case where the search process has ended, that is, when bs_flag == 1 (the "Yes" in S93), the process advances to S94. In the case where the search process has not ended, that is, when it is not the case that bs_flag == 1 (the "No" in S93), the CPU 34 ends the process of the timer interrupt.

[0165] In S94, the CPU 34 receives the search result from the FPGA 32. Furthermore, when the reception of the search result is completed, the CPU 34 sets the second flag (rcv_flag) to 1, which is a value indicating that a search result has been received.

[0166] Next, in S95, the CPU 34 generates the initial values of N auxiliary variables (p1 to p N ) respectively. In addition, the CPU 34 may also generate the initial values of N main variables (x1 to x N ) respectively.

[0167] Here, in the present embodiment, the FPGA 32 can execute multiple search processes in one main process of the CPU 34. In S95, the CPU 34 generates the initial values for executing the search processes after the second time (ini = 2 and later) among the multiple search processes executed in one main process. In S95, for each of the multiple search processes executed in the main process, the CPU 34 generates the initial values of N auxiliary variables (p1 to p N ) respectively, and the initial values of N main variables (x1 to x N ) respectively, in such a way that they form different combinations of values.

[0168] Next, in S96, the CPU 34 assigns the generated N auxiliary variables (p1 to p N)Send their respective initial values to FPGA32. Furthermore, when CPU34 generates the initial values of the main variables (x1 to x N ) and generates the initial values of the N main variables (x1 to x N ), it sends the respective initial values of the N main variables to FPGA32.

[0169] Next, in S97, CPU34 instructs FPGA32 to start the search process. Furthermore, CPU34 sets the second flag (rcv_flag) to 0, which represents the value indicating that the search result has not been received.

[0170] When FPGA32 receives the instruction to start the search process from CPU34, it does not change the definition information (J, h) and control parameters, but only changes the respective initial values of the N auxiliary variables (p1 to p N ) and the respective initial values of the N main variables (x1 to x N ), and starts the search process. Then, after CPU34 finishes the processing of S97, it ends the timer interrupt process.

[0171] Figure 18 It is a timing diagram of the processing executed by the information processing system 10 according to the fourth embodiment.

[0172] In the information processing system 10 according to the fourth embodiment, in the search process using FPGA32, CPU34 executes the main process in the combinatorial optimization problem to be solved next. Furthermore, until CPU34 finishes the main process, FPGA32 changes the respective initial values of the N auxiliary variables (p1 to p N ) and executes the search process multiple times.

[0173] For example, when the information processing system 10 executes the second search process (m = 2) for searching the ground state of the second Ising model after executing the first search process (m = 1) for searching the ground state of the first Ising model, CPU34 and FPGA32 perform the following processing.

[0174] First, CPU34 executes the first main process, and then executes the preprocessing and parameter sending process for the first search process (m = 1). Next, FPGA32 executes the first search process (m = 1). Next, during the period when FPGA32 executes the first search process (m = 1), CPU34 executes the second main process.

[0175] Here, when the CPU 34 finishes the first search process (m = 1) of the FPGA 32 during the execution of the second main process, it temporarily interrupts the second main process and executes a result receiving process for receiving the search result of the first search process (m = 1). Further, the CPU 34 sends new initial values of each of the N auxiliary variables (p1 to p N ) and causes the FPGA 32 to execute the first search process again with the new initial values. Then, until the execution of the second main process ends, the CPU 34 causes the FPGA 32 to repeat the first search process.

[0176] Then, when the CPU 34 receives multiple search results of the first search process with different initial values of the auxiliary variables during the execution of the second main process, it generates a search result of the first search process based on the received multiple search results.

[0177] In this way, the information processing system 10 according to the fourth embodiment can shorten the overall processing time and increase the throughput as a whole by causing the CPU 34 and the FPGA 32 to operate in parallel. Further, the information processing system 10 according to the fourth embodiment can obtain multiple search results for one combinatorial optimization problem and output a solution based on the multiple search results. Thus, the information processing system 10 according to the fourth embodiment can output a solution with better accuracy.

[0178] (First Modification Example)

[0179] Next, the first modification example will be described. The first modification example can be applied to all of the second to fourth embodiments.

[0180] The information processing system 10 according to the first modification example sequentially solves one of multiple combinatorial optimization problems. Before solving each combinatorial optimization problem, the information processing system 10 determines whether the circuit formed in the current FPGA 32 is suitable. If it is not suitable, it reconstructs the FPGA 32. If it is suitable, it advances the process without reconstructing the FPGA 32.

[0181] For example, the CPU 34 selects circuit information indicating an algorithm suitable for execution according to the combinatorial optimization problem or purpose (such as emphasizing convergence speed and emphasizing accuracy) to be solved from multiple circuit information, and reconstructs the FPGA 32 with the selected circuit information. Further, for example, the CPU 34 determines whether to reconstruct in a manner that shortens the overall processing time including the reconstruction time.

[0182] Figure 19It is a graph showing the processing time without reconfiguring the FPGA 32 and the processing time with reconfiguring the FPGA 32. For example, consider the case where the information processing system 10 executes an application for solving a combinatorial optimization problem in which the size of the J matrix changes dynamically.

[0183] It is assumed that the application solves a large-scale problem (N = N large ) in the first processing (m = 1), and then solves a small-scale problem (N = N small ) in the second processing (m = 2). In addition, N large > N small . In the second processing (m = 2), when no reconfiguration is performed, the FPGA 32 performs a search process for the base state through the circuit for solving N = N large . Therefore, in the second processing (m = 2), when no reconfiguration is performed, the processing time is determined by the variable update time for updating N large main variables and N large auxiliary variables, and the number of repetitions of the update process.

[0184] The second processing (m = 2) can perform a search process for a specified state through the circuit for solving N = N small . The variable update time using the circuit for solving N = N small is shorter than the variable update time using the circuit for solving N = N large . However, when the FPGA 32 installs the circuit for solving N = N small in the second processing (m = 2), a reconfiguration process must be performed. That is, when the total time of the processing time and the reconfiguration time in the reconfigured circuit is shorter than the processing time in the case of executing without reconfiguring the circuit immediately before, the FPGA 32 can shorten the overall processing time of the second processing (m = 2).

[0185] Therefore, when performing a search process for the base state of the second Ising model that can be searched by the first circuit in the state where the first circuit capable of searching the base state of the first Ising model is configured in the FPGA 32, the CPU 34 performs the following processing.

[0186] First, compare the first time indicating the expected execution time of the search process executed by the first circuit and the second time including the reconfiguration time for reconfiguring the FPGA 32 into the second circuit and the expected execution time of the search process executed by the second circuit. Here, the second circuit is a circuit that can search the base state of the second Ising model and has a shorter search time than the first circuit.

[0187] Then, when the second time is greater than or equal to the first time, the CPU 34 does not reconfigure the FPGA 32 that constitutes the first circuit, but causes the FPGA 32 to execute a search process for searching the ground state of the second Ising model. When the second time is shorter than the first time, the CPU 34 reconfigures the FPGA 32 into the second circuit and causes the FPGA 32 to execute a search process for searching the ground state of the second Ising model. By executing such processing, the information processing system 10 can shorten the overall processing time.

[0188] In addition, the information processing system 10 sometimes, after searching the ground state of the second Ising model, further continuously searches for the ground states of one or more Ising models that can search the ground state through the second circuit. In such a case, the CPU 34 adds the predicted execution time when searching the ground states of one or more Ising models following the second Ising model through the first circuit to the first time. Further, the CPU 34 adds the predicted execution time when searching the ground states of one or more Ising models following the second Ising model through the second circuit to the second time. Thereby, the information processing system 10 can shorten the overall processing time even when continuously searching for the ground states of multiple Ising models through the second circuit.

[0189] (Second Modification Example)

[0190] Next, the second modification example will be described. The second modification example can be applied to all of the first to fourth embodiments.

[0191] Figure 20 It is a diagram showing coupling information including coupling coefficients. In the second modification example, the information processing system 10 obtains definition information from a user or the like that defines an Ising model representing a combinatorial optimization problem to be solved. The definition information includes coupling information describing a plurality of coupling coefficients that define the Ising model. For example, the information processing system 10 obtains documented coupling information described in a predetermined format.

[0192] For each of the plurality of coupling coefficients included in the coupling information, the index for specifying the i-th and the index for specifying the j-th are made to correspond. Additionally, for example, regarding the coupling information, a plurality of coupling coefficients are arranged and described in the raster scan order of the indices of i and j. Therefore, the CPU 34 can detect the size of the J matrix from the indices (i, j) of the coupling coefficient at the final position. For example, in Figure 20 the example, the CPU 34 detects N≥max(i, j) and detects N = 4 as the size of the Ising model. In addition, max() is a function that detects the maximum value of i and j among the plurality of coupling coefficients included in the coupling information.

[0193] Before the search process of the combinatorial optimization problem, the CPU 34 selects appropriate circuit information from the multiple circuit information stored in the circuit information storage device 38, and provides the selected circuit information to the FPGA 32 to configure the circuit by the FPGA 32. In this case, the CPU 34 selects the circuit information according to the size of the Ising model detected from the coefficient information. For example, the CPU 34 selects the circuit information representing the circuit that searches for the Ising model with a size equal to or greater than the size detected from the coefficient information and the smallest size.

[0194] In addition, the CPU 34 may also select the circuit represented by the circuit information selected according to the coupling information as the second circuit in the first modification example.

[0195] In addition, when the circuit information storage device 38 includes multiple circuit information including circuits with different precisions of coupling coefficients, according to the precision of the coupling coefficients described in the coupling information, it selects the circuit information that selects one circuit information representing the circuit capable of searching for the ground state of the Ising model.

[0196] For example, if all of the multiple coupling coefficients described in the coupling information are represented by integers and are in the range of -32768 to 32767, the CPU 34 selects the circuit information representing the circuit that operates with an integer type 16-bit precision. In addition, when any one of the multiple coupling coefficients described in the coupling information includes a coupling coefficient representing a decimal, the CPU 34 selects the circuit information representing the circuit that operates with a floating-point type or a fixed-point type precision.

[0197] In addition, the CPU 34 may also display the selected circuit information, the detected size of the Ising model, and the precision of the coupling coefficients on the display device 42. Thereby, the CPU 34 can notify the user of this information.

[0198] In this way, the information processing system 10 according to the second modification example detects the size of the Ising model and the precision of the coupling coefficients included in the J matrix from the coupling information describing the coupling coefficients. According to the detected size and precision, it selects appropriate circuit information from the multiple circuit information and configures the FPGA 32. Thereby, the information processing system 10 according to the second modification example can omit the effort of the user specifying the circuit information and also eliminate the risk of specifying incorrect information. In addition, the format of the documented coupling information, the method for detecting the size, and the method for detecting the precision of the coupling coefficients are not limited to the above methods and can be any method.

[0199] (Third Modification Example)

[0200] Next, the third modification example will be described. The third modification example can be applied to all of the first to fourth embodiments.

[0201] In the third modification example, the circuit information storage device 38 stores a plurality of circuit information for implementing circuits that perform search processing by mutually different algorithms. In the third modification example, the user inputs information other than the information for specifying the algorithm. For example, the user inputs definition information (J matrix, h vector) and control parameters.

[0202] In the third example, the CPU 34 selects, from the plurality of circuit information, two or more pieces of circuit information in which the algorithms for calculating the main variable (x i ) and the auxiliary variable (p i ) are different in the main variable update process and the auxiliary variable update process. Then, for each of the two or more pieces of circuit information selected, the CPU 34 sequentially reconfigures the FPGA 32, executes the search process, and receives the search result. In this case, the FPGA 32 obtains the search result for each of the two or more pieces of circuit information with the same definition information, the same control parameters, the initial value of the same main variable (x i ) and the initial values of the same plurality of auxiliary variables (p i ). Then, the CPU 34 outputs the search result to the user by displaying, on the display device 42, the group of the information identifying the algorithm and the search result for each of the two or more pieces of circuit information.

[0203] The Ising machine 12 sometimes changes performance metrics such as the convergence speed and the solution accuracy due to a change in the algorithm. The information processing system 10 according to the third modification example can notify the user of an algorithm that is likely to obtain a suitable search result by performing search processing using a plurality of algorithms and outputting the search result for each of the plurality of algorithms.

[0204] (Fourth modification example)

[0205] Next, the fourth modification example will be described. The fourth modification example can be applied to all of the first to fourth embodiments.

[0206] The FPGA 32 (Ising machine 12) alternately repeats the auxiliary variable update process (S115) for updating the auxiliary variable (y Figure 4 ) and the main variable update process (S118) for updating the main variable (x i ) a predetermined number of times as i shown. In the fourth modification example, the information processing system 10 further includes an update history storage device that stores the update history of the N main variables (x Figure 4 ) and the update history of the N auxiliary variables (y i ) for each repetition process in i . For example, in the update process, the FPGA 32 (Ising machine 12) stores the number of repetitions, the values of the N main variables (x i ) and the N auxiliary variables (yi ) values are stored in the memory in correspondence, and output to the update history storage device after the search process is completed. When the CPU 34 (host unit 14) receives an instruction from the user, it receives the update history of the values of N main variables (x i ) stored in the update history storage device and the update history of the values of N auxiliary variables (y i ), and displays the received update history as a graph or the like on the display device 42.

[0207] Thus, the information processing system 10 according to the fourth modification example enables the user to refer to the update history of the values of N main variables (x i ) and the update history of the values of N auxiliary variables (y i ) for researching the combinatorial optimization problem and the like.

[0208] The embodiments of the present invention have been described above. However, the above embodiments are illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These new embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

[0209] In addition, the above embodiments can be summarized into the following technical solutions.

[0210] Technical solution 1

[0211] An information processing system for solving a combinatorial optimization problem, comprising:

[0212] An Ising machine as hardware, which executes a search process for searching for a ground state of an Ising model representing the combinatorial optimization problem; and

[0213] A host unit as hardware, which is connected to the Ising machine via an interface and controls the Ising machine,

[0214] In the search process, the Ising machine performs:

[0215] Storing the main variables and auxiliary variables corresponding to each of the plurality of Ising spins included in the Ising model in correspondence,

[0216] For each of the plurality of Ising spins, repeatedly executing the auxiliary variable update process of updating the auxiliary variable by the main variable and the main variable update process of updating the main variable by the auxiliary variable alternately for a plurality of times,

[0217] Output the value of the main variable corresponding to each Ising spin of the multiple Ising spins as a search result based on the main variable update process and the auxiliary variable update process being alternately executed multiple times.

[0218] Before the search process, the host unit sends the initial value of the auxiliary variable corresponding to each Ising spin of the multiple Ising spins to the Ising machine.

[0219] After the search process, the host unit receives the search result from the Ising machine and outputs the solution to the combinatorial optimization problem based on the received search result.

[0220] Technical solution 2

[0221] According to the information processing system described in Technical solution 1, wherein

[0222] Before the search process, the Ising machine sets the initial value of the main variable corresponding to each Ising spin of the multiple Ising spins to a predetermined value.

[0223] Technical solution 3

[0224] According to the information processing system described in Technical solution 1, wherein

[0225] Before the search process, the host unit sends the initial value of the main variable corresponding to each Ising spin of the multiple Ising spins to the Ising machine.

[0226] Technical solution 4

[0227] According to the information processing system described in any one of Technical solutions 1 to 3, wherein

[0228] Before the search process, the host unit sends the definition information for defining the Ising model and the control parameters for controlling the search process to the Ising machine.

[0229] Technical solution 5

[0230] According to the information processing system described in any one of Technical solutions 1 to 4, wherein

[0231] It further includes a first flag storage circuit for storing a first flag indicating whether the search process has ended.

[0232] The first flag storage circuit updates the value of the first flag according to the notification sent from the Ising machine when the search process ends.

[0233] The host unit receives the search result from the Ising machine according to the value of the first flag.

[0234] Technical solution 6

[0235] The information processing system according to any one of Technical solutions 1 to 5, wherein,

[0236] In the case where the second search process for searching for the ground state of the second Ising model is executed after the first search process for searching for the ground state of the first Ising model is executed,

[0237] The host unit executes a first main process for generating information used in the execution of the first search process,

[0238] After the host unit executes the first main process, the Ising machine executes the first search process,

[0239] During the execution of the first search process by the Ising machine, the host unit executes a second main process for generating information used in the execution of the second search process,

[0240] After the host unit executes the second main process, the Ising machine executes the second search process.

[0241] Technical solution 7

[0242] The information processing system according to Technical solution 6, wherein,

[0243] When the first search process ends during the execution of the second main process by the host unit, the host unit sends a new initial value of the auxiliary variable, and the Ising machine executes the first search process again with the new initial value of the auxiliary variable,

[0244] When the host unit receives a plurality of search results of the first search process with different initial values of the auxiliary variable during the execution of the second main process, the host unit generates the search result of the first search process according to the received plurality of search results.

[0245] Technical solution 8

[0246] The information processing system according to any one of Technical solutions 1 to 7, wherein,

[0247] The Ising machine is a reconstructable semiconductor device,

[0248] The information processing system further includes a circuit information storage device that stores a plurality of circuit information respectively representing circuits that enable the semiconductor device to implement the search process,

[0249] Before the search process, the host unit selects one piece of circuit information from the multiple pieces of circuit information that represents a circuit capable of searching for the ground state of the Ising model, and reconstructs the Ising machine using the selected circuit information.

[0250] Technical solution 9

[0251] The information processing system according to technical solution 8, wherein

[0252] In the case where the search process for searching the ground state of the second Ising model that can be searched by the first circuit is performed in a state where the first circuit capable of searching the ground state of the first Ising model is configured in the semiconductor device, the host unit performs:

[0253] Compare a first time representing the expected execution time of the search process performed by the first circuit, and a second time including the reconstruction time for reconstructing the semiconductor device into the second circuit and the expected execution time of the search process performed by the second circuit,

[0254] In the case where the second time is shorter than the first time, reconstruct the semiconductor device into the second circuit and cause the Ising machine to execute the search process,

[0255] The second circuit is a circuit capable of searching the ground state of the second Ising model and having a shorter search time than the first circuit.

[0256] Technical solution 10

[0257] The information processing system according to technical solution 8, wherein

[0258] The host unit performs:

[0259] Obtain coefficient information including a plurality of coupling coefficients that define the Ising model,

[0260] According to the number of the plurality of coupling coefficients included in the coefficient information, select one piece of circuit information from the multiple pieces of circuit information that represents a circuit capable of searching the ground state of the Ising model.

[0261] Technical solution 11

[0262] The information processing system according to technical solution 8, wherein

[0263] The host unit performs:

[0264] Obtain coefficient information including a coupling coefficient that defines the Ising model,

[0265] Select one piece of circuit information from the plurality of circuit information that represents a circuit capable of searching for the ground state of the Ising model according to the accuracy of the coupling coefficient included in the coefficient information.

[0266] Technical solution 12

[0267] The information processing system according to Technical solution 8, wherein

[0268] When receiving an instruction to search for the ground state of the Ising model, the host unit performs:

[0269] Select two or more pieces of circuit information from the plurality of circuit information, in which the algorithms for calculating the main variable and the auxiliary variable are different in the main variable update process and the auxiliary variable update process,

[0270] For each of the two or more pieces of circuit information, sequentially reconstruct the semiconductor device, execute the search process, and receive the search result,

[0271] Output the search results received from the two or more pieces of circuit information.

[0272] Technical solution 13

[0273] The information processing system according to any one of Technical solutions 1 to 12, wherein

[0274] Whenever the Ising machine executes the main variable update process, it stores the values of the main variables corresponding to the respective Ising spins of the plurality of Ising spins corresponding to the number of repetitions of the main variable update process.

[0275] After the search process, the host unit receives the values of the main variables corresponding to the respective Ising spins of the plurality of Ising spins corresponding to the number of repetitions of the main variable update process.

Claims

1. An information processing system that solves combinatorial optimization problems, wherein, Comprising: An Ising machine as hardware that performs a search process for searching for a ground state of an Ising model representing the combinatorial optimization problem; and A host unit as hardware that is connected to the Ising machine via an interface and controls the Ising machine, In the search process, the Ising machine performs: Storing the main variables and auxiliary variables corresponding to each of the plurality of Ising spins included in the Ising model in correspondence with each other, For each of the plurality of Ising spins, repeatedly executing an auxiliary variable update process for updating the auxiliary variable by the main variable and a main variable update process for updating the main variable by the auxiliary variable alternately a plurality of times, Outputting, as a search result, the value of the main variable corresponding to each of the plurality of Ising spins after alternately executing the main variable update process and the auxiliary variable update process a plurality of times, The host unit causes the Ising machine to execute the search process a plurality of times, For each of the plurality of search processes, the host unit sends the initial value of the auxiliary variable corresponding to each of the plurality of Ising spins to the Ising machine, The initial value of the auxiliary variable is different for each of the plurality of search processes, The host unit receives the search results of each of the plurality of search processes from the Ising machine, and outputs the solution of the combinatorial optimization problem based on the received search results.

2. The information processing system according to claim 1, wherein Before each of the plurality of search processes, the Ising machine sets the initial value of the main variable corresponding to each of the plurality of Ising spins to a predetermined value.

3. The information processing system according to claim 1, wherein Before each of the plurality of search processes, the host unit sends the initial value of the main variable corresponding to each of the plurality of Ising spins to the Ising machine.

4. The information processing system according to claim 1, wherein Before the plurality of search processes, the host unit sends definition information for defining the Ising model and control parameters for controlling the search process to the Ising machine.

5. The information processing system according to claim 1, wherein It further comprises a first flag storage circuit that stores a first flag indicating whether the search process has ended, The first flag storage circuit updates the value of the first flag according to a notification sent from the Ising machine when the search process ends, The host unit receives the search result from the Ising machine according to the value of the first flag.

6. The information processing system according to claim 1, wherein When performing a second search process for searching for the ground state of a second Ising model after performing a first search process for searching for the ground state of a first Ising model, The host unit executes a first main process for generating information used in the execution of the first search process, After the Ising machine executes the first main process through the host unit, it executes the first search process. During the execution of the first search process by the Ising machine, the host unit executes a second main process for generating information used in the execution of the second search process. After the host unit executes the second main process, the Ising machine executes the second search process.

7. The information processing system according to claim 6, wherein When the first search process ends during the execution of the second main process by the host unit, the host unit sends a new initial value of the auxiliary variable, and causes the Ising machine to execute the first search process again with the new initial value of the auxiliary variable. When the host unit receives a plurality of search results of the first search process with different initial values of the auxiliary variable during the execution of the second main process, the host unit generates the search result of the first search process based on the received plurality of search results.

8. The information processing system according to any one of claims 1 to 7, wherein The Ising machine is a reconstructable semiconductor device. The information processing system further includes a circuit information storage device that stores a plurality of circuit information respectively representing circuits that enable the semiconductor device to implement the search process. Before the search process, the host unit selects one piece of circuit information from the plurality of circuit information that represents a circuit capable of searching for the ground state of the Ising model, and reconstructs the Ising machine with the selected circuit information.

9. The information processing system according to claim 8, wherein When the search process for searching the ground state of the second Ising model that can be searched by the first circuit is executed in a state where the first circuit capable of searching the ground state of the first Ising model is configured in the semiconductor device, the host unit performs: Comparing a first time representing the expected execution time of the search process executed by the first circuit and a second time including the reconstruction time for reconstructing the semiconductor device into the second circuit and the expected execution time of the search process executed by the second circuit. When the second time is shorter than the first time, the semiconductor device is reconstructed into the second circuit and the Ising machine executes the search process. The second circuit is a circuit capable of searching for the ground state of the second Ising model and having a shorter search time than the first circuit.

10. The information processing system according to claim 1, wherein Whenever the Ising machine executes the main variable update process, it stores the values of the main variables corresponding to each of the plurality of Ising spins in correspondence with the number of repetitions of the main variable update process. After the search process, the host unit receives the values of the main variables corresponding to each of the plurality of Ising spins in correspondence with the number of repetitions of the main variable update process.

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