Automatic adjustment circuit for reading reference current of non-volatile memory
By designing an automatic read reference current adjustment circuit in non-volatile memory, the threshold voltage offset problem caused by process deviation is solved, and the adaptive adjustment of read reference current is realized, product yield and reliability are improved, and chip scrapping is reduced.
Patent Information
- Application Number
- CN202010831332.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-08-18
- Publication Date
- 2025-09-05
- Estimated Expiration
- 2040-08-18
AI Technical Summary
When the threshold voltage offset caused by process deviation of existing non-volatile memories, the read reference current cannot be adjusted in time, resulting in read errors and reliability problems, resulting in chip function failure and batch scrapping.
Design a reading reference current automatic adjustment circuit, including the main control module, the reading inspection control module, the reading result processing module, the reading reference current control module, the digital-to-analog conversion module and the signal switching module. By reading the memory unit row by row, the reading reference current is automatically adjusted to adapt to the process threshold voltage deviation and ensure the reading accuracy.
The product yield of non-volatile memory is improved, and the read reference current is adaptively adjusted to meet functional and reliability requirements, reducing chip scrapping caused by process deviations, and improving production efficiency and business opportunities.
Smart Images
Figure CN114078540B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a non-volatile memory, in particular to a read reference current automatic regulating circuit of the non-volatile memory. Background Art
[0002] The common readout method for non-volatile memory is to compare the readout current of the memory cell with the internal read reference current through a sense amplifier, and then distinguish whether to read a '0' or '1' value based on the current magnitude. The corresponding readout currents are hereinafter referred to as high readout current I0 and low readout current I1. The high readout current I0 is greater than the read reference current, and the low readout current I1 is less than the read reference current. Since the memory cell is in the saturation region during reading, the readout saturation current I corresponding to the high readout current I0 of the memory cell is cell and the gate-source voltage V GS and the initial threshold voltage V th The relationship between them is as follows:
[0003] I cell ∝(V GS -V th ) 2 (Formula 1)
[0004] The threshold voltage of a non-volatile memory cell is an important indicator of the data retention capability of the memory cell. Changes in the absolute value of the memory cell threshold voltage Vth affect the data retention time of the non-volatile memory. When the memory cell is just erased or programmed, the absolute value of the initial threshold voltage of the memory cell will be operated to a relatively large value; and as time goes by or the number of operations increases, the energy storage capacity of the memory cell gradually decreases, and the threshold voltage also gradually decreases accordingly, and the corresponding memory cell read current decreases. For the memory, it is specifically manifested as: the read saturation current I is expected to be larger than the read reference current cell , which is actually smaller than the read reference current, causing read errors.
[0005] For fixed memory cells, the erasing and programming processes determine their initial threshold voltage. The process determines the current threshold voltage to which this initial threshold voltage may decay over several years. Therefore, for manufactured memory, this value is fixed. The appropriateness of the read reference current used by the sense amplifier determines whether the read current from the memory cell at the current threshold voltage can produce accurate and reliable read results.
[0006] Conventionally, non-volatile memory devices contain an internal reference current generator. This module controls the internal analog circuitry to generate varying read reference currents based on changes in external digital signal values. During chip testing, the read reference current is typically adjusted to a fixed target. This target is typically determined through device testing data and design simulations.
[0007] Since device-level test results are usually not fed back into the design process in a timely manner, and the design simulation process is based on a SPICE (simulation circuit simulator) model of existing test results, the feedback from the above two points to the design stage is very slow, resulting in the read reference current target obtained in the design stage being based on outdated data and unable to timely feed back to the latest process conditions. At the same time, process deviations are often ubiquitous in the chip manufacturing process. Some unexpected process fluctuations in the manufacturing process may cause the threshold voltage during storage to shift in the same direction, resulting in a corresponding shift in the device read current and the memory read current window, causing functional failure or reliability failure during the test process, resulting in batches of chips being scrapped, and re-production often takes several months, resulting in not only a large amount of financial loss, but also missed business opportunities due to the waste of time. Summary of the Invention
[0008] The technical problem to be solved by the present invention is to provide a read reference current automatic adjustment circuit for the non-volatile memory, which can adaptively adjust the internal read reference current according to the process threshold voltage deviation during testing, meet the functional and reliability requirements of the non-volatile memory, and thus improve the product yield.
[0009] To solve the above technical problems, the present invention provides a read reference current automatic adjustment circuit for a non-volatile memory, which includes a main control module, a read verification control module, a read result processing module, a read reference current control module, a digital-to-analog conversion module, and a signal switching module;
[0010] The main control module sends an internal enable signal to the read test control module and the read reference current control module after receiving the external enable signal;
[0011] The signal switching module is used to select and output a bias gate voltage or a normal gate voltage to the gate of the storage unit according to the bias switching signal output by the read verification control module; the bias gate voltage is greater than the normal gate voltage;
[0012] The digital-to-analog conversion module is used to convert the digital adjustment signal into a read reference current and output it to the memory sense amplifier; the memory sense amplifier is used to compare the read current of the memory cell with the read reference current and distinguish between reading '0' and '1' according to the current size;
[0013] a read control circuit, detecting a read current of a memory cell corresponding to a read address and outputting the current to a memory sense amplifier;
[0014] The read result processing module is used to compare the read value of the storage unit corresponding to the read address of the current read operation of the read verification control module with the expected value, and output a read error signal to the read verification control module if they are inconsistent;
[0015] The read test control module, after receiving the internal enable signal, performs a read traversal operation on the memory row and column by row, outputs a read address and a read clock to the read control circuit, and outputs a bias switching signal to the signal switching module; while outputting the read address and the read clock to the read control circuit, the signal switching module simultaneously outputs a bias gate voltage Vtest to the gate of the memory cell corresponding to the read address;
[0016] The read check control module, when performing a read traversal operation on each row and column of the memory, stops the current read traversal operation and sends a read check error signal to the read reference current control module if a read error signal is received; otherwise, the read traversal operation on all addresses of the memory is completed and a read check pass signal is output to the read reference current control module;
[0017] The read reference current control module, after receiving the internal enable signal, sends the center value of the digital adjustment signal as the current adjustment value to the digital-to-analog conversion module; when receiving the read check pass signal, compares the stored digital adjustment signal optimal value with the current adjustment value, and if the current adjustment value is greater than the digital adjustment signal optimal value, updates the digital adjustment signal optimal value to the current adjustment value, and then increases the current adjustment value and sends it to the digital-to-analog conversion module; when receiving the read check error signal, reduces the current adjustment value and sends it to the digital-to-analog conversion module.
[0018] Preferably, the read current is the expected value of the high read current I0 is '0';
[0019] The read current is low and the expected value of the read current I1 is '1';
[0020] The high read current I0 is greater than the read reference current, and the low read current I1 is less than the read reference current;
[0021] The read result processing module only judges the bit with the expected value of 0 when comparing the read value of the storage unit corresponding to the read address of the current read operation of the read verification control module with the expected value.
[0022] Preferably, the read reference current control module adjusts the current adjustment value bit by bit based on a binary method when receiving a read verification pass signal or a read verification error signal.
[0023] Preferably, the highest bit of the center value is 1, and the other bits are 0;
[0024] The initial adjustment bit of the current adjustment value is the highest bit;
[0025] To increase the current adjustment value, the next bit of the current adjustment bit of the current adjustment value is changed from 0 to 1. If all bits of the current adjustment value are 1, the adjustment is completed. Otherwise, the next bit is used as the current adjustment bit.
[0026] To reduce the current adjustment value, the current adjustment bit of the current adjustment value is changed from 1 to 0, and the next bit of the current adjustment bit is changed from 0 to 1. If all bits of the current adjustment value are 0, the adjustment is completed, otherwise the next bit is used as the current adjustment bit.
[0027] Preferably, the digital adjustment signal has 3 bits in total, and the center value is 100.
[0028] Preferably, the read verification control module enables the signal switching module to output a normal gate voltage to the gate of the storage unit corresponding to the read address when the reading is stopped.
[0029] Preferably, the initial value of the optimal value of the digital adjustment signal is 0.
[0030] Preferably, when the read reference current control module receives a read check error signal after increasing the current adjustment value by 1, or receives a read check pass signal after decreasing the current adjustment value by 1, the main control module outputs the optimal value of the digital adjustment signal currently stored in the read reference current control module as the target read reference current to the outside.
[0031] Preferably, when the read reference current control module receives a read check error signal after reducing the current adjustment value to 0, the main control module outputs a process failure signal to the outside.
[0032] The present invention discloses a read reference current automatic adjustment circuit for a non-volatile memory, which is an adaptive read reference current automatic adjustment circuit with a threshold voltage window. Upon receiving an external enable signal, the center value of the read reference current digital adjustment signal is sent to a digital-to-analog conversion module as the current adjustment value, while simultaneously driving a read verification control module to initiate a read operation on the memory. Prior to the read operation, the read verification control module controls the switching of the memory cell gate voltage to the bias gate voltage Vtest on a row-by-row basis, performing a row read operation. The read verification control module then receives a comparison result between the memory cell read value and the expected value from the read result processing module. The read verification control module determines whether the read verification has passed based on the comparison result. The read reference current control module adjusts the digital adjustment signal based on whether the read verification has passed, thereby adjusting the read reference current via the digital-to-analog conversion module. This process of read verification, read result verification, and read reference current adjustment is repeated multiple times. Once the target read reference current is found, the main control module outputs the target read reference current externally and feeds back a completion signal to the external circuit. This automatic read reference current adjustment circuit for non-volatile memory can adaptively adjust the internal read reference current according to the process threshold voltage deviation when the process threshold voltage shifts, based on the change in device current caused by the threshold voltage. This circuit meets the functional and reliability requirements of the non-volatile memory, thereby improving product yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0034] Figure 1 It is a structural diagram of an embodiment of a read reference current automatic adjustment circuit for a non-volatile memory of the present invention;
[0035] Figure 2 This is a basic principle diagram of a non-volatile memory cell that fails to read due to a threshold voltage shift;
[0036] Figure 3 It is a schematic diagram showing the correspondence between the read reference current and the read result when the gate voltage of the memory cell is not biased;
[0037] Figure 4 It is a schematic diagram showing the correspondence between the read reference current and the read result after the gate voltage of the memory cell is biased;
[0038] Figure 5 The diagram is a schematic diagram of bit-by-bit adjustment of a 3-bit adjustment value of a digital adjustment signal based on a binary method. DETAILED DESCRIPTION
[0039] The following is a clear and complete description of the technical solutions of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.
[0040] Example 1
[0041] like Figure 1 As shown, the read reference current automatic adjustment circuit of the non-volatile memory includes a main control module, a signal switching module, a digital-to-analog conversion module, a read inspection control module, a read result processing module, and a read reference current control module;
[0042] The main control module sends an internal enable signal to the read test control module and the read reference current control module after receiving the external enable signal;
[0043] The signal switching module is used to select and output a bias gate voltage or a normal gate voltage to the gate of the storage unit according to the bias switching signal output by the read verification control module; the bias gate voltage is greater than the normal gate voltage;
[0044] The digital-to-analog conversion module is used to convert the digital adjustment signal into a read reference current and output it to the memory sense amplifier;
[0045] The read control circuit detects the read current of the memory cell corresponding to the read address and outputs it to the memory sense amplifier;
[0046] The memory sense amplifier compares the read current of the memory cell with the read reference current and reads '0' or '1' according to the current magnitude;
[0047] The read result processing module is used to compare the read value of the storage unit corresponding to the read address of the current read operation of the read verification control module with the expected value, and output a read error signal to the read verification control module if they are inconsistent;
[0048] The read test control module, after receiving the internal enable signal, performs a read traversal operation on the memory row by row and column by column, outputs a read address and a read clock to the read control circuit, and outputs a bias switching signal to the signal switching module; while outputting the read address and the read clock to the read control circuit, the signal switching module simultaneously outputs a bias gate voltage Vtest to the gate of the memory cell corresponding to the read address;
[0049] The read check control module, when performing a read traversal operation on each row and column of the memory, stops the current read traversal operation and sends a read check error signal to the read reference current control module if a read error signal is received; otherwise, the read traversal operation on all addresses of the memory is completed and a read check pass signal is output to the read reference current control module;
[0050] The read reference current control module, after receiving the internal enable signal, sends the center value of the digital adjustment signal as the current adjustment value to the digital-to-analog conversion module; when receiving the read check pass signal, compares the stored digital adjustment signal optimal value with the current adjustment value, and if the current adjustment value is greater than the digital adjustment signal optimal value, updates the digital adjustment signal optimal value to the current adjustment value, and then increases the current adjustment value and sends it to the digital-to-analog conversion module; when receiving the read check error signal, reduces the current adjustment value and sends it to the digital-to-analog conversion module.
[0051] Preferably, the read current is the expected value of the high read current I0 is '0';
[0052] The read current is low and the expected value of the read current I1 is '1';
[0053] The high read current I0 is greater than the read reference current, and the low read current I1 is less than the read reference current;
[0054] The read result processing module only judges the bit with the expected value of 0 when comparing the read value of the storage unit corresponding to the read address of the current read operation of the read verification control module with the expected value.
[0055] The signal switching module is a conventional analog signal switching circuit;
[0056] The digital-to-analog conversion module is a conventional digital-to-analog conversion circuit.
[0057] Preferably, when the read reference current control module receives a read check error signal after increasing the current adjustment value by 1, or receives a read check pass signal after decreasing the current adjustment value by 1, the main control module uses the optimal value of the digital adjustment signal currently stored in the read reference current control module as the target read reference current and outputs it to the outside.
[0058] Preferably, when the read reference current control module receives a read check error signal after reducing the current adjustment value to 0, the main control module outputs a process failure signal to the outside, indicating that no adjustment value can allow the current memory to read the correct value, that is, the memory process fails and cannot meet the functional or reliability requirements.
[0059] The threshold voltage shift of non-volatile memory is usually caused by fluctuations in process conditions. The resulting shift in the same direction often exceeds the design expectation, resulting in a relatively large change in the current of the corresponding memory cell under the same read conditions, which is reflected as a read failure of the memory cell. The basic principle of read failure of non-volatile memory cells due to threshold voltage shift is as follows: Figure 2 As shown in the figure, for a memory cell without threshold voltage shift, as shown on the left axis, the original read reference current is between the high read current I0 and the low read current I1, and the memory read circuit can operate correctly. However, when the threshold voltage shift occurs due to process conditions, the read window formed by the high read current I0 and the low read current I1 shifts as a whole, and correct reading may not be possible under the original read reference current conditions. If the read reference current is simply adjusted to the new process reference current, so that the shifted high read current I0 and low read current I1 can be correctly read again, then after the non-volatile memory ages for a long time (e.g., 10 years), the threshold voltage will normally shift over time. Therefore, the new process read reference current used during testing may not meet the current read conditions, resulting in read failure again and the reliability of the non-volatile memory cannot be guaranteed.
[0060] Typically, the aging threshold voltage change Vdecay of a non-volatile memory after aging can be obtained through device testing, and its corresponding aging read saturation current I cell_decay It is expressed as follows:
[0061] Icell_decay ∝(V GS -V′ th ) 2 (Formula 2)
[0062] The threshold voltage after aging is V′ th With the initial threshold voltage V th The changing relationship is shown in the following formula:
[0063] V′ th =V th -V decay (Formula 3)
[0064] From formula 2 and formula 3, we can get:
[0065] I cell_decay ∝(V GS -V th +V decay ) 2 (Formula 4)
[0066] Further transforming, if the gate test voltage (bias gate voltage) Vtest is established as in Formula 5, Formula 4 can be transformed into Formula 6.
[0067] V test =V gs +V decay (Formula 5)
[0068] I cell_decay ∝(V test -V th ) 2 (Formula 6)
[0069] As can be seen from Formula 6, by adjusting the gate test voltage (bias gate voltage) Vtest during the read operation during the test process, the read saturation current corresponding to the high read current I0 of the aged memory cell can be simulated in the conventional test.
[0070] The relationship between the non-volatile memory read result and the read reference current is as follows:
[0071] When the read reference current is within the range of high read current I0 and low read current I1, the stored values of 0 and 1 can be read correctly;
[0072] When the read reference current is greater than the high read current I0, the stored value of 0 will be incorrectly read as 1;
[0073] When the read reference current is less than the low read current I1, the stored 1 will be misread as 0.
[0074] When the gate-source voltage Vgs of the memory cell is not biased, Figure 3As shown in the figure, the left vertical axis represents the change of the read reference current value, and the right axis represents the change of the read value. The dotted box area corresponds to the range of correct reading. When the gate voltage of the memory cell is not biased, the range of change of the read reference current is very large.
[0075] When the memory cell gate-source voltage Vgs is biased to the bias gate voltage Vtest, Figure 4 As shown in FIG, the range of the read reference current that can be correctly read is narrowed. According to analysis, this is closer to the actual read condition of the memory cell after aging.
[0076] from Figure 3 and Figure 4 As can be seen from the figure, the change of the read reference current can be determined by whether the read result is correct or not:
[0077] When the read reference current changes from small to large, a certain read reference current result will be encountered, which is exactly the last read reference current that can correctly read 0 and 1; when the read reference current increases, the read reference current when 0 is read as 1 can just meet the reliability requirements of the memory.
[0078] The first embodiment of the present invention relates to a non-volatile memory read reference current automatic adjustment circuit, which is an adaptive read reference current automatic adjustment circuit with a threshold voltage window. Upon receiving an external enable signal, the center value of the read reference current digital adjustment signal is sent to a digital-to-analog conversion module as the current adjustment value, while simultaneously driving a read verification control module to initiate a read operation on the memory. Prior to the read operation, the read verification control module controls the switching of the memory cell gate voltage to the bias gate voltage Vtest on a row-by-row basis, performing a row read operation, and receiving a comparison result between the memory cell read value and the expected value from the read result processing module. The read verification control module determines whether the test is faulty based on the comparison result. The read reference current control module adjusts the digital adjustment signal based on whether the read verification passes, thereby adjusting the read reference current via the digital-to-analog conversion module. This process of read verification, read result verification, and read reference current adjustment is repeated multiple times. Once the target read reference current is found, the main control module outputs the target read reference current to the external circuit and feeds back a completion signal. This automatic read reference current adjustment circuit for non-volatile memory can adaptively adjust the internal read reference current according to the process threshold voltage deviation when the process threshold voltage shifts, based on the change in device current caused by the threshold voltage. This circuit meets the functional and reliability requirements of the non-volatile memory, thereby improving product yield.
[0079] Based on the non-volatile memory's automatic read reference current adjustment circuit, test engineers can simulate the non-volatile memory's aging conditions by setting the bias gate voltage based on the process device test results. The circuit automatically adjusts the internal read reference current and verifies it through actual read results to obtain the target read reference current. For example, if the process device test reveals that the normal operating threshold voltage of the current non-volatile memory has shifted by 100mV after aging, the original theoretical bias gate voltage specification is adjusted by 100mV during the test. This adjustment is directly applied to the circuit's automatic adjustment process, thereby matching the changes in the memory device.
[0080] Example 2
[0081] Based on the read reference current automatic adjustment circuit of the non-volatile memory of the first embodiment, the read reference current control module adjusts the current adjustment value bit by bit based on the binary method when receiving the read verification pass signal or the read verification error signal.
[0082] Preferably, the highest bit of the center value is 1, and the other bits are 0;
[0083] The initial adjustment bit of the current adjustment value is the highest bit;
[0084] To increase the current adjustment value, the next bit of the current adjustment bit of the current adjustment value is changed from 0 to 1. If all bits of the current adjustment value are 1, the adjustment is completed. Otherwise, the next bit is used as the current adjustment bit.
[0085] To reduce the current adjustment value, the current adjustment bit of the current adjustment value is changed from 1 to 0, and the next bit of the current adjustment bit is changed from 0 to 1. If all bits of the current adjustment value are 0, the adjustment is completed, otherwise the next bit is used as the current adjustment bit.
[0086] Better, such as Figure 5 As shown, the digital adjustment signal has 3 bits in total and the center value is 100.
[0087] (one) Figure 5 The bits in the square brackets are the current adjustment bits. The initial state of the highest layer is 100, and the initial selected bit is the highest bit (bit 2).
[0088] (2) First, perform initial state adjustment: If the read verification result is passed, the read reference current control module records the current adjustment value, and the next adjustment value is set to 110, and the next adjustment bit is selected as bit 1, and the read verification continues; if the read verification fails, the adjustment value is set to 010 and the read verification is performed again;
[0089] (3) When the adjustment value is set to 001: If a read check error occurs, it is necessary to perform an additional read check of 000. If the error still occurs, it means that no adjustment value can allow the current memory to read the correct value, which means that there is a process failure and cannot meet the functional or reliability requirements.
[0090] In the second embodiment of the non-volatile memory read reference current automatic adjustment circuit, the read reference current control module is based on a binary design and adjusts the current adjustment value of the digital adjustment signal bit by bit. The analysis is based on the read test result: if the read test result is a pass, it means that the current adjustment value is usable and the next adjustment value should increase the read reference current; if the read test result is an error, it means that the current adjustment value corresponds to an excessively large read reference current and the next adjustment value should be adjusted to a smaller value.
[0091] Example 3
[0092] Based on the read reference current automatic adjustment circuit of the non-volatile memory of the first embodiment, the read verification control module enables the signal switching module to output a normal gate voltage to the gate of the memory cell corresponding to the read address when reading is stopped.
[0093] Preferably, the initial value of the optimal value of the digital adjustment signal is 0.
[0094] Preferably, the read reference current automatic adjustment circuit of the non-volatile memory can be directly embedded in the memory IP or chip.
[0095] Preferably, the external enable signal and the expected readout result can be configured by an external control circuit.
[0096] Preferably, the bias gate voltage or the normal gate voltage can be provided from outside the memory or provided by an analog-to-digital conversion circuit in an integrated chip.
[0097] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A read reference current automatic adjustment circuit for a non-volatile memory, characterized in that: It includes a main control module, a read inspection control module, a read result processing module, a read reference current control module, a digital-to-analog conversion module and a signal switching module; The main control module sends an internal enable signal to the read test control module and the read reference current control module after receiving the external enable signal; The signal switching module is used to select and output a bias gate voltage or a normal gate voltage to the gate of the storage unit according to the bias switching signal output by the read verification control module; The bias gate voltage is greater than the normal gate voltage; The digital-to-analog conversion module is used to convert the digital adjustment signal into a read reference current and output it to the memory sense amplifier; the memory sense amplifier is used to compare the read current of the memory cell with the read reference current and distinguish between reading '0' and '1' according to the current size; a read control circuit, detecting a read current of a memory cell corresponding to a read address and outputting the current to a memory sense amplifier; The read result processing module is used to compare the read value of the storage unit corresponding to the read address of the current read operation of the read verification control module with the expected value, and output a read error signal to the read verification control module if they are inconsistent; The read verification control module, after receiving the internal enable signal, performs a read traversal operation on the memory row and column by row, outputs a read address and a read clock to the read control circuit, and outputs a bias switching signal to the signal switching module; While outputting the read address and the read clock to the read control circuit, the signal switching module outputs the bias gate voltage to the gate of the storage unit corresponding to the read address; The read check control module, when performing a read traversal operation on each row and column of the memory, stops the current read traversal operation and sends a read check error signal to the read reference current control module if a read error signal is received; otherwise, the read traversal operation on all addresses of the memory is completed and a read check pass signal is output to the read reference current control module; The read reference current control module sends the center value of the digital adjustment signal as the current adjustment value to the digital-to-analog conversion module after receiving the internal enable signal; When a read check pass signal is received, the stored optimal value of the digital adjustment signal is compared with the current adjustment value. If the current adjustment value is greater than the optimal value of the digital adjustment signal, the optimal value of the digital adjustment signal is updated to the current adjustment value, and then the current adjustment value is increased and sent to the digital-to-analog conversion module; when a read check error signal is received, the current adjustment value is reduced and sent to the digital-to-analog conversion module.
2. The read reference current automatic adjustment circuit for a non-volatile memory according to claim 1, wherein: The read current is high and the expected value of the read current I0 is '0'; The read current is low and the expected value of the read current I1 is '1'; The high read current I0 is greater than the read reference current, and the low read current I1 is less than the read reference current; The read result processing module only judges the bit with the expected value of 0 when comparing the read value of the storage unit corresponding to the read address of the current read operation of the read verification control module with the expected value.
3. The read reference current automatic adjustment circuit for a non-volatile memory according to claim 1, wherein: The read reference current control module adjusts the current adjustment value bit by bit based on the binary method when receiving the read test pass signal or the read test error signal.
4. The read reference current automatic adjustment circuit for a non-volatile memory according to claim 3, wherein: The highest bit of the center value is 1, and the others are 0; The initial adjustment bit of the current adjustment value is the highest bit; To increase the current adjustment value, the next bit of the current adjustment bit of the current adjustment value is changed from 0 to 1. If all bits of the current adjustment value are 1, the adjustment is completed. Otherwise, the next bit is used as the current adjustment bit. To reduce the current adjustment value, the current adjustment bit of the current adjustment value is changed from 1 to 0, and the next bit of the current adjustment bit is changed from 0 to 1. If all bits of the current adjustment value are 0, the adjustment is completed, otherwise the next bit is used as the current adjustment bit.
5. The read reference current automatic adjustment circuit of a non-volatile memory according to claim 4, wherein: The digital adjustment signal has 3 bits in total, and the center value is 100.
6. The read reference current automatic adjustment circuit for a non-volatile memory according to claim 1, wherein: The read verification control module enables the signal switching module to output a normal gate voltage to the gate of the storage unit corresponding to the read address when the reading is stopped.
7. The read reference current automatic adjustment circuit for a non-volatile memory according to claim 1, wherein: The initial value of the digital adjustment signal optimal value is 0.
8. The read reference current automatic adjustment circuit for a non-volatile memory according to claim 1, wherein: When the read reference current control module receives a read check error signal after increasing the current adjustment value by 1, or receives a read check pass signal after decreasing the current adjustment value by 1, the main control module outputs the optimal value of the digital adjustment signal currently stored in the read reference current control module as the target read reference current to the outside.
9. The read reference current automatic adjustment circuit for a non-volatile memory according to claim 1, wherein: When the read reference current control module receives a read check error signal after reducing the current adjustment value to 0, the main control module outputs a process failure signal to the outside.
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