Apparatus, system and method for memory directed access suspension

Abstract

The present invention relates to an apparatus, system, and method for memory-directed access suspension. A controller may perform an access operation on a memory by providing a command and an address. The memory may monitor the address to determine whether one or more forms of attacks (intentional or unintentional) have occurred. If an attack is detected, the memory may issue an alert signal (e.g., along an alert bus) and also provide suspension data (e.g., along a data bus). The suspension data may specify a time length, and in response to the alert and the suspension data, the controller may suspend access operations to the memory for the time length specified in the suspension data. The memory may use the time during which access operations are suspended to perform self-refresh, for example, to repair damage caused by the attack.

Description

Technical Field

[0001] The present application relates to apparatus, systems, and methods for memory directed access suspension. Background Art

[0002] A semiconductor device may include a controller and a memory. The controller may operate the memory, for example, by providing commands to the memory and sending and receiving data to and from the memory. The memory may be volatile memory in which information stored therein may decay over time. The memory may perform a self-refresh operation to restore the information before it decays. Certain patterns of commands sent by the controller may increase the rate at which information decays in the memory. The memory may track access patterns, for example, by tracking commands and / or addresses. Summary of the Invention

[0003] One aspect of the present application relates to a system comprising: a controller configured to provide commands and addresses along a command-address bus; and a memory configured to monitor the addresses and, based on the monitored addresses, provide an alert signal along an alert bus and provide pause data along a data bus, wherein in response to the alert signal and the pause data, the controller is configured to stop providing the commands and addresses to the memory for a length of time specified by the pause data.

[0004] Another aspect of the present application relates to an apparatus comprising: a refresh queue configured to store a plurality of addresses, wherein the refresh queue is configured to provide a full signal at an active level when a number of the plurality of addresses is higher than a threshold; an attack detector configured to provide an attack signal in response to receiving a next address to be stored when the full signal is at the active level; and alert logic configured to provide an alert signal at an active level to an alert terminal and provide pause data to a data terminal in response to the attack signal being at the active level.

[0005] Another aspect of the present application relates to an apparatus comprising: an aggressor detector circuit configured to store a plurality of count values, each count value associated with an access to one or more row addresses; an attack detector circuit configured to store a capacity count based on a number of the plurality of count values ​​that are above a threshold; a comparator circuit configured to provide an attack signal at an active level based on the value of the capacity count; and an alert logic circuit configured to provide pause data to a data terminal and an alert signal to an alert terminal in response to the attack signal being at the active level.

[0006] Yet another aspect of the present application relates to a method, comprising: sending a command and an address to a memory; determining, based on the address, that the memory is under attack; providing a warning signal and pause data from the memory in response to the determination that the memory is under attack; and suspending the sending of the command and address for a certain length of time based on the pause data. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a memory system according to some embodiments of the present disclosure.

[0008] Figure 2 is a block diagram of a device according to an embodiment of the present disclosure.

[0009] Figure 3 is a block diagram of a refresh control circuit according to some embodiments of the present disclosure.

[0010] Figure 4 is a block diagram of an attack detector circuit according to some embodiments of the present disclosure.

[0011] Figure 5 is a flow chart of a method of detecting an attack and suspending operation according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] The following descriptions of certain embodiments are merely exemplary in nature and are in no way intended to limit the scope of the present disclosure or the application or use of the present disclosure. In the following detailed description of embodiments of the systems and methods of the present invention, reference is made to the accompanying drawings that form a part hereof, and the accompanying drawings are presented by illustrating specific embodiments in which the described systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed systems and methods, and it is understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. In addition, for the sake of clarity, detailed descriptions of certain features will not be discussed when they will be obvious to those skilled in the art so as not to obscure the description of the embodiments of the present disclosure. Therefore, the following detailed description should not be understood in a restrictive sense, and the scope of the present disclosure is limited solely by the appended claims.

[0013] The memory can be operated by a controller that can provide various signals to the memory. For example, the controller can execute a read command by providing a read command and an address along a command / address (CA) bus. The address can specify where in the memory array of the memory the data should be read from. The memory can provide the data from the specified location along a data (DQ) bus. The controller can execute a write operation by providing a write command and an address along the CA bus and can receive the read information along the DQ bus.

[0014] A memory may store information in memory cells of a memory array, which may be arranged at the intersection of word lines (rows) and bit lines (columns or digit lines). Thus, row and column addresses may be used by a controller to specify the location of one or more memory cells. The memory array may be volatile, and the information in the memory cells may decay over time. The memory may refresh the information (e.g., on a row-by-row basis) to restore the information before it has decayed beyond a recovery point. Certain access patterns may increase the rate at which information decays. For example, repeated accesses to a given row (the aggressor row) may increase the rate at which information decays in an adjacent row (the victim row). Such a pattern may be referred to as row hammering. The memory may track accesses to identify the aggressor row so that its victim row can be refreshed.

[0015] In some cases, a controller may inadvertently access memory in a manner that causes an increased rate of information decay in some cells. In some cases, a malicious actor may intentionally attack memory by instructing the controller to behave in a manner that causes an increased rate of data decay, for example as part of an attempt to manipulate data stored in the memory. For simplicity, both types of access patterns (intentional and unintentional) may be referred to as attacks. In these and other situations, it may be useful to thwart the attack by preventing the controller from providing further instructions for a period of time.

[0016] The present disclosure relates to devices, systems, and methods for memory-directed access suspension. During operation, a controller may provide commands and addresses along a CA bus. The memory may monitor the addresses to determine whether one or more forms of attacks are occurring. If the memory determines that an attack is occurring, the memory may provide an alert signal (e.g., along an alert bus) to notify the controller of the attack. The memory may also provide pause data (e.g., along a DQ bus) indicating the length of time the memory will be offline. The controller may suspend access operations to the memory (e.g., by not providing commands and addresses) for a period of time specified by the pause data. The pause may allow the memory to perform refresh operations. The pause may also slow the rate at which attacks may occur, which may frustrate the attacker if the attack is intentional.

[0017] Figure 11 is a block diagram of a memory system according to some embodiments of the present disclosure. System 100 includes a controller 102 that can be coupled to one or more memories 110. For example, multiple memories 110 can be packaged together as part of a memory stack. Memories 110 can be coupled to controller 102 along various buses, each of which can include one or more conductive lines that couple a 'pin' of a memory 110 to a pin of controller 102. In some embodiments, the buses can be commonly coupled to each of memories 110. Because memories 110 can be generally similar to each other, some features and operations may be described with respect to a single memory 110, however, these features and operations should be understood to apply to each of memories 110.

[0018] Information can be provided as voltages along the bus. For example, different voltages received at pins of controller 102 and memory 110 can represent different logic levels. The bus can use a mix of serial and parallel transmissions to convey information. For example, a data bus can include sixteen conductive elements coupled to sixteen pins, each of which can convey eight bits as part of a serial burst of information (e.g., for a total of 128 bits). Other formats for carrying information can be used in other examples.

[0019] Controller 102 is coupled to memory 110 along a command / address bus CA, which carries both commands and addresses from controller 102 to one or more cells in memory 110. Controller 102 is also coupled to memory 110 along a data bus DQ, which carries data information between controller 102 and memory 110. For example, controller 102 may provide a read command along the CA bus, along with one or more addresses, such as a row address, a column address, and / or a bank address. The address may also specify one or more cells in memory 110 to be activated. In response to the read command, the memory may retrieve the information stored in the memory cells specified by the address and provide the read information back to controller 102 along the DQ bus.

[0020] As part of an example write operation, the controller 102 may provide a write command along with an address (which may specify one or more of the memories 110) along the CA bus. The controller 102 may also provide write data along the DQ bus. The memory may store the write data from the DQ bus in the one or more memory cells specified by the address. In some example operations, data may be read from (or written to) multiple memories 110 at once. In some example operations, data may be read from (or written to) selected memories in the memories 110.

[0021] Each of the memories 110 may include a refresh control circuit 112 that manages refresh operations in the memory. In some embodiments, there may be a refresh control circuit 112 for each bank of the memory. In other embodiments, other organizations of refresh control circuits 112 for different portions of the memory 110 are possible. During normal operation, the memory may be put into a refresh mode (e.g., based on logic within the memory 110, a signal from the controller 102, or a combination thereof). During refresh mode, the refresh control circuit 112 may refresh the word lines of the memory to restore information before the information has decayed. For example, as part of an auto-refresh operation, the refresh control circuit 112 may generate a refresh address based on an address sequence. Over time, the auto-refresh operation may cycle through all the word lines of the memory at a rate high enough to prevent information loss.

[0022] As part of a targeted refresh operation, the refresh control circuitry 112 may also target specific word lines for refresh. For example, the refresh control circuitry 112 may identify an aggressor row of the memory so that a victim row associated with the identified aggressor may be refreshed as part of the targeted refresh operation. It should be understood that the refresh control circuitry 112 may use criteria to identify the aggressor, and that the identified aggressor need not actually cause the increased data decay rate, or that the identified victim row need not actually experience the increased data decay rate.

[0023] Refresh control circuitry 112 may include an aggressor detector circuit 114 that can detect aggressor rows based on various criteria. For example, aggressor detector 114 may count accesses to various row addresses provided along the CA bus. If a given address is accessed a certain number of times (e.g., its access count crosses a threshold), the address may be identified as an aggressor. Aggressor detector 114 may include various monitoring circuits (e.g., counters, registers, etc.) as well as a refresh queue that stores identified aggressors until their corresponding victims can be refreshed.

[0024] During an attack on one or more memories 110, the word lines that need to be refreshed may accumulate faster than the memory can refresh them as part of a normal refresh operation. To prevent too many victims of aggressors from being left unrefreshed, the refresh control circuitry 110 may include an attack detector 116 that detects one or more types of attack patterns. An example attack pattern may include hammering different rows so that there are too many aggressor rows for the refresh queue to store. Such an attack pattern may be referred to as a queue overflow attack. An example attack may include accessing many rows, accessing each row at a number (or rate) just below a threshold at which the row would be determined to be an aggressor, and then rapidly accessing the rows again so that a large number of rows are suddenly determined to be aggressors. Such an attack pattern may be referred to as a waterfall attack. The attack detector 116 may use various criteria to identify one or more attack patterns. Figure 3 The instance attack detector is described in more detail in

[15] .

[0025] When attack detector 116 indicates that one or more attacks are in progress, the attack detector may signal alert logic 118 of refresh control circuitry 112. Alert logic 118 may signal controller 102 that memory 110 (or a portion of the memory) is under attack and provide pause data indicating the length of time controller 102 should pause access operations to memory 110 (or a portion of the memory). Refresh control circuitry 112 may include pause calculator circuitry 119 that can generate pause data. The pause data may indicate how long memory 110 is expected to pause access operations. The length of time specified in the pause data may depend in part on the type of attack detected by attack detector 116. For example, the pause data may specify a longer time in response to a detected waterfall attack than in response to a refresh queue overflow attack. Pause calculator circuitry 119 may receive a signal from attack detector 116 indicating which type of attack is occurring and may generate pause data accordingly. In some embodiments, pause calculator circuit 119 may also consider additional factors (eg, how many attacks have occurred within a given time span) when determining the length of time to specify in the pause data.

[0026] An alert signal may be provided along an alert bus that can be shared by multiple memories. For example, memories 110 may be commonly coupled to controller 102 via the alert bus. In some embodiments, the alert bus may be a single alert pin commonly coupled to each of memories 110. Thus, the alert signal may be a single binary signal that is either active or inactive. A memory 110 that detects an attack may provide an alert signal at an active level along the alert bus and may provide identification information to let controller 102 know which memory is being attacked. For example, a memory 110 may use data bus inversion (DBI) to identify which memory is being attacked. Each memory may have a DBI pin associated with it. If a memory provides an active signal along its associated DBI pin, the controller may use which DBI pin carries the active signal to determine which memory is requesting an operation pause.

[0027] The controller 102 may include pause logic 104, which can be used to pause operations on one or more memories (and / or memory portions) in response to a detected attack. For example, the pause logic 104 may receive an alert signal (and identifying information) indicating that one of the memories is undergoing an attack. In some embodiments, the alert signal may provide limited information (e.g., in embodiments where the alert signal is a single bit, it will not indicate what issue caused the alert). The controller 102 may query the memory 110 for more information, such as by performing a read operation to retrieve information from the memory 110 regarding the cause of the alert. The pause logic 104 may also cause the controller 102 to query the memory 110 to retrieve pause data. For example, the controller 102 may perform a read operation along the DQ bus to retrieve the pause data. In some embodiments, the controller 102 query may be combined, and the controller 102 may read the pause data as part of a query to determine whether an attack has occurred.

[0028] The pause logic 104 can use the pause data to determine how long to pause operations on the memory (or portion of the memory). For example, the pause data can specify a length of time (e.g., in clock cycles). The pause logic 104 can provide an internal signal to the controller 102 that instructs the controller not to send access commands to the specified memory for at least the length of time. The controller 102 can also have internal logic that can save the state of operations on the paused memory. For example, the controller 102 can save the most recent command sent to the paused memory and any additional commands that should have been sent during the pause in a queue to be provided after the pause has passed.

[0029] In some embodiments, memory 110 may take no action during the pause. In some embodiments, the paused memory 110 may enter a self-refresh mode to 'heal' the attack by executing refresh operations. For example, in the case of a refresh queue overflow attack, all victims of the aggressor stored in the refresh queue may be refreshed to clear the queue. In the case of a waterfall attack, the memory may refresh victims adjacent to all word lines detected as aggressors. In some embodiments, the memory may execute other refresh modes, such as refreshing all word lines. The length of time specified in the pause data may be based in part on how long the memory predicts it will take to execute these refresh operations.

[0030] Figure 2 is a block diagram of an apparatus according to an embodiment of the present disclosure. The apparatus may be a semiconductor device 200 and will be referred to as such. The device 200 may be included in Figure 1 In some embodiments, the semiconductor device 200 may include but is not limited to a DRAM device.

[0031] The semiconductor device 200 includes a memory array 228. The memory array 228 is shown as including a plurality of memory banks. Figure 2 In the embodiment of FIG, the memory array 228 is shown to include eight memory banks BANK0 (memory bank 0) to BANK7 (memory bank 7). Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL and / BL, and a plurality of memory cells MC arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL and / BL. The selection of the word lines WL is performed by the row decoder 224, and the selection of the bit lines BL and / BL is performed by the column decoder 226. Figure 2 In the embodiment of the present invention, row decoder 224 includes a corresponding row decoder for each memory bank, and column decoder 226 includes a corresponding column decoder for each memory bank. Bit lines BL and / BL are coupled to corresponding sense amplifiers (SAMPs). Read data from bit line BL or / BL is amplified by sense amplifier SAMP and transmitted to read / write amplifier 230 via complementary local data line (LIOT / B), transfer gate (TG), and complementary main data line (MIOT / B). Conversely, write data output from read / write amplifier 230 is transmitted to sense amplifier SAMP via complementary main data line MIOT / B, transfer gate TG, and complementary local data line LIOT / B, and is written into memory cell MC coupled to bit line BL or / BL.

[0032] The semiconductor device 200 may use a plurality of external terminals including a bus coupled to a command and address bus (eg, Figure 1Device 200 includes a command and address (CA) terminal for receiving commands and addresses, a clock terminal for receiving clock signals CK_t and CK_c and data clock signals WCK_t and WCK_c and providing access data clock signals RDQS_t and RDQS_c, data terminals DQ and DM, an alert terminal ALERT for transmitting / receiving alert signals, and power supply terminals for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ. The various terminals of device 200 may generally be referred to as "pins" and may be coupled to conductive elements that carry signals to the pins. For example, there may be many CA pins, each of which may receive a signal as a voltage. Each CA pin may receive a signal in a serial format, where the voltage level varies over time to indicate different logic levels.

[0033] The clock terminal is supplied with external clock signals CK_t and CK_c, which are provided to input buffer 218. These external clock signals may be complementary. Input buffer 218 generates an internal clock ICLK based on the CK_t and CK_c clock signals. The ICLK clock is provided to command decoder 216 and to internal clock generator 220. Internal clock generator 220 provides various internal clock signals LCLK based on the ICLK clock. The LCLK clock signal may be used to time operations of various internal circuits. In some embodiments, a data clock (not shown) may also be provided to control the operation of data written to / read from device 200.

[0034] The CA terminal can be supplied with a memory address. The memory address supplied to the CA terminal is transmitted to the address decoder 214 via the command / address input circuit 212. The address decoder 214 receives the address and supplies the decoded row address XADD to the row decoder 224 and the decoded column address YADD to the column decoder 226. The CA terminal can be supplied with a command. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., a read command for performing a read operation and a write command for performing a write operation), mode register write and read commands for performing mode register write and read operations, and other commands and operations.

[0035] The command may be provided as an internal command signal through the command / address input circuit 212 to the command decoder 216. The command decoder 216 includes circuitry for decoding the internal command signal to generate various internal signals and commands for performing operations. For example, the command decoder 216 may provide a row command signal ACT to select a word line and a column command signal R / W to select a bit line.

[0036] When a read command is received and a row address and a column address are supplied in due time together with the read command, read data is read from the memory cells corresponding to the row address and column address in the memory array 228. The read command is received by the command decoder 216, which provides an internal command so that the read data from the memory array 228 is provided to the read / write amplifier 230. The read data is output to the outside from the data terminal DQ through the input / output circuit 232.

[0037] When a write command is received and the row and column addresses are supplied in conjunction with the write command, the write data supplied to the data terminals DQ is written to the memory cells corresponding to the row and column addresses in the memory array 228. A data mask may be supplied to the data terminals DM to mask portions of the data when writing to the memory. The write command is received by the command decoder 216, which provides an internal command so that the write data is received by the data receiver in the input / output circuit 232. The write data is supplied to the read / write amplifier 230 via the input / output circuit 232, and is supplied by the read / write amplifier 230 to the memory array 228 for writing into the memory cells MC.

[0038] Refresh control circuitry 222 may receive a refresh signal AREF. The memory device 200 may be caused to enter self-refresh mode via an external signal (e.g., an external refresh signal) or a command that causes the memory device 200 to enter replacement mode. Once in self-refresh mode, the memory device 200 may activate (e.g., pulse) the refresh signal AREF. In response to each activation of the refresh signal AREF, the memory device may refresh one or more word lines. For example, in response to activation of AREF, the refresh control circuitry 222 may provide several 'pumps,' each of which may be associated with one or more refresh addresses. The refresh addresses may be provided to the row decoder 224, which may refresh the word lines. Signal AREF may continue to be periodically generated until the memory device exits self-refresh mode (e.g., in response to a replace mode exit command). The refresh control circuitry 222 may use internal logic to generate the refresh addresses. For example, the refresh control circuitry 222 may include a sequencer that provides the refresh addresses from a refresh address sequence.

[0039] In some embodiments, the refresh control circuitry 222 may additionally identify memory cells at risk of experiencing faster memory decay rates and refresh those memory cells out of sequence. For example, repeated accesses to a given row ('row hammering') may cause nearby rows to experience faster information decay. The refresh control circuitry 222 may identify these victim rows (e.g., based on access patterns) and refresh them as part of a targeted refresh. In some embodiments, the refresh control circuitry 222 may mix sequential and targeted refreshes of rows.

[0040] The refresh control circuit 222 can also monitor the status of commands and accesses to determine whether an attack has occurred. For example, the refresh control circuit 222 can monitor the number (or rate) of rows that have been hammered or are close to being hammered to determine whether one or more types of attacks have occurred. If the refresh control circuit 222 determines that an attack has occurred, it can provide pause data PAUSE and an alert signal ALERT at an active level. The pause data PAUSE can be provided to the IO circuit 232 and then provided along the data terminal DQ. The alert signal can be provided to the ALERT pin.

[0041] The pause data may be a number indicating the length of time the memory is intended to be offline. For example, the pause data may be a binary number specifying the number of clock cycles. In response to providing the alert signal ALERT and the pause data PAUSE, the memory may enter a self-refresh mode. In some embodiments, the controller may provide a signal causing the memory 200 to enter the self-refresh mode. In some embodiments, the memory 200 may enter the self-refresh mode on its own. During the self-refresh mode, the refresh control circuit 222 may perform a refresh operation based on the type of attack detected.

[0042] In some embodiments, the refresh control circuit can be repeatedly refreshed on a bank-by-bank basis, and thus the refresh control circuit 222 can determine whether an attack has occurred on a bank-by-bank basis. Thus, in response to detecting an attack, the bank under attack can have its access operations suspended and can enter a self-refresh mode, while other banks can continue to receive access operations normally. In other examples, other subdivisions of memory attack monitoring and refresh can be used (e.g., portion-by-portion, tile-by-tile). In embodiments where only a portion of the memory 200 has its access operations suspended, the memory can provide identification information (e.g., along with the suspension data) indicating which portion(s) of the memory were under attack.

[0043] The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 234. The internal voltage generator circuit 234 generates various internal potentials VPP, VOD, VARY, VTARGET, VPERI, etc. based on the power supply potentials VDD and VSS supplied to the power supply terminals.

[0044] The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 232. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input / output circuit 232 so that power supply noise generated by the input / output circuit 232 does not propagate to other circuit blocks.

[0045] Figure 3 is a block diagram of a refresh control circuit according to some embodiments of the present disclosure. In some embodiments, the refresh control circuit 300 may be included in Figure 1 The refresh control circuit 112 and / or Figure 2 The refresh control circuit 222 of the refresh control circuit 300 can provide the refresh address RXADD and timing to be refreshed based on the refresh signal AREF. The refresh control circuit 300 can determine whether the refresh address RXADD is an auto-refresh address as part of an auto-refresh operation or a target refresh address based on the identified aggressor row. The refresh address RXADD can be provided to a row decoder (e.g., Figure 2 224), the row decoder can refresh one or more word lines of the memory array associated with the refresh address RXADD. In some embodiments, various other signals (not shown) can also be provided to indicate the details of the refresh operation to the row decoder.

[0046] Refresh control circuit 300 includes a refresh state control 302 that manages the timing of various refresh operations. Refresh state control 302 can perform a number of refresh operations in response to receiving an activation (e.g., a pulse) of signal AREF. For example, refresh state control 302 can generate a number of refresh 'pumps,' each associated with a refresh operation. Thus, for example, activation of AREF can generate four refresh pumps and four refresh operations. In other examples, other numbers of pumps can be used per AREF activation. In some embodiments, the number of pumps per AREF activation can be variable.

[0047] Each pump can be associated with either an auto-refresh operation, in which a word line is refreshed as part of a refresh sequence, or a targeted refresh operation, in which a victim row of an identified aggressor is refreshed. The refresh state control 302 can allocate the pumps between these two operations based on various criteria. For example, if four pumps are provided per AREF activation, two pumps can be used for auto-refresh operations and two pumps can be used for targeted refresh operations. Other modes can be used in other examples, and some modes can span multiple activations of AREF. The refresh state control can provide pump signals NREF (to indicate auto-refresh) and RHR (to indicate targeted refresh) to the refresh address generator 304. In some embodiments, there can be a common pump signal that is active for all pumps, and the state of the RHR signal can determine whether the pump is used for auto-refresh or targeted refresh signals.

[0048] The refresh address generator 304 may provide a refresh address RXADD. If the signal NREF is active, the refresh address generator 304 may provide an auto-refresh address based on an internal auto-refresh address generator. If the signal RHR is active, the refresh address generator 304 may generate a refresh address RXADD based on the aggressor address stored in the aggressor refresh queue 320. The auto-refresh address may be generated based on an address sequence. For example, a first self-refresh address may be provided, and then a second self-refresh address may be provided from the next entry in the sequence. In some embodiments, the sequence may be based on the numerical value of the refresh address. For example, the refresh address may be incremented to generate the next address in the sequence. In some embodiments, the refresh address may be associated with multiple word lines of the memory array, and the multiple word lines may be refreshed simultaneously. For example, a row address may be truncated, and all columns that share the truncated row address may be refreshed together (e.g., rows in each different segment of the memory). In other example embodiments, other methods of generating the auto-refresh address may be used.

[0049] The target refresh address may be based on a row address stored in an aggressor refresh queue 320. The aggressor refresh queue 320 may include a set of address registers 322, each of which stores a row address identified as an aggressor by the aggressor detector circuit 310. When a target refresh operation is invoked (e.g., by an active signal RHR), the refresh address generator 304 may retrieve the address RHR_XADD from one of the address registers 322. The aggressor refresh queue 320 may include logic that determines the order in which addresses are retrieved for refresh.

[0050] The refresh address generator 304 may generate one or more refresh addresses RXADD based on the retrieved aggressor address. In some embodiments, the refresh addresses may include word lines adjacent to the aggressor word line (e.g., R+ / -1). In some embodiments, the refresh addresses may include word lines further from the aggressor address (e.g., R+ / -2). In some embodiments, the refresh address generator 304 may refresh the more distant victim at a slower rate than the more recent victim.

[0051] Aggressor detector circuit 310 may receive a row address XADD along a row address bus. Based on row addresses received over time, aggressor detector 310 may determine whether a given address is an aggressor. Example aggressor detector 310 is shown as including a number of count values ​​312. Count values ​​312 may each represent accesses to one or more row addresses. For example, a given count value 312 may represent the number of times a given row address has been provided along the row address bus. Aggressor detector 310 may compare the count value with a threshold to determine whether the address is an aggressor address. For example, if the count value is greater than the threshold, the row address associated with the count value may be determined to be an aggressor and may be stored in aggressor refresh queue 320 so that its victim can be refreshed. When an aggressor is detected, aggressor detector 310 may provide an aggressor signal AGGR at an active level, which may cause aggressor refresh queue 320 to latch the value of row address XADD off the row address bus and into one of address registers 322.

[0052] In some embodiments, the refresh control circuit 300 can sample the value of the row address rather than responding to every row address across the row address bus. The refresh control circuit 300 can include a sampling circuit that can activate a sampling signal with regular timing, random timing, timing based on one or more other signals, semi-random timing, pseudo-random timing, or a combination thereof. When the sampling signal is active, the aggressor detector 310 can respond to the row address.

[0053] The refresh control circuit 300 may include an attack detector circuit 306 that can monitor the state of the refresh control circuit 300 to determine when an attack is occurring. When the attack detector 306 determines that an attack is ongoing, it may provide an attack signal ATK at an active level. The attack signal may also indicate which type of attack is occurring if the attack detector 306 detects more than one type of attack. In some embodiments, there may be multiple attack signals, each of which may be active to indicate a different type of attack is occurring. Figure 4 The instance attack detector is described in more detail in

[15] .

[0054] An example attack may include a waterfall attack, in which the count value 312 remains close to, but just below, a hammering threshold that would cause the address associated with the count value to be identified as an aggressor. Once a large number of count values ​​312 are just below the hammering threshold, further accesses may be provided to push the count value 312 above the hammering threshold. The count value may be an overwhelming number of aggressor addresses that the refresh control 300 may not be able to process in a timely manner. The attack detector may monitor the count value 312 and, based on the count value 312, signal that a waterfall attack has occurred. For example, the attack detector may track a capacity count based on the number of count values ​​312 above a first threshold, the first threshold being less than the hammering threshold. When the capacity count rises above a second threshold, the attack detector 306 may signal that a waterfall attack has occurred.

[0055] An example attack may include a refresh queue overflow attack. In such an attack, a row may be hammered so quickly that the aggressor refresh queue 320 fills faster than it can be emptied. For example, if the address register 322 stores a maximum number of M different aggressor addresses and the aggressor detector 310 provides the signal AGGR, addresses may be lost due to the presence of M+1 identified aggressors. The attack detector 306 may monitor the state of the address register 322 and may indicate that an overflow attack has occurred based on the state of the address register 322. For example, when the address register 322 stores the maximum number of addresses, the aggressor refresh queue 320 may provide a queue full signal FULL at an active level. In response to another detected aggressor while the signal FULL is active (e.g., the signal AGGR is active), the attack detector 306 may indicate that a refresh queue overflow attack has occurred.

[0056] The refresh control circuit 300 may include an alert logic circuit 308, which activates an alert signal ALERT and generates a pause data PAUSE in response to the attack signal ATK indicating that an attack occurs. The alert logic circuit 308 may include a pause calculation circuit 309 (eg, Figure 1 The pause calculation circuit 309 may generate pause data PAUSE. The alert signal ALERT may be provided to the ALERT bus of the memory. The pause data PAUSE may indicate the length of time that operations on the memory should be paused. For example, the pause data PAUSE may be a binary number specifying the number of clock cycles. The pause calculation circuit 309 may be a component of the alert logic 308, or may be a separate component that receives the attack signal ATK and directly provides the pause data PAUSE.

[0057] The pause calculation circuit 309 may generate different values ​​for the pause data PAUSE depending on the type of attack indicated by the attack detector 306. For example, a first type of attack (e.g., a waterfall attack) may generate a first value for the pause data PAUSE, while a second type of attack (e.g., a refresh queue overflow attack) may generate a second value for the pause data PAUSE. In some embodiments, the PAUSE value for a waterfall attack may be longer than the PAUSE value for an overflow attack. In some embodiments, the pause calculation circuit 309 may also respond to the number of times the attack signal (or a particular type of attack signal) is provided. For example, if the signal indicating an overflow attack is provided a threshold number of times, the pause calculation circuit 309 may provide pause data PAUSE of a longer duration than when a lesser overflow attack is indicated. In some embodiments, if an overflow attack is detected more than the threshold number of times, the pause calculation circuit 309 may set the pause data PAUSE to the same duration as if a waterfall attack had been detected. The pause data PAUSE may be stored in a memory for retrieval by the controller. In some embodiments, various other signals (e.g., ATK) may be provided to a component of the memory to indicate an impending operation pause.

[0058] In some embodiments, the refresh state control 302 may also respond to a detected attack (e.g., it may respond to signals ATK, ALERT, PAUSE, or a combination thereof) to cause the memory to enter a refresh mode while suspending operations from the controller. For example, in response to the attack detector 306 indicating a refresh queue overflow attack, the refresh state control circuit 302 may enter a refresh mode in which a targeted refresh operation is performed until all addresses in the address register 322 have their victims refreshed. The 'extra' address that triggered the overflow may also have its victim refreshed because it may still be present along the row address bus. In response to the attack detector 306 indicating a waterfall attack, the refresh state control 302 may enter a mode in which one or more of the addresses associated with the counters 312 are refreshed. The refresh state control 302 may, for example, refresh every address associated with any counter 312 that is above a second threshold (e.g., near a hammer threshold). In some embodiments, in response to the attack, the refresh state control 302 may enter a mode in which all word lines are refreshed. In some embodiments, refresh state control 302 may enter a mode in which more word lines are refreshed than are identified as aggressors or nearly identified as aggressors. In some embodiments, a refresh operation may take all or part of the time indicated by pause data PAUSE.

[0059] Figure 4 is a block diagram of an attack detector circuit according to some embodiments of the present disclosure. In some embodiments, the attack detector 400 may be included in Figure 3In the attack detector circuit 306. Figure 4 Also shown in FIG. 4 is an example aggressor detector 410, which in some embodiments may be included in Figure 3 In the intruder detector 310.

[0060] Attack detector 400 includes a first threshold comparator 402. First threshold comparator 402 provides a signal INC at an active level for each count value 412 that is above a threshold THi. Threshold THi may be lower than a hammer threshold used to determine whether a count value is associated with one or more aggressor addresses. For example, if the count values ​​are 4001, 3988, 4996, and 2043, the hammer threshold may be 5000, the threshold THi may have a value of 4000, and first comparator 402 may provide two activations of signal INC. These values ​​are provided by way of example only, and other values ​​may be used in other exemplary embodiments.

[0061] In some embodiments, the threshold value THi used by the first comparator can be based on the manner in which the count value 412 is stored. For example, the count value 412 can be stored as an N-bit number. To simplify the operation of the first comparator 402, the first comparator can provide activation of the signal INC any time the next most significant bit (e.g., bit N-1) first becomes logic high in the count value.

[0062] In response to activation of signal INC, capacity counter circuit 404 may change the value of stored capacity count value CNT. For example, attack counter circuit 404 may increment capacity count value CNT. In response to activation of signal RHR_XADD indicating that an address from a target refresh queue (e.g., 320) is provided to the refresh address generator, attack counter circuit 404 may change the value of CNT in different directions. For example, attack counter circuit 404 may decrease value CNT in response to activation of RHR_XADD. In some embodiments, in response to signal RHR_XADD, value CNT may be decreased by a certain amount based on one or more thresholds (e.g., THi, THj, and / or hammer thresholds).

[0063] In some embodiments, the attack counter 404 may store multiple count values ​​(e.g., CNT0, CNT1, etc.) that can be used to determine the value of the total capacity count value CNT. For example, the attack counter 404 may periodically switch between a first count value CNT0 and a second count value CNT1 using the signals INC and RHR_XADD. The total count value CNT may then be the difference between CNT0 and CNT1 and may represent the change in the count value over a given period of time (e.g., the period over which the attack counter 404 switches count values).

[0064] The capacity count value CNT may be provided to a second threshold comparator 406, which may compare the count value CNT with a second threshold value THj. If the count value CNT is greater than the second threshold value THj, the second comparator 406 may provide an attack signal ATK_waterfall at an active level, indicating that a waterfall attack has occurred. The signal ATK_waterfall may be reset to an inactive level when operations on the memory are suspended and / or when the memory is refreshed to a point where the count value CNT is no longer greater than the threshold value THj.

[0065] Attack detector 400 may also monitor for overflow attacks. For example, overflow logic circuit 408 may monitor for overflows from a target refresh queue (e.g., Figure 3 320) and signals FULL and AGGR of aggressor detector 410. Signal FULL may be active when all address registers of target refresh queue 320 store unrefreshed aggressor addresses. Signal AGGR may be active when a new aggressor address is identified. In response to both signals being active, overflow logic 408 may provide signal ATK_overflow at an active level, which may indicate that an overflow attack has occurred. In some embodiments, overflow logic 408 may be an AND gate.

[0066] In some embodiments, one or more of the thresholds THi, THj, and / or the hammer threshold can be preset values, programmable values, or a combination thereof in memory. In some embodiments, one or more of the thresholds can change over time. For example, the memory can include a random number generator (or some other source of randomness) that can periodically change the value of one or more thresholds. This randomness can make it more difficult to predict the behavior of the memory during an attack.

[0067] In some embodiments, attack detector 400 may also trigger an attack signal based on the number and / or rate of detected attacks. For example, attack detector 400 may count the number of times the ATK_overflow signal is activated. The overflow count may be periodically reset. In this way, the overflow count may serve as a measure of the rate at which overflow attacks are detected. If the overflow count rises above a threshold, attack detector 400 may trigger an attack signal, which may be associated with pause data of longer duration than the pause data typically triggered by activation of ATK_overflow. In some embodiments, to simplify signaling, an overflow count rising above a threshold may cause activation of signal ATK_waterfall.

[0068] Figure 5 is a flow chart of a method for detecting an attack and suspending operation according to some embodiments of the present disclosure. In some embodiments, the method 500 may be Figures 1 to 4Although certain steps and operations are shown in method 500, it should be understood that other example methods may include different steps, steps performed in a different order, repeated steps, or a combination thereof.

[0069] Method 500 may include block 510, which depicts sending a command and address to a memory. Figure 1 102) can send commands and addresses along the command-address (CA) bus. The commands and addresses can be associated with access operations to the memory. The command can specify the type of operation to be performed, and the address can specify one or more memory cells associated with the operation. For example, a row address can specify a row of memory, a column address can specify a column of memory, and a bank address can specify a bank of memory.

[0070] Block 510 may generally be followed by block 520, which describes determining that the memory is under attack based on the address. The attack may be intentional (e.g., caused by a malicious actor) or may be unintentional (e.g., caused by an operation not intentionally intended to cause a problem in the memory). The memory may include attack detector circuitry that may monitor commands and / or addresses received by the memory to determine whether one or more types of attacks have occurred.

[0071] The attack detector can determine whether a queue overflow attack has occurred. The memory can identify the aggressor address. For example, the memory can count accesses to various row addresses and check to see if any of the counts rise above a hammering threshold. The memory can, for example, store the identified aggressor addresses in a target refresh queue. When the number of stored identified aggressor addresses rises above a threshold, the queue can provide a full signal at an active level. In some embodiments, the threshold can represent a maximum capacity of the target refresh queue. When additional addresses are to be stored in the queue (e.g., based on identifying a new aggressor address) and the full signal is at an active level, the attack detector can determine that an overflow attack has occurred.

[0072] The attack detector can determine whether a waterfall attack occurs. The memory can change multiple count values ​​(e.g., Figure 3 The attack detector may determine a volumetric count based on the number of the plurality of count values ​​that are above a first threshold. The attack detector may determine that a waterfall attack has occurred based on the volumetric count rising above a second threshold.

[0073] Block 520 may typically be followed by block 530, which describes providing an alert signal and suspend data from the memory in response to determining that the memory is under attack. The alert signal may indicate a problem has occurred in the memory. The controller may perform a read operation to retrieve the suspend data. In some embodiments where multiple memories are coupled to the same controller, the controller may also determine which memory is under attack. The alert signal may be provided along an alert bus (e.g., an alert pin). The suspend data may be provided along a data bus. For example, the controller may perform a read operation to retrieve the suspend data in response to the alert signal.

[0074] Block 530 may typically be followed by block 540, which describes pausing the sending of commands and addresses for a certain length of time based on the pause data. The pause data may specify a length of time (e.g., in clock cycles). The controller may suspend operations on the memory for the length of time specified in the pause data. The memory may consider the type of attack detected when setting the length of time specified by the pause data. For example, the pause data generated in response to an overflow attack may specify a shorter duration than the pause data generated in response to a waterfall attack.

[0075] When the command and address are paused, the memory can enter a refresh mode to refresh the word lines of the memory. For example, the memory can refresh enough word lines associated with the type of attack detected. In some embodiments, the length of time specified by the pause data can be based in part on the length of time it will take to perform the refresh.

[0076] It should be understood that any of the examples, embodiments, or processes described herein may be combined with or separated from one or more other examples, embodiments, and / or processes and / or performed in a separate device or device portion according to the systems, devices, and methods of the present invention.

[0077] Finally, the above discussion is intended to be merely illustrative of the present invention system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the present invention system has been described in detail with reference to exemplary embodiments, it should be understood that those skilled in the art may devise numerous modifications and alternative embodiments without departing from the broader and intended spirit and scope of the present invention system as set forth in the appended claims. The specification and drawings are, therefore, to be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A semiconductor system comprising: a controller configured to provide commands and addresses along a command-address bus; as well as a memory configured to monitor the address and provide an alert signal along an alert bus and suspend data along a data bus based on the monitored address, In response to the alert signal and the pause data, the controller is configured to stop providing the command and the address to the memory for a length of time specified by the pause data.

2. The semiconductor system of claim 1 , wherein the memory comprises a refresh control circuit configured to store a plurality of count values ​​each associated with one or more of the provided addresses, and configured to store a selected one of the provided addresses in a target refresh queue based on the count value associated with the selected one of the provided addresses being above a hammer threshold.

3. The semiconductor system of claim 2 , wherein the refresh control circuit is further configured to store a second count value based on a number of the plurality of count values ​​above a first threshold different from the hammer threshold, and wherein the memory is configured to provide the alert signal and the pause data in response to the second count value rising above a second threshold. 4 . The semiconductor system of claim 2 , wherein the memory is configured to provide the alert signal and the suspend data in response to the target refresh queue being full and additional ones of the provided addresses need to be stored in the target refresh queue. 5 . The semiconductor system of claim 1 , wherein in response to receiving the alert signal, the controller performs a read operation on the memory to retrieve the suspend data. 6 . The semiconductor system according to claim 1 , wherein the memory is configured to enter a self-refresh mode after the alert signal and the suspend data are provided.

7. The semiconductor system of claim 1 , wherein the memory comprises a plurality of memory banks, and wherein the alert signal and the suspend data are associated with a selected memory bank among the plurality of memory banks, and wherein in response to the alert signal and the suspend data, the controller is configured to stop sending the command and the address to the selected memory bank among the plurality of memory banks while still sending the command and the address to other memory banks among the plurality of memory banks.

8. An electronic device comprising: a flush queue configured to store a plurality of addresses, wherein the flush queue is configured to provide a full signal at an active level when a number of the plurality of addresses is above a threshold; an attack detector configured to provide an attack signal in response to receiving a next address to be stored while the full signal is at the active level; as well as Alert logic is configured to provide an alert signal at an active level to an alert terminal and provide pause data to a data terminal in response to the attack signal being at the active level.

9. The electronic device of claim 8 , further comprising an aggressor detector circuit comprising a plurality of count values ​​each associated with one or more addresses, wherein the attack detector is configured to count a number of the plurality of count values ​​that are above a first threshold, and wherein when the number is above a second threshold, the attack detector is configured to provide the attack signal at the active level.

10. The electronic device of claim 9 , wherein the alert logic is configured to generate a first value for the pause data in response to the attack signal being at the activity level based on receiving the next address when the full signal is at the activity level, and is configured to generate a second value for the pause data in response to the attack signal being at the activity level based on the number being above the second threshold.

11. The electronic device of claim 8 , further comprising a refresh state control circuit configured to refresh victim word lines associated with the plurality of addresses and the next address in the refresh queue in response to a suspension of operation based on the alert signal and the suspend data being at the active level. 12 . The electronic device according to claim 8 , wherein the electronic device is a memory, and wherein the pause data represents an amount of time that the memory wants operations from a controller to be paused. 13 . The electronic device of claim 8 , further comprising a pause calculation circuit configured to generate the pause data in response to the attack signal. 14 . The electronic device of claim 13 , wherein the pause calculation circuit is configured to set the value of the pause data in response to a type of the attack signal, a number of times the attack signal has been provided, or a combination thereof.

15. An electronic device comprising: an aggressor detector circuit configured to store a plurality of count values, each count value associated with an access to one or more row addresses; an attack detector circuit configured to store a capacity count based on a number of the plurality of count values ​​above a threshold, wherein the threshold is less than a hammer threshold; a comparator circuit configured to provide an attack signal at an active level based on a value of the capacity count; An alert logic circuit is configured to provide pause data to a data terminal and an alert signal to an alert terminal in response to the attack signal being at the active level.

16. The electronic device of claim 15 , further comprising a refresh queue configured to store a plurality of aggressor addresses, wherein the refresh queue is configured to provide a full signal at an active level in response to a number of the plurality of aggressor addresses exceeding a threshold, and wherein the attack detector circuit is further configured to provide a second attack signal at an active level in response to receiving a next address to be stored while the full signal is at the active level. 17 . The electronic device of claim 16 , wherein the alert logic is configured to generate a first value of the pause data in response to the attack signal being active, and to generate a second value of the pause data in response to the second attack signal being active.

18. The electronic device of claim 16, wherein the capacity count changes in a first direction in response to one of the plurality of count values ​​rising above the threshold, and changes in a second direction in response to one of the plurality of aggressor addresses being provided for refresh.

19. The electronic device of claim 15, wherein the comparator circuit is configured to provide the attack signal at the active level in response to the capacity count being above a second threshold.

20. The electronic device of claim 15 , further comprising a refresh state control circuit configured to refresh a victim of any word line associated with one of the plurality of stored count values ​​exceeding the threshold in response to a suspension of operation based on the alert signal at the active level and the suspension data.

21. The electronic device of claim 15 , wherein the attack detector comprises a first count value and a second count value, each of which changes based on which of the plurality of count values ​​is above the threshold in different time periods, and wherein the capacity count is based on a difference between the first count value and the second count value.

22. The electronic device of claim 15, further comprising a pause calculation circuit configured to generate the pause data in response to the attack signal being at the active level.

23. A method for memory operation, comprising: Send commands and addresses to memory; determining, based on the address, that the memory is attacked; providing an alert signal and suspend data from the memory in response to the determination that the memory is under attack; The sending of the command and address is suspended for the length of time specified by the suspension data.

24. The method of claim 23, further comprising: Identify the offender's address Storing the aggressor's address; providing a full signal at an active level when the number of stored addresses is above a threshold; as well as The memory is determined to be under attack based on identifying an aggressor address while the full signal is at the active level.

25. The method of claim 23, further comprising: changing a selected count of a plurality of counts based on the address; determining a capacity count based on a number of the plurality of counts above a first threshold; as well as Based on the capacity count rising above a second threshold, it is determined that the memory is under attack.

26. The method of claim 23, further comprising: Determine the type of attack; as well as The length of time specified by the pause data is set based on the type of the attack.

27. The method of claim 23, further comprising placing the memory into a refresh mode while suspending the commands and addresses.

28. The method of claim 23, further comprising reading the pause data along a data bus in response to the alert signal being at an active level.

29. The method of claim 23, further comprising suspending sending of the commands and addresses to a selected bank of the memory while continuing to send the commands and the addresses to other banks of the memory.

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