Semiconductor element and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor element and a method for preparing the semiconductor element. The semiconductor element has a substrate, a dielectric layer, a plug, and a landing pad of a conductive polymer; the dielectric layer is disposed on the substrate; the plug is disposed in the dielectric layer; and the landing pad of the conductive polymer is disposed on the dielectric layer. The method includes: providing a substrate; forming a dielectric layer having a plug on the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protrusion of the plug; forming a conductive polymer layer to cover the dielectric layer and the protrusion; and performing a heat treatment to form a landing pad on the dielectric layer in a self-aligned manner. The landing pad of the conductive polymer includes a protrusion of the plug, a first silicide layer, and a second silicide layer; the first silicide layer is disposed on the protrusion; and the second silicide layer is disposed on a sidewall of the protrusion.

Description

Technical Field

[0001] This application claims priority to and the benefit of U.S. regular application No. 16 / 992,986, filed on August 13, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device and a method for preparing the semiconductor device, and more particularly to a semiconductor device having a landing pad of a conductive polymer and a method for preparing the semiconductor device. Background Art

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor device sizes are steadily shrinking to meet the increasing demand for computing power. However, this reduction in size creates a variety of challenges. Consequently, achieving improvements in quality, yield, and reliability remains a constant challenge.

[0004] The above description of “prior art” is merely to provide background technology, and does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the Invention

[0005] One embodiment of the present disclosure provides a semiconductor device, comprising a substrate; a dielectric layer disposed on the substrate; a plug disposed in the dielectric layer, wherein the plug has a protrusion having a first width; and a landing pad disposed on the dielectric layer, wherein the landing pad comprises a conductive polymer and has a second width that is greater than the first width of the protrusion.

[0006] In some embodiments of the present disclosure, the landing pad further includes a barrier layer located between the protrusion and the second silicide layer.

[0007] In some embodiments of the present disclosure, the conductive polymer layer includes graphene.

[0008] In some embodiments of the present disclosure, the conductive polymer layer comprises a conjugated polymer.

[0009] In some embodiments of the present disclosure, the conjugated polymer comprises polystyrene sulfonate (PEDOT) or polyaniline (PANI).

[0010] In some embodiments of the present disclosure, the semiconductor device further includes a capacitor contact point located on the substrate, the landing pad is disposed on the capacitor contact point, the capacitor contact point has a neck and a head, the head is located on the neck, wherein an upper width of the head is greater than an upper width of the neck, and the second width of the landing pad is greater than the upper width of the head.

[0011] In some embodiments of the present disclosure, the upper width of the head is greater than the lower width of the head.

[0012] In some embodiments of the present disclosure, the upper width of the neck is substantially the same as the lower width of the head.

[0013] In some embodiments of the present disclosure, the head has a curved sidewall.

[0014] In some embodiments of the present disclosure, the head has a tapered profile.

[0015] In some embodiments of the present disclosure, the semiconductor device further includes: a bit line contact and a bit line, the bit line contact being disposed on the substrate, the bit line being disposed on the bit line contact, wherein the bit line is an undulating stripe extending between two adjacent capacitor contact points on the substrate; and a capacitor structure disposed on the landing pad.

[0016] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device. The method includes: providing a substrate; forming a dielectric layer having a plug on the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protrusion of the plug; forming a conductive polymer layer to cover the dielectric layer and the protrusion, wherein the protrusion has a first width; and removing a portion of the conductive polymer layer to form a landing pad on the dielectric layer, wherein the landing pad has a second width that is greater than the first width of the protrusion.

[0017] In some embodiments of the present disclosure, the method for preparing the semiconductor device further includes: forming a barrier layer between the plug and the dielectric layer, and the etching process removes a portion of the dielectric layer to expose the protrusion of the plug and an upper portion of the barrier layer.

[0018] In some embodiments of the present disclosure, the step of removing the conductive polymer layer includes: aligning a mask having a patterned hole on the conductive polymer layer; and radiating multiple charged particle beams through the patterned hole of the mask to form a patterned conductive polymer.

[0019] In some embodiments of the present disclosure, the conductive polymer layer is made of a conjugated polymer.

[0020] In some embodiments of the present disclosure, a radiation region of the conductive polymer layer forms an isolation polymer layer, and the charged particle beam is one of a plurality of electrons and a plurality of ions.

[0021] In some embodiments of the present disclosure, the mask is a shadow mask, and the ions are a material of a plurality of ions selected from the following group: hydrogen (H), lithium (Li), sodium (Na), potassium (K), rubidium (Rb), firthium (Fr), chlorine (Cl), bromine (Br), iodine (I), astatine (At), neon (Ne), krypton (Kr), xenon (Xe), radon (Rn), helium (He), argon (Ar), nitrogen (N), oxygen (O), and cesium (Cs).

[0022] In some embodiments of the present disclosure, the method for preparing the semiconductor device further includes: forming a capacitor contact point on the substrate, and the landing pad is formed on the capacitor contact point; wherein the capacitor contact point has a neck and a head, the head is located on the neck, and an upper width of the head is larger than an upper width of the neck.

[0023] In some embodiments of the present disclosure, forming the capacitor contact point includes: forming a contact hole in a dielectric stack, the dielectric stack having a first layer and a second layer, the second layer being located on the first layer; removing a portion of the second layer surrounding the contact hole to form a transformed hole, the transformed hole having a narrow portion and a wide portion, the narrow portion being in the first layer and the wide portion being in the second layer; and filling a conductive material into the transformed hole.

[0024] In some embodiments of the present disclosure, the contact hole is integrally formed with a bit line trench in the second layer, and the method further includes: filling the bit line trench and a lower portion of the contact point with a filling material; wherein the removal of the portion of the second layer surrounding the contact hole is performed after filling the lower portion of the contact hole with a sacrificial material.

[0025] The width of the landing pad is larger than that of the capacitor plug; therefore, misalignment between the sequentially formed capacitor structure and the landing pad can be significantly resolved.

[0026] Furthermore, since the capacitor contact point has a neck and a head and a tapered profile, misalignment between the subsequently formed capacitor structure and the capacitor contact point can be significantly resolved. Furthermore, the cover layer can reduce defects formed in the semiconductor device, thereby correspondingly improving the yield of the semiconductor device.

[0027] The above has provided a fairly broad overview of the technical features and advantages of the present disclosure, allowing for a better understanding of the detailed description of the present disclosure below. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure pertains that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same purposes as those of the present disclosure. It should also be understood by those skilled in the art to which the present disclosure pertains that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] A more complete understanding of the disclosure of this application may be obtained by referring to the embodiments and claims in conjunction with the drawings, in which like reference numerals refer to like elements.

[0029] Figure 1 The figure is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0030] Figure 2 and Figure 3 The figure is a cross-sectional diagram of a partial process for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0031] Figure 4 Based on Figure 3 Schematic top view of a semiconductor component.

[0032] Figures 5 to 7 The figure is a cross-sectional diagram of a partial process for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0033] Figure 8 Based on Figure 7 Schematic top view of a semiconductor component.

[0034] Figure 9 The figure is a cross-sectional diagram of a partial process for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0035] Figure 10 The figure is a cross-sectional diagram of a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0036] Figure 11 Based on Figure 10 Schematic top view of a semiconductor component.

[0037] Figure 12 The figure is a cross-sectional diagram of a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0038] Figure 13 Based on Figure 12 Schematic top view of a semiconductor component.

[0039] Figure 14 The figure is a cross-sectional diagram of a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0040] Figure 15 Based on Figure 14 Schematic top view of a semiconductor component.

[0041] Figure 16 The figure is a cross-sectional diagram of a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0042] Figure 17 Based on Figure 16 Schematic top view of a semiconductor component.

[0043] Figure 18 The figure is a cross-sectional diagram of a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0044] Figure 19 Based on Figure 18 Schematic top view of a semiconductor component.

[0045] Figure 20 The figure is a cross-sectional diagram of a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0046] Figure 21 Based on Figure 20 Schematic top view of a semiconductor component.

[0047] Figures 22 to 27 The figure is a cross-sectional diagram of a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0048] Figure 28 to Figure 29 The figure is a cross-sectional diagram of a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0049] Figures 30 to 33 The figure is a cross-sectional diagram of a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0050] Figure 34 Based on Figure 33 Schematic top view of a semiconductor component.

[0051] Figures 35 to 38 The figure is a cross-sectional diagram of a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0052] The description of the accompanying drawings is as follows:

[0053] 101: Base

[0054] 103: Insulation structure

[0055] 105: Active Zone

[0056] 201: Character line

[0057] 203: Lower level

[0058] 205: Middle layer

[0059] 207: Upper

[0060] 209: Groove opening

[0061] 211: Charged particle beam

[0062] 213: Mask

[0063] 213': Patterned holes

[0064] 301: first doped region

[0065] 303: Second doping region

[0066] 311: Conductive polymer layer

[0067] 312: Photoresist pattern

[0068] 313: Conjugated conductive polymer layer (patterned conductive polymer)

[0069] 313A: Conductive block

[0070] 313B: Isolation block

[0071] 401: Touchpoint

[0072] 402: Contact hole

[0073] 402-1: Filling Material

[0074] 403: Capacitor contact point

[0075] 403-1: Neck

[0076] 403-2: Head

[0077] 403-3: Curved sidewalls

[0078] 404: Conversion hole

[0079] 404-1: Narrow

[0080] 404-2: Wide

[0081] 405: Bit line contact

[0082] 407: First covering layer

[0083] 408: Bit line trench opening

[0084] 408-1: Filling Material

[0085] 409: Bit line

[0086] 411: Capacitor Embolism

[0087] 411A: Protrusion

[0088] 412: Barrier layer

[0089] 412A: Upper part

[0090] 413: Conductive vias

[0091] 415: First conductive layer

[0092] 417: Second covering layer

[0093] 419: Overlay

[0094] 501: Capacitor structure

[0095] 503: Capacitor groove

[0096] 505: Lower electrode

[0097] 507: Capacitor isolation layer

[0098] 509: Upper electrode

[0099] 801: First isolation film

[0100] 803: Second isolation membrane

[0101] 805: The third isolation membrane

[0102] 807: Fourth isolation membrane

[0103] 808: Conductive polymer layer

[0104] 808A: First interstitial

[0105] 808B: Second interstitial

[0106] 809: The fifth isolation membrane

[0107] 810: Landing Pad

[0108] 810A: Landing Pad

[0109] 811: Sixth isolation membrane

[0110] 813: Seventh Isolation Membrane

[0111] 814: Fifth isolation membrane

[0112] 816: Internal connection plug

[0113] 10: Method

[0114] S11: Steps

[0115] S13: Steps

[0116] S15: Steps

[0117] S17: Steps

[0118] S19: Steps

[0119] W1: width

[0120] W2: width

[0121] W3: Width

[0122] W4: Width

[0123] W5: width

[0124] X: Direction

[0125] Z: Direction DETAILED DESCRIPTION

[0126] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, the description of a first component formed on a second component may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is for simplicity and clarity, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0127] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0128] It should be understood that when forming a component on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0129] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0130] Unless the context indicates otherwise, as used herein, terms such as "same," "equal," "planar," or "coplanar" when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but rather include nearly identical orientation, layout, location, shape, size, amount, or other measure within acceptable variations that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, terms such as substantially the same, substantially equal, or substantially planar mean exactly the same, equal, or planar, or they may be the same, equal, or planar within an acceptable variance, where, for example, the acceptable variance may occur due to the manufacturing process.

[0131] In this disclosure, a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics, and an electro-optical device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of semiconductor devices.

[0132] It should be understood that in the description of the present disclosure, above (or up) is the direction corresponding to the Z-direction arrow, and below (or down) is the relative direction corresponding to the Z-direction arrow.

[0133] Figure 1 The figure is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 2 and Figure 3 The figure is a cross-sectional diagram of a partial process for manufacturing a semiconductor device according to one embodiment of the present disclosure. Figure 4 Based on Figure 3 Schematic top view of a semiconductor component.

[0134] Please refer to Figure 1 and Figure 2 In step S11, a substrate 101 is provided, and a plurality of first regions and second regions are formed in the substrate. For example, the substrate 101 can be made of the following materials: silicon, doped silicon, silicon germanium, silicon on insulator, silicon on sapphire, silicon germanium on insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, gallium arsenide phosphide, indium phosphide, or indium gallium phosphide.

[0135] Please refer to Figure 3 and Figure 4 , multiple insulating structures 103 can be formed in the substrate 101. In the cross-sectional view, the multiple insulating structures 103 are separated from each other and define multiple active regions 105. For example, the multiple insulating structures 103 can be made of an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluoride-dopedsilicate or the like. In the top view, the multiple active regions 105 can extend in a direction that is inclined relative to a direction X. It should be understood that in the present disclosure, silicon oxynitride represents a substance containing silicon, nitrogen and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide represents a substance containing silicon, oxygen and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0136] Figures 5 to 7 The figure is a cross-sectional diagram of a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 8 Based on Figure 7 Schematic top view of a semiconductor component.

[0137] Please refer to Figure 1 and Figures 5 to 8 , a plurality of word lines 201 may be formed in the substrate 101. In the embodiment described, the plurality of word lines 201 may extend along a direction X. Each word line 201 includes a lower layer 203, a middle layer 205, an upper layer 207, and a trench opening 209. Please refer to Figure 5In the embodiment described, a photolithography process may be used to pattern the substrate 101 to define the locations of the plurality of trench openings 209. An etching process, such as an anisotropic dry etching process, may be performed to form the plurality of trench openings 209 in the substrate 101. Figure 6 After the etching process, a plurality of lower layers 203 may be formed and adhered to the sidewalls of the plurality of trench openings 203 and the bottoms of the plurality of trench openings 209. For example, the plurality of lower layers 203 may be made of the following materials: silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like.

[0138] Please refer to Figure 7 and Figure 8 , multiple intermediate layers 205 can be formed correspondingly on the multiple lower layers 203. Each upper surface of the multiple intermediate layers 205 can be lower than an upper surface of the substrate 101. For example, the multiple intermediate layers 205 can be made of the following materials: doped polysilicon, metal material or metal silicide. For example, the metal silicide can be nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide or the like. Multiple upper layers 207 can be formed correspondingly on the multiple intermediate layers 205. Each upper surface of the multiple upper layers 207 can be located at the same vertical plane as the upper surface of the substrate 101. For example, the multiple upper layers 207 can be made of the following materials: silicon oxide, silicon nitride oxide, silicon nitride oxide, silicon nitride or the like.

[0139] Figure 9 The figure is a cross-sectional diagram of a partial process for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0140] Please refer to Figure 1 and Figure 9 , multiple first regions and second regions can be formed in multiple active regions 105 of the substrate 101. The multiple doping regions may include a first doping region 301 and multiple second doping regions 303. The first doping region 301 is arranged between adjacent pairs of word lines 201. The second doping regions 303 are respectively arranged between multiple insulating structures 103 and multiple word lines 201. The first doping region 301 and the second doping region 303 are respectively doped with a dopant, such as phosphorus, arsenic or antimony. The first doping region 301 and the second doping region 303 each have a doping concentration between 1E17 atoms / cm 3 and 1E19 atoms / cm 3 between.

[0141] Figure 10 The figure is a cross-sectional diagram of a partial process for manufacturing a semiconductor device according to one embodiment of the present disclosure. Figure 11 Based on Figure 10 Schematic top view of a semiconductor component.

[0142] Please refer to Figure 10 and Figure 11 , a plurality of bit line contacts may be formed on the substrate. For example, a first isolation film 801 may be formed on the substrate 101. For example, the first isolation film 801 may be made of the following materials: silicon nitride, silicon oxide, silicon oxynitride, undoped silica glass, borosilica glass, phosphosilica glass, borophosphosilica glass, or a combination thereof, but is not limited thereto. A plurality of contact points 401 may be formed in the first isolation film 801. A lithography process may be used to pattern the first isolation film 801 to define the positions of the plurality of contact points 401. After the lithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a plurality of openings in the first isolation film 801. After the etching process, a conductive material such as aluminum, copper, tungsten, cobalt, or another suitable metal or metal alloy may be deposited in the plurality of openings by a metallization process, for example, such as chemical vapor deposition, physical vapor deposition, sputtering, or the like, to form a plurality of contacts 401. Following the metallization process, a planarization process such as chemical mechanical polishing may be performed to remove excess deposited material and provide a substantially planar surface for subsequent processing steps.

[0143] In some embodiments, please refer to Figure 10 and Figure 11 Contact 401 is disposed on and electrically connected to first doped region 301. In the embodiment described, contact 401 comprises tungsten. When the top surface of contact 401 is exposed to oxygen or a gas, multiple defects can easily form on the top surface of contact 401 comprising tungsten. These defects can affect the yield of the semiconductor device.

[0144] Figure 12 The figure is a cross-sectional diagram of a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 13 Based on Figure 12 Schematic top view of a semiconductor component.

[0145] Please refer to Figure 1 and Figure 12 and Figure 13 , a plurality of bit line contacts 405 may be formed on the substrate 101. (In Figure 12Only one bit line contact 405 is shown. A second isolation film 803 can be made of the same material as the first isolation film 801, but is not limited thereto. A lithography process can be used to pattern the second isolation film 803 to define a plurality of bit line contacts 405. After the lithography process, an etching process, such as an anisotropic dry etching process, can be performed to form a plurality of bit line contact openings in the second isolation film 803. An upper surface of the contact 401 can be exposed through the plurality of bit line contact openings. A cleaning process can optionally be performed using a reducing agent to remove the defect line on the upper surface of the contact 401 comprising tungsten. The reducing agent can be titanium tetrachloride, tantalum tetrachloride, or a combination thereof.

[0146] Please refer to Figure 11 and Figure 12 After the cleaning process, a first capping layer 407 comprising tungsten nitride is formed to cover the bottoms and sidewalls of the plurality of bitline contact openings. The first capping layer 407 prevents the upper surface of the tungsten-containing contacts 401 from being exposed to oxygen and air; therefore, the first capping layer 407 reduces the formation of the aforementioned defects on the upper surface of the tungsten-containing contacts 401. For example, a conductive material is deposited in the plurality of bitline contact openings by a metallization process to form the plurality of bitline contacts 405. The conductive material is, for example, aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy. The metallization process is, for example, chemical vapor deposition, physical vapor deposition, sputtering, or the like. Following the metallization process, a planarization process, such as chemical mechanical polishing, is performed to remove excess deposited material and provide a substantially planar surface for subsequent processing steps.

[0147] Please refer to Figure 12 and Figure 13 , the plurality of bit line contacts 405 are electrically connected to the first contact points 401 ; that is, the plurality of bit line contacts 405 are electrically coupled to the first doped region 301 .

[0148] Figure 14 The figure is a cross-sectional diagram of a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 15 Based on Figure 14 Schematic top view of a semiconductor component.

[0149] Please refer to Figure 14 and Figure 15 , a plurality of bit lines can be formed on a plurality of bit line contact points on the substrate, respectively. Figure 14Only one bit line 409 is shown. A third isolation film 805 may be formed on the second isolation film 803. The third isolation film 805 is made of the same material as the first isolation film 801, but is not limited thereto. A lithography process may be used to pattern the third isolation film 805 to define the locations of the plurality of bit lines 409. Following the lithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a plurality of bit line trench openings 408 in the third isolation film 805. In some embodiments, the lithography process may also pattern the third isolation film 805 to define the locations of the plurality of contact holes 402, and an etching process may be performed to form the plurality of contact holes 402 through the third isolation film 805, the second isolation film 803, and the first isolation film 801. In other words, the contact holes 402 are considered deep holes, while the bit line trench openings 408 are considered relatively shallow holes.

[0150] Figure 16 The figure is a cross-sectional diagram of a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 17 Based on Figure 16 Schematic top view of a semiconductor device. In some embodiments, the bitline trench opening 408 and the contact hole 402 may be filled with a material through a process such as chemical vapor deposition, physical vapor deposition, sputtering, or the like. In some embodiments, the contact hole 402 may be deeper than the bitline trench opening 408, and the bitline trench opening 408 may be completely filled with a filling material 408-1. The contact hole 402 may also be partially filled with a filling material 402-1, which may be the same as the filling material 408-1. In some embodiments, the upper portion of the contact hole 402 within the third isolation film 805 is not filled with the filling material 402-1.

[0151] Please refer to Figure 18 and Figure 21 , a plurality of capacitor contact points are respectively located on the second region of the substrate. Figure 18 The figure is a cross-sectional diagram of a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 19 Based on Figure 18 Schematic top view of a semiconductor device. In some embodiments, an etching process, such as an isotropic etching process, may be performed to remove a portion of the third isolation film 805 surrounding the contact hole 402, thereby forming a plurality of conversion holes 404. Each conversion hole 404 has a narrow portion 404-1 and a wide portion 404-2. The narrow portion 404-1 is occupied by the filling material 402-1 in the second isolation film 803, while the wide portion 404-2 is located in the third isolation film 805.

[0152] Figure 20 The figure is a cross-sectional diagram of a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 21 Based on Figure 20 Schematic top view of a semiconductor device. In some embodiments, fill material 402-1 and fill material 408-1 are stripped from the conversion hole 404 and the bit line trench opening 408, respectively. After stripping the fill material, a conductive material such as aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy is deposited in the plurality of bit line trench openings 408 to form a plurality of bit lines 409, and in the conversion hole 404 to form a plurality of capacitor contacts 403, by a metallization process such as chemical vapor deposition, physical vapor deposition, sputtering, or the like. After the metallization process, a planarization process such as chemical mechanical polishing can be performed to remove excess deposited material and provide a substantially planar surface for subsequent processing steps.

[0153] In some embodiments, capacitor contact point 403 includes a neck portion 403-1 and a head portion 403-2. Head portion 403-2 is positioned above neck portion 403-1, wherein an upper width W1 of head portion 403-2 is greater than an upper width W2 of neck portion 403-1. In some embodiments, upper width W2 of neck portion 403-1 is substantially equal to a lower width of head portion 403-2. In some embodiments, head portion 403-2 has a curved sidewall 403-3. In some embodiments, head portion 403-2 has a tapered profile.

[0154] Please refer to Figure 20 and Figure 21 In the top view, the plurality of bit lines 409 may extend along a direction Y and may be implemented as wavy lines. The plurality of bit line contacts 405 are located at the intersections of the plurality of bit lines 409 and the plurality of active regions 105. Implementing the plurality of bit lines 409 as wavy lines can increase the contact area between the plurality of bit line contacts 403 and the plurality of active regions 105; thus, the contact resistance between the plurality of bit line contacts 405 and the plurality of active regions 105 can be reduced.

[0155] Please refer to Figure 1 and Figure 22 In step S13, a dielectric layer having a plurality of capacitor plugs is formed on the plurality of capacitor contacts. Figure 22 This is a cross-sectional diagram of a partial process for preparing a semiconductor device according to an embodiment of the present disclosure. Figure 1 and Figure 22, a plurality of capacitor plugs 411 may be formed on the substrate 101. A fourth isolation film 807 may be formed on the third isolation film 805. The fourth isolation film 807 may be made of the same material as the first isolation film 801, but is not limited thereto. A lithography process may be used to pattern the fourth isolation film 807 to define the locations of the plurality of capacitor plugs 411. After the lithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a plurality of plug openings through the fourth isolation film 807, the third isolation film 805, and the second isolation film 803. After the etching process, a conductive material is deposited in the plurality of plug openings by a metallization process to form a plurality of capacitor plugs 411 on the header 403-2. For example, the conductive material may be aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy. The metallization process may be performed by chemical vapor deposition, physical vapor deposition, sputtering, or the like. In some embodiments, a plurality of barrier layers 412 may be disposed between the capacitor plugs 411 and the second isolation film 803. A plurality of capping layers 419 may be disposed on and adhered to the sidewalls of the plurality of plugs 411. The capping layers 419 may comprise titanium (Ti), titanium nitride (TiN), or a combination thereof. After the metallization process, a planarization process, such as chemical mechanical polishing, may be performed to remove excess deposited material and provide a substantially flat surface for subsequent processing steps.

[0156] Please refer to Figure 1 and Figure 23 In step S15 , an etching process is performed to remove a portion of the dielectric layer, thereby exposing a protruding portion of the capacitor plug. Figure 23 This is a cross-sectional diagram of a partial process for preparing a semiconductor device according to an embodiment of the present disclosure. Figure 1 and Figure 23 , an etch-back process is performed to remove a portion of the fourth isolation film 807, thereby exposing a protruding portion 411A of the capacitor plug 411 and an upper portion 412A of the barrier layer 412. In some embodiments, after the etch-back process, the upper surface of the capacitor plug 411 is higher than the upper surface of the fourth isolation film 807, and the sidewalls of the upper portion 412A are exposed.

[0157] Please refer to Figure 1 and Figure 24 In step S17 , a deposition process is performed to form a conductive polymer layer, which covers the dielectric layer and the protrusion. Figure 24Figure 8 is a schematic cross-sectional view of a portion of the process for fabricating a semiconductor device according to one embodiment of the present disclosure. In some embodiments, a deposition process is performed to form a conductive polymer layer 808. Conductive polymer layer 808 covers the upper surface of fourth isolation film 807, the upper surface of protrusion 411A, and the sidewalls of upper portion 412A. In some embodiments, conductive polymer layer 808 is a silicon-containing layer, such as a polysilicon layer.

[0158] Please refer to Figure 1 and Figure 25 In step S19 , a portion of the conductive polymer layer is removed to form a landing pad on the dielectric layer, wherein the landing pad has a second width that is greater than the first width of the protrusion. Figure 25 The figure is a cross-sectional diagram of a partial process for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0159] In some embodiments, please refer to Figure 26 , the conductive polymer layer 311 includes graphene, a lithography process is performed to form a plurality of photoresist patterns 312 on the conductive polymer layer 311, and an etching process is performed to remove a portion of the conductive polymer layer 311 to form a plurality of landing pads 810 as shown in FIG. Figure 27 The landing pad 810 is disposed on the fourth isolation film 807, wherein the landing pad includes the protrusion 411A of the capacitor plug 411 and the upper portion 412A of the barrier layer 412. In some embodiments, the landing pad 810 has a width W4 that is greater than the width W3 of the protrusion 411A of the capacitor plug 411.

[0160] In some embodiments, please refer to Figure 28 , the conductive polymer layer is a conjugated conductive polymer layer 313 comprising a conjugated polymer, and the conjugated polymer is, for example, polyethylenediox ythiophene (PEDOT) or polyaniline (PANI). In some embodiments, after forming the conjugated conductive polymer layer 313 on the fourth isolation film 807, a mask 213 having a patterned hole 213' is aligned on the conjugated conductive polymer layer 313; a plurality of charged particle beams 211 are irradiated through the patterned hole 213' of the mask 213 to convert the conjugated conductive polymer layer 313 into a patterned conductive polymer 313, and the patterned conductive polymer 313 has a plurality of conductive blocks 313A and a plurality of isolation blocks 313B. Next, in some embodiments, the isolation blocks 313B are then removed to form a plurality of landing pads 810A on the fourth isolation film 807, such as Figure 29In some embodiments, the landing pad 810A has a width W4 that is greater than the width W3 of the protrusion 411A of the capacitor plug 411. In some embodiments, the charged particle beam is one of electrons and ions, the mask is a shadow mask, and the ions are a material of ions selected from the group consisting of hydrogen (H), lithium (Li), sodium (Na), potassium (K), rubidium (Rb), firthium (Fr), chlorine (Cl), bromine (Br), iodine (I), astatine (At), neon (Ne), krypton (Kr), xenon (Xe), radon (Rn), helium (He), argon (Ar), nitrogen (N), oxygen (O), and cesium (Cs).

[0161] Figure 30 This is a cross-sectional schematic diagram of a partial process for fabricating a semiconductor device according to one embodiment of the present disclosure. In some embodiments, a fifth isolation film 814 having a plurality of interconnect plugs 816 may be formed on the landing pad 810. The fifth isolation film 814 may be made of the same material as the first isolation film 801, but is not limited thereto. A lithography process may be performed to pattern the fifth isolation film 814 to define the locations of the plurality of interconnect plugs 816. Following the lithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a plurality of plug openings through the fifth isolation film 804. Following the etching process, a conductive material, such as aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy, is deposited in the plurality of plug openings by a metallization process, such as chemical vapor deposition, physical vapor deposition, sputtering, or the like, to form a plurality of interconnect plugs 816 on the landing pad 810. After the metallization process, a planarization process, such as chemical mechanical polishing, may be performed to remove excess deposited material and provide a substantially flat surface for subsequent processing steps. In some embodiments, the landing pad 810 has a width W4 that is greater than the width W5 of the interconnect plug 816 , and the width W4 of the landing pad 810 is greater than the upper width W1 of the head 403 - 2 .

[0162] Figures 31 to 33 The figure is a cross-sectional diagram of a partial process for manufacturing a semiconductor device according to one embodiment of the present disclosure. Figure 34 Based on Figure 33 A top view of a semiconductor device. Figures 30 to 33 The plurality of capacitor structures 501 are respectively formed on the plurality of landing pads 810. In some embodiments, the plurality of capacitor structures 501 may include a lower electrode 505, a capacitor isolation layer 507, and an upper electrode 509.

[0163] Please refer to Figure 31A fifth isolation film 809 may be formed on the fourth isolation film 807. The fifth isolation film 809 may be made of the same material as the first isolation film 801, but is not limited thereto. A lithography process may be used to pattern the fifth isolation film 809 to define the locations of the plurality of capacitor trenches 503. Following the lithography process, an etching process, such as an anisotropic dry etching process, may be performed to form the plurality of capacitor trenches 503 through the fifth isolation film 809. The plurality of interconnect plugs 816 may be exposed through the plurality of capacitor trenches 503.

[0164] Please refer to Figure 32 The plurality of lower electrodes 505 can be formed in the plurality of capacitor trenches 503, respectively. In other words, the plurality of lower electrodes 505 can be formed inwardly within the fifth isolation film 809. For example, the plurality of lower electrodes 505 can be made of doped polysilicon, metal silicide, aluminum, copper, or tungsten. The plurality of lower electrodes 505 can be connected to the plurality of internal connection plugs 816, respectively.

[0165] Please refer to Figure 32 , a capacitor isolation layer 507 can be formed to adhere to the sidewalls and bottoms of the multiple lower electrodes 505 and the upper surfaces of the fifth isolation film 809. The capacitor isolation layer 507 can be a single layer or multiple layers. In the embodiment described, the capacitor isolation layer 507 can be a single layer or multiple layers. In particular, the capacitor isolation layer 507 can be a single layer made of a high dielectric constant material, such as barium strontium titanate, lead zirconium titanate, titanium oxide, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, or the like. Alternatively, in another embodiment, the capacitor isolation layer 507 can be a multilayer made of silicon oxide, silicon nitride, and silicon oxide.

[0166] Please refer to Figure 33 and Figure 34 , a top electrode 509 may be formed to fill the plurality of capacitor trenches 503 and cover the capacitor isolation layer 507. For example, the top electrode 509 is made of doped polysilicon, copper, or aluminum.

[0167] Figures 35 to 37 FIG. 4 is a cross-sectional view of a partial process for preparing a semiconductor device according to an embodiment of the present disclosure. In some embodiments, a conductive via 413 and a first conductive layer 415 may be formed on the substrate 101. Figure 31, a sixth isolation film 811 can be formed on the fifth isolation film 809. The sixth isolation film 811 can be made of the same material as the first isolation film 801, but is not limited thereto. A lithography process can be used to pattern the sixth isolation film 811 to define the location of the conductive via 413. After the lithography process, an etching process, such as an anisotropic dry etching process, can be performed to form a conductive via opening that passes through the sixth isolation film 811. After the etching process, a conductive material is deposited in the conductive via opening by a metallization process to form the conductive via 413 in the sixth isolation film 811. For example, the conductive material is aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy. The metallization process is, for example, chemical vapor deposition, physical vapor deposition, sputtering, or the like. After the metallization process, a planarization process, such as chemical mechanical polishing, may be performed to remove excess deposited material and provide a substantially planar surface for subsequent processing steps.

[0168] Please refer to Figure 35 In the embodiment described, the conductive via 413 includes tungsten. When the upper surface of the conductive via 413 is exposed to oxygen or air, multiple defects may be easily formed on the upper surface of the conductive via 413 including tungsten. These defects may affect the yield of the semiconductor device.

[0169] Please refer to Figure 36 , a seventh isolation film 813 can be formed on the sixth isolation film 811. The seventh isolation film 813 can be made of the same material as the first isolation film 801, but is not limited thereto. A lithography process can be used to pattern the seventh isolation film 813 to define the position of the first conductive layer 415. After the lithography process, an etching process, such as an anisotropic dry etching process, can be performed to form a first conductive layer trench in the seventh isolation film 813. The upper surface of the conductive via 413 can be exposed through the first conductive layer trench. A cleaning process using a reducing agent can be optionally performed to remove the defects on the upper surface of the conductive via 413 containing tungsten. The reducing agent can be titanium tetrachloride, tantalum tetrachloride, or a combination thereof.

[0170] Please refer to Figure 36 and Figure 37After the cleaning process, a second capping layer 417 comprising tungsten nitride may be formed to cover a bottom and sidewalls of the first conductive layer trench. The second capping layer 417 may prevent the upper surface of the conductive via 413 comprising tungsten from being exposed to oxygen or air; therefore, the second capping layer 417 may reduce the formation of multiple defects on the upper surface of the conductive via 413 comprising tungsten. A conductive material is deposited in the first conductive layer trench by a metallization process to form the first conductive layer 415. For example, the conductive material is aluminum, copper, tungsten, cobalt or other suitable metal or metal alloy. The metallization process is, for example, chemical vapor deposition, physical vapor deposition, sputtering or the like. After the metallization process, a planarization process, such as chemical mechanical polishing, may be performed to remove excess deposited material and provide a substantially flat surface for subsequent processing steps.

[0171] Figure 38 The figure is a cross-sectional diagram of a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0172] Please refer to Figure 38 A semiconductor device may include a substrate 101, multiple insulating structures 103, multiple word lines 201, multiple doped regions, multiple isolation films, multiple contacts, multiple bit line contacts 405, a first covering layer 407, multiple bit lines 409, multiple plugs 411, multiple landing pads 810, multiple internal connection plugs 816, a conductive via 413, a first conductive layer 415, a second covering layer 417, and multiple capacitor structures 501.

[0173] Please refer to Figure 38 , multiple insulating structures 103 can be set in the substrate 101 and separated from each other. The multiple insulating structures 103 can define multiple active areas 105. Multiple word lines 201 can be set in the substrate 101 and separated from each other. Each word line 201 includes a lower layer 203, an intermediate layer 205 and an upper layer 207. The multiple lower layers 203 can be set separately and inwardly in the substrate 101. The multiple intermediate layers 205 can be respectively set on the multiple lower layers 203. Each upper surface of the multiple intermediate layers 205 can be lower than an upper surface of the substrate 101. The multiple upper layers 207 can be respectively set on the multiple intermediate layers 205. Each upper surface of the multiple upper layers 207 can be located at the same vertical plane as the upper surface of the substrate 101.

[0174] Please refer to Figure 38 Multiple doped regions can be disposed in multiple active regions 105 of the substrate 101. Each doped region includes a first doped region 301 and multiple second doped regions 303. For each doped region, the first doped region 301 is disposed between adjacent pairs of word lines 201. The second doped regions 303 are respectively disposed between the multiple insulating structures 103 and the multiple word lines 201.

[0175] Please refer to Figure 38 , multiple isolation films may be disposed on the substrate 101. The multiple isolation films may include a first isolation film 801, a second isolation film 803, a third isolation film 805, a fourth isolation film 807, a fifth isolation film 809, a sixth isolation film 811, and a seventh isolation film 813. The first isolation film 801 may be disposed on the substrate 101. Multiple contact points may be disposed in the first isolation film 801. The multiple contact points may include a contact point 401 and multiple capacitor contact points 403. The contact point 401 may be disposed on the first doped region 301 and electrically connected to the first doped region 301. The capacitor contact points 403 may be disposed on the second doped region 303, respectively, and electrically connected to the second doped region 303, respectively. In the embodiment described, the contact point 401 comprises tungsten.

[0176] Please refer to Figure 38 , the second isolation film 803 can be provided on the first isolation film 801. A plurality of bit line contacts 405 can be provided in the second isolation film 803. (In Figure 38 Only one bitline contact is shown. A first capping layer 407 may be disposed within the second isolation film 803 and on an upper surface of the contact 401. In other words, the first capping layer 407 may be disposed between the plurality of bitline contacts 405 and the contact 401. Furthermore, the first capping layer 407 may be disposed on and adhered to the sidewalls of the plurality of bitline contacts 405. The first capping layer 407 may comprise tungsten nitride.

[0177] Please refer to Figure 38 , the third isolation film 805 can be provided on the second isolation film 803. A plurality of bit lines 409 can be provided in the third isolation film 805 and on a plurality of bit line contacts and the first capping layer 407. (In Figure 38 Only one bit line 409 is shown. A fourth isolation film 807 may be disposed on the third isolation film 805. A plurality of plugs 411 may be disposed to pass through the fourth isolation film 807, the third isolation film 805, and the second isolation film 803. The plurality of plugs 411 may be electrically connected to the capacitor contact points 403, respectively.

[0178] Please refer to Figure 38Capacitor contact point 403 includes a neck portion 403-1 and a head portion 403-2. Head portion 403-2 is positioned above neck portion 403-1, wherein an upper width W1 of head portion 403-2 is greater than an upper width W2 of neck portion 403-1. In some embodiments, upper width W2 of neck portion 403-1 is substantially equal to a lower width of head portion 403-2. In some embodiments, head portion 403-2 has a curved sidewall 403-3. In some embodiments, head portion 403-2 has a tapered profile.

[0179] Please refer to Figure 38 In some embodiments, a plurality of first spacers 808A are disposed on the protrusion 411A of the plug 411. In some embodiments, the first spacers 808A include metal silicide and are disposed on a sidewall of the protrusion 411A. In some embodiments, the width W4 of the first spacers 808A is greater than the width W3 of the capacitor plug 411. In some embodiments, a plurality of second spacers 808B are disposed on the first spacers 808A. In some embodiments, the first spacers 808A include polysilicon and are disposed on a sidewall of the protrusion 411A, and the second spacers 808B include metal silicide formed from the polysilicon of the first spacers 808A. In some embodiments, the protrusion 411A, the first spacers 808A, and the second spacers 808B form a landing pad 810 on the capacitor contact 403.

[0180] Please refer to Figure 38 The fifth isolation film 809 may be disposed on the fourth isolation film 807. Multiple capacitor structures 501 may be disposed in the fifth isolation film 809. The multiple capacitor structures 501 may include multiple lower electrodes 505, a capacitor isolation layer 509, and an upper electrode 509. The multiple lower electrodes 505 may be disposed inwardly in the fifth isolation film 809 and electrically connected to the multiple internal connection plugs 816, respectively. The capacitor isolation layer 507 may be disposed on the multiple lower electrodes 505. The upper electrode 509 may be disposed on the capacitor isolation layer 507.

[0181] Please refer to Figure 38 A sixth isolation film 811 may be disposed on the fifth isolation film 809. A conductive via 413 may be disposed in the sixth isolation film 811 and electrically connected to the upper electrode 509. The conductive via 413 may include tungsten. A seventh isolation film 813 may be disposed on the sixth isolation film 811. A first conductive layer 415 may be disposed in the seventh isolation film 813 and on the conductive via 413. A second capping layer 417 may be disposed on an upper surface of the conductive via 413 and between the conductive via 413 and the first conductive layer 415. Furthermore, the second capping layer 417 may be disposed on each sidewall of the first conductive layer 415 and adhered to each sidewall of the first conductive layer 415.

[0182] The width W4 of the landing pad 810 is larger than the width of the protrusion 411A of the capacitor plug 411 ; therefore, the misalignment between the capacitor structure 501 and the landing pad 810 formed in sequence can be significantly resolved.

[0183] Furthermore, since the capacitor contact 403 has a neck portion 403-1 and a head portion 403-2 and a tapered profile, misalignment between the sequentially formed capacitor structure 503 and the capacitor contact 403 can be significantly resolved. Furthermore, the capping layers 407 and 417 can reduce the formation of various defects in the semiconductor device, thereby correspondingly improving the yield of the semiconductor device.

[0184] One embodiment of the present disclosure provides a semiconductor device, comprising a substrate; a dielectric layer disposed on the substrate; a plug disposed in the dielectric layer, wherein the plug has a protrusion having a first width; and a landing pad disposed on the dielectric layer, wherein the landing pad comprises a conductive polymer and has a second width that is greater than the first width of the protrusion.

[0185] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device. The method includes: providing a substrate; forming a dielectric layer having a plug on the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protrusion of the plug; forming a conductive polymer layer to cover the dielectric layer and the protrusion, wherein the protrusion has a first width; and removing a portion of the conductive polymer layer to form a landing pad on the dielectric layer, wherein the landing pad has a second width that is greater than the first width of the protrusion.

[0186] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above may be implemented in different ways, and other processes or combinations thereof may be substituted for many of the processes described above.

[0187] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with this disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of this application.

Claims

1. A semiconductor element comprising: a base; a dielectric layer disposed on the substrate; a plug disposed in the dielectric layer, wherein the plug has a protrusion having a first width; a landing pad disposed on the dielectric layer, wherein the landing pad comprises a conductive polymer and has a second width that is greater than the first width of the protrusion; and A capacitor contact point is located on the substrate, and the landing pad is disposed on the capacitor contact point.

2. The semiconductor device according to claim 1, wherein The landing pad further includes a barrier layer located between the protrusion and a second silicide layer.

3. The semiconductor device according to claim 2, wherein The conductive polymer layer comprises graphene.

4. The semiconductor device according to claim 1, wherein The conductive polymer layer comprises a conjugated polymer.

5. The semiconductor device according to claim 4, wherein The conjugated polymer comprises polystyrene sulfonate or polyaniline.

6. The semiconductor device according to claim 1, wherein The capacitive contact point has a neck and a head, the head is located on the neck, wherein an upper width of the head is larger than an upper width of the neck, and the second width of the landing pad is larger than the upper width of the head.

7. The semiconductor device according to claim 6, wherein The upper width of the head is greater than the lower width of the head.

8. The semiconductor device according to claim 6, wherein The upper width of the neck is substantially the same as the lower width of the head.

9. The semiconductor device according to claim 6, wherein The head has a curved side wall.

10. The semiconductor device according to claim 6, wherein The head has a tapered profile.

11. The semiconductor device according to claim 1 , further comprising: a bit line contact point and a bit line, wherein the bit line contact point is disposed on the substrate, and the bit line is disposed on the bit line contact point, wherein the bit line is a wavy stripe extending between two adjacent capacitor contact points on the substrate; and A capacitor structure is disposed on the landing pad.

12. A method for preparing a semiconductor element, comprising: providing a substrate; forming a dielectric layer having a plug on the substrate; performing an etching process to remove a portion of the dielectric layer, thereby exposing a protruding portion of the plug; forming a conductive polymer layer to cover the dielectric layer and the protrusion, wherein the protrusion has a first width; removing a portion of the conductive polymer layer to form a landing pad on the dielectric layer, wherein the landing pad has a second width that is greater than the first width of the protrusion; as well as A capacitor contact point is formed on the substrate, and the landing pad is formed on the capacitor contact point.

13. The method for preparing a semiconductor device according to claim 12, further comprising: A barrier layer is formed between the plug and the dielectric layer, and the etching process removes a portion of the dielectric layer to expose the protruding portion of the plug and an upper portion of the barrier layer.

14. The method for manufacturing a semiconductor device according to claim 12, wherein: The step of removing a portion of the conductive polymer layer comprises: aligning a mask having a patterned hole over the conductive polymer layer; and A plurality of charged particle beams are irradiated through the patterned holes of the mask to form a patterned conductive polymer.

15. The method for manufacturing a semiconductor device according to claim 12, wherein: The conductive polymer layer is made of a conjugated polymer.

16. The method for manufacturing a semiconductor device according to claim 14, wherein: A radiation region of the conductive polymer layer forms an isolation polymer layer, and the charged particle beam is one of a plurality of electrons and a plurality of ions.

17. The method for manufacturing a semiconductor device according to claim 14, wherein: The mask is a shield, and the plurality of ions is a material of a plurality of ions, the material being selected from the group consisting of hydrogen, lithium, sodium, potassium, rubidium, ferromagnetic acid, chlorine, bromine, iodine, astatine, neon, krypton, xenon, radon, helium, argon, nitrogen, oxygen, and cesium.

18. The method for manufacturing a semiconductor device according to claim 12, The capacitor contact point has a neck and a head, the head is located on the neck, and an upper width of the head is greater than an upper width of the neck.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: Forming the capacitor contact point includes: forming a contact hole in a dielectric stack having a first layer and a second layer, the second layer being located on the first layer; removing a portion of the second layer surrounding the contact hole to form a conversion hole having a narrow portion and a wide portion, wherein the narrow portion is in the first layer and the wide portion is in the second layer; and A conductive material is filled into the conversion hole.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: The contact hole is formed integrally with a bit line trench in the second layer, and the method further comprises: Filling the bit line trench and a lower portion of the contact point with a filling material; The removal of the portion of the second layer surrounding the contact hole is performed after filling the lower portion of the contact hole with a sacrificial material.

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