A data processing method and related apparatus

Abstract

Embodiments of the present application provide a data processing method and related device, comprising receiving each data processing request with a request category, and writing each data processing request into a corresponding request category queue; determining a preceding data processing request and a following data processing request according to the writing order of the data processing request at the head of each request category queue; determining the storage space of a current level module corresponding to the preceding request data according to the preceding data processing request; when the preceding request data is not obtained, determining the storage space of a current level module corresponding to the following request data according to the following data processing request, obtaining the following request data, and when the preceding obtained data is obtained from the preceding request data and the following request data, processing the request category of the data processing request corresponding to the preceding obtained data. Embodiments of the present application can improve the efficiency of cache data processing.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of computer, and in particular, to a data processing method and related apparatus. BACKGROUND

[0002] In computer technology, a processor and a multi-level memory are typical computer structures. In a data operation process, a main memory in the multi-level memory stores instructions and data, a processor obtains instructions and corresponding data from the main memory, executes the instructions, and writes result data back to the main memory. Between the processor and the main memory, there is usually one or more levels of cache memory (Cache). The cache memory is used to reduce the time for the processor to read instructions and data.

[0003] In core operations such as data operation and matrix operation of high-performance computing, there is usually a clear processing order for data. When a cache receives an operation request, the received request is executed in strict accordance with the order of the request, that is, a first-arriving request is read and received data is returned before data processing, and then a second-arriving request is processed.

[0004] However, the above operation is prone to read-write blocking problems. For example, when the cache processing receives a queue of read-write requests, the read request that arrives first should be processed first according to the order of the request, but the write data required by the write request that arrives later has already been in place, which causes the read request to block the write request, resulting in low cache data processing efficiency.

[0005] Therefore, how to improve the efficiency of cache data processing has become a technical problem to be solved. SUMMARY

[0006] The technical problem solved by the embodiments of the present application is to improve the efficiency of cache data processing.

[0007] To solve the above problems, the embodiments of the present application provide a data processing method and related apparatus, comprising:

[0008] In a first aspect, the embodiments of the present application provide a data processing method, comprising: receiving each data processing request, and writing each data processing request into a corresponding request category queue according to the request category of each data processing request, the number of request categories of each data processing request being at least two;

[0009] determine a preceding data processing request and a following data processing request according to a writing sequence of the data processing requests located at the head of each of the request category queues, determine a storage space of a current level module corresponding to preceding request data according to the preceding data processing request, wherein the current level module is a module receiving each of the data processing requests;

[0010] when the preceding request data is not obtained, determine a storage space of a current level module corresponding to following request data according to the following data processing request, obtain the following request data, and when the preceding obtained data is obtained from both the preceding request data and the following request data, complete the data processing request according to a request category of the data processing request corresponding to the preceding obtained data.

[0011] In a second aspect, an embodiment of the present application provides a data processing apparatus, and the apparatus comprises:

[0012] a receiving module, adapted to receive each of the data processing requests, and write each of the data processing requests into a corresponding request category queue according to the request category of each of the data processing requests, wherein the number of the request categories of each of the data processing requests is at least two;

[0013] a request determining module, configured to determine a preceding data processing request and a following data processing request according to a writing sequence of the data processing requests located at the head of each of the request category queues, determine a storage space of a current level module corresponding to preceding request data according to the preceding data processing request, and obtain the preceding request data, wherein the current level module is a module receiving each of the data processing requests;

[0014] a processing module, adapted to, when the preceding request data is not obtained, determine a storage space of a current level module corresponding to following request data according to the following data processing request, obtain the following request data, and when the preceding obtained data is obtained from both the preceding request data and the following request data, complete the data processing request according to a request category of the data processing request corresponding to the preceding obtained data.

[0015] In a third aspect, an embodiment of the present application further provides a cache memory, adapted to execute the data processing method in the first aspect.

[0016] In a fourth aspect, an embodiment of the present application further provides an electronic device comprising the cache memory in the third aspect.

[0017] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0018] In the embodiment of the present application, firstly, the received data processing requests with request categories are respectively put into the request category queues corresponding to the request categories, then the preceding data processing request and the following data processing request are determined according to the receiving order of the data processing requests at the head of each request category queue, the storage space of the current level module corresponding to the preceding request data is determined according to the preceding data processing request, when the preceding request data is not acquired, the storage space of the current level module corresponding to the following request data is determined according to the following data processing request, the following request data is acquired, when the preceding acquired data in the preceding request data and the following request data is obtained, the data processing request is completed according to the request category of the data processing request corresponding to the preceding acquired data.

[0019] It can be seen that the technical scheme provided by the embodiment of the present application puts the received data processing requests into different queues according to categories, executes each request in the same queue according to the order of the data processing requests, and processes the data processing requests in different queues simultaneously, so that the mutual blocking of different types of data processing requests can be reduced without affecting the correctness of the processing result, thereby improving the overall efficiency of processing data. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical scheme in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiment or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by the drawings provided by the person skilled in the art without creative labor.

[0021] Figure 1 The basic system architecture for data processing is shown in the figure.

[0022] Figure 2 The basic system architecture for data processing is shown in the figure.

[0023] Figure 3a The architecture for data processing provided by the data processing method of the embodiment of the present application is shown in the figure.

[0024] Figure 3b The flowchart of the data processing method provided by the embodiment of the present application is shown in the figure.

[0025] Figure 4 Another flowchart of the data processing method provided by the embodiment of the present application is shown in the figure.

[0026] Figure 5 Another flowchart of the data processing method provided by the embodiment of the present application is shown in the figure.

[0027] Figure 6 The structural block diagram of the data processing device provided in the embodiment of the present application is shown.

[0028] Figure 7 The structural block diagram of the cache memory provided in the embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0030] Figure 1 An exemplary basic system architecture diagram of data processing of high-performance computing of a computer is shown, as shown in the figure, the system architecture can include a processor 110, a cache memory 120 and a main memory 130. Figure 1

[0031] The processor 110 is mainly a high-performance computing processor, generally a CPU (central processing unit) or a GPGPU (general-purpose graphics processor), the processor 110 can send a data processing request, the main memory 130 can store instructions and data, the processor 110 obtains instructions and corresponding data from the main memory 130, then executes the instructions, and writes the result data back to the main memory 130.

[0032] The interface for data transmission between the processor 110 and the memory is MAR (address register) and MDR (data register), the memory can include the cache memory 120 and the main memory 130, the MAR can accept an instruction address from a program counter or an operand address from an address forming component to determine the unit to be accessed. The MDR is a buffer component for writing data to or reading data from the main memory 130. The functions of the MAR and the MDR are similar to those of the main memory 130, but they are often placed in the processor 110 in small computers and microcomputers.

[0033] The main memory 130 is a storage area of program execution code and data, and generally uses a DRAM (dynamic random access memory) type storage chip.

[0034] ​In some embodiments, during the process of data processing, when the operation performed is a read operation, which means that the information is taken from the memory unit specified by the address sent from the processor 110 and then sent to the processor 110, specifically: first, the processor 110 sends the address of the memory unit to the MAR; then, the processor 110 issues a read command; then, it waits for the memory operation completion signal; finally, the information is read and returned to the processor 110. In other embodiments, when the operation performed is a write operation, which means that the information to be written is stored in the memory unit specified by the processor 110, the specific operation is: first, the processor 110 sends the address signal to the address bus; then, the processor 110 sends the data to be written to the data bus; then, the processor 110 issues a write command; finally, it waits for the memory operation completion signal.

[0035] Since the speed of the processor 110 directly reading instructions and data from the main memory 130 is slow, a cache memory 120 is usually provided between the processor 110 and the main memory 130, wherein the cache memory 120 can be set to one or more levels of cache memory according to actual use needs.

[0036] In some embodiments, the cache memory 120 can also be provided between the memory and the hard disk, and in other embodiments, the cache memory 120 can also be provided between the hard disk and the network, i.e. between two kinds of hardware with large speed difference, for coordinating the speed difference of data transmission between the two, which can be generally referred to as cache memory 120. Its material is generally SRAM (Static Random Access Memory), and its performance is between that of a register and a main memory DRAM (Dynamic Random Access Memory).

[0037] The cache memory 120 is usually implemented using SRAM, which is small in size and large in capacity, and has a faster access speed than the main memory 130. Using it to store some frequently accessed information in the main memory 130 can greatly improve the program execution speed. In some embodiments, the access speed of the main memory 130 is 1 μs, and the access speed of the cache memory 120 can reach 0.1 μs. It can be seen that the speed of the cache memory 120 is much higher than that of the main memory 130. When the processor 110 directly obtains data from the main memory 130, it needs to wait for a certain period of time, while the cache memory 120 can save a part of data that has just been used by the processor 110 or is used repeatedly. If the processor 110 needs to use this part of data again, it can directly call it from the cache memory 120, which avoids repeated access to data and reduces the waiting time of the processor 110, thereby improving the efficiency of the system.

[0038] In some embodiments, the data information is usually stored in the main memory 130, and each time it is used, it is assigned to a cache memory 120 with high access speed. When the processor 110 accesses a specific set of information, it first checks whether it is in the cache memory 120. If it exists, it is directly taken; otherwise, the information is read from the main memory 130. It is generally considered that the probability of this set of information being used again is high, so the information read from the main memory 130 is also copied to the cache memory 120 to facilitate fast data access next time.

[0039] When the cache memory 120 performs data processing requests, it needs to strictly follow the order of receiving each data processing request, Figure 2 An exemplary system architecture diagram for the cache memory to process data requests is shown.

[0040] As shown in the figure, the system architecture includes a processor 110, a cache memory 120, and a main memory 130.

[0041] It can be seen that the cache memory 120 is located between the processor 110 and the main memory 130 (here the processor refers to a high-performance computing processor).

[0042] The processor 110 sends multiple data processing requests to the cache memory 120, which are arranged in a queue according to the order of sending. The cache memory 120 strictly follows the order of receiving each data processing request when performing each data processing request, as shown in Figure 2 In some embodiments, the order of arrival of data processing requests is R0, R1, W0, R2, W1, R3, W2, W3, and the execution order of the cache memory 120 is also R0, R1, W0, R2, W1, R3, W2, W3, and the output order to the processor 110 is also R0, R1, W0, R2, W1, R3, W2, W3, and so on. Among them, R is a read data processing request, and W is a write data processing request. Such an execution mode is prone to read and write request blocking, as shown in Figure 2 According to the order of receiving, R0 at the head of the queue needs to be processed first, but the data that W0 needs to write has already arrived, which causes the read data request to block the write data request, and vice versa.

[0043] It can be seen that the above-mentioned data processing mode will cause data request processing blocking, affecting the overall efficiency of data processing.

[0044] The data processing method provided by the embodiments of the present application can separately process received data processing requests, and place read and write requests in different queues, thereby improving the overall data processing efficiency.

[0045] Figure 3a The system architecture of the data processing method provided by the embodiments of the present application is shown in the figure. The system architecture includes a processor 110, a cache memory 120, and a main memory 130.

[0046] The cache memory 120 can be divided into a level one cache, a level two cache, and a level three cache. The level one cache is usually built-in the processor 110 and runs at the same speed as the processor 110, which can effectively improve the running efficiency of the processor 110. The larger the level one cache is, the higher the running efficiency of the processor 110 is. However, due to the limitation of the internal structure of the processor 110, the capacity of the level one cache is very small.

[0047] The level two cache can coordinate the speed between the level one cache and the memory. When the processor 110 calls the cache, the first query is the level one cache. When the data of the level one cache cannot support the running of the processor 110, the data needs to be found in the level two cache. The speed of the level two cache is relatively slower than that of the level one cache, but the space capacity of the level two cache is larger than that of the level one cache, and it is mainly used for the temporary exchange of data between the level one cache and the memory.

[0048] The level three cache is used to find the requested data in the level three cache when the requested data is not found in the level two cache. In the processor 110 with the level three cache, only a small amount of data needs to be called from the memory, which further improves the efficiency of the processor 110.

[0049] In some embodiments, the processor 110 can be a high-performance computing processor. At this time, the levels of the cache memory 120 process the received data processing requests in sequence according to the needs of data processing.

[0050] Specifically, when the processor 110 sends each data processing request with different request categories to the cache memory 120, the first place where each data processing request is sent is the level one cache of the cache memory 120. Therefore, the level one cache of the cache memory 120 receives each data processing request. A plurality of different queues can be set in the level one cache, which are used to place each data processing request in a different queue according to the category of each data processing request. Although the data processing requests in the same queue still need to be executed in the processing order of first-in-first-out, the processing order of the data processing requests in different queues does not need to follow the processing steps of first-in-first-out. Specifically, the processing order of the data processing requests in different queues can be:

[0051] According to the write order of the data processing requests located at the head of each request category queue, a preceding data processing request and a following data processing request are determined, and a storage space of a current level module corresponding to preceding request data is determined according to the preceding data processing request, wherein the current level module is a module receiving each data processing request, such as a level one cache.

[0052] When the preceding request data is not obtained, a storage space of a current level module corresponding to following request data is determined according to the following data processing request, and the following request data is obtained, and when the preceding obtained data in both the preceding request data and the following request data is obtained, the data processing request is completed according to the request category of the data processing request corresponding to the preceding obtained data.

[0053] In this way, data requests in multiple queues can be processed simultaneously, and the problem of blocking of data processing requests of different categories and affecting the overall efficiency of data processing can be solved.

[0054] In some other embodiments, the device receiving each data processing request can also be a level two cache of the cache memory 120, such as when the level one cache needs to send a data processing request to the level two cache.

[0055] Specifically, the level one cache sends each data processing request with different request categories to the level two cache, and similarly, multiple different queues can be provided in the level two cache, and each data processing request received is placed in a different queue corresponding to the category, so that the data processing requests in each queue can be processed independently, and the specific processing steps are the same as the foregoing steps, which will not be described here.

[0056] The data processing requests in each queue can be processed respectively, so that the data processing requests of different categories will not be blocked.

[0057] In the embodiments of the present application, when the cache memory 120 receives a data processing request queue sent by the processor 110 or the previous level cache, each data processing request of different categories is placed in a different queue according to the respective request category, and the types of request category queues can be multiple. In an embodiment, the data processing request can include a read data processing request and a write data processing request, and the data processing method provided by the present application can set multiple queues of different categories in the cache memory 120 according to the different categories of the requests, and then simultaneously process the data processing requests in the multiple queues. In this way, the mutual blocking of data processing requests can be solved, and the overall efficiency of data processing is effectively improved.

[0058] To further illustrate the implementation of the embodiments of the present application, Figure 3b A flow chart of the data processing method provided by the embodiments of the present application is shown. In some embodiments, the flow can be executed in Figure 3a the architecture system shown.

[0059] As Figure 3b shown, the flow can include the following steps:

[0060] In step S140, the processor sends each data processing request.

[0061] It is easy to understand that the data processing request can be sent by a high-performance computing processor or a level cache. For the convenience of description, the present application describes the high-performance computing processor sending the data processing request, and correspondingly, the high-speed cache memory receiving the data processing request. If the high-speed cache memory includes multiple levels of cache, the high-speed cache memory of the first level receives the data processing request.

[0062] In step S150, the high-speed cache memory receives each data processing request and writes it into different request queues according to the corresponding request categories.

[0063] After the high-performance computing processor sends each data processing request, the high-speed cache memory receives each data processing request and writes it into different request queues.

[0064] It should be noted that the data processing request category queue is set in the high-speed cache memory in advance. In the present embodiment, the data processing request category queue can be set in the first level cache.

[0065] In other embodiments, the high-speed cache memory of the first level sends the data processing request, and the data processing request queue can be set in the second level cache.

[0066] In this way, each received data processing request can be divided into different queues according to different request categories. When processing each data processing request, only the data processing requests in the same queue are executed according to the order of the data processing requests, and the data processing requests in different queues are not executed according to the order of the received data processing requests.

[0067] In step S151, according to the writing order of the data processing requests at the head of each request category queue, the preceding data processing request and the following data processing request are determined.

[0068] The cache memory completes processing according to the order of the received data processing requests when performing the data processing requests, and therefore, after the order of the data processing requests in the different category queues is ensured, the order of the data processing requests at the head of the different queues is compared, so that the correctness of the data processing result is ensured.

[0069] In the specific determination, the write order of the data processing requests at the head of the different category queues is determined, the data processing request written first is determined as the prior data processing request, and the data processing request written later is determined as the subsequent data processing request.

[0070] In step S152, the storage space of the current level module corresponding to the prior request data is determined according to the prior data processing request, and the prior request data is obtained.

[0071] After the prior data processing request is determined, the storage space of the current level module corresponding to the prior request data is determined according to the data address in the request.

[0072] Specifically, the storage space is determined as the cache unit (specifically, a cache line) with the same data address as the data address in the prior data processing request, and the prior request data is further obtained.

[0073] In step S153, when the prior request data is not obtained, the subsequent data processing request is processed, the storage space of the current level module corresponding to the subsequent request data is determined, and the subsequent request data is obtained.

[0074] Of course, when the prior request data is not obtained, the data of the read data processing request is not hit in the cache unit of the current level cache, and the data of the write data processing request is not transmitted to the current level module. During the waiting of the data, the subsequent data processing request can be processed, the storage space of the current level module corresponding to the subsequent request data is determined, and therefore, the time of the current level module can be fully utilized.

[0075] It is easy to understand that when the prior request data is obtained, the prior data processing request is processed preferentially, and only when the prior request data is not obtained, the storage space of the current level module corresponding to the subsequent request data is determined, and the subsequent request data is obtained.

[0076] When the post-processing data request is the head request in a queue different from the queue of the prior data processing request, when the required request data of the prior data processing request does not exist in the storage space of the current level module, the post-processing data request can be processed at this time, so that different queue data processing requests can be processed simultaneously, and the data processing requests are processed after the order of the received data processing requests is determined, so that the order of processing the data processing requests can be ensured, the correctness of the data processing result can be ensured, and the overall data processing efficiency can be improved.

[0077] In step S154, according to the acquisition order of the prior request data and the post-request data, the prior data is determined, and the data processing request is completed according to the request category of the prior data.

[0078] In the foregoing steps, not only the prior request data but also the post-request data are acquired, therefore, the further processing of the data is based on the acquisition order of the prior request data and the post-request data, for this reason, it is easy to understand that the prior data obtained in the present disclosure can be the prior request data or the post-request data, if the prior request data is acquired first, the prior data obtained is the prior request data, if the post-request data is acquired first, the prior data obtained is the post-request data.

[0079] Regardless of whether the prior data obtained is the prior request data or the post-request data, the data processing of the data processing request corresponding to the prior data obtained is given priority.

[0080] It is easy to understand that the data processing requests are received successively, after the processing of each data processing request is completed, the above-mentioned operation is performed on the data processing request located at the head of each request category queue, until the processing of all data processing requests is completed.

[0081] It can be seen that the technical scheme provided by the embodiment of the present disclosure can put the received data processing requests into corresponding different queues according to categories, and only execute each request in the same queue according to the order of the data processing requests, the data processing requests between different queues can be processed simultaneously, therefore, the mutual blocking of different types of data processing requests can be reduced without affecting the correctness of the processing result, so that the overall efficiency of the cache processing data can be improved.

[0082] As mentioned above, the data processing request can include at least two or more different request categories, and the request queue is set according to the types of the data processing request categories, when the data processing request includes a read data processing request and a write data processing request, then the request queue can be set as a read data processing request category queue and a write data processing request category queue.

[0083] For the convenience of understanding, the following is based on "determining that the read data processing request is the prior data processing request and the write data processing request is the subsequent data processing request" and "determining that the read data processing request is the subsequent data processing request and the write data processing request is the prior data processing request" respectively.

[0084] First, the determination that the read data processing request is the prior data processing request and the write data processing request is the subsequent data processing request is described, please refer to Figure 4 , Figure 4 Another flowchart of the data processing method is shown, which can include the following steps.

[0085] In step S210, each read data processing request and each write data processing request is received.

[0086] Specifically, a certain current level module in the cache memory can receive the data processing request.

[0087] The specific content of step S210 is described in detail in Figure 3b The part of step S150 is not described here.

[0088] In step S211, the read data processing request queue receives each read data processing request, and the write data processing request category queue receives each write data processing request.

[0089] The specific content of step S211 is described in detail in Figure 3b The part of step S151 is not described here.

[0090] In step S212, according to the data processing request located at the head of the read data processing request queue and the write data processing request queue, it is determined that the read data processing request is the prior data processing request.

[0091] The order of the data processing requests located at the head of the two queues is determined on the basis of the order of each data processing request in the same queue, and the order of the data processing requests between different queues is further determined to ensure the correctness of the data processing result.

[0092] In step S213, it is determined whether the read data exists in the storage space of the corresponding current level module according to the read data processing request, if not, steps S215 and 216 are executed, if yes, step S214 is executed.

[0093] It is easy to understand that the current level module here refers to a cache memory provided with different request category queues, in some embodiments, the processor is a high-performance computing processor, and the current level module refers to a level one cache; in other embodiments, the current level module can refer to a level two cache or a level three cache.

[0094] Specifically, according to a data address in a read data processing request, a corresponding data address is searched in the current level module, if the corresponding data address is found, i.e. a hit, a step S214 is executed to return the read data to an upper level module, wherein the upper level module is a module sending each data processing request, i.e. data in a corresponding cache unit (cache line) is directly returned, without processing a write data processing request in the process of executing the read data processing request; if the corresponding data address is not found, a step S216 is executed to execute the write data processing request.

[0095] Of course, it is easy to understand that when the read data is not obtained in the storage space, for the read data processing request, a step S215 is further executed to send a new read data processing request to a lower level module, wherein the lower level module is a module sending a request to the current level module.

[0096] In the step S214, the read data is returned to the upper level module.

[0097] In the step S215, the new read data processing request is sent to the lower level module.

[0098] Of course, when the new read data processing request is sent to the lower level module, a cache unit with a replaceable address in the current level module is further determined, and a read data processing request is further sent to the lower level module or the main memory.

[0099] In the step S216, a storage space of the current level module corresponding to the write data processing request is determined according to the write data processing request.

[0100] When the read data and the write data are obtained at the same time, due to the influence of the data obtaining speed, the read data processing request sent first may not be able to obtain the read data first.

[0101] The step of completing the data processing request according to the request category of the data processing request obtaining the data first further includes:

[0102] In the step S217, it is judged whether the obtaining time of the read data is earlier than the obtaining time of the write data, if yes, a step S218 is executed, if not, a step S219 is executed.

[0103] In the step S218, the read data is sent to the upper level module.

[0104] In step S219, the write data is written into the current level module.

[0105] In this way, the processing of each data processing request can be completed according to the write order.

[0106] Of course, in another embodiment, when the prior request data and the subsequent request data are obtained at the same time, one of the two can be randomly determined as the prior obtained data, and then the data processing request is processed according to the data request category corresponding to the randomly determined prior obtained data.

[0107] Next, the detailed process will be described by taking the read data processing request as the subsequent data processing request and the write data processing request as the prior data processing request as an example.

[0108] Reference Figure 5 , Figure 5 is another optional flowchart of the data processing method provided by the embodiment of the present application. As shown in the figure, the flowchart can include the following steps.

[0109] In step S310, each read data processing request and each write data processing request is received.

[0110] Specifically, the data processing request, including the read data processing request and the write data processing request, can be received by a certain current level module in the cache memory.

[0111] For the specific content of step S310, please refer to Figure 3b The part of the description about step S150 will not be repeated here.

[0112] In step S311, the read data processing request queue receives each read data processing request, and the write data processing request category queue receives each write data processing request.

[0113] For the specific content of step S311, please refer to Figure 3b The part of the description about step S151 will not be repeated here.

[0114] In step S312, according to the data processing request located at the head of the read data processing request queue and the write data processing request queue, the write data processing request is determined as the prior data processing request.

[0115] In step S313, the storage space of the current level module corresponding to the write data is determined according to the write data processing request.

[0116] Of course, the current level module here also refers to a device provided with multiple request queues of different categories. In some embodiments, the current level module can be a level one cache, and in other embodiments, the current level module can be a level two cache.

[0117] It is easy to understand that, no matter whether there is storage space corresponding to the write data in the current level module at the moment of receiving the write data processing request, the corresponding storage space needs to be determined, if there is at the time of receiving the data processing request, then it can be determined directly, if not, then it needs to be determined by replacing or occupying the idle storage unit.

[0118] In step S314, it is judged whether the write data is obtained, if yes, step S315 is executed, if not, step S316 is executed.

[0119] In step S315, the write data is written into the storage space of the current level module.

[0120] In step S316, the storage space of the current level module corresponding to the read data is determined according to the read data processing request, and the read data of the read data processing request is obtained.

[0121] Then, further based on the time of the corresponding data of the two types of requests obtained, it is decided which data processing request is executed, specifically:

[0122] In step S317, it is judged whether the acquisition time of the read data is earlier than or equal to the acquisition time of the write data, if yes, step S318 is executed, if not, step S319 is executed.

[0123] In step S318, the read data is sent to the upper level module.

[0124] In step S319, the write data is written into the storage space of the current level module.

[0125] In this way, the processing of each data processing request can be completed according to the order of writing.

[0126] When the prior request data and the subsequent request data are obtained at the same time, one of the two is randomly determined as the prior obtained data, and then the data processing request is processed according to the data request category corresponding to the randomly determined prior obtained data.

[0127] In this way, no matter which prior data processing request is judged, the processing method is to process each one according to the order of receiving the data processing request, and the subsequent data processing request can be processed in the case that the prior request data cannot be processed continuously, so that different data processing requests in different queues can be processed at the same time, thereby the overall efficiency of data processing can be improved while ensuring the correctness of the data processing result.

[0128] The various optional manners introduced by each of the embodiments provided by the embodiments of the present application can be combined with each other and cross-referenced without conflict, thereby extending a plurality of possible embodiments, which can all be considered as the embodiments disclosed and provided by the embodiments of the present application.

[0129] To solve the foregoing problems, the embodiments of the present application further provide a data processing apparatus, which can be considered as a functional module required to be set to implement the data processing method provided by the embodiments of the present application. The apparatus content described below can be cross-referenced with the method content described above.

[0130] As an optional implementation, Figure 6 An optional block diagram of the data processing apparatus provided by the embodiments of the present application is shown. As shown in the figure, Figure 6 The apparatus can include:

[0131] The receiving module 610 is adapted to receive each data processing request, and write each data processing request into a corresponding request category queue according to the request category of each data processing request, and the number of request categories of each data processing request is at least two.

[0132] In further embodiments, when the request categories include read data processing requests and write data processing requests, and the request category queues include read data processing request queues and write data processing request queues, the module is further adapted to write each read data processing request into a read data processing request queue and each write data processing request into a write data processing request queue.

[0133] The request determination module 611 is used to determine a preceding data processing request and a following data processing request according to the writing order of the data processing request located at the head of each request category queue, determine the storage space of the current module corresponding to the preceding request data according to the preceding data processing request, and obtain the preceding request data, wherein the current module is the module receiving each data processing request.

[0134] The processing module 612 is adapted to determine the storage space of the current module corresponding to the following request data according to the following data processing request when the preceding request data is not obtained, obtain the following request data, and complete the data processing request according to the request category of the data processing request corresponding to the preceding obtained data when the preceding obtained data is obtained from both the preceding request data and the following request data.

[0135] In a further embodiment, when the request determining module 611 determines that the read data processing request is the prior data processing request and the write data processing request is the subsequent data processing request, the processing module 612 is further configured to determine the storage space of the current level module corresponding to the read data according to the read data processing request.

[0136] According to the above further embodiment, the specific implementation can further include that when the read data is not obtained in the storage space, the processing module 612 is further configured to determine the storage space of the current level module corresponding to the write data processing request according to the write data processing request, and obtain the write data of the write data processing request.

[0137] In some embodiments, the processing module 612 is further adapted to return the read data to the upper level module when the read data is obtained in the current storage space, wherein the upper level module is the module sending the data processing request, and specifically, the upper level module can be a high-performance computing processor or a level one cache.

[0138] In another embodiment, the processing module 612 is further adapted to send the new read data processing request to the lower level module when the read data is not obtained in the current storage space, wherein the lower level module can be a level two cache, a level three cache, or a main memory 130.

[0139] After obtaining the data corresponding to each data processing request, the processing module 612 is further adapted to send the read data to the upper level module when it is determined that the first obtained data is read data, and write the write data into the storage space of the corresponding current level module when it is determined that the first obtained data is write data.

[0140] The current level module refers to a device provided with multiple request queues of different categories, which can be a level one cache or a level two cache.

[0141] Of course, in another embodiment, when the time of obtaining the data corresponding to each data processing request is equal, the processing module 612 is further adapted to randomly determine one data as the first obtained data and process the data processing request corresponding to the data.

[0142] Specifically, when the read data is randomly determined as the first obtained data, the processing module 612 is adapted to complete the processing of the read data processing request according to the read data processing request corresponding to the read data, and return the read data to the upper level module.

[0143] When the write data is randomly determined as the first obtained data, the processing module 612 is adapted to complete the processing of the write data processing request according to the write data processing request corresponding to the write data, and write the write data into the current level module.

[0144] The above use case is that the read data processing request is determined as the former data processing request and the write data processing request is determined as the latter data processing request. In some other embodiments, the request determining module 611 is further adapted to determine the write data processing request as the former data processing request and the read data processing request as the latter data processing request, in which case the processing module 612 is further adapted to: determine the storage space of the current level module corresponding to the write data according to the write data processing request;

[0145] When the write data is not obtained, the storage space of the current level module corresponding to the read data processing request is determined according to the read data processing request, and the read data of the read data processing request is obtained.

[0146] When the data corresponding to each data processing request is obtained, the processing module 612 can further process the data processing request corresponding to the former obtained data according to the former obtained data.

[0147] Specifically, when the former obtained data is read data, the processing module 612 is adapted to return the read data to the upper level module, which can be a level cache or a high-performance computing processor.

[0148] When the former obtained data is write data, the processing module 612 is adapted to write the write data into the storage space of the corresponding current level module, which can be a level two cache or a level one cache.

[0149] When the read data and the write data are obtained at the same time, a data is randomly determined as the former obtained data, and then the processing module 612 can complete the processing of the corresponding data processing request according to the category of the data processing request corresponding to the randomly determined data.

[0150] In this way, the processing module 612 can implement the received data processing requests of different categories into different request queues for processing according to the categories, and the data processing requests in the same queue are processed in the order of the first and the latter, and the data processing requests in different queues can be processed at the same time. It can be seen that the processing module 612 can effectively improve the efficiency of data processing while ensuring the correctness of the data processing result.

[0151] The embodiment of the application further provides a cache memory 120 adapted to implement the data processing method provided by the embodiment of the application.

[0152] In some embodiments, the cache memory 120 can include the above-mentioned various functional modules for implementing the data processing method provided by the embodiment of the application, which can be combined with Figure 1 , refer to Figure 7 , Figure 7 A structure diagram of the cache memory provided by the embodiment of the application is shown.

[0153] As shown in the figure, the receiving module 610 receives a data processing request, the request determination module 611 determines a previous data processing request, and the processing module 612 processes each data processing request.

[0154] The cache memory 120 provided by the embodiment of the present application can be designed in advance to receive data processing requests of different categories, so that when the cache memory 120 processes each data processing request, the data processing request can be directly placed in a different request category queue according to the category, facilitating subsequent processing.

[0155] The embodiment of the present application also provides an electronic device, which can include the cache memory 120 provided by the embodiment of the present application.

[0156] Although the above is disclosed in the embodiment of the present application, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A data processing method, characterized in that, include: Each data processing request is received, and each data processing request is written into a corresponding request category queue according to the request category of each data processing request. The number of request categories for each data processing request is at least two. Based on the writing order of the data processing requests located at the head of each request category queue, the earlier data processing request and the later data processing request are determined. Based on the earlier data processing request, the storage space of the current level module corresponding to the earlier requested data is determined, and the earlier requested data is obtained. The current level module is the module that receives each of the data processing requests. When the prior requested data is not obtained, the storage space of the current level module corresponding to the subsequent requested data is determined according to the subsequent data processing request, and the subsequent requested data is obtained. When the prior requested data and the subsequent requested data are obtained, the data processing request is completed according to the request category of the data processing request corresponding to the prior requested data.

2. The data processing method as described in claim 1, characterized in that, The request categories include read data processing requests and write data processing requests, and the request category queues include read data processing request queues and write data processing request queues. The step of writing each data processing request into a corresponding request category queue according to the request category of each data processing request includes: Each read data processing request is written to the read data processing request queue, and each write data processing request is written to the write data processing request queue.

3. The data processing method as described in claim 2, characterized in that, When it is determined that the read data processing request is the prior data processing request and the write data processing request is the subsequent data processing request, the step of determining the storage space of the current-level module corresponding to the prior data request based on the prior data processing request includes: The step of determining the storage space of the current-level module corresponding to the read data based on the read data processing request, and determining the storage space of the current-level module corresponding to the subsequent data request based on the subsequent data processing request when the prior requested data is not obtained, and obtaining the subsequent requested data includes: When the read data is not obtained from the storage space, the storage space of the current level module corresponding to the write data processing request is determined according to the write data processing request, and the write data of the write data processing request is obtained.

4. The data processing method as described in claim 3, characterized in that, After the step of determining the storage space of the current-level module corresponding to the read data based on the read data processing request, the method further includes: When the read data is obtained from the storage space, the read data is returned to the previous level module, wherein the previous level module is the module that sends each of the data processing requests.

5. The data processing method as described in claim 3, characterized in that, After the step of determining the storage space of the current-level module corresponding to the read data based on the read data processing request, the method further includes: When the read data is not obtained from the storage space, a new read data processing request is sent to the next level module, wherein the next level module is the module that sent the request to the current level module.

6. The data processing method as described in claim 3, characterized in that, The step of completing the data processing request according to the request category of the data processing request corresponding to the first-obtained data and the second-obtained data when the first-obtained data is obtained includes: When the previously obtained data is the read data, the read data is sent to the next-level module, which is the module that sends each of the data processing requests; or, When the previously obtained data is the write data, the write data is written to the storage space of the current level module.

7. The data processing method as described in claim 6, characterized in that, The step of obtaining the earlier of the previously requested data and the later requested data includes: When both the first requested data and the second requested data are obtained simultaneously, one of them is randomly determined as the first obtained data.

8. The data processing method as described in claim 2, characterized in that, When it is determined that the write data processing request is the prior data processing request and the read data processing request is the subsequent data processing request. The step of determining the storage space of the current-level module corresponding to the prior data request based on the prior data processing request includes: The storage space of the current-level module corresponding to the write data is determined based on the write data processing request; When the previously requested data is not obtained, the step of determining the storage space of the current-level module corresponding to the subsequently requested data based on the subsequently requested data, and obtaining the subsequently requested data, includes: When the write data is not obtained, the storage space of the current level module corresponding to the read data processing request is determined according to the read data processing request, and the read data of the read data processing request is obtained.

9. The data processing method according to any one of claims 1-8, characterized in that, The current-level module includes a first-level cache or a second-level cache.

10. A data processing apparatus, characterized in that, include: The receiving module is adapted to receive each of the data processing requests and write each of the data processing requests into a corresponding request category queue according to the request category of each data processing request, and the number of request categories of each data processing request is at least 2. The request determination module is used to determine the earlier and later data processing requests based on the writing order of the data processing requests located at the head of each request category queue, determine the storage space of the current level module corresponding to the earlier requested data based on the earlier data processing request, and obtain the earlier requested data, wherein the current level module is the module that receives each of the data processing requests. The processing module is adapted to determine the storage space of the current-level module corresponding to the subsequent data request based on the subsequent data processing request when the prior requested data is not obtained, and to obtain the subsequent requested data. When the prior requested data and the subsequent requested data are obtained, the data processing request is completed according to the request category of the data processing request corresponding to the prior requested data.

11. The data processing apparatus as claimed in claim 10, characterized in that, The request categories include read data processing requests and write data processing requests, and the request category queues include read data processing request queues and write data processing request queues. The receiving module is adapted to write each data processing request into its corresponding request category queue according to the request category of each data processing request, including: Each read data processing request is written to the read data processing request queue, and each write data processing request is written to the write data processing request queue.

12. The data processing apparatus as claimed in claim 11, characterized in that, When the request determination module determines that the read data processing request is the prior data processing request and the write data processing request is the subsequent data processing request, the processing module is adapted to determine the storage space of the current-level module corresponding to the prior requested data based on the prior data processing request. When the prior requested data is not obtained, the processing module determines the storage space of the current-level module corresponding to the subsequent requested data based on the subsequent data processing request. Obtaining the subsequent requested data includes: The storage space of the current-level module corresponding to the read data is determined according to the read data processing request; when the read data is not obtained in the storage space, the storage space of the current-level module corresponding to the write data processing request is determined according to the write data processing request, and the write data of the write data processing request is obtained.

13. The data processing apparatus as claimed in claim 12, characterized in that, The processing module is further adapted to return the read data to the next-level module when the storage space obtains the read data, wherein the next-level module is the module that sends each of the data processing requests.

14. The data processing apparatus as claimed in claim 12, characterized in that, The processing module is also adapted to send a new read data processing request to the next-level module when the storage space does not obtain the read data, wherein the next-level module is the module that sent the request to the current-level module.

15. The data processing apparatus as claimed in claim 12, characterized in that, The processing module is also adapted to send the read data to the next-level module when the previously obtained data is the read data, wherein the next-level module is the module that sends each of the data processing requests; When the previously obtained data is the write data, the write data is written to the storage space of the corresponding current-level module.

16. The data processing apparatus as claimed in claim 15, characterized in that, The processing module is adapted to select either data as the first obtained data when both the first requested data and the second requested data are obtained simultaneously.

17. The data processing apparatus as claimed in claim 11, characterized in that, When the request determination module determines that the write data processing request is the prior data processing request and the read data processing request is the subsequent data processing request, the processing module is further adapted to determine the storage space of the current-level module corresponding to the prior requested data based on the prior data processing request. When the prior requested data is not obtained, the module determines the storage space of the current-level module corresponding to the subsequent requested data based on the subsequent data processing request, and obtains the subsequent requested data, including: The storage space of the current-level module corresponding to the write data is determined according to the write data processing request; when the write data is not obtained, the storage space of the current-level module corresponding to the read data processing request is determined according to the read data processing request, and the read data of the read data processing request is obtained.

18. A high-speed cache memory, characterized in that, Suitable for performing the data processing method as described in any one of claims 1-9.

19. An electronic device, characterized in that, Includes the cache memory as described in claim 18.

Images