Display device

Abstract

A display device is provided, including: a substrate; a data line on the substrate; a first insulating layer on the data line; a first transistor on the first insulating layer; a second insulating layer on the first transistor; a pixel electrode on the second insulating layer, the pixel electrode electrically connected to the first transistor; and an auxiliary data pattern on the second insulating layer, the auxiliary data pattern on the same layer as the pixel electrode, the auxiliary data pattern electrically connected to the data line.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0089589, filed on July 20, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The disclosure relates generally to a display device. BACKGROUND

[0003] A display device can be formed by depositing and patterning several layers on a substrate. The patterning of the layers can be performed through a photolithography process using a photomask. A different mask can be used to pattern each layer, and a plurality of photomasks corresponding to the number of layers to be patterned can be used. Accordingly, by designing a display device to reduce the number of photomasks used to form the display device, the manufacturing cost of the display device can be reduced.

[0004] The above information disclosed in this Background section is only for enhancing the understanding of the background and therefore it can include information that is not prior art. SUMMARY

[0005] Aspects of one or more embodiments relate to a display device capable of preventing, reducing, or minimizing deterioration of electrical and physical characteristics while reducing the number of photomasks used in the manufacturing of the display device.

[0006] A display device according to an embodiment includes a substrate; a data line on the substrate; a first insulating layer on the data line; a first transistor on the first insulating layer; a second insulating layer on the first transistor; a pixel electrode on the second insulating layer, the pixel electrode electrically connected to the first transistor; and an auxiliary data pattern on the second insulating layer on the same layer as the pixel electrode, the auxiliary data pattern electrically connected to the data line.

[0007] The display device can further include a first connection member on the first insulating layer, the first connection member connected to an electrode of the first transistor; and a third insulating layer between the first connection member and the second insulating layer. The pixel electrode is connected to the first transistor through the first connection member.

[0008] The display device can further include a light-blocking layer between the substrate and the first insulating layer, the light-blocking layer overlapping a channel region of the first transistor. The first connection member can be connected to the light-blocking layer.

[0009] The display device can further include a second transistor on the first insulating layer, and a second connection member between the first insulating layer and the third insulating layer, the second connection member connected to an electrode of the second transistor and the data line. The auxiliary data pattern can be connected to the data line through the second connection member.

[0010] The auxiliary data pattern can be connected to the second connection member through a contact hole formed in the second insulating layer and the third insulating layer.

[0011] The display device can further include a light blocking layer between the base and the first insulating layer, the light blocking layer overlapping a channel region of the first transistor, and a first bridge on the second insulating layer, the first bridge connected to the pixel electrode, an electrode of the first transistor, and the light blocking layer.

[0012] The display device can further include a second transistor on the first insulating layer, and a second bridge on the second insulating layer, the second bridge connected to an electrode of the second transistor and the data line.

[0013] The display device can further include a third bridge on the second insulating layer, the third bridge connected to another electrode of the first transistor and another electrode of the second transistor.

[0014] The pixel electrode and the auxiliary data pattern can include a plurality of layers, and at least one layer from among the plurality of layers can include copper.

[0015] The plurality of layers can include a first layer, a second layer, a third layer, a fourth layer, and a fifth layer sequentially disposed on the second insulating layer. The second layer can include copper.

[0016] The first layer can include titanium or a copper alloy. The third layer can include titanium. The fourth layer can include silver. The fifth layer can include a transparent conductive oxide.

[0017] A display device according to an embodiment includes a base, a first conductor on the base, the first conductor including a light blocking layer and a data line, a first insulating layer on the first conductor, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer, a second conductor on the second insulating layer, the second conductor including a first gate electrode and a second gate electrode, a third insulating layer on the second conductor, a fourth insulating layer on the third insulating layer, and a third conductor on the fourth insulating layer, the third conductor including a pixel electrode and an auxiliary data pattern. The pixel electrode can be electrically connected to the light blocking layer, and the auxiliary data pattern can be electrically connected to the data line.

[0018] The display device can further include a first transistor including a portion of the semiconductor layer and a first gate electrode between the first insulating layer and the third insulating layer, a second transistor including a portion of the semiconductor layer and a second gate electrode between the first insulating layer and the third insulating layer, and a first connection member connected to an electrode of the first transistor between the first insulating layer and the third insulating layer. The pixel electrode can be connected to the electrode of the first transistor through the first connection member.

[0019] The first connection member can be connected to the light-blocking layer through a contact hole formed in the first insulating layer. The pixel electrode can be connected to the first connection member through contact holes formed in the third insulating layer and the fourth insulating layer.

[0020] The display device can further include a second connection member connected to an electrode of the second transistor between the first insulating layer and the third insulating layer. The auxiliary data pattern can be connected to the data line through the second connection member.

[0021] The second connection member can be connected to the data line through a contact hole formed in the first insulating layer. The auxiliary data pattern can be connected to the second connection member through contact holes formed in the third insulating layer and the fourth insulating layer.

[0022] The third conductor can further include a first bridge connected to the electrode of the first transistor and the light-blocking layer, and a second bridge connected to the electrode of the second transistor and the data line.

[0023] The third conductor can include a first layer, a second layer, a third layer, a fourth layer, and a fifth layer sequentially positioned on the fourth insulating layer. The second layer can include copper.

[0024] The first layer can include titanium or a copper alloy. The third layer can include titanium. The fourth layer can include silver. The fifth layer can include a transparent conductive oxide.

[0025] The display device can further include a fifth insulating layer having an opening superposed with the pixel electrode on the third conductor, an emission layer on the pixel electrode, and a common electrode on the emission layer.

[0026] According to embodiments, it is possible to prevent, reduce, or minimize deterioration of electrical and physical characteristics of a display device while reducing the number of photomasks used in the manufacturing of the display device. In addition, according to embodiments, it is possible to provide advantageous effects recognizable throughout the specification. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a top plan view schematically showing a display device according to an embodiment.

[0028] Figure 2 is a circuit diagram of a pixel of a display device according to an embodiment.

[0029] Figure 3 is a schematic cross-sectional view of a display device according to an embodiment.

[0030] Figure 4 is a cross-sectional view of a first electrode of a light emitting diode (LED) in a display device according to an embodiment.

[0031] Figures 5 to 9 is a cross-sectional view of a method of manufacturing a display device shown in Figure 3

[0032] Figure 10 is a schematic cross-sectional view of a display device according to an embodiment.

[0033] Figures 11 to 15 is a cross-sectional view of a method of manufacturing a display device shown in Figure 10

[0034] Figure 16 and Figure 17 is an electron micrograph of a titanium / copper / titanium conductor.

[0035] Figure 18 is a cross-sectional view of a display device according to an embodiment. DETAILED DESCRIPTION

[0036] Embodiments will be described in greater detail with reference to the accompanying drawings, so that those skilled in the art to which the disclosure belongs can easily implement them.

[0037] The terms used herein are merely used to describe specific example embodiments and are not intended to limit the example embodiments described herein.

[0038] Unless the context clearly indicates otherwise, as used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well.

[0039] As used herein, when a phrase such as "at least one of," "one or more of," or "one selected from a plurality of," appears together with a list of one or more members, it means any of the members of the list can be present together with any combination of the members of the list.

[0040] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] In addition, when describing the disclosed embodiments, the use of "may" means "one or more embodiments of the disclosure."

[0042] ​​In the drawings, the relative sizes and the relative dimensions of elements, layers, and regions shown in the figures can be exaggerated and / or simplified for clarity. Spatial relative terms, such as "beneath", "below", "lower", "above", "upper", "bottom", "top", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatial relative descriptors used herein interpreted accordingly.

[0043] As used herein, the terms "substantially", "approximately" and similar terms are used as an approximation term and not as an exact term, and are intended to account for variations that would be recognized by a person of ordinary skill in the art as equivalent.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as "a", "an" and "the" should not be construed to mean "only one" unless otherwise explicitly defined. Embodiments of the present disclosure will now be described, by way of example only, with reference to the attached figures, wherein:

[0045] Furthermore, the dimensions and the thicknesses of the constituent components shown in the drawings are given for better understanding and ease of description.

[0046] It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0047] In addition, unless explicitly described otherwise, the word "comprise" and variations such as "comprising" or "comprises" will not be construed as implying that there are no additional elements. It will be understood that, although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms since these terms are only used to distinguish one element from another. For example, a first element could be termed a second element without departing from the teachings of the present disclosure.

[0048] Throughout the specification, "connection" refers not only to a direct connection between two or more constituent elements, but also to an indirect connection through other constituent elements. In addition, even if substantially integral components can be referred to by different names according to positions or functions, "connection" can include cases in which they are connected to each other, as well as cases of physical or electrical connection.

[0049] In the drawings, the symbols "x", "y", and "z" representing directions are used, in which "x" is a first direction, "y" is a second direction perpendicular to the first direction, and "z" is a third direction perpendicular to the first and second directions. The first, second, and third directions x, y, and z can correspond to a horizontal direction, a vertical direction, and a thickness direction of the display device, respectively.

[0050] Unless otherwise specified in the specification, "stacked" means stacked in a plan view and stacked in the third direction z.

[0051] Figure 1 is a schematic plan view showing a display device according to an embodiment.

[0052] Referring to Figure 1 , the display device can include a display panel 10, a flexible printed circuit film 20, an integrated circuit chip 30, and a printed circuit board (PCB) 40.

[0053] The display panel 10 includes a display area DA corresponding to a screen on which an image is displayed, and a non-display area NA in which a circuit and / or a signal line for generating and / or transmitting a signal (e.g., several signals) applied to the display area DA are disposed. The non-display area NA can surround the display area DA. In Figure 1 , a boundary between the display area DA and the non-display area NA is represented by a dotted quadrilateral. However, the present disclosure is not limited thereto. For example, the non-display area NA indicated by the dotted line can be any suitable shape.

[0054] The pixels PX can be arranged in a matrix form in the display region DA of the display panel 10. In the display region DA, signal lines such as the first scan line 121, the second scan line 122, the data line 171, the drive voltage line 172, the common voltage line 173, the initialization voltage line 174, and the like can be arranged. The first scan line 121 and the second scan line 122 can extend substantially or substantially in the first direction x. The data line 171, the drive voltage line 172, the common voltage line 173, and the initialization voltage line 174 can extend substantially or substantially in the second direction y. At least one of the drive voltage line 172, the common voltage line 173, and the initialization voltage line 174 includes a voltage line extending substantially or substantially in the first direction x and a voltage line extending substantially or substantially in the second direction y, thereby being arranged in a grid form. The first scan line 121, the second scan line 122, the data line 171, the drive voltage line 172, the common voltage line 173, the initialization voltage line 174, and the like are connected to each of the pixels PX, and each of the pixels PX can receive a first scan signal, a second scan signal, a data voltage, a drive voltage (e.g., ELVDD), a common voltage (e.g., ELVSS), an initialization voltage, and the like from these signal lines. The pixels PX can be implemented as light emitting elements such as light emitting diodes (LEDs). In one or more embodiments, each of the pixels PX can be implemented as a light emitting element such as an LED.

[0055] In the display region DA of the display panel 10, a touch sensor for sensing a contact touch and / or a non-contact touch (e.g., a finger, a stylus, or the like hovering near the touch sensor) of a user can be arranged.

[0056] A pad (or called “land”) portion PP can be arranged in the non-display region NA of the display panel 10, and pads for receiving signals from the outside of the display panel 10 are arranged in the pad portion PP. In one or more embodiments, the flexible printed circuit film 20 can be bonded to the pad portion PP. The pads of the flexible printed circuit film 20 can be connected (e.g., electrically connected) to the pads of the pad portion PP. The display panel 10 can include two or more pad portions PP, and the pad portions PP can be arranged apart from or spaced from each other along one edge of the display panel 10. A corresponding flexible printed circuit film 20 can be bonded to each of the pad portions PP. The display panel 10 can include one pad portion PP according to the size, and one flexible printed circuit film 20 can be bonded to the pad portion PP.

[0057] A driving unit for generating and / or processing signals (e.g., a number of signals) to drive the display panel 10 can be disposed in the non-display area NA of the display panel 10. The driving unit can include a data driver to apply a data signal to the data line 171, a gate driver to apply a gate signal to the first scan line 121 and the second scan line 122, and a signal controller to control the gate driver and the data driver. The pixel PX can receive a data voltage or an initialization voltage according to a scan signal generated in the gate driver at a set timing (e.g., a predetermined timing). The gate driver can be integrated on the display panel 10, and can be disposed on at least one side of the display area DA.

[0058] The data driver can be disposed as an integrated circuit chip 30, and the integrated circuit chip 30 can be mounted on the flexible printed circuit film 20. Signals output from the integrated circuit chip 30 can be transmitted to the display panel 10 through the pad portion PP of the flexible printed circuit film 20 and the pad portion PP of the display panel 10. The integrated circuit chip 30 can be mounted on the non-display area NA of the display panel 10, and can be disposed between the display area DA and the pad portion PP. The display apparatus can include a plurality of integrated circuit chips 30, and the number of integrated circuit chips 30 can increase as the size of the display panel 10 increases. The signal controller can be disposed as an integrated circuit chip, and can be mounted on a printed circuit board (PCB) 40. The data driver and the signal controller can each be disposed as an integrated chip. The flexible printed circuit film 20 can be bonded to the printed circuit board (PCB) 40 to be connected (e.g., electrically connected) thereto to transmit signals between the display panel 10 and the printed circuit board (PCB) 40.

[0059] The integrated circuit chip 30 can output signals provided to the display area DA. For example, the integrated circuit chip 30 can output a data voltage, a driving voltage, a common voltage, an initialization voltage, etc. Data voltage transmission lines, driving voltage transmission lines, common voltage transmission lines, and initialization voltage transmission lines can be disposed in the non-display area NA to transmit the data voltage, the driving voltage, the common voltage, and the initialization voltage output from the integrated circuit chip 30 to the data line 171, the driving voltage line 172, the common voltage line 173, and the initialization voltage line 174 of the display area DA. The integrated circuit chip 30 can also output signals for controlling the gate driver to the non-display area NA, and lines to transmit the signals can be connected thereto.

[0060] Figure 2 is a circuit diagram of a pixel PX of a display apparatus according to an embodiment.

[0061] The pixel PX can include transistors T1, T2, and T3, a storage capacitor C ST and an LED.

[0062] The transistors T1, T2, and T3 include a first transistor T1, a second transistor T2, and a third transistor T3. As Figure 2 indicated in the middle, the transistors T1, T2, and T3 can be N-type transistors. However, the disclosure is not limited thereto. For example, the transistors T1, T2, and T3 can be P-type transistors, and can also include N-type transistors and P-type transistors with appropriate changes to the circuit.

[0063] The first transistor T1 includes a gate electrode G1 (referred to as a control electrode) connected to a first electrode of a storage capacitor C ST and a drain electrode D2 of the second transistor T2, a source electrode S1 (referred to as a first electrode or an input electrode) connected to a driving voltage line 172, and a drain electrode D1 (referred to as a second electrode or an output electrode) connected to a pixel electrode of an LED and a second electrode of the storage capacitor C ST . The first transistor T1 can receive a data voltage V DAT according to a switching operation of the second transistor T2 to supply a driving current to the LED according to a voltage stored in the storage capacitor C ST . The first transistor T1 can be a transistor that outputs a driving current to the LED, and can be referred to as a driving transistor.

[0064] The second transistor T2 includes a gate electrode G2 connected to a first scan line 121, a source electrode S2 connected to a data line 171, and a drain electrode D2 connected to a first electrode of the storage capacitor C ST and the gate electrode G1 of the first transistor T1. The second transistor T2 is turned on according to a first scan signal SC applied through the first scan line 121, so that a reference voltage or a data voltage V DAT may be transmitted to the gate electrode G1 of the first transistor T1 and the first electrode of the storage capacitor C ST . The second transistor T2 can be referred to as a switching transistor.

[0065] The third transistor T3 includes a gate electrode G3 connected to a second scan line 122, a source electrode S3 connected to an initialization voltage line 174, and a drain electrode D3 connected to a second electrode of the storage capacitor C ST and the pixel electrode of the LED. The third transistor T3 is turned on according to a second scan signal SS applied through the second scan line 122 to transmit an initialization voltage V ST to the pixel electrode of the LED and the second electrode of the storage capacitor C INT , thereby initializing the voltage of the pixel electrode of the LED. The third transistor T3 can be referred to as an initialization transistor.

[0066] The storage capacitor C STThe first electrode includes the gate electrode G1 of the first transistor T1 and the second electrode includes the pixel electrode of the LED.

[0067] The LED includes the pixel electrode connected to the drain electrode D1 of the first transistor T1 and the common electrode connected to the common voltage line 173. When the first transistor T1 is turned on, a driving current flows to the LED, and the LED can emit light having a set brightness (e.g., a predetermined brightness).

[0068] The operation of the pixel PX during one frame is described in more detail below. Figure 1 The pixel PX can be operated (e.g., driven) during one frame in about four periods (e.g., four phases), i.e., an initialization period, a sensing period, a data input period, and a light emission period.

[0069] In the initialization period, the first scan signal SC of a high level and the second scan signal SS of a high level are supplied, so that the second transistor T2 and the third transistor T3 are turned on. The reference voltage from the data line 171 is supplied to the gate electrode G1 of the first transistor T1 and the first electrode of the storage capacitor C ST through the turned-on second transistor T2, and the initialization voltage V INT is supplied to the drain electrode D1 of the first transistor T1 and the pixel electrode of the LED through the turned-on third transistor T3. Accordingly, during the initialization period, the drain electrode D1 of the first transistor T1 and the pixel electrode of the LED are initialized to the initialization voltage V INT . At this time, a voltage corresponding to the difference between the reference voltage and the initialization voltage V INT is stored in the storage capacitor C ST .

[0070] In the sensing period, if the second scan signal SS becomes a low level in a state where the first scan signal SC of a high level is maintained, the second transistor T2 maintains the on state, and the third transistor T3 is turned off. The gate electrode G1 of the first transistor T1 and the first electrode of the storage capacitor C ST maintain the reference voltage through the turned-on second transistor T2, and the drain electrode D1 of the first transistor T1 and the pixel electrode of the LED are disconnected from the initialization voltage V INT through the turned-off third transistor T3. Accordingly, when a current flows from the source electrode S1 to the drain electrode D1, if the voltage of the drain electrode D1 becomes "the reference voltage - the threshold voltage of the first transistor T1", the first transistor T1 is turned off. At this time, the voltage difference between the gate electrode G1 and the drain electrode D1 of the first transistor T1 is stored in the storage capacitor C STIn the process, the threshold voltage of the first transistor T1 is sensed. By generating a data voltage that reflects the characteristic information sensed during the sensing period, the characteristic deviation of the first transistor T1 for each pixel PX may be compensated externally.

[0071] During the data input period, if a high-level first scan signal SC is supplied and a low-level second scan signal SS is supplied, then the second transistor T2 is turned on, while the third transistor T3 is turned off. The data voltage V from data line 171... DAT The second transistor T2, which is in operation, supplies power to the gate electrode G1 of the first transistor T1 and the storage capacitor C. ST The first electrode. At this time, the drain electrode D1 of the first transistor T1 and the pixel electrode of the LED can maintain their potentials almost unchanged during the sensing period through the first transistor T1 in the off state.

[0072] During the light emission period, the data voltage V transmitted to the gate electrode G1 DAT The first transistor T1 is turned on according to the data voltage V DAT A driving current is generated, so that the LED can emit light based on the driving current to set the brightness (e.g., a predetermined brightness).

[0073] Figure 3 This is a schematic cross-sectional view of a display device according to an embodiment. Figure 3 It schematically shows the situation in relation to Figure 1 The area corresponding to approximately one pixel in the display area DA of the display panel 10 shown in the figure. Figure 2 This is a portion of the constituent elements of the pixel circuit shown.

[0074] Reference Figure 3 The display panel 10 of the display device includes a substrate 110 and layers, components, and wiring on the substrate 110. The substrate 110 may include an insulating material such as glass or plastic.

[0075] The first conductor, including the data line 171 and the light-blocking layer 175, can be disposed on the substrate 110. For example, the data line 171 and the light-blocking layer 175 can be located on the same layer of the substrate 110.

[0076] The light-blocking layer 175 blocks or substantially blocks external light from reaching the semiconductor layer of the transistor, thereby preventing or reducing deterioration of characteristics of the semiconductor layer. The light-blocking layer 175 can control the drain current of the first transistor T1 in which current characteristics are important, particularly in an emission display device. The light-blocking layer 175 can function as an electrode that receives a specific voltage in the display panel 10. In this case, the rate of change of current in the saturation region of the voltage-current characteristic graph of the first transistor T1 can be reduced to improve the characteristics as a driving transistor.

[0077] The first conductor can further include a driving voltage line 172, a common voltage line 173, and / or an initialization voltage line 174. The data line 171, the driving voltage line 172, the common voltage line 173, and / or the initialization voltage line 174 can be laminated with the semiconductor layer of the transistor, thereby functioning like the light-blocking layer 175.

[0078] The components of the first conductor can be formed of the same material in the same process. The first conductor can be formed by forming a layer of conductive material on the substrate 110 and patterning it by using one photomask. Since the first conductor includes the data line 171 in addition to the light-blocking layer 175, a separate photomask used to form the data line 171 or the like can be eliminated. Accordingly, the number of photomasks used to manufacture the display device can be reduced. The first conductor can include a metal such as copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), titanium (Ti), and tantalum (Ta), or one or more alloys thereof. For example, the first conductor can be a multilayer structure such as titanium (Ti) / copper (Cu) or titanium (Ti) / copper (Cu) / titanium (Ti) / copper (Cu). However, the present disclosure is not limited thereto.

[0079] The first insulating layer 120 can be provided on the first conductor. The first insulating layer 120 can block impurities that can be diffused from the substrate 110 to the semiconductor layer in a process of forming the semiconductor layer and reduce stress received by the substrate 110. The first insulating layer 120 can be referred to as a buffer layer. The first insulating layer 120 can include an inorganic insulating material such as silicon nitride (SiN x ) and / or silicon oxide (SiO x ).

[0080] The semiconductor layer of the transistor can be provided on the first insulating layer 120. The semiconductor layer can include a channel region A1 of the first transistor T1 and a channel region A2 of the second transistor T2. The source electrode S1 and the drain electrode D1 of the first transistor T1 on respective sides of the channel region A1 and the source electrode S2 and the drain electrode D2 of the second transistor T2 on respective sides of the channel region A2 can be regions in which the semiconductor layer is a conductor. The channel region A1 of the first transistor T1 can be laminated with the light-blocking layer 175. The semiconductor layer can further include a channel region of the third transistor T3.

[0081] The semiconductor layer can be formed by forming a semiconductor material layer on the first insulating layer 120 and patterning it by using one photo mask. The semiconductor layer can include an oxide semiconductor, polysilicon, or amorphous silicon. The oxide semiconductor can include an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or the like, or a combination of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or the like and an oxide thereof. The oxide semiconductor can include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), or indium zinc tin oxide (IZTO).

[0082] A second insulating layer 140 overlapping the channel regions A1 and A2 can be provided on the semiconductor layer. The second insulating layer 140 can be referred to as a gate insulating layer. The second insulating layer 140 can include an inorganic insulating material such as silicon oxide and / or silicon nitride.

[0083] A second conductor including the gate electrode G1 of the first transistor T1, the gate electrode G2 of the second transistor T2, the connection member CN1, and the connection member CN2 can be provided on the semiconductor layer and the second insulating layer 140.

[0084] The gate electrode G1 of the first transistor T1 can overlap the channel region A1, and the gate electrode G2 of the second transistor T2 can overlap the channel region A2. The gate electrode G1 of the first transistor T1 can extend to be connected to the drain electrode D2 of the second transistor T2. The connection member CN1 in contact with the drain electrode D1 of the first transistor T1 is connected to the light-blocking layer 175 through the contact hole H21 formed in the first insulating layer 120, thereby electrically connecting the drain electrode D1 and the light-blocking layer 175. The connection member CN2 in contact with the source electrode S2 of the second transistor T2 is connected to the data line 171 through the contact hole H22 formed in the first insulating layer 120, thereby electrically connecting the source electrode S2 and the data line 171.

[0085] In one or more embodiments, the second conductor can further include the gate electrode G3 of the third transistor T3. The second conductor can further include a connection member electrically connecting the source electrode S1 of the first transistor T1 and the driving voltage line 172, a connection member electrically connecting the source electrode S3 of the third transistor T3 and the initialization voltage line 174, and a connection member connected to the common voltage line 173. The second conductor can further include the first scan line 121, the second scan line 122, and one electrode of the storage capacitor C ST The gate electrode G2 of the second transistor T2 can be connected to the first scan line 121 or a part of the first scan line 121.

[0086] The second conductor can include at least one of a driving voltage line 172, a common voltage line 173, and an initialization voltage line 174.

[0087] The components of the second conductor can be formed of the same material in the same process. The second conductor can be formed by forming a layer of conductive material on the substrate 110 on which the second insulating layer 140 is formed and patterning it by using a single photomask. The second conductor can include a metal such as copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), titanium (Ti), tantalum (Ta), etc., or an alloy thereof. For example, the second conductor can be a multilayer structure such as titanium (Ti) / copper (Cu) or titanium (Ti) / copper (Cu) / titanium (Ti) / copper (Cu). However, the present disclosure is not limited thereto.

[0088] The contact holes H21 and H22 of the first insulating layer 120 and the second insulating layer 140 can be formed by forming a layer of insulating material on the first insulating layer 120 and the semiconductor layer and patterning it by using one photomask. For example, one photomask can be used to form a layer of insulating material on the semiconductor layer and to pattern the layer of insulating material to form the second insulating layer 140 and the contact holes H21 and H22 in the first insulating layer 120.

[0089] A third insulating layer 160 can be disposed on the second conductor. The third insulating layer 160 can include an inorganic insulating material such as silicon oxide and / or silicon nitride. The third insulating layer 160 can be referred to as a passivation layer.

[0090] A fourth insulating layer 180 can be disposed on the third insulating layer 160. The fourth insulating layer 180 can include an organic insulating material such as an acryl-based polymer, a silicone-based polymer, and / or an imide-based polymer. The fourth insulating layer 180 can be referred to as a planarization layer.

[0091] A third conductor including a pixel electrode E1 and an auxiliary data pattern AD of an LED can be disposed on the fourth insulating layer 180. The pixel electrode E1 can be connected (e.g., electrically connected) to the connection member CN1 through a contact hole H80 formed in the fourth insulating layer 180 and the third insulating layer 160. Since the connection member CN1 is connected to the drain electrode D1 of the first transistor T1, the pixel electrode E1 can be connected (e.g., electrically connected) to the drain electrode D1. The auxiliary data pattern AD can be connected (e.g., electrically connected) to the data line 171 through a contact hole H81 formed in the fourth insulating layer 180 and the third insulating layer 160, since the connection member CN2 is connected to the data line 171.

[0092] The third conductor including the pixel electrode E1 and the auxiliary data pattern AD can be a multilayer structure, and reference is made to Figure 4Detailed structure is explained. Figure 4 is a cross-sectional view of a pixel electrode E1 of an LED in a display device according to an embodiment.

[0093] Referring to Figure 4 , the third conductor including the pixel electrode E1 can have a structure (e.g., a multi-layer structure) in which the first layer L1, the second layer L2, the third layer L3, the fourth layer L4, and the fifth layer L5 are stacked (e.g., sequentially stacked).

[0094] The first layer L1 can increase adhesion of the pixel electrode E1 to the fourth insulating layer 180. The first layer L1 can also be a lower barrier layer that prevents or substantially prevents the lower surface of the second layer L2 from being corroded. The first layer L1 can include a material having a stronger corrosion resistance than the second layer L2. The first layer L1 can include a metal such as titanium (Ti), molybdenum (Mo), copper (Cu), or one or more alloys thereof.

[0095] The second layer L2 located above the first layer L1 can include a metal such as copper (Cu) having a small specific resistance. In the case where the second layer L2 includes copper (Cu), the first layer L1 can include a material having excellent adhesion properties with the fourth insulating layer 180 and the second layer L2. For example, the first layer L1 can include a copper alloy such as a copper (Cu)-magnesium (Mg)-aluminum (Al) alloy and / or a copper (Cu)-calcium (Ca) alloy. To reduce the resistance of the pixel electrode E1, the second layer L2 can be formed to be relatively thick. The second layer L2 can have a thickness of about 3000 angstroms or more.

[0096] The third layer L3 located on the second layer L2 can be an upper barrier layer that covers the upper surface of the second layer L2 and prevents or substantially prevents the upper surface of the second layer L2 from being corroded. The third layer L3 can include a material having a stronger corrosion resistance than the second layer L2. The third layer L3 can include a metal such as titanium (Ti) and / or molybdenum (Mo) or one or more alloys thereof.

[0097] The fourth layer L4 located on the third layer L3 can reflect light emitted from an emission layer (EL) of the LED to improve light emission efficiency. The fourth layer L4 can include a metal such as silver (Ag) or an alloy thereof (e.g., a silver (Ag)-indium (In) alloy) having a low specific resistance and excellent reflectivity.

[0098] The fifth layer L5 located on the fourth layer L4 can prevent or substantially prevent the upper surface of the fourth layer L4 from being corroded. The fifth layer L5 can include a material having a stronger corrosion resistance than the fourth layer L4. The fifth layer L5 can include a transparent conductive oxide such as indium tin oxide (ITO) and / or indium zinc oxide (IZO). The fifth layer L5 can be the uppermost layer of the pixel electrode E1.

[0099] As described above, the data line 171, etc. is formed as a first conductor such as a light blocking layer 175 located between the base 110 and the first insulating layer 120. It is advantageous to increase the thickness of the first conductor to reduce the resistance of the data line 171, etc., thereby reducing RC delay. However, when the thickness of the first conductor increases, the step of the insulating layer such as the first insulating layer 120 formed on the first conductor increases, and the step coverage of the insulating layer can be poor, causing defects such as cracking or adhesion deterioration to possibly occur in the insulating layer, the semiconductor layer, and / or the conductor. In one or more embodiments, when the third conductor including the pixel electrode E1 and the auxiliary data pattern AD is formed to include a metal layer containing a low-resistance metal such as copper (Cu), the resistance of the wiring in the display device can be reduced. For example, because the auxiliary data pattern AD is connected (e.g., electrically connected) to the data line 171, the resistance of the data line 171 can be reduced. Thus, even if the first conductor is formed to a set thickness (e.g., a predetermined thickness) such that the problem due to the step does not occur, the first conductor can be designed to satisfy the resistance characteristics required for the display device. In other words, in one or more embodiments of the disclosure, the desired resistance characteristics of the display device can be satisfied without increasing the thickness of the first conductor to a thickness that can cause defects.

[0100] The third conductor can further include another electrode of a storage capacitor C ST .

[0101] The components of the third conductor can be formed by the same material in the same process. The third conductor on the fourth insulating layer 180 can be formed by forming (e.g., sequentially forming) a first conductive material layer, a second conductive material layer, a third conductive material layer, a fourth conductive material layer, and a fifth conductive material layer and patterning them by using one photomask.

[0102] Referring again to Figure 3 , a fifth insulating layer 360 can be disposed on the fourth insulating layer 180 and the third conductor. The fifth insulating layer 360 can have an opening 61 superposed with the pixel electrode E1. The opening 61 of the fifth insulating layer 360 can define each pixel area, and can be referred to as a pixel defining layer or a partition. The fifth insulating layer 360 can include an organic insulating material such as an acryl-based polymer and / or an imide-based polymer. The fifth insulating layer 360 can include a black pigment or a black dye. In this case, the black pigment or the black dye of the fifth insulating layer 360 can improve contrast and prevent or substantially prevent reflection of the metal layer located below the fifth insulating layer 360 from being viewed.

[0103] The emission layer EL can be provided on the pixel electrode E1. The emission layer EL can be provided within the opening 61 of the fifth insulating layer 360. The emission layer EL can also be provided on the fifth insulating layer 360. In addition to the emission layer EL, at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer can be provided on the pixel electrode E1.

[0104] The common electrode E2 can be provided on the emission layer EL. The common electrode E2 can be provided so as to span several pixels PX. The common electrode E2 can be connected to a connection member that is directly or indirectly connected to the common voltage line 173, thereby being electrically connected to the common voltage line 173. In the emission layer EL and the fifth insulating layer 360, a contact hole for connecting the common electrode E2 to the connection member can be formed by laser drilling. The common electrode E2 can be formed thinly of a metal or a metal alloy having a low work function, such as calcium (Ca), barium (Ba), magnesium (Mg), aluminum (Al), silver (Ag), or the like, so as to have a light-transmitting property. The common electrode E2 can include a transparent conductive oxide such as indium tin oxide (ITO) and / or indium zinc oxide (IZO).

[0105] The pixel electrode E1, the emission layer EL, and the common electrode E2 of each pixel PX form an LED such as an organic light-emitting diode. The pixel electrode E1 can be an anode of a light-emitting diode (LED), and the common electrode E2 can be a cathode of the light-emitting diode (LED). The LED can emit blue light. The LED can emit light of one of the three primary colors (e.g., red, green, or blue) or emit white light.

[0106] An encapsulation layer can be provided on the common electrode E2. The encapsulation layer can be a glass substrate combined with the substrate 110 by a sealant. The encapsulation layer can be a thin film encapsulation layer in which at least one inorganic layer and at least one organic layer are stacked.

[0107] Reference will now be made in detail Figures 5 to 9 One example of a method for manufacturing Figure 3 the display device shown in FIG. 1A.

[0108] Figures 5 to 9 is a cross-sectional view illustrating a method of manufacturing Figure 3 the display device shown in FIG. 1A.

[0109] Reference will now be made in detail Figure 5 A layer of conductive material can be formed on the substrate 110 and patterned to form first conductors including the data lines 171, the drive voltage lines 172, the common voltage line 173, the initialization voltage line 174, and the light-blocking layer 175.

[0110] A first insulating layer 120 may be formed on the first conductor. A semiconductor material layer may be formed on the first insulating layer 120 and patterned to form a semiconductor layer including a channel region A1 of the first transistor T1, a channel region A2 of the second transistor T2, and a channel region of the third transistor T3. The semiconductor layer may also include a source region and a drain region on a respective side of each channel region of transistors T1, T2, and T3.

[0111] An insulating material layer can be formed on the semiconductor layer and patterned to form a second insulating layer 140 and contact holes H21 and H22 in the first insulating layer 120. That is, the second insulating layer 140 and contact holes H21 and H22 can be formed using a photomask. The source and drain regions of transistors T1, T2, and T3 not covered by the second insulating layer 140 can be conductors serving as source electrodes S1, S2, and S3 and drain electrodes D1, D2, and D3. During heat treatment to activate the channel region, the formation of the third insulating layer 160, and / or separate plasma treatment or heat treatment, the source and drain regions can be made conductive by diffusion or doping with hydrogen (H) or the like.

[0112] A conductive material layer can be formed and patterned on a substrate 110 including a second insulating layer 140 to form a second conductor including gate electrodes G1, G2 and G3 of transistors T1, T2 and T3 and connecting members CN1 and CN2.

[0113] A third insulating layer 160 can be formed on the second conductor, and a fourth insulating layer 180 can be formed on the third insulating layer 160. The fourth insulating layer 180 can be patterned to form contact holes H80 and H81.

[0114] A conductive material layer 190 can be formed on the fourth insulating layer 180 and patterned to form a third conductor including a pixel electrode E1 and an auxiliary data pattern AD. Figure 4 As shown, the third conductor may include a first layer L1, a second layer L2, a third layer L3, a fourth layer L4, and a fifth layer L5. The third conductor, having a multilayer structure, can be formed by forming (e.g., sequentially forming) a first conductive material layer comprising (e.g., titanium (Ti),) a second conductive material layer comprising (e.g., copper (Cu),) a third conductive material layer comprising (e.g., titanium (Ti),) a fourth conductive material layer comprising (e.g., silver (Ag),) and a fifth conductive material layer comprising (e.g., indium tin oxide (ITO)) on the fourth insulating layer 180 and then patterning them.

[0115] The following reference Figures 6 to 9 The formation process of the third conductor will be explained in more detail.

[0116] Referring to Figure 6 A conductive material layer 190 including first to fifth conductive material layers (i.e., a first conductive material layer, a second conductive material layer, a third conductive material layer, a fourth conductive material layer, and a fifth conductive material layer) is formed on the fourth insulating layer 180. In this case, the conductive material layer 190 can be connected to the connection members CN1 and CN2 through the contact holes H80 and H81 of the fourth insulating layer 180 and the third insulating layer 160. A photoresist is coated on the conductive material layer 190, and the photoresist is patterned using a photomask through a photolithography process to form a photoresist pattern PR. The photoresist pattern PR can be superposed with the third conductor.

[0117] Referring to Figure 7 First, the fifth conductive material layer and the fourth conductive material layer are wet-etched by using the photoresist pattern PR as a mask. A phosphoric acid-acetic acid-nitric acid etchant can be used in the first wet-etching. Through the first wet-etching, the fourth conductive material layer including silver (Ag) and the fifth conductive material layer including indium tin oxide (ITO) are etched, and the first to third conductive material layers (i.e., the first conductive material layer, the second conductive material layer, and the third conductive material layer) are left without being etched (i.e., unetched). Accordingly, in the conductive material layer 190, the first to fifth conductive material layers exist (e.g., are present) in regions superposed with the photoresist pattern PR, and the first to third conductive material layers exist (e.g., are present) in regions not superposed with the photoresist pattern PR (i.e., exposed by the photoresist pattern PR). During the first wet-etching, the second conductive material layer is protected from the etching solution by the third conductive material layer, so that the second conductive material layer is not damaged or etched.

[0118] Referring to Figure 8 The third conductive material layer, the second conductive material layer, and the first conductive material layer are twice wet-etched by using the photoresist pattern PR as a mask. A non-hydrogen peroxide etchant including nitric acid and hydrofluoric acid can be used in the second wet-etching. Through the second wet-etching, the third conductive material layer including titanium (Ti), the second conductive material layer including copper (Cu), and the first conductive material layer including titanium (Ti) are etched. Accordingly, in the conductive material layer 190, the first to fifth conductive material layers exist in regions superposed with the photoresist pattern PR, and the first to fifth conductive material layers are removed in regions not superposed with the photoresist pattern PR (i.e., exposed by the photoresist pattern PR), thereby forming a third conductor including a pixel electrode E1 and an auxiliary data pattern AD.

[0119] Referring to Figure 9 The photoresist pattern PR disposed on the third conductor is removed through a lift-off process.

[0120] As described above, the third conductor including the first to fifth layers L1 to L5 (i.e., the first layer L1, the second layer L2, the third layer L3, the fourth layer L4, and the fifth layer L5) can be formed by one-time wet etching and two-time wet etching, but the third conductor can be formed using a single photomask.

[0121] After the third conductor is formed, reference is made again to Figure 3 An insulating material layer is formed over the third conductor and is patterned to form a fifth insulating layer having an opening 61 superposed with the pixel electrode E1. Subsequently, the emission layer EL and the common electrode E2 are formed (e.g., sequentially formed), thereby manufacturing a display device having a cross-sectional structure as shown in Figure 3 When such a display device is manufactured, seven photomasks can be used, and one photomask can be excluded compared to a display device including a conductor between the fourth insulating layer 180 and the fifth insulating layer 360.

[0122] Figure 10 is a schematic cross-sectional view of a display device according to an embodiment.

[0123] As described above, Figure 3 similarly, Figure 10 is schematically shown in a region corresponding to about one pixel region in the display region DA of the display panel 10 shown in Figure 1 is a part of the constituent elements of the pixel circuit shown in Figure 2 Figure 10 Embodiments of

[0124] Referring to Figure 10 , the first conductor including the data line 171 and the light-blocking layer 175 can be provided over the substrate 110. The first conductor can further include the drive voltage line 172, the common voltage line 173, and / or the initialization voltage line 174.

[0125] The first insulating layer 120 as an insulating layer can be provided over the first conductor. The semiconductor layer of the transistor can be provided over the first insulating layer 120. The semiconductor layer can include the channel region Al of the first transistor Tl, the channel region A2 of the second transistor T2, and the channel region of the third transistor T3.

[0126] The second insulating layer 140 superposed with the channel regions Al and A2 can be provided over the semiconductor layer. The second conductor including the gate electrode Gl of the first transistor Tl and the gate electrode G2 of the second transistor T2 can be provided over the semiconductor layer and the second insulating layer 140. The second conductor can further include the gate electrode G3 of the third transistor T3. The second conductor can further include the first scan line 121, the second scan line 122, and the storage capacitor C ST ​The second conductor can include at least one of a driving voltage line 172, a common voltage line 173, and an initialization voltage line 174.

[0127] A third insulating layer 160 can be disposed on the second conductor. A fourth insulating layer 180 can be disposed on the third insulating layer 160.

[0128] A third conductor including a first bridge BR1, a second bridge BR2, a third bridge BR3, and a pixel electrode E1 of an LED can be disposed on the fourth insulating layer 180.

[0129] The first bridge BR1 is connected to the drain electrode D1 of the first transistor T1 through a contact hole H82 formed in the fourth insulating layer 180 and the third insulating layer 160, and is connected to the light blocking layer 175 through a contact hole H83 formed in the fourth insulating layer 180, the third insulating layer 160, and the first insulating layer 120, thereby electrically connecting the light blocking layer 175 and the drain electrode D1.

[0130] The second bridge BR2 is connected to the data line 171 through a contact hole H84 formed in the fourth insulating layer 180, the third insulating layer 160, and the first insulating layer 120, and is connected to the source electrode S2 of the second transistor T2 through a contact hole H85 formed in the fourth insulating layer 180 and the third insulating layer 160, thereby electrically connecting the source electrode S2 and the data line 171. Since the second bridge BR2 is connected to the data line 171, the resistance of the data line 171 can be reduced. Accordingly, the second bridge BR2 can be an auxiliary data pattern AD that reduces the resistance of the data line 171. The auxiliary data pattern AD can further include a portion extending from the second bridge BR2.

[0131] The third bridge BR3 is connected to the gate electrode G1 of the first transistor T1 through a contact hole H86 formed in the fourth insulating layer 180 and the third insulating layer 160, and is connected to the drain electrode D2 of the second transistor T2 through a contact hole H87 formed in the fourth insulating layer 180 and the third insulating layer 160, thereby electrically connecting the gate electrode G1 and the drain electrode D2.

[0132] The pixel electrode E1 can be connected to the first bridge BR1. Since the first bridge BR1 is connected to the drain electrode D1 of the first transistor T1, the pixel electrode E1 can be connected (e.g., electrically connected) to the drain electrode D1. The pixel electrode E1 can be connected to the light blocking layer 175 through the contact hole H83, and can be connected to the drain electrode D1 of the first transistor T1 through the contact hole H82.

[0133] Similar to the embodiment of FIG. 1A, Figure 3 The third conductor can have multiple layers. The specific configuration of the third conductor is as described above with reference to the embodiment of FIG. 1A. Figure 4 Figure 4 ​The third conductor illustrated in FIG. 1 can reduce the resistance of the wiring (e.g., the data line 171) even if the first conductor is formed to have a set thickness (e.g., a predetermined thickness) such that a problem caused by the step does not exist, in the display device, and thus the first conductor can be designed to satisfy the resistance characteristics required for the display device.

[0134] The third conductor can further include a bridge electrically connecting the source electrode S1 of the first transistor T1 and the driving voltage line 172, a bridge electrically connecting the source electrode S3 of the third transistor T3 and the initialization voltage line 174, a connection member connected to the common voltage line 173, etc. The third conductor can further include another electrode of the storage capacitor C ST .

[0135] A fifth insulating layer 360 capable of having the opening 61 superposed with the pixel electrode E1 can be disposed on the fourth insulating layer 180 and the third conductor. An emission layer EL can be disposed on the pixel electrode E1. A common electrode E2 can be disposed on the emission layer EL. An encapsulation layer can be disposed on the common electrode E2.

[0136] Figures 11 to 15 is a cross-sectional view illustrating a method of manufacturing a display device illustrated in FIG. 1. Figure 10

[0137] Referring to Figure 11 , a layer of conductive material can be formed on the base 110 and patterned to form the first conductor capable of including the data line 171, the driving voltage line 172, the common voltage line 173, the initialization voltage line 174, and the light-blocking layer 175.

[0138] A first insulating layer 120 can be formed on the first conductor. A layer of semiconductor material can be formed on the first insulating layer 120 and patterned to form a semiconductor layer capable of including a channel region A1 of the first transistor T1, a channel region A2 of the second transistor T2, and a channel region of the third transistor T3. The semiconductor layer can further include a source region and a drain region on a respective side of each of the channel regions of the transistors T1, T2, and T3.

[0139] An insulating material layer can be formed on the semiconductor layer, and a layer of conductive material can be formed on the insulating material layer and patterned to form a second conductor capable of including gate electrodes G1, G2, and G3 of the transistors T1, T2, and T3, and a second insulating layer 140 can be formed. That is, the second conductor and the second insulating layer 140 can be formed using one photomask. The source regions and the drain regions of the transistors T1, T2, and T3 that are not covered by the second insulating layer 140 can be made conductive to become source electrodes S1, S2, and S3 and drain electrodes D1, D2, and D3.

[0140] ​A third insulating layer 160 can be formed on the second conductor, and a fourth insulating layer 180 can be formed on the third insulating layer 160. The fourth insulating layer 180 is patterned to form contact holes H82, H83, H84, H85, H86, and H87.

[0141] A conductive material layer 190 can be formed on the fourth insulating layer 180 and patterned to form a third conductor that can include the pixel electrode E1, the first bridge BR1, the second bridge BR2, and the third bridge BR3. As shown in FIG. 1C, the third conductor can include a first layer L1, a second layer L2, a third layer L3, a fourth layer L4, and a fifth layer L5. The third conductor having a multi-layer structure can be formed by forming (e.g., sequentially forming) a first conductive material layer including titanium (Ti), a second conductive material layer including copper (Cu), a third conductive material layer including titanium (Ti), a fourth conductive material layer including silver (Ag), and a fifth conductive material layer including indium tin oxide (ITO) on the fourth insulating layer 180 and then patterning them. Figure 4

[0142] Reference is made to FIGS. 1A to 1C. Figures 12 to 15 The formation process of the third conductor is described in more detail.

[0143] Reference is made to FIGS. 1A to 1C. Figure 12 The conductive material layer 190 including the first conductive material layer to the fifth conductive material layer is formed on the fourth insulating layer 180. In this case, the conductive material layer 190 can be connected to the drain electrode D1 of the first transistor T1, the gate electrode G1 of the first transistor T1, the drain electrode D2 of the second transistor T2, and the source electrode S2 of the second transistor T2 through the respective contact holes H82, H86, H87, and H85 of the fourth insulating layer 180 and the third insulating layer 160, and can be connected to the light-blocking layer 175 and the data line 171 through the respective contact holes H83 and H84 of the fourth insulating layer 180, the third insulating layer 160, and the first insulating layer 120.

[0144] A photoresist is coated on the conductive material layer 190 and patterned, and a photolithography process using a photomask is performed to form a photosensitive film pattern PR. The photosensitive film pattern PR can be superposed on the third conductor.

[0145] Reference is made to FIGS. 1A to 1C. Figure 13 ​, the fifth conductive material layer is first wet-etched by using the photosensitive film pattern PR as a mask. In the first wet-etching, phosphoric acid, nitric acid, and acetic acid etching agents can be used. By the first wet-etching, the fourth conductive material layer including silver (Ag) and the fifth conductive material layer including indium tin oxide (ITO) are etched, and the first to third conductive material layers are not etched and remain. Thus, in the conductive material layer 190, the first to fifth conductive material layers exist (e.g., are present) in regions overlaid with the photosensitive film pattern PR, and the first to third conductive material layers exist (e.g., are present) in regions not overlaid with the photosensitive film pattern PR (i.e., exposed to the photosensitive film pattern PR).

[0146] Referring to Figure 14 , the third, second, and first conductive material layers are second wet-etched by using the photosensitive film pattern PR as a mask. In the second wet-etching, non-hydrogen peroxide copper etching agents can be used. By the second wet-etching, the third conductive material layer including titanium (Ti), the second conductive material layer including copper (Cu), and the first conductive material layer including titanium (Ti) are etched. Thus, in the conductive material layer 190, the first to fifth conductive material layers exist (e.g., are present) in regions overlaid with the photosensitive film pattern PR, and the first to fifth conductive material layers are removed in regions not overlaid with the photosensitive film pattern PR (i.e., exposed to the photosensitive film pattern PR), thereby forming a third conductor capable of including the pixel electrode E1, the first bridge BR1, the second bridge BR2, and the third bridge BR3.

[0147] Referring to Figure 15 , the photosensitive film pattern PR provided on the third conductor is removed by a peeling process.

[0148] As described above, the third conductor including the first to fifth layers L1 to L5 can be formed by two times of wet-etching, but can be formed using one photomask. Subsequent processes are the same as the processes described above with reference to the embodiment of Figure 3 . In manufacturing such a display device, six photomasks can be used, and two photomasks can be excluded compared to a display device including a conductor between the fourth insulating layer 180 and the fifth insulating layer 360.

[0149] Figure 16 and Figure 17 is an electron micrograph of a titanium (Ti) / copper (Cu) / titanium (Ti) conductor.

[0150] Referring to Figure 16After forming the conductive layer in which titanium (Ti), copper (Cu), titanium (Ti), silver (Ag), and ITO are stacked in this order on the insulating layer, the ITO layer and the silver layer were etched with a phosphoric acid-nitric acid-acetic acid etchant. The copper layer was confirmed not to be damaged. This indicates that the copper layer is not damaged by the first etching in the process for forming the third conductor according to the embodiment.

[0151] Referring to Figure 17 After forming the conductive layer of titanium (Ti) / copper (Cu) / titanium (Ti) on the insulating layer, etching evaluation using a non-hydrogen peroxide etchant was performed. The titanium (Ti) / copper (Cu) / titanium (Ti) conductive layer was etched entirely and exhibited a good etching profile. This indicates that the titanium (Ti) / copper (Cu) / titanium (Ti) conductive layer is well etched by the second etching in the process for forming the third conductor according to the embodiment.

[0152] Figure 18 is a cross-sectional view of a display device according to an embodiment.

[0153] In Figure 3 the embodiment and Figure 10 the embodiment, the common electrode E2 is provided on the top. The constituent elements that can be provided on the common electrode E2 in the display device according to the embodiment are described in more detail below with reference to Figure 18 .

[0154] Referring to Figure 18 , the display device can include pixels PX1, PX2, and PX3 that emit different colors of light.

[0155] The pixel electrode E1 of each of the pixels PX1, PX2, and PX3 can be provided on the substrate 110. The fifth insulating layer 360 having an opening superposed with the pixel electrode E1 can be provided on the substrate 110, and the emission layer EL and the common electrode E2 can be provided on the pixel electrode E1 and the fifth insulating layer 360. The emission layer EL can include a light-emitting material that emits a first color light, which can be blue light. In Figure 18 , the insulating layers and the conductors provided between the substrate 110 and the pixel electrode E1, the auxiliary data pattern provided on the same layer as the pixel electrode E1, the conductors such as a bridge, and the like are omitted, but they can be provided as shown in Figure 3 or Figure 10 .

[0156] The encapsulation layer 380 can be provided on the common electrode E2. The encapsulation layer 380 can be a thin-film encapsulation layer including inorganic insulating layers 381 and 383 and an organic insulating layer 382.

[0157] The filling layer 390 including a filler can be located on the encapsulation layer 380. The cover layer 400 including an insulating material, the color conversion layers 430a and 430b, and the transmission layer 430c can be disposed on the filling layer 390.

[0158] The transmission layer 430c can transmit first color light, which can be blue light. The transmission layer 430c can include a polymer material that transmits the first color light. An area in which the transmission layer 430c is disposed can correspond to a light emitting area that emits blue light. The transmission layer 430c does not include semiconductor nanocrystals and can pass the incident first color light as it is.

[0159] The color conversion layers 430a and 430b can include different semiconductor nanocrystals. For example, first color light incident on the color conversion layer 430a can be converted into second color light and emitted by the semiconductor nanocrystals included in the color conversion layer 430a. First color light incident on the color conversion layer 430b can be converted into third color light and emitted by the semiconductor nanocrystals included in the color conversion layer 430b.

[0160] The semiconductor nanocrystals can include at least one of a phosphor and a quantum dot material that converts the incident first color light into second color light or third color light.

[0161] The quantum dot can include a II-VI compound, a III-V compound, a IV-VI compound, a IV element or compound, a I-III-VI compound, a II-III-VI compound, a I-II-IV-VI compound, or one or more combinations thereof.

[0162] The II-VI compound can be selected from a group including a binary compound, a ternary compound, and a quaternary compound, the binary compound being selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and mixtures thereof; the ternary compound being selected from the group consisting of CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS, and mixtures thereof; the quaternary compound being selected from the group consisting of CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe, and mixtures thereof. The II-VI compound can further include a Group III metal.

[0163] The III-V compound can be selected from the group comprising binary compounds, ternary compounds, and quaternary compounds, the binary compounds being selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof; the ternary compounds being selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InNAs, InNSb, InPAs, InPSb, and mixtures thereof; the quaternary compounds being selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and mixtures thereof.

[0164] The III-V compound can further comprise a Group II metal (e.g., InZnP).

[0165] The IV-VI compound can be selected from the group comprising binary compounds, ternary compounds, and quaternary compounds, the binary compounds being selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof; the ternary compounds being selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and mixtures thereof; the quaternary compounds being selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof.

[0166] The Group IV element or compound can be selected from the group comprising single element compounds and binary compounds: the single element compounds being selected from the group consisting of Si, Ge, and combinations thereof; the binary compounds being selected from the group consisting of SiC, SiGe, and combinations thereof.

[0167] The I-III-VI compound can be selected from AgInS, CuInS, CuInSe2, CuInS2, CuInGaSe, and CuInGaS.

[0168] The group II-III-VI compound can be selected from the group consisting of ZnGaS, ZnAlS, ZnInS, ZnGaSe, ZnAlSe, ZnInSe, ZnGaTe, ZnAlTe, ZnInTe, ZnGaO, ZnAlO, ZnInO, HgGaS, HgAlS, HgInS, HgGaSe, HgAlSe, HgInSe, HgGaTe, HgAlTe, HgInTe, MgGaS, MgAlS, MgInS, MgGaSe, MgAlSe, MgInSe, and combinations thereof.

[0169] The group I-II-IV-VI compound can be selected from CuZnSnSe and CuZnSnS.

[0170] The quantum dots can not include cadmium. The quantum dots can include semiconductor nanocrystals based on a group III-V compound including indium and phosphorus. The group III-V compound can further include zinc. The quantum dots can include semiconductor nanocrystals based on a group II-VI compound including a chalcogen element (e.g., sulfur, selenium, tellurium, or one or more combinations thereof) and zinc.

[0171] In the quantum dots, the binary compound, the ternary compound, or the quaternary compound as described above can be present in a uniform concentration in the particles, or in the same particle whose concentration distribution can be partially divided into different states. Further, they can have a core / shell structure in which one quantum dot surrounds another quantum dot. The interface between the core and the shell can have a concentration gradient in which the concentration of the element present in the shell decreases toward the center.

[0172] In some embodiments, the quantum dots can have a core-shell structure including a core and a shell, the core including the nanocrystals described above, the shell surrounding the core. The shell of the quantum dot can act as a protective layer for maintaining the semiconductor property by preventing or substantially preventing chemical modification of the core and / or a charged layer for imparting electrophoretic properties to the quantum dot. The shell can be a single-layer shell or a multi-layer shell. The interface between the core and the shell can have a concentration gradient in which the concentration of the element present in the shell decreases toward the center (e.g., the core). Examples of the shell of the quantum dot include a metal or non-metal oxide, a semiconductor compound, or a combination thereof.

[0173] For example, the metal or non-metal oxide can be exemplified as a binary compound such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, or NiO, or a ternary compound such as MgAl2O4, CoFe2O4, NiFe2O4, or CoMn2O4.

[0174] Further, the semiconductor compound can be exemplified as CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, or AlSb.

[0175] The quantum dot can have a full width at half maximum (FWHM) of about 45 nm or less, preferably about 40 nm or less, more preferably about 30 nm or less, and can improve color purity or color reproducibility in the range. Further, since light emitted by the quantum dot is emitted in all directions, a wide viewing angle can be improved.

[0176] In the quantum dot, the shell material and the core material can have different energy bandgaps from each other. For example, the energy bandgap of the shell material can be greater or less than that of the core material. The quantum dot can have a multi-shell. In the multi-shell, the energy bandgap of the outer layer can be greater than that of the inner layer (i.e., the layer closer to the core). In the multi-shell, the energy bandgap of the outer layer can be less than that of the inner layer.

[0177] The shape of the quantum dot is not particularly limited. For example, the shape of the quantum dot can be any suitable shape such as exemplified in a spherical shape, a polyhedral shape, a pyramid shape, a polygonal (or multipod) shape, a square shape, a cuboid shape, a nanotube, a nanorod, a nanowire, a nanoplate, or a combination thereof.

[0178] The quantum dot can include an organic ligand (e.g., having a hydrophobic portion). The organic ligand portion can be bound to the surface of the quantum dot. The organic ligand can include RCOOH, RNH2, R2NH, R3N, RSH, R3PO, R3P, ROH, RCOOR, RPO(OH)2, RHPOOH, R2POOH, or one or more combinations thereof. Here, R is independently a C3 to C40 substituted aliphatic hydrocarbon group or an unsubstituted aliphatic hydrocarbon group (such as a C3 to C40 (e.g., C5 or greater and C24 or less) substituted or unsubstituted alkyl group, or a substituted or unsubstituted alkenyl group), a C6 to C40 (e.g., C6 or greater and C20 or less) substituted aromatic hydrocarbon group or an unsubstituted aromatic hydrocarbon group (such as a substituted or unsubstituted C6 to C40 aryl group), or a combination thereof.

[0179] Examples of the organic ligand can be: a thiol compound (such as methyl mercaptan, ethyl mercaptan, propyl mercaptan, butyl mercaptan, pentyl mercaptan, hexyl mercaptan, octyl mercaptan, dodecyl mercaptan, hexadecyl mercaptan, octadecyl mercaptan, or benzyl mercaptan); an amine (such as methylamine, ethylamine, propylamine, butylamine, pentylamine, hexylamine, octylamine, nonylamine, decylamine, dodecylamine, hexadecylamine, octadecylamine, dimethylamine, diethylamine, dipropylamine, tributylamine, or trioctylamine); a carboxylic acid compound (such as formic acid, acetic acid, propionic acid, butyric acid, valeric acid, hexanoic acid, heptanoic acid, octanoic acid, dodecanoic acid, hexadecanoic acid, octadecanoic acid, oleic acid, or benzoic acid); a phosphine compound (such as methyl phosphine, ethyl phosphine, propyl phosphine, butyl phosphine, pentyl phosphine, octyl phosphine, dioctyl phosphine, tributyl phosphine, or trioctyl phosphine); a phosphine compound or an oxide compound thereof (such as methyl phosphine oxide, ethyl phosphine oxide, propyl phosphine oxide, butyl phosphine oxide, pentyl phosphine oxide, tributyl phosphine oxide, octyl phosphine oxide, dioctyl phosphine oxide, or trioctyl phosphine oxide; a diphenyl phosphine, triphenyl phosphine compound, or an oxide compound thereof; a C5 to C20 alkyl phosphinic acid (such as hexyl phosphinic acid, octyl phosphinic acid, dodecyl phosphinic acid, tetradecyl phosphinic acid, hexadecyl phosphinic acid, or octadecyl phosphinic acid), etc., but are not limited thereto. The quantum dot can include a single hydrophobic organic ligand or a mixture of at least two types. The hydrophobic organic ligand can not include a photopolymerizable moiety (e.g., an acrylate group, a methacrylate group, etc.).

[0180] The quantum dot can control the color of light emitted according to the size thereof, and thus the quantum dot can have various light emission colors such as blue, red, and green.

[0181] The insulating layer 440 can be disposed on the color conversion layers 430a and 430b and the transmission layer 430c. The color filters 450a, 450b, and 450c and the light blocking member 460 can be disposed on the insulating layer 440. The color filter 450a can represent the second color light, the color filter 450b can represent the third color light, and the color filter 450c can represent the first color light.

[0182] The light blocking member 460 can be disposed between the adjacent color filters 450a, 450b, and 450c.

[0183] The substrate 210 can be disposed on the color filters 450a, 450b, and 450c and the light blocking member 460. Thus, the color conversion layers 430a and 430b and the color filters 450a, 450b, 450c can be disposed between the substrate 110 and the substrate 210.

[0184] The display apparatus can not include the color conversion layers 430a and 430b and the transmission layer 430c, and the emission layer EL can include the quantum dot.

[0185] While the present disclosure has been particularly shown and described with reference to some example embodiments thereof, it will be understood that the present disclosure is not limited to the disclosed embodiments. Rather, the present disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the present disclosure, as expressed in the appended claims and their equivalents.

Claims

1. A display device comprising: a substrate; a data line over the substrate; a first insulating layer over the data line; a first transistor over the first insulating layer and including a semiconductor layer and a gate electrode provided over the semiconductor layer; a second transistor over the first insulating layer and including a drain electrode connected to the gate electrode of the first transistor; a second insulating layer over the first transistor; a pixel electrode over the second insulating layer, the pixel electrode electrically connected to the first transistor; an auxiliary data pattern over the second insulating layer, the auxiliary data pattern electrically connected to the data line; and a pixel defining layer covering the pixel electrode and the auxiliary data pattern and having an opening superposed with the pixel electrode.

2. The display device according to claim 1, further comprising: a first connection member over the first insulating layer, the first connection member connected to a source electrode of the first transistor; and a third insulating layer between the first connection member and the second insulating layer, wherein the pixel electrode is connected to the first transistor through the first connection member.

3. The display device according to claim 2, further comprising: a light-blocking layer between the substrate and the first insulating layer, the light-blocking layer superposed with a channel region of the first transistor, wherein the first connection member is connected to the light-blocking layer.

4. The display device according to claim 2, further comprising: a second connection member between the first insulating layer and the third insulating layer, the second connection member connected to a source electrode of the second transistor and the data line, wherein the auxiliary data pattern is connected to the data line through the second connection member.

5. The display device according to claim 4, wherein the auxiliary data pattern is connected to the second connection member through a contact hole formed in the second insulating layer and the third insulating layer.

6. The display device according to claim 1, further comprising: a light-blocking layer between the substrate and the first insulating layer, the light-blocking layer superposed with a channel region of the first transistor; and a first bridge over the second insulating layer, the first bridge connected to the pixel electrode, a drain electrode of the first transistor, and the light-blocking layer.

7. The display device according to claim 6, further comprising: a second bridge over the second insulating layer, the second bridge connected to a source electrode of the second transistor and the data line.

8. The display device according to claim 7, further comprising: a third bridge over the second insulating layer, the third bridge connected to a gate electrode of the first transistor and a drain electrode of the second transistor.

9. The display device according to claim 1, wherein ​ ​ The pixel electrode and the auxiliary data pattern include a plurality of layers, and at least one layer from among the plurality of layers includes copper. 10.The display device according to claim 9, wherein The plurality of layers include a first layer, a second layer, a third layer, a fourth layer, and a fifth layer sequentially disposed on the second insulating layer, and The first layer includes titanium or a copper alloy, the second layer includes copper, the third layer includes titanium, the fourth layer includes silver, and the fifth layer includes a transparent conductive oxide.

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