Method for manufacturing a contact hole and a dram
By forming a honeycomb-shaped bottom hard mask layer through two photolithography patterning and sidewall transfer techniques, the problem of contact hole size limitation in photolithography process was solved, the capacitor electrode spacing was optimized, and the performance of photolithography process was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2020-07-30
- Publication Date
- 2026-06-05
AI Technical Summary
The critical dimensions of existing photolithography processes limit the relevant dimensions of contact holes, resulting in contact resistance and leakage current that do not meet the requirements of memory products.
A honeycomb-shaped bottom hard mask layer pattern is formed by using two photolithography patterning processes and sidewall transfer technology, reducing the number of photolithography processes, and half-pitch contact holes are formed by sidewall transfer technology.
The size of the contact holes was optimized to ensure that the spacing between capacitor electrodes met the requirements, which improved the focus depth and process margin of the photolithography process and reduced bridging defects.
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Figure CN114093833B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and in particular to a contact hole and a manufacturing method of DRAM. BACKGROUND
[0002] Memory is a device or component used to store a large amount of information in a digital system, and is an important part of a computer and a digital device. Memory can be divided into two categories: random access memory (RAM) and read-only memory (ROM). RAM includes DRAM, PRAM, MRAM, etc., and a capacitor is one of the key components for manufacturing these RAMs. The capacitor contact is used to electrically connect the capacitor with other conductors.
[0003] In the manufacturing of a semiconductor, a contact is widely used to connect a conductor with a conductor, and a contact hole is used to form the contact or a capacitor electrode. As the integration level of a memory product increases, the size of the memory product also decreases, but the size required by the existing memory product has been reduced to the limit (critical dimension) of the photolithography process. Therefore, the diameter of the contact required by the memory product, as well as the spacing specification between the contacts, i.e., the spacing specification between the contact holes, is also restricted, which can cause the specifications of the contact resistance between the wirings and the leakage between the wirings to not meet the requirements of the memory product, thereby resulting in a poor memory. SUMMARY
[0004] In view of the above analysis, the embodiments of the present application aim to provide a contact hole and a manufacturing method of DRAM to solve the problem that the critical dimension of the existing photolithography process causes the related size of the contact hole to be limited.
[0005] In one aspect, the embodiments of the present application provide a manufacturing method of a contact hole, comprising: providing a semiconductor substrate; forming a device layer on the semiconductor substrate; sequentially forming, from bottom to top, a bottom hard mask layer, a second mask layer, and a first mask layer on the device layer; forming the second mask layer into a combined pattern composed of a first pattern and a second pattern; transferring the second mask layer pattern into a side wall pattern and removing the second mask layer pattern; transferring the side wall pattern to the bottom hard mask layer to form a bottom hard mask layer pattern; and etching the device layer to form a contact hole pattern with the bottom hard mask layer pattern as a mask.
[0006] The beneficial effects of the above technical solution are as follows: the manufacturing method of the contact hole provided by the embodiments forms a bottom hard mask layer pattern through twice photolithography patterning process and subsequent side wall transfer technology, and reduces three times of photolithography process to twice photolithography process. In addition, the hard mask can be used to form a half-pitch contact hole, which can be used to form an electrode that can ensure the required spacing between the capacitor electrodes.
[0007] A further improvement to the above method, forming the second mask layer into a combined pattern of the first pattern and the second pattern, further includes: performing a first patterning process on the first mask layer using a third mask to form a first mask layer pattern, wherein the third mask has the first pattern; depositing a fourth mask layer over the first mask layer pattern; performing a second patterning process on the fourth mask layer using a fifth mask to form a fourth mask layer pattern, wherein the fourth mask has the second pattern; and performing the first patterning process and the second patterning process on the second mask layer using the first mask layer pattern and the fourth mask layer pattern to form the second mask layer into a second mask layer pattern having the combined pattern.
[0008] A further improvement to the above method involves transferring the second mask layer pattern into a sidewall pattern and removing the second mask layer pattern, which further includes: depositing a sidewall material layer on the second mask layer pattern; and anisotropically etching the sidewall material layer to remove the second mask layer pattern, wherein the sidewall is a honeycomb sidewall of the first pattern, the second pattern, and the third pattern.
[0009] A further improvement to the above method is made to transfer the sidewall pattern onto the bottom hard mask layer to form the bottom hard mask layer pattern, which further includes: etching the bottom hard mask layer with the sidewall as a mask to form the honeycomb bottom hard mask layer pattern, wherein the first pattern, the second pattern and the third pattern do not overlap with each other.
[0010] Based on a further improvement of the above method, the first mask layer and the second mask layer both include a carbon mask layer and a silicon oxynitride mask layer above the carbon mask layer; and the third mask and the fifth mask both include a carbon mask and a silicon oxynitride mask above the carbon mask.
[0011] Based on a further improvement of the above method, after performing the first patterning process on the first mask layer, and then performing the first patterning process and the second patterning process on the second mask layer, the carbon mask layer is removed by oxygen, nitrogen, and hydrogen plasma etching.
[0012] Based on a further improvement of the above method, the material of the carbon mask layer is an organic material, wherein the organic material includes an amorphous carbon ALC layer or a spin-coated organic hard mask SOH.
[0013] Based on further improvements to the above method, the material of the sidewall material layer is silicon, silicon oxide, silicon nitride, carbon, titanium nitride, or tungsten nitride.
[0014] Based on a further improvement of the above method, the first pattern, the second pattern, and the third pattern are all multiple cylindrical patterns located at the corners and center of a regular hexagon, and the first pattern, the second pattern, and the third pattern are arranged alternately to form a honeycomb pattern.
[0015] On the other hand, embodiments of the present invention provide a method for manufacturing DRAM, including the steps described above.
[0016] Based on a further improvement of the above method, the device layer includes multiple stacks, wherein each stack includes a molding oxide layer and a support layer above the molding oxide layer.
[0017] Based on a further improvement of the above method, the DRAM manufacturing method further includes: etching the device layer 210 using the honeycomb bottom hard mask layer pattern as a mask to form a plurality of honeycomb contact holes; forming an electrode material layer in the contact holes; removing the electrode material layer outside the contact holes by a dry etching process to form a plurality of honeycomb bottom electrodes; removing the remaining material of the device layer while retaining the bottom electrodes, wherein the contact holes are capacitor holes.
[0018] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:
[0019] 1. A honeycomb-shaped bottom hard mask layer pattern is formed by two photolithography patterning processes and subsequent sidewall transfer technology, reducing the three-stage photolithography process to two-stage photolithography processes;
[0020] 2. A honeycomb bottom hard mask layer pattern is used to form half-pitch contact holes, which can form electrodes that ensure the required spacing between the electrodes of the unit capacitor.
[0021] 3. The size of the spacer transfer technology is related to the thickness of the deposited film, making it independent of photolithography conditions. This significantly increases the process window, thereby improving the focus depth and process margin of the photolithography process; and
[0022] 4. The final electrode can improve the bridging defects between the electrodes of the unit capacitor.
[0023] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description
[0024] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0025] Figure 1 A flowchart illustrating a method for manufacturing a contact hole according to an embodiment of the present invention;
[0026] Figure 2 This is a top view and a corresponding cross-sectional schematic diagram of an intermediate stage of a method for manufacturing a contact hole according to an embodiment of the present invention;
[0027] Figure 3 This is a top view and a corresponding cross-sectional schematic diagram of an intermediate stage of a method for manufacturing a contact hole according to an embodiment of the present invention;
[0028] Figure 4 This is a top view and a corresponding cross-sectional schematic diagram of an intermediate stage of a method for manufacturing a contact hole according to an embodiment of the present invention;
[0029] Figure 5 A top view and a corresponding cross-sectional schematic diagram of an intermediate stage in a method for manufacturing a contact hole according to an embodiment of the present invention; and
[0030] Figure 6 This is a top view and a corresponding cross-sectional schematic diagram of an intermediate stage of a method for manufacturing a contact hole according to an embodiment of the present invention.
[0031] Figure label:
[0032] 210 - Device layer; 212 - Bottom hard mask layer; 214 - Second mask layer; 216 - First mask layer; 218 - Third mask; 224 - Fourth mask layer; 226 - Fifth mask; 228 - Sidewall material layer; 230 - Sidewall; 232 - Sidewall; 234, 236 - Bottom hard mask layer patterns Detailed Implementation
[0033] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the disclosure. Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These drawings are not to scale, and some details are enlarged for clarity and may be omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art can further design regions / layers with different shapes, sizes, and relative positions as needed.
[0034] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0035] A specific embodiment of the present invention discloses a method for manufacturing a contact hole. Reference will be made below. Figures 1 to 6 The manufacturing method of the contact hole is described in detail.
[0036] refer to Figure 1 and Figure 2 The method for manufacturing contact holes includes step S102, providing a semiconductor substrate, which is only used in... Figure 2 As shown in the diagram, to simplify the view, in Figures 3 to 6 The semiconductor substrate is not shown.
[0037] refer to Figure 1 and Figure 2 After providing the semiconductor substrate, the process proceeds to step S104, where a device layer (also known as the etchable layer) 210 is formed on the semiconductor substrate. The device layer may include multiple stacks, wherein each stack may include a molding oxide layer and a support layer above the molding oxide layer. The support layer is used to support electrodes, and the material of the support layer is SiN.
[0038] refer to Figure 1 and Figure 2 After forming the device layer, the process proceeds to step S106, where a bottom hard mask layer 212, a second mask layer 214, and a first mask layer 216 are sequentially formed on the device layer from bottom to top. The bottom hard mask layer 212 can be made of silicon. Both the first mask layer 216 and the second mask layer 214 can include a carbon mask layer and a silicon oxynitride mask layer above the carbon mask layer, with the thickness of the carbon mask layer being greater than the thickness of the silicon oxynitride mask layer. In one embodiment, the carbon mask layer is made of an organic material, wherein the organic material includes an amorphous carbon layer (ALC) or a spin-on organic hard mask (SOH).
[0039] refer to Figure 1 and Figure 2 After forming a bottom hard mask layer 212, a second mask layer 214, and a first mask layer 216 sequentially from bottom to top on the device layer, step S108 is performed to form the second mask layer 214 into a combined pattern of the first pattern and the second pattern. (Referring to the following...) Figure 2 and Figure 3The formation of the second mask layer 214 into a combined pattern consisting of the first pattern and the second pattern will be described in detail.
[0040] First, refer to Figure 2 A first patterning process is performed on the first mask layer 216 using a third mask 218 to form a first mask layer pattern, wherein the third mask has a first pattern P1. After forming the first mask layer pattern, the third mask with the first pattern P1 is removed. The first pattern P1 is a plurality of cylindrical patterns located at the corners and center of a regular hexagon. Specifically, the third mask 218 includes a carbon mask and a silicon oxynitride mask above the carbon mask. Specifically, the carbon mask in the third mask 218 is removed by oxygen, nitrogen, and hydrogen plasma etching. Specifically, compared with oxides, oxygen, nitrogen, and hydrogen plasma is used to selectively etch the carbon mask in the third mask 218. Next, refer to Figure 3 After forming the first mask layer pattern, a fourth mask layer 224 is deposited on top of the first mask layer pattern. Next, refer to... Figure 3 A second patterning process is performed on the fourth mask layer 224 using the fifth mask 226 to form a pattern for the fourth mask layer, wherein the fourth mask has a second pattern P2. Specifically, the fifth mask 226 includes a carbon mask and a silicon oxynitride mask above the carbon mask. Next, refer again... Figure 3 The second mask layer 214 is subjected to a first patterning process and a second patterning process using the first mask layer pattern and the fourth mask layer pattern, so as to form the second mask layer 214 with a combined pattern (see reference). Figure 4 The second mask layer pattern (top view) is a combination of the first pattern P1 and the second pattern P2. The second pattern P2 is also a combination of multiple cylindrical patterns located at the corners and center of a regular hexagon; the second pattern P2 has the same size as the regular hexagon of the first pattern P1. Specifically, the cylinders of the second pattern P2 are located at the center of the equilateral triangle formed by three adjacent cylinders of the first pattern P1. Finally, the first mask layer pattern and the fourth mask layer pattern containing the second pattern P2 are removed. The carbon mask in the fourth mask is removed by oxygen, nitrogen, and hydrogen plasma etching. Specifically, compared with oxides, oxygen, nitrogen, and hydrogen plasma is used to selectively etch the carbon mask layer in the second mask.
[0041] refer to Figure 1 , Figure 4 and Figure 5After forming the second mask layer 214 with a combined pattern, step S110 is performed to transfer the second mask layer pattern to a sidewall pattern and remove the second mask layer pattern. Specifically, transferring the second mask layer pattern to a sidewall pattern and removing the second mask layer pattern is a pattern transfer process. Specifically, transferring the second mask layer pattern to a sidewall pattern and removing the second mask layer pattern may further include depositing a sidewall material layer 228 on the second mask layer pattern. Specifically, the sidewall material layer 228 is deposited using a chemical vapor deposition process or an atomic layer deposition process. Specifically, the material of the sidewall material layer 228 is silicon, silicon oxide, silicon nitride, carbon, titanium nitride, or tungsten nitride. Here, the deposition amount of the sidewall material layer 228 needs to be greater than half the spacing between the two cylindrical patterns after photolithography to ensure that the two cylinders can expand and intersect after deposition. The deposition amount is greater than d / 2, where d is the spacing between the two cylindrical patterns. For example, when the spacing between the two cylindrical patterns is 60 nm, the deposition amount of the sidewall material layer 228 is greater than 30 nm.
[0042] Next, refer to Figure 5 The transfer process may further include anisotropic etching of the sidewall material layer 228 and removal of the second mask layer pattern, wherein the sidewalls are honeycomb sidewalls of the first pattern, the second pattern, and the third pattern. Specifically, the sidewall material layer 228 is anisotropically etched to form sidewalls 230 and 232, wherein sidewalls 230 and 232 are honeycomb sidewalls of the first pattern P1, the second pattern P2, and the third pattern P3 (see reference). Figure 5 (Top view). During this etching process, the second mask layer pattern and the sidewall material above it are etched away, leaving sidewall material forming sidewalls 230 and 232. In this embodiment, oxygen, nitrogen, and hydrogen plasma etching is used to remove the carbon mask layer in the second mask layer pattern. Specifically, compared to oxides, oxygen, nitrogen, and hydrogen plasma is used to selectively etch the carbon mask layer in the first mask layer pattern. Furthermore, because the deposition amount of the sidewall material layer 228 is controlled in the previous deposition process, the two intersecting cylindrical sidewalls after deposition are not removed, thus allowing the etching process to form sidewalls with the first pattern P1, the second pattern P2, and the third pattern P3. The third pattern P3 also consists of multiple cylindrical patterns located at the corners and center of a regular hexagon, with the same hexagonal dimensions as the first pattern P1 and the second pattern P2. Specifically, the cylinders of the third pattern P3 are located at the center of the hexagon formed by the multiple cylindrical patterns of the first pattern P1 and the second pattern P2.
[0043] By improving the third lithography process to sidewall transfer technology, the size of which is related to the thickness of the deposited film and is not limited by lithography conditions, the process window can be significantly increased, that is, the DOF (depth of focus) and process margin of the lithography process can be improved.
[0044] refer to Figure 1 , Figure 5 and Figure 6 After forming sidewalls 230 and 232, step S112 is performed to transfer the sidewall patterns onto the bottom hard mask layer 212 to form a bottom hard mask layer pattern. Transferring the sidewall patterns onto the bottom hard mask layer to form the bottom hard mask layer pattern further includes etching the bottom hard mask layer using the sidewalls as masks to form honeycomb-shaped bottom hard mask layer patterns 234 and 236, wherein the first pattern P1, the second pattern P2, and the third pattern P3 do not overlap, such that the spacing between any two adjacent bottom hard mask layer patterns is less than the minimum lithography size. In this embodiment, the bottom hard mask layer 212 is etched using the sidewalls having the first pattern P1, the second pattern P2, and the third pattern P3 (reverse self-aligned dual patterning), that is, the first pattern P1, the second pattern P2, and the third pattern P3 of the sidewalls are transferred to the bottom hard mask layer 212 to form a honeycomb-shaped bottom hard mask layer pattern having the first pattern P1, the second pattern P2, and the third pattern P3. The material of the bottom hard mask layer is silicon, silicon oxide, silicon nitride, carbon, titanium nitride, or tungsten nitride. Here, the first pattern P1, the second pattern P2, and the third pattern P3 are multiple cylindrical patterns located at the corners and center of a regular hexagon. The first pattern P1, the second pattern P2, and the third pattern P3 are arranged alternately to form a honeycomb pattern.
[0045] refer to Figure 1 and Figure 6 After forming the bottom hard mask layer pattern, step S114 is performed, using the bottom hard mask layer pattern as a mask to etch the device layer to form a contact hole pattern. Specifically, the device layer 210 is etched using the honeycomb-shaped bottom hard mask layer pattern as a mask to form multiple honeycomb-shaped contact holes, wherein the contact holes can be capacitor holes. The device layer includes multiple stacks, wherein each stack can include a mold oxide layer and a support layer above the mold oxide layer. The contact hole can be a capacitor hole.
[0046] Another specific embodiment of the present invention discloses a method for manufacturing DRAM. DRAM is formed from multiple memory cells, each memory cell including a capacitor and a transistor. Therefore, the method for manufacturing DRAM includes the various steps of the contact hole manufacturing method described above. However, to avoid redundancy, a detailed description of its formation steps is omitted here.
[0047] An electrode material layer is formed in a contact hole; the electrode material layer outside the contact hole is removed by a dry etching process to form multiple honeycomb-shaped lower electrodes; the remaining material of the device layer is removed while retaining the lower electrodes, wherein the spacing between any two adjacent lower electrodes in the multiple honeycomb-shaped lower electrodes is less than the minimum photolithography size. Specifically, the device layer includes multiple stacks, wherein each stack may include a molding oxide layer and a support layer above the molding oxide layer.
[0048] A dielectric layer and an upper electrode can then be formed. The upper electrode, dielectric layer, and lower electrode manufactured here constitute a capacitor. The method for forming the upper electrode can be the same as the method for forming the lower electrode. Furthermore, the method for manufacturing the contact holes here can be used to form contacts.
[0049] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:
[0050] 1. A honeycomb hard mask is formed by two photolithography patterning processes and subsequent sidewall transfer technology, reducing the three-stage photolithography process to two-stage photolithography processes;
[0051] 2. By using honeycomb hardening to form half-pitch contact holes, electrodes that ensure the required spacing between the electrodes of the unit capacitor can be formed;
[0052] 3. The size of the spacer transfer technology is related to the thickness of the deposited film, making it independent of photolithography conditions. This significantly increases the process window, thereby improving the focus depth and process margin of the photolithography process; and
[0053] 4. The final electrode can improve the bridging defects between the electrodes of the unit capacitor.
[0054] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0055] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A method for manufacturing a contact hole, characterized in that, include: Provide semiconductor substrates; A device layer is formed on the semiconductor substrate; A bottom hard mask layer, a second mask layer, and a first mask layer are formed sequentially from bottom to top on the device layer; The second mask layer is formed into a combined pattern of the first and second patterns through two photolithography patterning processes, which serves as the pattern of the second mask layer. The process of transferring the second mask layer pattern into a sidewall pattern and removing the second mask layer pattern further includes: depositing a sidewall material layer on the second mask layer pattern; and performing anisotropic etching on the sidewall material layer and removing the second mask layer pattern to form a sidewall having a first pattern, a second pattern, and a third pattern, wherein the deposition amount of the sidewall material layer is controlled to be greater than half the spacing between the two cylindrical patterns after the two photolithographic patterning processes in the previous deposition process, and the two intersecting cylindrical sidewalls are not removed. The sidewall pattern is transferred onto the bottom hard mask layer to form the bottom hard mask layer pattern; and The device layer is etched using the bottom hard mask layer pattern as a mask to form a contact hole pattern. The first pattern, the second pattern, and the third pattern are all multiple cylindrical patterns located at the corners and center of a regular hexagon. The first pattern, the second pattern, and the third pattern are arranged alternately to form a honeycomb pattern. The size of the regular hexagon of the third pattern is the same as the size of the regular hexagon of the first pattern and the second pattern. The cylinder of the second pattern is located at the center of the equilateral triangle formed by three adjacent cylinders of the first pattern, and the cylinder of the third pattern is located at the center of the hexagon formed by multiple cylinders of the first pattern and the second pattern.
2. The method for manufacturing a contact hole according to claim 1, characterized in that, Forming the second mask layer into a combined pattern consisting of the first pattern and the second pattern further includes: A first patterning process is performed on the first mask layer using a third mask to form a first mask layer pattern, wherein the third mask has the first pattern; A fourth mask layer is deposited over the first mask layer pattern; A second patterning process is performed on the fourth mask layer using a fifth mask to form a pattern for the fourth mask layer, wherein the pattern for the fourth mask layer has the second pattern; and The first patterning process and the second patterning process are used on the second mask layer using the first mask layer pattern and the fourth mask layer pattern to form the second mask layer into a second mask layer pattern having the combined pattern.
3. The method for manufacturing a contact hole according to claim 1, characterized in that, Transferring the sidewall pattern onto the bottom hard mask layer to form the bottom hard mask layer pattern further includes: The bottom hard mask layer is etched using the sidewall as a mask to form a honeycomb bottom hard mask layer pattern, wherein the first pattern, the second pattern, and the third pattern do not overlap with each other.
4. The method for manufacturing a contact hole according to claim 2, characterized in that, Both the first mask layer and the second mask layer include a carbon mask layer and a silicon oxynitride mask layer above the carbon mask layer; and Both the third mask and the fifth mask include a carbon mask and a silicon oxynitride mask above the carbon mask.
5. The method for manufacturing a contact hole according to claim 4, characterized in that, After performing a first patterning process on the first mask layer, and then performing the first and second patterning processes on the second mask layer, the carbon mask layer is removed by oxygen, nitrogen, and hydrogen plasma etching.
6. The method for manufacturing a contact hole according to claim 5, characterized in that, The carbon mask layer is made of organic material, which includes an amorphous carbon ALC layer or a spin-coated organic hard mask SOH.
7. The method for manufacturing a contact hole according to claim 1, characterized in that, The material of the sidewall material layer is silicon, silicon oxide, silicon nitride, carbon, titanium nitride, or tungsten nitride.
8. A method for manufacturing DRAM, characterized in that, Includes the steps described in any one of claims 1 to 7.
9. The method for manufacturing DRAM according to claim 8, characterized in that, The device layer comprises multiple stacks, wherein each stack includes a molding oxide layer and a support layer above the molding oxide layer.
10. The method for manufacturing DRAM according to claim 9, characterized in that, Also includes: The device layer is etched using a honeycomb-shaped bottom hard mask layer pattern as a mask to form multiple honeycomb-shaped contact holes; An electrode material layer is formed in the contact hole; Multiple honeycomb-shaped lower electrodes are formed by removing the electrode material layer outside the contact holes through a dry etching process. The remaining material of the device layer is removed while the lower electrode is retained, wherein the contact hole is a capacitor hole.