Dual pattern etching method and method for manufacturing DRAM
By implementing sidewall oxide and silicon oxynitride etching processes in the process chamber and spin-coating carbon etching processes in the photoresist stripping chamber, the problem of high manufacturing costs in DRAM manufacturing has been solved, process time has been shortened and costs have been reduced, and the utilization rate of the process chamber has been improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2020-10-28
- Publication Date
- 2026-07-07
AI Technical Summary
In existing technologies, all etching processes in DRAM manufacturing are completed in expensive process chambers, resulting in high manufacturing costs and long process times.
A dual patterning etching method is adopted, in which sidewall oxide and silicon oxynitride etching processes are carried out in the process chamber, and carbon spin-coating etching process is carried out in the photoresist stripping chamber. The top mask layer is patterned by photolithography, and the etching selectivity is controlled by different etchant ratios. Combined with atomic layer deposition, the sidewall material layer is formed. Finally, the spin-coated carbon mask layer is removed in the photoresist stripping chamber.
It shortens the service life of the process chamber, reduces manufacturing costs, and improves the utilization rate of the process chamber. By controlling the etching selectivity and the thickness of the sidewall material to adjust the trench width, it achieves efficient DRAM manufacturing.
Smart Images
Figure CN114420548B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more particularly to a dual patterning etching method and a method for manufacturing DRAM. Background Technology
[0002] Memory is a device or component in a digital system used to store large amounts of information, and it is an important part of computers and digital devices. Memory can be divided into two main categories: Random Access Memory (RAM) and Read-Only Memory (ROM). RAM includes DRAM, PRAM, MRAM, etc., and capacitors are one of the key components in the manufacture of these RAMs. Each memory cell in a DRAM device consists of 1T1C (i.e., one transistor and one capacitor).
[0003] A typical etching tool may consist only of a process chamber, but it can also be combined with a photoresist (PR) lift-off chamber. The etching recipe for capacitive via structures within the process chamber includes at least three etching steps: atomic layer deposition (ALD) sidewall oxide etching, silicon oxynitride (SiON) etching, and spin-coated carbon (SOC) etching. Because all of these steps utilize expensive process chambers, the process suffers from high manufacturing costs and long processing times. Summary of the Invention
[0004] Based on the above analysis, the embodiments of the present invention aim to provide a dual pattern etching method and a DRAM manufacturing method to solve the problem of increased manufacturing costs caused by performing all etching processes in a process chamber.
[0005] On one hand, embodiments of the present invention provide a dual patterning etching method, comprising: providing a semiconductor substrate in a process chamber; sequentially forming a first hard mask layer, a second hard mask layer, a bottom mask layer, and a top mask layer over the semiconductor substrate, wherein the top mask layer includes a spin-coated carbon mask layer and a top silicon oxynitride mask layer above the spin-coated carbon mask layer; patterning the top mask layer by photolithography; depositing a sidewall material layer over the patterned top mask layer; etching the sidewall material layer and the top silicon oxynitride mask layer to expose the top surface of the spin-coated carbon mask layer; and transferring the semiconductor substrate from the process chamber to a photoresist stripping chamber to remove the spin-coated carbon mask layer by etching.
[0006] The beneficial effects of the above technical solution are as follows: implementing sidewall oxide etching and silicon oxynitride (SiON) etching processes in the process chamber and spin-coating carbon etching processes in the photoresist stripping chamber can reduce the usage time of the process chamber and reduce manufacturing costs.
[0007] A further improvement to the above method is to pattern the top mask layer using photolithography, which includes: patterning the photoresist mask layer into a plurality of first openings and a plurality of first protrusions using photolithography, wherein the first openings and the first protrusions are arranged alternately.
[0008] A further improvement to the above method involves depositing a sidewall material layer over the patterned top mask layer by depositing the sidewall material layer over the plurality of first openings and the plurality of first protrusions using an atomic layer deposition process to form a plurality of second openings.
[0009] Based on a further improvement of the above method, the top surface of the sidewall material layer includes: a first top surface located at the top surface of the sidewall material layer of the first protrusion and a second top surface of the sidewall material layer located in the first opening, wherein the first top surface is lower than the second top surface.
[0010] Further improvements to the above method include etching the sidewall material layer and the top silicon oxynitride mask layer to expose the top surface of the spin-coated carbon mask layer, which involves: in-situ etching the sidewall material layer on the bottom surface of the first opening and the top surface of the first protrusion using a first etching process to expose the top surface of the top silicon oxynitride mask layer and the bottom surface of the second opening; and in-situ etching the exposed top silicon oxynitride mask layer using a second etching process to remove the top silicon oxynitride mask layer.
[0011] Based on further improvements to the above method, the etchants used in the first etching process and the second etching process include CF4 and CHF3.
[0012] Based on a further improvement of the above method, in the first etching process, the gas flow rate of CF4 is greater than the gas flow rate of CHF3; and in the second etching process, the gas flow rate of CF4 is less than the gas flow rate of CHF3.
[0013] Based on a further improvement of the above method, the spin-coated carbon mask layer is removed by an etching process: in the photoresist stripping chamber, the exposed spin-coated carbon mask layer is non-in-situ etched using an etchant to form a first trench, thereby exposing the third top surface of the bottom mask layer, wherein the etchant includes any one of N2, He, H2, H2N2, Ar and CF4 and O2 plasma.
[0014] Based on a further improvement of the above method, during the etching of the top silicon oxynitride mask layer and the spin-coated carbon mask layer, the bottom mask layer in the opening is partially etched to form a second trench, causing the bottom mask layer to be partially recessed to expose the fourth top surface of the partially recessed bottom mask layer, wherein the fourth top surface is lower than the third top surface, and the sidewall material layer protrudes between the first trench and the second trench.
[0015] Based on a further improvement of the above method, the dual patterning etching method further includes: using the sidewall material layer protrusion as a mask, etching the bottom mask layer, the second hard mask layer and the first hard mask layer in the first trench and the second trench to form the capacitor hole, wherein the material of the second hard mask layer includes amorphous carbon and the material of the first hard mask layer includes oxide.
[0016] On the other hand, embodiments of the present invention provide a method for manufacturing DRAM, comprising: forming a capacitor aperture using the dual pattern etching method described above; forming a lower electrode inside the capacitor aperture; removing the sidewall material layer, bottom mask layer, second hard mask layer and first hard mask layer outside the lower electrode; and sequentially forming a capacitor dielectric layer and an upper electrode inside and outside the capacitor aperture.
[0017] Based on further improvements to the above method, the materials of the lower electrode and the upper electrode include TaN or TiN.
[0018] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:
[0019] 1. In the art, the etching processes of sidewall oxide, silicon oxynitride (SiON) and spin-coated carbon are all completed in the same process chamber. However, in this embodiment, the etching processes of sidewall oxide and silicon oxynitride (SiON) are carried out in the process chamber, while the etching process of spin-coated carbon is carried out in the PR stripping chamber. This can reduce the usage time of the process chamber and reduce manufacturing costs.
[0020] 2. Process chambers are expensive, but compared to high-priced process chambers, PR stripping chambers are inexpensive. Therefore, when batch processing a large number of semiconductor substrates simultaneously, sidewall oxide and silicon oxynitride (SiON) etching processes can be performed in the process chamber, while spin-coating carbon etching processes can be performed in the PR stripping chamber. This reduces the process chamber usage time for a single semiconductor substrate, thereby improving the utilization rate of the process chamber.
[0021] 3. The etching selectivity is improved by changing the ratio of CF4 to CHF3 to etch the sidewall oxide material and silicon oxynitride (SiON) material.
[0022] 4. The groove width is adjusted by controlling the deposition thickness of the mandrel and the sidewall oxide material on the mandrel sidewall.
[0023] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description
[0024] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0025] Figure 1 This is a schematic diagram of loading a semiconductor substrate into a process chamber according to an embodiment of the present invention.
[0026] Figure 2 This is a schematic diagram of an intermediate stage of the dual patterning etching method according to an embodiment of the present invention.
[0027] Figure 3 This is a schematic diagram of an intermediate stage of the dual patterning etching method according to an embodiment of the present invention.
[0028] Figure 4 This is a schematic diagram of an intermediate stage of the dual patterning etching method according to an embodiment of the present invention.
[0029] Figure 5 This is a schematic diagram of an intermediate stage of the dual patterning etching method according to an embodiment of the present invention.
[0030] Figure 6 This is a schematic diagram illustrating the transfer of a semiconductor substrate from a process chamber to a photoresist stripping chamber according to an embodiment of the present invention.
[0031] Figure label:
[0032] 102 - Process chamber; 202 - Semiconductor substrate; 204 - First hard mask layer; 206 - Second hard mask layer; 208 - Bottom mask layer; 210 - Spin-on carbon mask layer; 212 - Top silicon oxynitride mask layer; 214 - First protrusion; 216 - First opening; 218 - First top surface; 220 - Second top surface; 222 - Sidewall material layer; 224 - Second opening; 226 - Top surface; 228 - Second trench; 230 - Fourth top surface; 232 - First trench; 234 - Third top surface; 236 - Sidewall material layer protrusion; 238 - Third opening; 602 - Photoresist stripping chamber Detailed Implementation
[0033] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0034] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0035] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0036] One specific embodiment of the present invention discloses a dual-pattern etching method. Hereinafter, reference will be made to... Figures 1 to 6 The dual-pattern etching method is described in detail.
[0037] refer to Figure 1 and Figure 2 A semiconductor substrate 202 is provided in the process chamber 102. For a simplified view, only... Figure 2 The semiconductor substrate 202 is shown, but in Figures 2 to 5 The semiconductor substrate 202 is omitted in the text.
[0038] Refer again Figure 2 A first hard mask layer 204, a second hard mask layer 206, a bottom mask layer 208, and a top mask layer are sequentially formed above a semiconductor substrate 202. The top mask layer includes a spin-on carbon (SOC) mask layer 210 and a top silicon oxynitride mask layer 212 above the spin-on carbon mask layer 210. The first hard mask layer 204 is made of oxide, the second hard mask layer 206 is made of amorphous carbon, and the bottom mask layer 208 is made of silicon oxynitride.
[0039] Refer again Figure 2The top mask layer is patterned using a photolithography process. Specifically, this includes patterning the top mask layer into a plurality of first openings 216 and a plurality of first protrusions 214 using a photolithography process, wherein the first openings 216 and the first protrusions 214 are arranged alternately. In an embodiment, the width of the first protrusion 214 is three times the width of the first opening 216, or the width of the first opening 216 may be equal to or unequal to the width of the first protrusion 214.
[0040] refer to Figure 3 A sidewall material layer 222 is deposited over a patterned photoresist mask layer to form a plurality of second openings 224. The deposition of the sidewall material layer reduces the pattern spacing and increases the pattern density. Specifically, this includes depositing the sidewall material layer 222 over a plurality of first openings 216 and a plurality of first protrusions 214 using an atomic layer deposition process to form a plurality of second openings 224, such that the width of the first protrusion 214 is the same as or different from the width of the sidewall material layer 222 on the two opposite sidewalls of the first protrusion 214. The width of the first protrusion 214 can be the same as or different from the width of the second openings 224 remaining after the sidewall material layer 222 is deposited. The top surface of the sidewall material layer 222 includes a first top surface 218 located at the top surface of the sidewall material layer of the first protrusion 214 and a second top surface 220 located in the first opening 216, wherein the first top surface 218 is higher than the second top surface 220.
[0041] Compared with the prior art, the dual pattern etching method provided in this embodiment adjusts the trench width by controlling the thickness of the mandrel and the sidewall oxide material on the opposite sidewall of the mandrel.
[0042] refer to Figure 4 The sidewall material layer and the top silicon oxynitride mask layer are etched to expose the top surface of the spin-coated carbon mask layer. Specifically, the etchants used for etching the sidewall material layer and the top silicon oxynitride mask layer both include CF4 and CHF3. First, the sidewall material layer 222 on the bottom surface of the first opening 216 and the top surface of the first protrusion 214 is etched in situ using a first etching process to form a third opening 238, thereby exposing the top surface 226 of the top silicon oxynitride mask layer. In this first etching process, the gas flow rate of CF4 is greater than that of CHF3. Then, the exposed top silicon oxynitride mask layer 212 is etched in situ using a second etching process to remove the top silicon oxynitride mask layer 212, while leaving the remaining sidewall material layer unetched, thereby exposing the top surface of the spin-coated carbon mask layer 210. In this second etching process, the gas flow rate of CF4 is less than that of CHF3.
[0043] Compared with the prior art, the dual patterning etching method provided in this embodiment etches the sidewall oxide material and silicon oxynitride (SiON) material by changing the ratio of CF4 and CHF3.
[0044] refer to Figure 5 and Figure 6 The semiconductor substrate is transferred from the process chamber 102 to the photoresist stripping chamber 602, where the spin-coated carbon mask layer is removed by an etching process. Specifically, firstly, the load lock module (LLM) is opened, and the semiconductor substrate is transferred to the outside of the process chamber 102 via the load port (LP) through the load module. Then, the semiconductor substrate is moved into the photoresist stripping chamber 602, and the load lock module is closed. In the photoresist stripping chamber 602, the exposed spin-coated carbon mask layer 210 is non-in-situ etched using an etchant to form a first trench 232, thereby exposing the third top surface 234 of the bottom mask layer. The etchant includes any one of N2, He, H2, H2N2, Ar, and CF4, and O2 plasma. During the etching of the top silicon oxynitride mask layer 212 and the spin-coated carbon mask layer 210, the bottom mask layer 208 in the third opening is partially etched to form the second trench 228, causing the bottom mask layer 208 to be partially recessed to expose the fourth top surface 230 of the partially recessed bottom mask layer 208, wherein the fourth top surface 230 is lower than the third top surface 234, and the sidewall material layer protrusion 236 is disposed between the first trench 232 and the second trench 228.
[0045] After forming the first trench 232 and the second trench 228, using the sidewall material layer protrusion 236 as a mask, the bottom mask layer 208, the second hard mask layer 206 and the first hard mask layer 204 in the first trench 232 and the second trench 228 are etched to form capacitor holes, wherein the material of the second hard mask layer includes amorphous carbon and the material of the first hard mask layer includes oxide.
[0046] Compared with the prior art, the dual patterning etching method provided in this embodiment, which performs sidewall oxide etching and silicon oxynitride (SiON) etching in the process chamber and spin-coated carbon etching in the PR lift-off chamber, can reduce the usage time of the process chamber and reduce manufacturing costs.
[0047] One specific embodiment of the present invention discloses a method for manufacturing DRAM, comprising: forming a capacitor aperture using the dual patterning etching method described above; forming a lower electrode inside the capacitor aperture; removing the sidewall material layer, bottom mask layer, second hard mask layer, and first hard mask layer outside the lower electrode; and sequentially forming a capacitor dielectric layer and an upper electrode inside and outside the capacitor aperture. The lower electrode, together with the inner capacitor dielectric layer and the inner upper electrode, forms a first capacitor, and the lower electrode, together with the outer capacitor dielectric layer and the outer upper electrode, forms a second capacitor. The materials of the lower electrode and the upper electrode include TaN or TiN.
[0048] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:
[0049] 1. In the art, the etching processes of sidewall oxide, silicon oxynitride (SiON) and spin-coated carbon are all completed in the same process chamber. However, in this embodiment, the etching processes of sidewall oxide and silicon oxynitride (SiON) are carried out in the process chamber, while the etching process of spin-coated carbon is carried out in the PR stripping chamber. This can reduce the usage time of the process chamber and reduce manufacturing costs.
[0050] 2. Process chambers are expensive, but compared to high-priced process chambers, PR stripping chambers are inexpensive. Therefore, when batch processing a large number of semiconductor substrates simultaneously, sidewall oxide and silicon oxynitride (SiON) etching processes can be performed in the process chamber, while spin-coating carbon etching processes can be performed in the PR stripping chamber. This reduces the process chamber usage time for a single semiconductor substrate, thereby improving the utilization rate of the process chamber.
[0051] 3. The etching selectivity is improved by changing the ratio of CF4 to CHF3 to etch the sidewall oxide material and silicon oxynitride (SiON) material.
[0052] 4. The groove width is adjusted by controlling the thickness of the mandrel and the sidewall oxide material on the opposite sidewalls of the mandrel.
[0053] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0054] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A dual-pattern etching method, characterized in that, include: A semiconductor substrate is provided in the process chamber; A first hard mask layer, a second hard mask layer, a bottom mask layer, and a top mask layer are sequentially formed on the semiconductor substrate, wherein the top mask layer includes a spin-coated carbon mask layer and a top silicon oxynitride mask layer above the spin-coated carbon mask layer; The top mask layer is patterned by photolithography, wherein the patterning of the top mask layer by photolithography includes: patterning the top mask layer into a plurality of first openings and a plurality of first protrusions by photolithography, wherein the first openings and the first protrusions are arranged alternately. Depositing a sidewall material layer on the patterned top mask layer, wherein depositing the sidewall material layer on the patterned top mask layer includes: depositing the sidewall material layer on the plurality of first openings and the plurality of first protrusions by an atomic layer deposition process to form a plurality of second openings; Etching the sidewall material layer and the top silicon oxynitride mask layer to expose the top surface of the spin-coated carbon mask layer, wherein etching the sidewall material layer and the top silicon oxynitride mask layer to expose the top surface of the spin-coated carbon mask layer includes: in-situ etching of the sidewall material layer on the bottom surface of the first opening and the top surface of the first protrusion using a first etching process to expose the top surface of the top silicon oxynitride mask layer and the bottom surface of the second opening; and in-situ etching of the exposed top silicon oxynitride mask layer using a second etching process to remove the top silicon oxynitride mask layer; and The semiconductor substrate is transferred from the process chamber to the photoresist stripping chamber, and the spin-coated carbon mask layer is removed by an etching process.
2. The dual-pattern etching method according to claim 1, characterized in that, The top surface of the sidewall material layer includes: a first top surface located at the top surface of the sidewall material layer of the first protrusion and a second top surface of the sidewall material layer located in the first opening, wherein the first top surface is higher than the second top surface.
3. The dual-pattern etching method according to claim 1, characterized in that, The etchants used in the first etching process and the second etching process include CF4 and CHF3.
4. The dual-pattern etching method according to claim 3, characterized in that, In the first etching process, the gas flow rate of CF4 is greater than that of CHF3; as well as In the second etching process, the gas flow rate of CF4 is less than that of CHF3.
5. The dual-pattern etching method according to claim 1, characterized in that, The spin-coated carbon mask layer is removed by an etching process: In the photoresist stripping chamber, the exposed spin-coated carbon mask layer is non-in-situ etched using an etchant to form a first trench, thereby exposing the third top surface of the bottom mask layer, wherein the etchant includes any one of N2, He, H2, H2N2, Ar and CF4 and O2 plasma.
6. The dual-pattern etching method according to claim 5, characterized in that, During the etching of the top silicon oxynitride mask layer and the spin-coated carbon mask layer, the bottom mask layer in the second opening is partially etched to form a second trench, causing the bottom mask layer to be partially recessed to expose the fourth top surface of the partially recessed bottom mask layer, wherein the fourth top surface is lower than the third top surface, and the sidewall material layer protrudes between the first trench and the second trench.
7. The dual-pattern etching method according to claim 6, characterized in that, Further includes: Using the protrusion of the sidewall material layer as a mask, the bottom mask layer, the second hard mask layer, and the first hard mask layer in the first trench and the second trench are etched to form capacitor holes, wherein the material of the second hard mask layer includes amorphous carbon, and the material of the first hard mask layer includes oxide.
8. A method for manufacturing DRAM, characterized in that, include: The capacitor via is formed using the dual patterning etching method according to any one of claims 1 to 7; A lower electrode is formed inside the capacitor hole; Remove the sidewall material layer, bottom mask layer, second hard mask layer, and first hard mask layer outside the lower electrode; as well as A capacitor dielectric layer and an upper electrode are sequentially formed inside and outside the capacitor hole.
9. The method for manufacturing DRAM according to claim 8, characterized in that, The materials of the lower electrode and the upper electrode include TaN or TiN.