Lithographic processes and semiconductor structures

Abstract

This invention provides a photolithography process and a semiconductor structure. In the photolithography process, during the soft baking of the photoresist layer, the baking temperature is increased to enhance the performance of the liquid barrier layer and reduce the defect formation rate. Furthermore, during exposure, the exposure speed of defect-prone areas is reduced, which also helps to reduce the defect formation rate and improve exposure quality. Further, during the rinsing process after development, the defect removal effect is enhanced by lengthening the rinsing time for the central region and slowing down the rinsing scanning speed from the central region towards the edge regions. Based on this, the photolithography process provided by this invention alleviates defect problems at their root cause, not only reducing the probability of downtime due to defects and shortening defect verification time, thus improving process efficiency, but also avoiding the expansion of the impact range due to detection rate issues, and significantly improving product yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a photolithography process and semiconductor structure. Background Technology

[0002] With the continuous development of integrated circuits, the critical dimensions of chips are becoming smaller and smaller. To meet the photolithography requirements for smaller critical dimensions, immersion lithography technology has emerged. Immersion lithography is based on traditional photolithography technology, replacing air with liquid between the lens and the photoresist, thereby improving resolution by utilizing the shortened wavelength of light passing through the liquid medium.

[0003] However, because the medium between the lens and the photoresist changes from air to a liquid medium, such as water, water stains are easily formed on the wafer surface during photolithography. Furthermore, water droplets can cause the top of the photoresist to expand, affecting its uniformity and consequently the photolithography effect. Additionally, air bubbles can easily form at the wafer edges due to unevenness, also causing photolithography defects and severely impacting product yield. Current technology addresses this by first using a Process Defect Monitor (PDM) system to detect photolithography defects or routing trail defects. Then, the equipment is stopped, and engineers inspect the immersion mask. Based on the inspection results, a decision is made whether to clean the immersion mask. If cleaning is necessary, it can be done manually or using the machine's built-in immersion mask cleaning program. Next, after performing the photolithography process on a test wafer, PDM is used again for defect detection. If the product defect requirements are not met, the above process must be repeated until they are met. Clearly, this entire defect handling process is not only time-consuming to restart, but also, due to the limited detection frequency, cannot effectively detect anomalies in a timely manner, leading to a wider impact range. Furthermore, existing defect handling methods can only passively detect defects and cannot fundamentally optimize defect problems during the process.

[0004] Therefore, a new process method is needed to solve the above-mentioned technical problems. Summary of the Invention

[0005] The purpose of this invention is to provide a photolithography process and semiconductor structure to solve at least one of the problems of how to improve the photolithography effect of immersion lithography machines and how to alleviate the photolithography defects of immersion lithography machines.

[0006] To solve the above-mentioned technical problems, the present invention provides a photolithography process, comprising:

[0007] A wafer is provided, the surface of which is coated with a photoresist layer;

[0008] The photoresist layer is soft-baked at a preset temperature to form a liquid barrier layer on top of the photoresist layer;

[0009] The photoresist layer is exposed using an immersion lithography machine; wherein the exposure rate of defect-prone areas in the photoresist layer is lower than the exposure rate of the remaining areas in the photoresist layer.

[0010] The photoresist layer is rinsed with a developer to form a patterned photoresist layer;

[0011] The patterned photoresist layer is rinsed with a cleaning solution.

[0012] Optionally, in the photolithography process, the preset temperature is higher than the standard softening temperature, and satisfies the following relationship:

[0013] T0 < T1 ≤ T0 + 10℃;

[0014] Wherein, T0 is the standard temperature for soft baking; T1 is the preset temperature.

[0015] Optionally, in the photolithography process, the standard baking temperature is 90°C, and the preset temperature is 95°C.

[0016] Optionally, in the photolithography process, before exposing the photoresist layer using an immersion lithography machine, the photolithography process includes:

[0017] Based on the defect list source file, machine record data, and exposure path file stored on the machine, the maximum exposure speed is obtained, and the coordinate range of the defect risk area is determined.

[0018] Optionally, in the photolithography process, after obtaining the maximum exposure speed and determining the coordinate range of the defect risk region, the photolithography process includes:

[0019] Step 1: Provide a test wafer; the surface of the test wafer is coated with the photoresist layer; and the photoresist layer is softened at the preset temperature;

[0020] Step 2: Reduce the maximum exposure speed by a preset unit increment to determine the exposure speed for the defect risk area;

[0021] Step 3: Expose the defect risk area in the test wafer using the exposure speed of the defect risk area;

[0022] Step 4: Perform defect detection on the defect risk area and obtain the detection results; if the detection results meet the defect requirements, output the current exposure speed of the defect risk area; if the detection results do not meet the defect requirements, repeat steps 1 to 4 until the detection results meet the defect requirements.

[0023] Optionally, in the photolithography process, during the exposure of the photoresist layer using an immersion lithography machine, the defect risk area is exposed using the current exposure speed of the defect risk area; and the remaining areas are exposed using the maximum exposure speed.

[0024] Optionally, in the photolithography process, during the washing of the patterned photoresist layer with a cleaning solution:

[0025] The central region of the patterned photoresist layer is rinsed for a preset time;

[0026] The patterned photoresist layer is scanned and rinsed from the center region toward the edge region at a preset speed.

[0027] Optionally, in the photolithography process, the preset time and the preset speed satisfy the following relationship:

[0028] 150% H0 ≤ H1 ≤ 300% H0;

[0029] 10%V0≤V1≤50%V0;

[0030] Wherein, H0 is the standard time for rinsing the central area, and H1 is the preset time; V0 is the standard speed for rinsing and scanning, and V1 is the preset speed.

[0031] Optionally, in the photolithography process, the process of coating a photoresist layer on the wafer surface includes:

[0032] A bottom anti-reflective layer is coated on the surface of the wafer;

[0033] A first baking process is performed on the bottom anti-reflective layer;

[0034] The photoresist layer is coated on the surface of the bottom anti-reflective layer;

[0035] Furthermore, after exposing the photoresist layer using an immersion lithography machine, and before rinsing the photoresist layer with a developer to form a patterned photoresist layer, the lithography process further includes:

[0036] A second baking process is performed on the exposed photoresist layer.

[0037] Based on the same inventive concept, the present invention also provides a semiconductor structure, which is prepared by the aforementioned photolithography process.

[0038] In summary, this invention provides a photolithography process and a semiconductor structure. Compared to existing technologies, this photolithography process increases the softening temperature during the softening of the photoresist layer to enhance the performance of the liquid barrier layer and reduce the defect formation rate. Furthermore, during exposure, reducing the exposure speed in defect-prone areas also helps reduce the defect formation rate and improve exposure quality. Further, during the post-development rinsing process, extending the rinsing time for the central region and slowing down the rinsing scanning speed from the central region towards the edge regions enhances the defect removal effect. Therefore, the photolithography process provided by this invention alleviates defect problems at their root cause, not only reducing the probability of downtime due to defects and shortening defect verification time, thus improving process efficiency, but also avoiding the expansion of the impact range due to detection rate issues, and significantly improving product yield. Attached Figure Description

[0039] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0040] Figure 1 This is a flowchart of the photolithography process in an embodiment of the present invention.

[0041] Figure 2 This is a schematic diagram showing the positions of the wafer, the bottom anti-reflective layer, and the photoresist layer in an embodiment of the present invention.

[0042] Figure 3 This is a schematic diagram showing the position of the liquid separator in an embodiment of the present invention.

[0043] Figure 4 This is a flowchart of the optimized exposure formulation process in an embodiment of the present invention.

[0044] Figure 5 This is a flowchart illustrating the process of obtaining the optimal exposure speed for the defect risk area in an embodiment of the present invention.

[0045] Figure 6 This is a schematic diagram of the structure of the photoresist layer exposed by an immersion lithography machine in an embodiment of the present invention.

[0046] Figure 7 This is a schematic diagram of the central region of the patterned photoresist layer being rinsed in an embodiment of the present invention.

[0047] Figure 8 This is a schematic diagram of scanning and rinsing from the center region toward the edge region in an embodiment of the present invention.

[0048] Figure 9 This is a schematic diagram of rinsing to the edge area in an embodiment of the present invention.

[0049] And, in the attached image:

[0050] 100 - Wafer; 101 - Bottom anti-reflective layer; 102 - Photoresist layer; 102a - Liquid separator layer;

[0051] 200 - Lens; 201 - Immersion hood;

[0052] 300 - Rinse platform; 301 - Rinse nozzle; 302 - Cleaning fluid;

[0053] S - wetting flow field; D1 - first direction; D2 - second direction. Detailed Implementation

[0054] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0055] Please see Figure 1 This embodiment provides a photolithography process, including:

[0056] Step 1 S10: Provide a wafer, the surface of which is coated with a photoresist layer;

[0057] Step 2 S20: Perform soft baking on the photoresist layer at a preset temperature to form a liquid barrier layer on top of the photoresist layer;

[0058] Step 3 S30: Expose the photoresist layer using an immersion lithography machine; wherein, the exposure rate of the defect risk area in the photoresist layer is lower than the exposure rate of the other areas in the photoresist layer;

[0059] Step 4 S40: Rinse the photoresist layer with a developer to form a patterned photoresist layer;

[0060] Step 5 S50: Rinse the patterned photoresist layer with a cleaning solution.

[0061] Therefore, the photolithography process provided in this embodiment increases the softening temperature during the softening of the photoresist layer to enhance the performance of the liquid barrier layer and reduce the defect formation rate. Furthermore, reducing the exposure speed in defect-prone areas during exposure also helps to reduce the defect formation rate and improve exposure quality. Based on this, the photolithography process provided in this embodiment alleviates defect problems at their root cause, not only reducing the probability of downtime due to defects and shortening defect verification time, thus improving process efficiency, but also avoiding the expansion of the impact range due to detection rate issues, and significantly improving product yield.

[0062] The following is in conjunction with the appendix Figures 1 to 9 This embodiment provides a detailed description of the photolithography process.

[0063] The photolithography process includes:

[0064] Step 1 S10: Please refer to Figure 2 A wafer 100 is provided, the surface of which is coated with a photoresist layer 102.

[0065] The wafer 100 referred to in this embodiment includes, but is not limited to, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. Before forming the photoresist layer 102 on the surface of the wafer 100, the photolithography process further includes: firstly coating a bottom anti-reflection layer 101 on the surface of the wafer 100; and then performing a first baking process on the bottom anti-reflection layer 101. The bottom anti-reflection layer 101 mainly consists of crosslinkable resin, a thermosetting acid generator, a surfactant, and a solvent. The function of the bottom anti-reflection layer 101 is to reduce light reflection on the surface of the wafer 100, thereby reducing the standing wave effect and improving photolithography accuracy. Furthermore, performing the first baking process on the bottom anti-reflection layer 101 can make the interface between the bottom anti-reflection layer 101 and the photoresist layer 102 smoother, reduce the thickness change and pattern deformation of the photoresist layer 102 caused by reflection, thereby improving the performance and reliability of the photoresist layer 102.

[0066] Furthermore, after performing the first baking process on the bottom anti-reflective layer 101, the photoresist layer 102 is coated on the surface of the bottom anti-reflective layer 101. In this embodiment, the photoresist layer 102 is not limited to being a positive or negative photoresist.

[0067] Step 2 S20: Please refer to Figure 3 The photoresist layer 102 is soft-baked at a preset temperature to form a liquid barrier layer 102a on top of the photoresist layer 102.

[0068] It should be noted that the purpose of performing soft baking on the photoresist layer 102 is to remove the solvent in the photoresist layer 102, changing it from a liquid to a solid state, thereby enhancing the adhesion of the photoresist layer 102 to the surface of the wafer 100. In addition, the soft baking process can also alleviate the internal stress of the photoresist layer 102, preventing problems such as cracking or peeling of the photoresist layer 102 in subsequent processes.

[0069] Furthermore, in this embodiment, a preset temperature is used to perform soft baking on the photoresist layer 102. The preset temperature is higher than the standard soft baking temperature and satisfies the following relationship:

[0070] T0 < T1 ≤ T0 + 10℃;

[0071] Wherein, T0 is the standard softening temperature; T1 is the preset temperature. The standard softening temperature is the temperature used in normal processes, generally between 80℃ and 120℃. However, the standard softening temperature varies depending on the process requirements. Therefore, in this embodiment, the standard softening temperature can be considered as the average softening temperature used in the same type of photolithography process. Before performing step two S20, this average softening temperature can be obtained based on the historical data of the machine and used as the standard softening temperature. In this embodiment, the preset temperature used in the softening process of the photoresist layer 102 is slightly higher than the standard softening temperature, the purpose of which is to improve the performance of the liquid barrier layer 102a during the softening process. For example, the standard softening temperature is 90℃, and the preset temperature is 95℃.

[0072] Specifically, such as Figure 3As shown, during the soft baking process, the photoresist layer 102 spontaneously generates a liquid barrier layer 102a. The liquid barrier layer 102a is formed by the automatic migration of an F-containing polymer to the top of the photoresist layer 102. The performance of the liquid barrier layer 102a directly affects the contact angle (CA) and leaching rate in immersion lithography, and changes in the hydrophilicity / hydrophobicity of the liquid barrier layer 102a affect the degree of water residue during exposure in the immersion lithography machine. The soft baking temperature has a certain impact on both the photoresist layer 102 and the liquid barrier layer 102a. For example, if the photoresist layer 102 is a positive resist, the soft baking temperature will affect the solvent ratio in the photoresist layer 102, thus affecting the critical dimension (CD); and the film thickness and density of the liquid barrier layer 102a are positively correlated with the thickness of the photoresist layer 102, while the film thickness and density of the liquid barrier layer 102a have a non-linear relationship with the soft baking temperature. Based on this, the applicant has verified that when the softening temperature is increased by no more than 10°C from the standard softening temperature, the performance of the liquid barrier layer 102a and its impact on CD can be balanced. That is, while obtaining the target CD, the performance of the liquid barrier layer 102a can be optimized, reducing water residue during immersion lithography exposure and improving the lithography effect.

[0073] Step 3 S30: Please refer to Figure 3 , Figure 4 and Figure 5 The photoresist layer 102 is exposed using an immersion lithography machine; wherein the exposure rate for defect-risk areas in the photoresist layer 102 is lower than the exposure rate for the remaining areas in the photoresist layer 102.

[0074] It should be noted that, based on historical process data, the applicant discovered that defect formation areas in immersion lithography machines generally exist along the path between scanning exposure and step exposure. Furthermore, because faster exposure speeds result in lower dynamic contact angles, it is easier to exceed the speed limit allowed by the photoresist layer 102, leading to water residue, decreased exposure quality, and potential defects such as bubbles, further reducing the exposure effect. Therefore, the lithography process provided in this embodiment pre-determines defect risk areas based on historical machine data; then, it modifies the exposure formula to reduce the exposure speed in these defect risk areas, thereby optimizing the exposure effect.

[0075] Specifically, such as Figure 4As shown, before executing step S30, the coordinates of the exposure defects are obtained from the defect list source file stored in the machine; the exposure speed information is obtained from the Machine Data (Diagnostic) Logging (MDL); and the exposure path and exposure speed information are obtained from the product film layer exposure path file. After obtaining these data, the maximum exposure speed and the coordinate range of the defect risk area are obtained through data integration and analysis. It should be noted that the defect risk area is the location corresponding to each defect coordinate as statistically analyzed in the defect list source file, which can be a single area within a defect set or multiple areas within a defect set.

[0076] For further details, please refer to Figure 5 and Figure 6 After obtaining the maximum exposure speed and determining the coordinate range of the defect risk area, the photolithography process includes:

[0077] Sub-step S300: A test wafer is provided; the surface of the test wafer is coated with the photoresist layer 102; and the photoresist layer 102 is soft-baked at the preset temperature.

[0078] The test wafer is a dedicated wafer used for verifying processes, calibrating equipment, and performing quality control. Furthermore, to adhere to the single variable principle, the test wafer needs to first undergo the processes described in steps S10 and S20 above. That is, the surface of the test wafer is sequentially coated with the bottom anti-reflective layer 101 and the photoresist layer 102, and the photoresist layer 102 is soft-baked at the preset temperature.

[0079] Sub-step S301: Reduce the maximum exposure speed by a preset unit increment to serve as the exposure speed for the defect risk area.

[0080] Sub-step S302: Expose the defect risk area in the test wafer using the exposure speed of the defect risk area.

[0081] As described above, excessively high exposure speeds in the defect-risk areas can easily lead to exposure defects. Therefore, the photolithography method provided in this embodiment gradually reduces the exposure speed in these areas to achieve optimal exposure results, effectively mitigating defect formation at its source. This reduces the need for disassembly and cleaning of the immersion cover 201 of the lens 200, ensuring a stable immersion flow field S environment and lowering the probability of downtime due to defect detection. In this embodiment, the unit magnitude of the reduction in exposure speed each time is not limited and can be set according to the process requirements.

[0082] Sub-step four S303: Perform defect detection on the defect risk area and obtain the detection result; if the detection result meets the defect requirements, output the current exposure speed of the defect risk area; if the detection result does not meet the defect requirements, repeat sub-step one S300 to sub-step four S303 until the detection result meets the defect requirements.

[0083] To determine whether the current exposure speed for the defect risk area is optimal, the exposure speed formula after each adjustment needs to be verified. Specifically, a defect inspection machine is used to inspect the test wafer for defects after exposure. If the inspection results meet the defect requirements, the current exposure speed for the defect risk area can be considered the optimized exposure speed. If the inspection results show that the defect rate is still high and does not meet the defect requirements, the above operation needs to be repeated, and another test wafer is used for optimization testing until the inspection results meet the defect requirements.

[0084] Furthermore, after the optimization tests in sub-steps S300 to S303, a better exposure speed for the defect risk area can be obtained. Therefore, during the exposure of the photoresist layer 102 using an immersion lithography machine, the defect risk area is exposed using the optimized exposure speed obtained for the current defect risk area; and the remaining areas are exposed using the maximum exposure speed. The remaining areas are those areas that show no defects or a low defect rate in historical data. Thus, the above method for obtaining the optimal exposure speed formula is based on data analysis and rapid online verification, requiring no machine downtime for inspection, minimizing impact on machine capacity. Moreover, customized exposure speed optimization offers productivity advantages compared to a fixed-speed exposure machine, achieving the best balance between defect performance and productivity.

[0085] Preferably, after performing step three (S30) and before performing step four (S40), the photolithography process further includes performing a second baking process on the exposed photoresist layer 102. The purpose of the second baking is to balance the standing wave effect and smooth the photoresist sidewalls to improve the photolithography resolution.

[0086] Step 4 S40: Please refer to Figure 6 The photoresist layer 102 is rinsed with a developer to form a patterned photoresist layer 102.

[0087] The developer is a chemical solvent that dissolves the soluble areas of the photoresist caused by exposure. It can effectively remove some of the photoresist structure after exposure and make the exposed image visible, thereby forming a patterned photoresist layer 102.

[0088] Step 5 S50: Please refer to Figures 6 to 9The patterned photoresist layer 102 is rinsed with cleaning solution 302.

[0089] It should be noted that the purpose of rinsing the patterned photoresist layer 102 with cleaning solution 302 after the exposure and development process is to remove residual developer and impurities and contaminants from the surface of the patterned photoresist layer 102. This not only helps optimize the uniformity and corrosion resistance of the patterned photoresist layer 102, but also helps reduce defects caused by incomplete development or residues. Furthermore, to further alleviate photolithography defects, during the rinsing process with cleaning solution 302, the central region of the patterned photoresist layer 102 is first rinsed for a preset time; then, a preset speed is used to scan and rinse from the central region towards the edge region. Preferably, the cleaning solution 302 is deionized water.

[0090] For details, please refer to Figure 7 During the rinsing process, the wafer 100 is first placed on the rinsing support platform 300, and then a rinsing nozzle 301 sprays cleaning fluid 302 onto the surface of the wafer 100. Specifically, the rinsing nozzle 301 first sprays the cleaning fluid 302 towards the central region of the wafer 100. Simultaneously, the rinsing support platform 300 causes the wafer 100 to rotate along a first direction D1, or in the opposite direction to the first direction D1, so that the cleaning fluid 302 evenly rinses the central region of the wafer 100. Preferably, the rinsing time for the central region is the preset time, and the preset time is greater than the standard rinsing time for the central region, satisfying the following relationship:

[0091] 150% H0 ≤ H1 ≤ 300% H0;

[0092] Wherein, H0 is the standard rinsing time for the central region, and H1 is the preset time. In this embodiment, the standard time can be the average time for cleaning the patterned photoresist layer 102 in the same type of photolithography process, or it can be a time value commonly used in the industry. For example, the total time of the entire rinsing process is generally about 30 seconds, while the standard rinsing time for the central region is about 5 seconds, so the preset time can be extended to 7.5 seconds, 10 seconds, or 15 seconds. It is understood that the yield of the central region of the wafer 100 is generally higher than that of the edge region, so increasing the cleaning time of the central region can further reduce the defect rate and improve the product yield.

[0093] Please see Figure 8 and Figure 9After cleaning the central region for a preset time, the rinsing nozzle 301 moves along the second direction D2, that is, from the central region of the wafer 100 towards the edge region, to thoroughly clean the wafer 100. Preferably, the rinsing speed from the central region towards the edge region is the preset speed, and the preset speed is less than the standard rinsing scanning speed, and satisfies the following relationship:

[0094] 10%V0≤V1≤50%V0;

[0095] Wherein, V0 is the standard rinsing scan speed, and V1 is the preset speed. In this embodiment, the standard rinsing scan speed can be the average rinsing scan speed for cleaning the patterned photoresist layer 102 in the same type of photolithography process, or it can be a speed standard value commonly used in the industry. For example, the standard speed is generally 10 mm / s, then the preset speed can be reduced to: 1 mm / s, 3 mm / s, or 5 mm / s. Similarly, reducing the rinsing scan speed can more thoroughly rinse the area between the central region and the edge region, as well as the edge region, further reducing the defect rate and improving the product yield.

[0096] Preferably, during the rinsing of the central region of the wafer 100, and / or during the rinsing from the central region toward the edge region, the rotation speed of the rinsing stage 300 can be reduced; that is, the rotation speed of the wafer 100 is reduced so that the cleaning fluid 302 can fully rinse the wafer 100, further enhancing the rinsing effect, reducing the defect rate, and improving the product yield.

[0097] After rinsing is completed, the wafer 100 can be further dried by spin drying, and after the wafer 100 has cooled down, it can be transferred out of the cleaning chamber for other subsequent processes.

[0098] Based on the same concept, this embodiment also provides a semiconductor structure. The fabrication process of the semiconductor structure includes the photolithography process described above.

[0099] In summary, this embodiment provides a photolithography process and a semiconductor structure. Specifically, during the soft baking of the photoresist layer 102, the soft baking temperature is increased to enhance the performance of the liquid separator layer 102a and reduce the defect formation rate. Furthermore, during exposure, an optimized exposure speed formula is pre-obtained, specifically reducing the exposure speed in defect-risk areas, which also helps reduce the defect formation rate and improve exposure quality. Additionally, during the post-development rinsing process, the rinsing time for the central region is lengthened, and the rinsing scanning speed from the central region towards the edge regions is slowed down to enhance defect removal. Therefore, the photolithography process provided in this embodiment alleviates defect problems at their root cause, not only reducing the probability of downtime due to defects and shortening defect verification time, but also improving process efficiency. It also avoids the expansion of the impact range due to detection rate issues and significantly improves product yield.

[0100] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A photolithography process, characterized in that, include: A wafer is provided, the surface of which is coated with a photoresist layer; The photoresist layer is soft-baked at a preset temperature to form a liquid barrier layer on top of the photoresist layer; The photoresist layer is exposed using an immersion lithography machine; wherein the exposure rate of defect-prone areas in the photoresist layer is lower than the exposure rate of the remaining areas in the photoresist layer. The photoresist layer is rinsed with a developer to form a patterned photoresist layer; The patterned photoresist layer is rinsed with a cleaning solution.

2. The photolithography process according to claim 1, characterized in that, The preset temperature is higher than the standard temperature for soft baking, and satisfies the following relationship: T0 < T1 ≤ T0 + 10℃; Wherein, T0 is the standard temperature for soft baking; T1 is the preset temperature.

3. The photolithography process according to claim 2, characterized in that, The standard temperature for soft baking is 90°C, and the preset temperature is 95°C.

4. The photolithography process according to claim 1, characterized in that, Before exposing the photoresist layer using an immersion lithography machine, the lithography process includes: Based on the defect list source file, machine record data, and exposure path file stored on the machine, the maximum exposure speed is obtained, and the coordinate range of the defect risk area is determined.

5. The photolithography process according to claim 4, characterized in that, After obtaining the maximum exposure speed and determining the coordinate range of the defect risk region, the photolithography process includes: Step 1: Provide a test wafer; the surface of the test wafer is coated with the photoresist layer; and the photoresist layer is softened at the preset temperature; Step 2: Reduce the maximum exposure speed by a preset unit increment to determine the exposure speed for the defect risk area; Step 3: Expose the defect risk area in the test wafer using the exposure speed of the defect risk area; Step 4: Perform defect detection on the defect risk area and obtain the detection results; if the detection results meet the defect requirements, output the current exposure speed of the defect risk area; if the detection results do not meet the defect requirements, repeat steps 1 to 4 until the detection results meet the defect requirements.

6. The photolithography process according to claim 5, characterized in that, During the process of exposing the photoresist layer using an immersion lithography machine, the defect risk area is exposed using the current exposure speed of the defect risk area; And, the remaining area is exposed using the maximum exposure speed.

7. The photolithography process according to claim 1, characterized in that, During the process of rinsing the patterned photoresist layer with a cleaning solution: The central region of the patterned photoresist layer is rinsed for a preset time; The patterned photoresist layer is scanned and rinsed from the center region toward the edge region at a preset speed.

8. The photolithography process according to claim 7, characterized in that, The preset time and the preset speed satisfy the following relationship: 150%H0≤H1≤300%H0; 10%V0≤V1≤50%V0; Wherein, H0 is the standard time for rinsing the central area, and H1 is the preset time; V0 is the standard speed for rinsing and scanning, and V1 is the preset speed.

9. The photolithography process according to claim 1, characterized in that, The process of coating a photoresist layer on the wafer surface includes: A bottom anti-reflective layer is coated on the surface of the wafer; A first baking process is performed on the bottom anti-reflective layer; The photoresist layer is coated on the surface of the bottom anti-reflective layer; Furthermore, after exposing the photoresist layer using an immersion lithography machine, and before rinsing the photoresist layer with a developer to form a patterned photoresist layer, the lithography process further includes: A second baking process is performed on the exposed photoresist layer.

10. A semiconductor structure, characterized in that, It is prepared using the photolithography process described in any one of claims 1 to 9.

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