Backside metallization structure of a semiconductor device and method of manufacturing the same

Abstract

This invention provides a back-side metallization structure for a semiconductor device and its manufacturing method, comprising the following steps: forming a seed layer on the back side of a semiconductor substrate; forming an electroplated gold layer on the surface of the seed layer; forming a first photoresist pattern with an opening width of CD1 on the electroplated gold layer; using the first photoresist pattern as a mask to perform an etching process on the electroplated gold layer; removing the first photoresist pattern to form an electroplated gold pattern with a line spacing of CD2; forming a second photoresist pattern with an opening width of CD3 on the surface of the electroplated gold pattern, wherein CD3 < CD1; using the second photoresist pattern as a mask to perform an etching process on the seed layer; removing the second photoresist pattern to form a metallization structure. This invention, through a dual photolithography process, forms a unique inverted trapezoidal stepped metallization structure with a wide bottom and narrow top on the back side of the semiconductor substrate, significantly enhancing the adhesion between the metallization structure and the semiconductor substrate, and improving the device's shear force test value, electrical performance, and long-term operational reliability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, and in particular relates to a back-side metallization structure of a semiconductor device and its manufacturing method. Background Technology

[0002] In the field of compound semiconductor manufacturing, especially in the fabrication of high-performance devices such as gallium arsenide (GaAs) high electron mobility transistors (pHEMTs) and heterojunction bipolar transistors (HBTs), back-side metallization is one of the key steps to ensure device electrical performance and long-term reliability. This process typically involves depositing a seed layer and a conductive metal layer (such as gold) sequentially on the back side of a thinned GaAs substrate to form good ohmic contacts and external circuit connections. The seed layer plays a crucial role; it serves as an adhesion layer between the GaAs substrate and the subsequent gold layer, and also acts as an effective diffusion barrier to prevent gold atoms from diffusing into the GaAs substrate during subsequent processes or device operation, thereby avoiding device electrical performance degradation due to gold contamination.

[0003] Currently, titanium-tungsten (TiW) alloys are widely used in back-side seed layer sputtering due to their excellent diffusion-blocking properties. However, because TiW alloys have a high tungsten content and are chemically inert, their physicochemical bonding with the GaAs substrate surface is weak. This inherent lack of adhesion exposes the back-side metallized structure to the risk of mechanical failure during subsequent packaging, testing, and use. Specifically, during shear force testing, the back-side metal layer (starting from the seed layer) is prone to detachment or peeling. Shear force testing is a destructive mechanical testing method primarily used to evaluate the mechanical strength and quality of interconnect structures in semiconductor devices. Its basic principle is to apply a controlled, continuously increasing mechanical force to the micro-interconnect structure of the semiconductor device until it fails. By measuring the destructive force and analyzing the failure mode, the mechanical strength and process quality of the interconnect structure are quantitatively evaluated. Low shear force test values ​​directly reflect weak interface bonding strength, which not only reduces product yield but also severely affects the probability of the device passing long-term reliability tests such as mechanical shock and temperature cycling, ultimately limiting the application of the device in harsh environments.

[0004] Therefore, there is an urgent need for a new method or structure that can significantly enhance the interfacial bonding strength between the back seed layer and the GaAs substrate (i.e., improve the shear force test value) to improve the yield of GaAs semiconductor devices and the probability of passing reliability tests. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a back metallization structure for semiconductor devices and a method for manufacturing the same, in order to solve the technical problems in the prior art where gallium arsenide semiconductor devices use titanium-tungsten alloy as the back seed layer, which leads to poor adhesion between the alloy layer and the gallium arsenide substrate, resulting in easy detachment of the back metallization structure, low device mechanical reliability, and reduced yield.

[0006] To achieve the above and other related objectives, the present invention provides a method for manufacturing a back-side metallization structure of a semiconductor device, comprising the following steps:

[0007] S1. A seed layer is formed on the back side of the semiconductor substrate;

[0008] S2. An electroplated gold layer is formed on the surface of the seed layer;

[0009] S3. Perform a first photolithography process on the electroplated gold layer to form a first photoresist pattern with an opening width of CD1;

[0010] S4. Using the first photoresist pattern as a mask, perform an etching process on the electroplated gold layer to remove the areas of the electroplated gold layer not covered by the mask.

[0011] S5. Remove the first photoresist pattern to form an electroplated gold pattern with a line spacing of CD2;

[0012] S6. Perform a second photolithography process on the surface of the electroplated gold pattern to form a second photoresist pattern with an opening width of CD3, where CD3 < CD1;

[0013] S7. Using the second photoresist pattern as a mask, perform an etching process on the seed layer to remove the seed layer area not covered by the mask, forming a seed layer pattern with a line spacing of CD4.

[0014] S8. Remove the second photoresist pattern to form a metallized structure with a bottom line distance of CD4 and a top line distance of CD2.

[0015] Preferably, the semiconductor substrate in step S1 is a GaAs substrate.

[0016] Preferably, the seed layer in step S1 is a Ti / Au or TiW / Au stack, and the thickness of the seed layer is 50nm~400nm.

[0017] Preferably, the thickness of the electroplated gold layer formed in step S2 is 2μm to 6μm.

[0018] Preferably, in step S3, the sidewall angle of the first photoresist pattern is 70°~90°, and the thickness of the first photoresist pattern is 10μm~16μm.

[0019] Preferably, in step S5, the line distance CD2 of the electroplated gold pattern is greater than the opening width CD1 of the first photoresist pattern.

[0020] Preferably, in step S6, the sidewall angle of the second photoresist pattern is 70°~90°, and the thickness of the second photoresist pattern is 10μm~16μm.

[0021] Preferably, in the metallized structure formed in step S8 with a bottom line distance of CD4 and a top line distance of CD2, CD4 > CD2.

[0022] The present invention also provides a semiconductor device, characterized in that it comprises:

[0023] Semiconductor substrate;

[0024] A metallization structure formed on the back side of the semiconductor substrate;

[0025] The metallization structure includes a seed layer pattern and an electroplated gold pattern located above the seed layer pattern; wherein the line width of the seed layer pattern is greater than the line width of the electroplated gold pattern.

[0026] Preferably, the seed layer pattern is a Ti / Au stack pattern or a TiW / Au stack pattern.

[0027] As described above, the back-side metallization structure of the semiconductor device and its manufacturing method of the present invention have the following beneficial effects:

[0028] This invention employs a unique dual photolithography process to sequentially etch the sidewalls of the electroplated gold layer and the seed layer. A second photolithography process defines the protective area of ​​the seed layer, precisely controlling the bottom dimensions of the metallized structure. This avoids the severe pattern shrinkage problem caused by lateral etching in traditional processes, ensuring the accuracy of device design. A unique inverted trapezoidal stepped metallized structure with a wide bottom and narrow top is formed on the back side of the semiconductor substrate. In shear force testing, this structure not only increases the contact area between the metallized structure and the semiconductor substrate, but also allows molten solder to fill the grooves of the step, creating a strong mechanical interlock between the metallized structure and the semiconductor substrate. This significantly enhances the adhesion between the metallized structure and the semiconductor substrate, improves the shear force test value of the device, and effectively prevents the metal layer from detaching during subsequent dicing or packaging processes, solving the technical problem of poor metal layer adhesion. Furthermore, the inverted trapezoidal metallized structure increases the contact area between the metal and the substrate, reduces contact resistance, and improves the conductivity and heat dissipation performance of the device, thereby improving the electrical performance and long-term operational reliability of the device. Attached Figure Description

[0029] Figure 1The diagram shows a manufacturing process flow diagram of the back metallization structure of the semiconductor device in Example 1.

[0030] Figures 2-9 The diagram shows the structural schematics of each step in the manufacturing method of the back metallization structure of the semiconductor device in Example 1.

[0031] Figure 10 The diagram shows the structure following step S4 in Comparative Example 1.

[0032] Figure 11 The diagram shown is a schematic of the back-side metallization structure prepared in Comparative Example 1.

[0033] Figure 12 The diagram shows the metallized structures in Example 2 and Comparative Example 1 during shear force testing.

[0034] Component designation explanation

[0035] 10 Semiconductor substrate 20 Seed layer 201 Seed layer graph 30 Electroplated gold layer 301 Electroplated gold graphics 40 First photoresist pattern 50 Second photoresist pattern 60 solder layer 70 heat sink Detailed Implementation

[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] Before further describing specific embodiments of the present invention, it should be understood that the scope of protection of the present invention is not limited to the specific embodiments described below; it should also be understood that the terminology used in the embodiments of the present invention is for describing specific embodiments and not for limiting the scope of protection of the present invention. Test methods in the following embodiments that do not specify specific conditions are generally performed under conventional conditions or as recommended by the respective manufacturers.

[0038] When numerical ranges are given in the embodiments, it should be understood that, unless otherwise stated in the present invention, both endpoints of each numerical range and any value between the two endpoints may be selected. Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art. In addition to the specific methods, apparatus, and materials used in the embodiments, based on the knowledge of the prior art possessed by one of ordinary skill in the art and the description of this invention, any prior art methods, apparatus, and materials similar to or equivalent to those described, apparatus, and materials in the embodiments of this invention may be used to implement the present invention.

[0039] Please see Figures 1-12It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0040] See Figure 1 This embodiment provides a method for manufacturing a back-side metallization structure of a semiconductor device, including the following steps:

[0041] S1. A seed layer 20 is formed on the back side of the semiconductor substrate 10;

[0042] S2. An electroplated gold layer 30 is formed on the surface of the seed layer 20;

[0043] S3. Perform a first photolithography process on the electroplated gold layer 30 to form a first photoresist pattern 40 with an opening width of CD1.

[0044] S4. Using the first photoresist pattern 40 as a mask, perform an etching process on the electroplated gold layer 30 to remove the area of ​​the electroplated gold layer 30 not covered by the mask.

[0045] S5. Remove the first photoresist pattern 40 to form an electroplated gold pattern 301 with a line spacing of CD2;

[0046] S6. A second photolithography process is performed on the surface of the electroplated gold pattern 301 to form a second photoresist pattern 50 with an opening width of CD3, where CD3 < CD1.

[0047] S7. Using the second photoresist pattern 50 as a mask, perform an etching process on the seed layer 20 to remove the area of ​​the seed layer 20 not covered by the mask, forming a seed layer pattern 201 with a line spacing of CD4.

[0048] S8. Remove the second photoresist pattern 50 to form a metallized structure with a bottom line distance of CD4 and a top line distance of CD2.

[0049] This embodiment employs a unique dual photolithography process to sequentially etch the sidewalls of the electroplated gold layer 30 and the seed layer 20. A second photolithography process defines the protective area of ​​the seed layer 20, precisely controlling the bottom dimensions of the metallized structure. This avoids the severe pattern shrinkage problem caused by lateral etching in traditional processes, ensuring the accuracy of the device design. A unique inverted trapezoidal stepped metallized structure with a wide bottom and narrow top is formed on the back side of the semiconductor substrate 10. In shear force testing, this structure not only increases the contact area between the metallized structure and the semiconductor substrate 10, but also allows molten solder to fill the grooves in the steps, thus forming a strong mechanical interlocking structure between the metallized structure and the semiconductor substrate 10. This significantly enhances the adhesion between the metallized structure and the semiconductor substrate 10, improves the shear force test value of the device, and effectively prevents the metal layer from detaching during subsequent dicing or packaging processes, solving the technical problem of poor metal layer adhesion. Furthermore, the inverted trapezoidal metallized structure increases the contact area between the metal and the substrate, reduces contact resistance, and improves the conductivity and heat dissipation performance of the device, thereby improving the electrical performance and long-term operational reliability of the device.

[0050] The following is in conjunction with the instruction manual. Figures 2-9 The fabrication of the back-side metallization structure of the semiconductor device will be further explained.

[0051] First, refer to Figure 2 Step S1 is performed to form a seed layer 20 on the back side of the semiconductor substrate 10.

[0052] As an example, the semiconductor substrate 10 in step S1 is a GaAs substrate.

[0053] Specifically, the GaAs substrate includes a sapphire substrate and a GaAs epitaxial layer, meaning that a GaAs thin film is grown on the sapphire substrate using heteroepitaxial technology. The size and thickness of the GaAs substrate can be selected as needed, and no excessive restrictions are imposed here.

[0054] As an example, the seed layer 20 in step S1 is a Ti / Au or TiW / Au stack, and the thickness of the seed layer 20 is 50nm~400nm.

[0055] Specifically, the seed layer 20 is a metal stack formed by physical vapor deposition sputtering or evaporation. In a specific embodiment of the present invention, a Ti / Au or TiW / Au stacked seed layer 20 is formed on the back side of the semiconductor substrate 10 by sputtering. The thickness of the seed layer 20 may include any value in the range of 50nm, 100nm, 200nm, 300nm, 350nm, 400nm, etc., and can be adjusted according to actual conditions.

[0056] Next, refer to Figure 3Step S2 is executed to form an electroplated gold layer 30 on the surface of the seed layer 20;

[0057] As an example, in step S2, a cyanide-free electroplating process is used to electroplat a gold layer 30 on the surface of the seed layer 20.

[0058] Specifically, the gold salt used in the cyanide-free electroplating process is sodium gold sulfite (Na3Au(SO3)2) or gold citrate. By controlling pH, temperature and current density, a uniformly thickened electroplated gold layer 30 is achieved. The specific steps of the cyanide-free electroplating process will not be elaborated here; it is sufficient to achieve an electroplated gold layer 30 that meets the actual requirements.

[0059] As an example, the thickness of the electroplated gold layer 30 formed in step S2 is 2μm to 6μm.

[0060] Specifically, the thickness of the formed electroplated gold layer 30 can be any value within the range of 2μm, 3μm, 4μm, 5μm, 6μm, etc., and can be adjusted according to the actual situation.

[0061] Next, refer to Figure 4 Step S3 is executed, and a first photolithography process is performed on the electroplated gold layer 30 to form a first photoresist pattern 40 with an opening width of CD1.

[0062] As an example, the photoresist used in the first photolithography process is a positive photoresist, including SPR-220 or AZ4620.

[0063] As an example, in step S3, the sidewall angle of the first photoresist pattern 40 is 70°~90°, and the thickness of the first photoresist pattern 40 is 10μm~16μm.

[0064] Specifically, the first photolithography process includes coating a first photoresist, exposure, and development to form a first photoresist pattern 40 with an opening width of CD1, so that the electroplated gold layer 30 below can be etched through the opening. The thickness of the coated first photoresist is the thickness of the formed first photoresist pattern 40, which can include any value in the range of 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, etc. The purpose of coating a thicker first photoresist is to form a distinctly sloping first photoresist pattern 40, with its sidewall angles of 70°~90°, such as 70°, 75°, 80°, 85°, 90°, etc. At the same time, a thicker first photoresist can provide sufficient protection for subsequent wet etching. However, the first photoresist should not be too thick. If it is too thick, the uniformity of the coating will be poor, and the difficulty of exposure and development will increase sharply.

[0065] Next, refer to Figure 5 In step S4, the first photoresist pattern 40 is used as a mask to perform an etching process on the electroplated gold layer 30 to remove the areas of the electroplated gold layer 30 not covered by the mask.

[0066] As an example, in step S4, a gold etching solution is used to perform a wet etching process on the electroplated gold layer 30.

[0067] Specifically, the wafer with the first photoresist pattern 40 is immersed in a gold etching solution. The gold etching solution selectively etches the areas of the electroplated gold layer 30 not covered by the first photoresist pattern 40, while the areas of the electroplated gold layer 30 covered by the first photoresist pattern 40 are preserved due to the masking protection of the photoresist. By controlling the etching time and the concentration of the etching solution, it is ensured that the electroplated gold layer 30 is completely etched through, thereby forming an independent electroplated gold pattern 301 on the seed layer 20. The selection of the gold etching solution should meet the requirement of selectively removing the thick electroplated gold layer 30, retaining the desired electroplated gold pattern 301, while not damaging the underlying seed layer 20. The specific materials of the gold etching solution are not specifically limited here, nor are the parameters of this wet etching process.

[0068] Next, refer to Figure 6 Step S5 is executed to remove the first photoresist pattern 40 and form an electroplated gold pattern 301 with a line spacing of CD2.

[0069] Specifically, the first photoresist pattern 40 is usually removed by using organic solvents or plasma ashing. In a specific embodiment of the present invention, the dissolving power of NMP (N-methylpyrrolidone) solution is used to dissolve the first photoresist pattern 40 by controlling its temperature and time, ultimately leaving only the electroplated gold pattern 301.

[0070] As an example, the line distance CD2 of the electroplated gold pattern 301 in step S5 is greater than the opening width CD1 of the first photoresist pattern 40.

[0071] Specifically, in the wet etching process, the gold etching solution flows down the sloping sidewall of the first photoresist pattern 40. When the gold etching solution flows laterally, it will continuously erode the side of the electroplated gold layer 30, causing lateral erosion, which makes the line distance of the formed electroplated gold pattern 301 larger than the opening width of the first photoresist pattern 40.

[0072] Next, refer to Figure 7 Step S6 is executed to perform a second photolithography process on the surface of the electroplated gold pattern 301 to form a second photoresist pattern 50 with an opening width of CD3, where CD3 < CD1.

[0073] Specifically, the second photolithography process can be adjusted to make the opening width CD3 of the formed second photoresist pattern 50 less than CD1. Specific process adjustments include one or more combinations of increasing the photoresist thickness, reducing the exposure energy, and shortening the development time.

[0074] In a specific embodiment of the present invention, see [reference]. Figure 7 The second photoresist pattern 50 completely covers the formed electroplated gold pattern 301, and its opening width is larger than that of the first photoresist pattern 40.

[0075] As an example, in step S6, the sidewall angle of the second photoresist pattern 50 is 70°~90°, and the thickness of the second photoresist pattern 50 is 10μm~16μm.

[0076] Specifically, the second photolithography process includes steps such as coating the first photoresist, exposure, and development. The thickness of the coated second photoresist is the thickness of the formed second photoresist pattern 50, which can include any value in the range of 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, etc. The purpose of coating a thicker second photoresist is to form a distinctly sloping second photoresist pattern 50, with its sidewall angles being 70°~90°, such as 70°, 75°, 80°, 85°, 90°, etc.

[0077] As an example, the photoresist used in the second photolithography process is a positive photoresist, including SPR-220 or AZ4620.

[0078] Next, refer to Figure 8 In step S7, the seed layer 20 is etched using the second photoresist pattern 50 as a mask to remove the areas of the seed layer 20 not covered by the mask, forming a seed layer pattern 201 with a line spacing of CD4.

[0079] As an example, in step S7, a mixture of hydrogen peroxide and water is used to perform a wet etching process on the seed layer 20.

[0080] Specifically, when the seed layer 20 is wet-etched using a mixture of hydrogen peroxide and water, the mixture removes the areas of the seed layer 20 not covered by the second photoresist pattern 50, thereby exposing the underlying GaAs substrate. Wet etching is not anisotropic, and there will be some lateral erosion during the etching process, so that the sidewall morphology of the seed layer 20 is not etched vertically downwards, resulting in the line distance CD4 of the formed seed layer pattern 201 being greater than CD3.

[0081] Finally, see Figure 9Step S8 is executed to remove the second photoresist pattern 50, forming a metallized structure with a bottom line distance of CD4 and a top line distance of CD2.

[0082] As an example, in the metallized structure formed in step S8 with a bottom line distance of CD4 and a top line distance of CD2, CD4 > CD2.

[0083] For details, please refer to Figure 9 The final metallized structure includes a seed layer pattern 201 and an electroplated gold pattern 301 on the surface of the seed layer pattern 201. Since the metallized structure is formed on the back side of the semiconductor substrate 10, the metallized structure is in the shape of an inverted trapezoidal step, which increases the contact area between the metal layer and the substrate, reduces the contact resistance, and improves the conductivity and heat dissipation performance of the device. Furthermore, the metallized structure forms a mechanical interlocking structure with the contact interface of the semiconductor substrate 10, which greatly increases the adhesion between the two.

[0084] Example 2

[0085] See Figures 2-9 This embodiment also provides a semiconductor device, characterized in that it includes:

[0086] Semiconductor substrate 10;

[0087] A metallization structure formed on the back side of the semiconductor substrate 10;

[0088] The metallization structure includes a seed layer pattern 201 and an electroplated gold pattern 301 located above the seed layer pattern 201; wherein the line width of the seed layer pattern 201 is greater than the line width of the electroplated gold pattern 301.

[0089] For details, please refer to Figure 9 The line width of the seed layer pattern 201 is greater than the line width of the electroplated gold pattern 301, which means that the line distance CD4 of the seed layer pattern 201 is less than the line distance CD2 of the electroplated gold layer 30.

[0090] As an example, the semiconductor substrate 10 is a GaAs substrate.

[0091] As an example, the seed layer pattern 201 is a Ti / Au stack pattern or a TiW / Au stack pattern.

[0092] In this embodiment, the semiconductor device can be prepared using the manufacturing method in Example 1, but it is not limited to this. In this embodiment, the semiconductor device is prepared directly using the manufacturing method in Example 1. Therefore, the material, structure, preparation, etc. of the back metallization structure of the semiconductor device will not be described in detail here.

[0093] Comparative Example 1

[0094] This comparative example provides a back-side metallization structure of a semiconductor device in the prior art and its manufacturing method. The manufacturing method differs from that in Example 1 in that: after step S4, refer to... Figure 10 The etching process continues on the seed layer 20 below the electroplated gold layer 30 to remove the areas of the electroplated gold layer 30 and the seed layer 20 not covered by the mask. Then, the photoresist pattern is removed to form a metallized structure with a bottom line spacing of CD4-1 and a top line spacing of CD2-1. This metallized structure includes a seed layer pattern 201 and an electroplated gold pattern 301, and the line spacing CD4-1 of the seed layer pattern 201 is greater than the line spacing CD2-1 of the electroplated gold pattern 301. (See reference...) Figure 11 The preceding steps are the same as in Example 1, and will not be repeated here.

[0095] Shear force test:

[0096] Using GaAs substrates from the same batch, the back-side metallization structures of the semiconductor devices in Example 2 and Comparative Example 1 were prepared by the method in Example 1, and shear force tests were performed on each.

[0097] The testing method is as follows:

[0098] (1) See Figure 12 The metallization structures of the semiconductor devices under test in Example 2 and Comparative Example 1 are soldered onto the heat sink 70 through solder layer 60, wherein solder layer 60 is made of gold-tin solder.

[0099] (2) Using a shearing tool made of cemented carbide, the semiconductor substrate 10 is pushed horizontally at a constant speed. The shearing tool applies a shearing force to the semiconductor substrate 10, which is parallel to the surface of the heat sink 70.

[0100] (3) The maximum force required to push the semiconductor substrate 10 away from the back metallization structure is recorded by a sensor, which is the shear strength. The test results are shown in Table 1 below.

[0101] Table 1. Shear force test results

[0102]

[0103] As can be seen from Table 1, the average shear force of Example 2 is as high as 5498.4 gf, and the data is extremely stable (fluctuation range is only 2), which fully meets the industry standard of minimum qualified shear force (spec) ≥1130 gf; the average shear force of Comparative Example 1 is only 3673.6 gf, and the data fluctuates greatly (fluctuation range is as high as 3586), which poses a serious risk of failure.

[0104] As can be seen from the comparison, in the specific embodiment of the present invention, a unique inverted trapezoidal step structure is formed at the edge of the metal layer through two photolithography processes. In the shear test, this structure not only increases the contact area between the metal layer and the substrate, but more importantly, the molten gold-tin solder can fill the groove of the step, forming a strong mechanical interlocking structure. This structure greatly improves the shear resistance of the interface, thereby solving the problems of easy metal layer detachment and poor reliability in the traditional BSL process.

[0105] In summary, this invention employs a unique dual photolithography process to sequentially etch the sidewalls of the electroplated gold layer and the seed layer. A second photolithography process defines the protective area of ​​the seed layer, precisely controlling the bottom dimensions of the metallized structure. This avoids the severe pattern shrinkage problem caused by lateral etching in traditional processes, ensuring the accuracy of device design. A unique inverted trapezoidal stepped metallized structure with a wide bottom and narrow top is formed on the back side of the semiconductor substrate. In shear force testing, this structure not only increases the contact area between the metallized structure and the semiconductor substrate, but also allows molten solder to fill the grooves of the step, creating a strong mechanical interlock between the metallized structure and the semiconductor substrate. This significantly enhances the adhesion between the metallized structure and the semiconductor substrate, improves the shear force test value of the device, and effectively prevents the metal layer from detaching during subsequent dicing or packaging processes, solving the technical problem of poor metal layer adhesion. Furthermore, the inverted trapezoidal metallized structure increases the contact area between the metal and the substrate, reduces contact resistance, and improves the conductivity and heat dissipation performance of the device, thereby improving the electrical performance and long-term operational reliability of the device. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0106] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a back-side metallization structure of a semiconductor device, characterized in that, Includes the following steps: S1. A seed layer is formed on the back side of the semiconductor substrate; S2. An electroplated gold layer is formed on the surface of the seed layer; S3. Perform a first photolithography process on the electroplated gold layer to form a first photoresist pattern with an opening width of CD1; S4. Using the first photoresist pattern as a mask, perform an etching process on the electroplated gold layer to remove the areas of the electroplated gold layer not covered by the mask. S5. Remove the first photoresist pattern to form an electroplated gold pattern with a line spacing of CD2; S6. Perform a second photolithography process on the surface of the electroplated gold pattern to form a second photoresist pattern with an opening width of CD3, where CD3 < CD1; S7. Using the second photoresist pattern as a mask, perform an etching process on the seed layer to remove the seed layer area not covered by the mask, forming a seed layer pattern with a line spacing of CD4. S8. Remove the second photoresist pattern to form a metallized structure with a bottom line distance of CD4 and a top line distance of CD2.

2. The method for manufacturing the back metallization structure of a semiconductor device according to claim 1, characterized in that: The semiconductor substrate mentioned in step S1 is a GaAs substrate.

3. The method for manufacturing the back-side metallization structure of a semiconductor device according to claim 1 or 2, characterized in that: The seed layer in step S1 is a Ti / Au or TiW / Au stack, and the thickness of the seed layer is 50nm~400nm.

4. The method for manufacturing the back-side metallization structure of a semiconductor device according to claim 1 or 2, characterized in that: The thickness of the electroplated gold layer formed in step S2 is 2μm~6μm.

5. The method for manufacturing the back-side metallization structure of a semiconductor device according to claim 1 or 2, characterized in that: In step S3, the sidewall angle of the first photoresist pattern is 70°~90°, and the thickness of the first photoresist pattern is 10μm~16μm.

6. The method for manufacturing the back-side metallization structure of a semiconductor device according to claim 1, characterized in that: In step S5, the line spacing CD2 of the electroplated gold pattern is greater than the opening width CD1 of the first photoresist pattern.

7. The method for manufacturing the back-side metallization structure of a semiconductor device according to claim 1 or 2, characterized in that: In step S6, the sidewall angle of the second photoresist pattern is 70°~90°, and the thickness of the second photoresist pattern is 10μm~16μm.

8. The method for manufacturing the back-side metallization structure of a semiconductor device according to claim 1 or 2, characterized in that: In the metallized structure formed in step S8 with a bottom line distance of CD4 and a top line distance of CD2, CD4 > CD2.

9. A back-side metallization structure for a semiconductor device, characterized in that: include: Semiconductor substrate; A metallization structure formed on the back side of the semiconductor substrate; The metallization structure includes a seed layer pattern and an electroplated gold pattern located above the seed layer pattern; wherein the line width of the seed layer pattern is greater than the line width of the electroplated gold pattern.

10. The back-side metallization structure of the semiconductor device according to claim 9, characterized in that: The seed layer pattern is a Ti / Au stack pattern or a TiW / Au stack pattern.

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