Method of processing semiconductor structure and three-dimensional memory

Abstract

The application provides a semiconductor structure processing method and a three-dimensional memory. The semiconductor structure comprises a stack structure, a gate slit structure penetrating through the stack structure and protruding from the stack structure, and a slit between the gate slit structure and the stack structure. The semiconductor structure processing method comprises: forming a dielectric layer in the slit; and forming a semiconductor layer covering the dielectric layer. The semiconductor structure processing method and the three-dimensional memory provided by the application can reduce the risk of short circuit leakage of the semiconductor layer and the gate conductive layer (word line) through the slit, and can save production cost.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to methods for processing semiconductor structures and three-dimensional memories. Background Technology

[0002] In some 3D memory fabrication processes, the channel layer is exposed by removing the substrate and the functional layer of silicon oxide-silicon nitride-silicon oxide (ONO) that extends into the substrate. Further, a semiconductor layer is formed in contact with the exposed channel layer, thereby electrically connecting the channel layer and the semiconductor layer.

[0003] In some practical applications, complex mask patterns are required to avoid adverse effects on structures such as gate gaps during the removal of functional layers from the channel structure. However, this approach is not conducive to saving manufacturing costs and also increases process complexity.

[0004] On the other hand, during the waiting period following the removal of the functional layers of the channel structure, the exposed channel layer may form a native oxide layer. Similarly, the process of removing the native oxide layer may adversely affect, for example, the gate gap structure.

[0005] Therefore, how to address the aforementioned technical problems that arise during the fabrication process of three-dimensional memory is one of the research directions that those skilled in the art are dedicated to. Summary of the Invention

[0006] This application provides a method for processing a semiconductor structure, the semiconductor structure including: a stacked structure, a gate gap structure that penetrates the stacked structure and protrudes from the stacked structure, and a slit located between the gate gap structure and the stacked structure, wherein the method for processing the semiconductor device includes: forming a dielectric layer in the slit; and forming a semiconductor layer covering the dielectric layer.

[0007] In some embodiments, while forming a dielectric layer in the slit, the dielectric layer may cover a first side of the stacked structure, and the portion of the gate slit structure protruding from the stacked structure is located on the first side.

[0008] In some embodiments, the semiconductor structure may further include a channel structure that extends through and protrudes from the stacked structure, wherein a portion of the channel structure protruding from the stacked structure has an outer wall of the channel layer, such that a dielectric layer is formed in the slit while the dielectric layer covers the channel layer, and the portion of the channel structure protruding from the stacked structure is located on a first side.

[0009] In some embodiments, after the step of forming a dielectric layer in the slit, the processing method may include removing the portion of the dielectric layer outside the slit.

[0010] In some implementations, the thickness of the portion of the dielectric layer outside the slit is greater than or equal to 15 nm.

[0011] In some embodiments, prior to the step of forming a dielectric layer in the slit, the processing method may include: removing the native oxide layer located on the channel layer and forming the slit.

[0012] In some embodiments, the material of the dielectric layer may include silicon oxide.

[0013] This application provides a three-dimensional memory, which includes: a stacked structure; a gate gap structure that penetrates the stacked structure and protrudes from the stacked structure; a slit structure located between the gate gap structure and the stacked structure, wherein the slit structure is made of a dielectric material; and a semiconductor layer that covers the slit structure.

[0014] In some embodiments, the dielectric material may include silicon oxide.

[0015] In some embodiments, the three-dimensional memory may further include: a channel structure extending through and protruding beyond the stacked structure, wherein a portion of the channel structure protruding beyond the stacked structure has an outer wall of the channel layer, and a semiconductor layer is in contact with the channel layer.

[0016] According to the semiconductor structure processing method and three-dimensional memory provided in this application, by forming a dielectric layer in the slit, on the one hand, it is beneficial to reduce the risk of short-circuiting and leakage between the semiconductor layer and the gate conductive layer (word line) through the semiconductor material in the slit after the semiconductor layer is formed, thereby improving the yield of the processed semiconductor structure. On the other hand, in the case of exceeding the waiting time, it is compatible with the process of removing the natural oxide layer, which is beneficial to improve the flexibility of the semiconductor structure processing and to save the production cost of semiconductor structure scrapping caused by removing the natural oxide layer. Attached Figure Description

[0017] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0018] Figure 1 It is a cross-sectional schematic diagram of a semiconductor structure based on related technologies;

[0019] Figure 2 This is a cross-sectional schematic diagram of the formation of a natural oxide layer in a semiconductor structure based on relevant technologies;

[0020] Figure 3 This is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of this application;

[0021] Figure 4This is a flowchart of a semiconductor structure processing method according to an embodiment of this application; and

[0022] Figures 5A to 5C This is a schematic cross-sectional view of the process of the semiconductor structure processing method according to the embodiment of the application. Detailed Implementation

[0023] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0024] The terminology used herein is for the purpose of describing particular exemplary embodiments and is not intended to be limiting. When used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” indicate the presence of the stated features, integrals, elements, components, and / or combinations thereof, but do not exclude the presence of one or more other features, integrals, elements, components, and / or combinations thereof.

[0025] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0026] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0027] Figure 1 This is a schematic cross-sectional view of a semiconductor structure 100' according to related technologies. Exemplarily, the semiconductor structure 100' may be an intermediate structure in the fabrication process of a three-dimensional memory, such as a 3D NAND memory. Figure 1 As shown, the semiconductor structure 100' may include a stacked structure 110, a gate gap structure 120, and a channel structure 130.

[0028] In some embodiments, the stacked structure 110 may include a plurality of dielectric layers and a plurality of conductive layers alternately stacked along a first direction D1, such as a gate dielectric layer 111 and a gate conductive layer 112. Optionally, the material of the gate conductive layer 112 may include conductive materials such as tungsten, cobalt, copper, aluminum, or any combination thereof. Optionally, a polysilicon layer 113 may be formed on the first surface 11 of the stacked structure 110.

[0029] In some embodiments, the gate gap structure 120 may extend through the stacked structure 110 along a first direction D1 or in a direction substantially parallel to the first direction D1 and protrude beyond the first surface 11 of the stacked structure 110. Optionally, the gate gap structure 120 may include a conductive layer 121 and an insulating layer 122 located on the outer wall of the conductive layer 121. Optionally, a high dielectric constant layer (not shown) may be located on at least a portion of the outer wall of the gate gap structure 120, such as the outer wall corresponding to the plurality of gate dielectric layers 111 in the stacked structure 110 and the portion of the outer wall protruding beyond the first surface 11 of the stacked structure 110. Optionally, the material of the conductive layer 121 may include conductive materials such as tungsten, cobalt, copper, aluminum, doped polysilicon, or any combination thereof. Optionally, the material of the insulating layer 122 may include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Optionally, the material of the high dielectric constant layer may include high dielectric constant materials such as aluminum oxide, hafnium oxide, tantalum oxide, or any combination thereof.

[0030] In some embodiments, the channel structure 130 may penetrate the stacked structure 110 along a first direction D1 or in a direction substantially parallel to the first direction D1 and protrude beyond the first surface 11 of the stacked structure 110. The portion of the channel structure 130 penetrating the stacked structure 110 may have an outer wall of a functional layer 132 and a channel layer 131, arranged from the outside in. The portion of the channel structure 130 protruding beyond the first surface 11 (e.g., the portion protruding beyond the polysilicon layer 113) may have an outer wall of the channel layer 131. Exemplarily, the functional layer 132 may include a charge blocking layer 1321, a charge trapping layer 1322, and a tunneling layer 1323, arranged from the outside in. Optionally, the materials of the charge blocking layer 1321, the charge trapping layer 1322, and the tunneling layer 1323 may, for example, sequentially comprise silicon oxide, silicon nitride, and silicon oxide. Optionally, the material of the channel layer 131 may, for example, comprise doped polysilicon.

[0031] In some related technologies for processing semiconductor structure 100', the gate gap structure 120 and channel structure 130 in semiconductor structure 100' can be obtained through the process methods described below. Exemplarily, semiconductor structure 100' may include a substrate (not shown) outside the first surface 11 of stacked structure 110, and the initial channel structure (not shown) may have an outer wall of outward-facing functional layer 132 and channel layer 131. A portion of functional layer 132 and channel layer 131 may extend into the substrate. Optionally, a dry or wet etching process may be used to remove the portion of functional layer 132 extending into the substrate, exposing a portion of channel layer 131 protruding from stacked structure 110 (e.g., a portion protruding from polysilicon layer 113) to form a semiconductor layer (not shown) in contact with channel layer 131 in subsequent processes. However, during the process of removing the portion of the functional layer 132 that extends into the substrate, the etching material (e.g., etching gas) may cause a divot between the gate divot structure 120 and, for example, the high dielectric constant layer and the stacked structure 110. In other words, the divot may be located between the gate divot structure 120 and the stacked structure 110.

[0032] In some practical processes, Figure 2 The diagram shows a native oxide layer 141 formed on a channel layer 131 after a portion of the functional layer 132 has been removed from the semiconductor structure 100'. Figure 3 The semiconductor structure 100' formed after removing the native oxide layer 141 is shown. For example... Figure 2 and Figure 3 As shown, the risk of native oxide 141 forming on the exposed channel layer 131 after substrate removal can be reduced by controlling the waiting time (Q-time, e.g., less than 3.5 hours) between the removal of functional layer 132 and the formation of semiconductor layer. Optionally, if a polysilicon layer 113 is formed on the first surface 11 of stacked structure 110, native oxide 141 may also be formed on the polysilicon layer 113, and the thickness of native oxide 141 may be, for example, about 1 nm to 2 nm. If native oxide 141 has been formed, it can be removed from the channel layer 131 by, for example, a hydrofluoric acid solution. However, during the process of removing native oxide 141, a slit 142 may be generated between, for example, a high-dielectric-constant layer and the stacked structure 110 on both sides of the gate gap structure 120.

[0033] As described above, if a slit has already been formed during the process of removing a portion of the functional layer 132, the formation of the native oxide layer 141 due to exceeding the waiting time and the subsequent removal of the native oxide layer 141 may cause the slit 142 to expand. Exemplarily, the slit 142 may extend into the gate conductive layer 112, causing semiconductor material to fill the slit 142 and contact the gate conductive layer 112 during subsequent semiconductor layer formation processes. This could result in short-circuiting leakage between the semiconductor layer and the gate conductive layer 112 (i.e., the word line) through the semiconductor material filling the slit. Optionally, the dimension of the slit 142 in the direction parallel to the first surface 11 of the stacked structure 110 and perpendicular to the gate gap structure 120 is approximately 20 nm, and the dimension of the slit 142 in the first direction D1 is approximately 100 nm.

[0034] The semiconductor structure 100 processing method of the present application embodiment can at least partially solve the technical problem of short-circuiting and leakage between the semiconductor layer and the gate conductive layer (i.e., word line) through the semiconductor material filled in the slit. Figure 4 This is a flowchart of a processing method 1000 for a semiconductor structure 100 according to an embodiment of this application. For example... Figure 4 As shown, the processing method 1000 of the semiconductor structure 100 may include: S110, forming a dielectric layer in the slit; and S120, forming a semiconductor layer covering the dielectric layer.

[0035] Figures 5A to 5C This is a schematic cross-sectional view of the process of the semiconductor structure 100 according to an embodiment of this application. The following will be combined with... Figures 5A to 5C The processing method 1000 of the embodiments of this application is described in detail.

[0036] In step S110, as Figure 5A As shown, in some embodiments, thin film deposition processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination thereof can be used to deposit thin films on slit 142 (see reference 142). Figure 3 A dielectric layer 151 is formed in the slit 142. Optionally, during the process of forming the dielectric layer 151 in the slit 142, the dielectric layer 151 may be formed on the surface of the channel layer 131 that protrudes beyond a portion of the stacked structure 100 (e.g., the portion protruding beyond the polysilicon layer 113). Optionally, during the process of forming the dielectric layer 151 in the slit 142, the dielectric layer 151 may be formed on a first side of the stacked structure 110 (e.g., the surface of the polysilicon layer 113). Optionally, the material of the dielectric layer 151 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Optionally, such as Figure 5BAs shown, the portion of the dielectric layer 151 located outside the slit 142, such as the portion of the dielectric layer 151 located on the surface of the channel layer 131 and / or the portion on the surface of the polysilicon layer 113, can be removed using, for example, dry or wet etching processes. Optionally, during the process of forming the dielectric layer 151, the thickness of the portion of the dielectric layer 151 located outside the slit 142, such as the portion of the dielectric layer 151 located on the surface of the channel layer 131 and / or the portion on the surface of the polysilicon layer 113, can be greater than or equal to 15 nm. This facilitates control over the process (e.g., etching process) for removing the portion of the dielectric layer 151 located outside the slit 142, thereby reducing the risk of etching and creating a slit between the channel structure 130 and the stacked structure 110 during the process of removing the portion of the dielectric layer 151 located outside the slit 142. Alternatively, if the material of the dielectric layer 151 is silicon oxide, the portion of the dielectric layer 151 located outside the slit 142 can be removed using, for example, a hydrofluoric acid solution.

[0037] In some embodiments, the dielectric layer 151 may be filled in the slit 142 without being formed outside the slit 142, for example, by controlling the thin film deposition process (e.g., the surface of the dielectric layer 151 located in the portion of the channel layer 131 and / or the surface of the portion of the polysilicon layer 113).

[0038] In step S120, as Figure 5C As shown, the semiconductor layer 152 covering the dielectric layer 151 in the slit 142 can be formed using thin film deposition processes such as PVD, CVD, ALD, or any combination thereof. Optionally, during the process of forming the semiconductor layer 152 covering the dielectric layer 151 in the slit 142, the semiconductor layer 152 can be made to contact the channel layer 131, for example, by making the semiconductor layer 152 cover the surface of the polysilicon layer 113 and surround the gate gap structure 120 and the portion of the channel structure 130 protruding from the polysilicon layer 113. Optionally, the material of the semiconductor layer 152 may include, for example, polysilicon.

[0039] In some embodiments, when the semiconductor layer 152 is made of polycrystalline silicon, the semiconductor layer 152 can be fabricated using the methods described below. First, an amorphous silicon layer (not shown) covering the dielectric layer 151 can be formed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. Further, the amorphous silicon can be crystallized into polycrystalline silicon using, for example, a laser annealing process to form the semiconductor layer 152.

[0040] According to the semiconductor structure processing method provided in this application, by forming a dielectric layer in the slit, on the one hand, it is beneficial to reduce the risk of short-circuiting and leakage between the semiconductor layer and the gate conductive layer (word line) through the semiconductor material in the slit after the semiconductor layer is formed, thereby improving the yield of the processed semiconductor structure. On the other hand, in the case of exceeding the waiting time, it is compatible with the process of removing the natural oxide layer, which is beneficial to improve the flexibility of the semiconductor structure processing and to save the production cost of semiconductor structure scrapping caused by removing the natural oxide layer.

[0041] Another aspect of this application provides a three-dimensional memory, which may include: a stacked structure, a gate gap structure, a slit structure, and a semiconductor layer.

[0042] The gate gap structure penetrates and protrudes from the stacked structure. A slit structure is located between the gate gap structure and the stacked structure, and its material is a dielectric material. A semiconductor layer covers the slit structure.

[0043] In some embodiments, the dielectric material includes silicon oxide.

[0044] In some embodiments, the three-dimensional memory further includes a channel structure. The channel structure extends through and protrudes beyond the stacked structure, wherein a portion of the channel structure protruding beyond the stacked structure includes the outer wall of the channel layer, and a semiconductor layer contacts the channel layer.

[0045] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated.

[0046] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for processing a semiconductor structure, characterized in that, The semiconductor structure includes a stacked structure, a gate gap structure that penetrates the stacked structure and protrudes from the stacked structure, and a slit located between the gate gap structure and the stacked structure, wherein the processing method includes: A dielectric layer is formed in the slit; and A semiconductor layer is formed covering the dielectric layer.

2. The processing method according to claim 1, characterized in that, While forming the dielectric layer in the slit, the dielectric layer covers a first side of the stacked structure, and the portion of the gate slit structure protruding from the stacked structure is located on the first side.

3. The processing method according to claim 1, characterized in that, The semiconductor structure further includes a channel structure that extends through and protrudes from the stacked structure, wherein a portion of the channel structure protruding from the stacked structure has an outer wall of a channel layer, and the dielectric layer is formed in the slit such that the dielectric layer covers the channel layer, and the portion of the channel structure protruding from the stacked structure is located on a first side of the stacked structure.

4. The processing method according to claim 2 or 3, characterized in that, After the step of forming a dielectric layer in the slit, the processing method further includes: Remove the portion of the dielectric layer located outside the slit.

5. The processing method according to claim 2 or 3, characterized in that, The thickness of the portion of the dielectric layer outside the slit is greater than or equal to 15 nm.

6. The processing method according to claim 3, characterized in that, Prior to the step of forming a dielectric layer in the slit, the processing method includes: Remove the natural oxide layer located on the channel layer and form the slit.

7. The processing method according to claim 1, characterized in that, The dielectric layer is made of silicon oxide.

8. A three-dimensional memory, characterized in that, include: Layered structure; A gate gap structure that penetrates the stacked structure and protrudes from the stacked structure; A slit structure is located between the gate slit structure and the stacked structure, and the material of the slit structure is a dielectric material; as well as A semiconductor layer covers the slit structure.

9. The three-dimensional memory according to claim 8, characterized in that, The dielectric material includes silicon oxide.

10. The three-dimensional memory according to claim 8, characterized in that, The three-dimensional memory also includes: A channel structure extends through and protrudes from the stacked structure, wherein a portion of the channel structure protruding from the stacked structure has an outer wall of a channel layer, and the semiconductor layer is in contact with the channel layer.

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