Display device

Abstract

A display device is provided. The display device includes: a substrate defining a plurality of sub-pixels; a plurality of light-emitting diodes disposed in the plurality of sub-pixels, the plurality of light-emitting diodes having an organic layer shared between the plurality of light-emitting diodes and a cathode electrode shared between the plurality of light-emitting diodes; a bank disposed between pairs of light-emitting diodes in the plurality of light-emitting diodes and below the cathode electrodes; a plurality of wirings disposed between the bank and the substrate; and a first pattern extending through a thickness of the bank and overlapping with a first wiring in the plurality of wirings, wherein a first portion of the cathode electrode is disposed outside the first pattern, and a second portion of the cathode electrode is disposed within the first pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0056145 filed on May 11, 2020, in the Korean Intellectual Property Office, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device that can improve color mixing of light emitted from a plurality of light emitting diodes. Background Art

[0004] Currently, as technology enters the comprehensive information age, the field of display devices that visually express electrical information signals has rapidly developed, and research continues to improve performance of various display devices, such as thin thickness, light weight, and low power consumption.

[0005] Among various types of display devices, light-emitting display devices, such as organic display devices, are self-luminous, eliminating the need for a separate light source, unlike liquid crystal display devices. Consequently, light-emitting display devices can be manufactured to be lightweight and thin. Furthermore, since light-emitting display devices operate at low voltage, they offer advantages not only in terms of power consumption but also in terms of color realization, response speed, viewing angle, and contrast. Consequently, light-emitting display devices are being researched as next-generation displays. Summary of the Invention

[0006] One object to be achieved by the present disclosure is to provide a display device that can reduce leakage current when the display device is driven.

[0007] Another object to be achieved by the present disclosure is to provide a display device that reduces emission due to leakage current of some light emitting diodes among a plurality of light emitting diodes having a common layer.

[0008] Yet another object to be achieved by the present disclosure is to provide a display device that improves the display quality of low grayscale images.

[0009] The objects of the present disclosure are not limited to the above-mentioned objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0010] According to one aspect of the present disclosure, a display device includes: a substrate defining a plurality of sub-pixels; a plurality of light-emitting diodes disposed in the plurality of sub-pixels, the plurality of light-emitting diodes having an organic layer shared between the plurality of light-emitting diodes and a cathode electrode shared between the plurality of light-emitting diodes; a bank disposed between pairs of light-emitting diodes in the plurality of light-emitting diodes and below the cathode electrodes; a plurality of wirings disposed between the bank and the substrate; and a first pattern extending through a thickness of the bank and overlapping with a first wiring in the plurality of wirings, wherein a first portion of the cathode electrode is disposed outside the first pattern and a second portion of the cathode electrode is disposed within the first pattern. Consequently, the length of the cathode electrode and the organic layer in the first pattern increases, thereby increasing the length of a path through which leakage current flows, which can reduce degradation of display quality due to the leakage current.

[0011] In one embodiment, a display device includes: a substrate in which a plurality of sub-pixels are defined; a plurality of light-emitting diodes, the plurality of light-emitting diodes being arranged in the plurality of sub-pixels, the plurality of light-emitting diodes having an organic layer shared between the plurality of light-emitting diodes and a cathode electrode shared between the plurality of light-emitting diodes; a dam, the dam being arranged between pairs of light-emitting diodes among the plurality of light-emitting diodes and below the cathode electrode; and a wiring, the wiring being arranged between the dam and the substrate, wherein a first portion of the cathode electrode overlapping with the wiring is closer to the wiring than a second portion of the cathode electrode not overlapping with the wiring.

[0012] Additional details of exemplary embodiments are included in the detailed description and the accompanying drawings.

[0013] According to the present disclosure, leakage of current passing through a common layer of a plurality of light emitting diodes can be improved.

[0014] According to the present disclosure, when a display device is driven, undesired emission of a light emitting diode is reduced to improve color reproduction rate.

[0015] According to the present disclosure, when displaying an image with a low grayscale level, display quality can be improved by minimizing visual recognition of dots or color abnormalities.

[0016] The effects according to the present disclosure are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure.

[0019] Figure 2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0020] Figure 3A is an enlarged plan view of a display device according to an exemplary embodiment of the present disclosure.

[0021] Figure 3B According to an exemplary embodiment of the present disclosure Figure 3A Cross-sectional view taken along IIIb-IIIb'.

[0022] Figure 4 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure.

[0023] Figure 5 is a cross-sectional view of a display device according to still another exemplary embodiment of the present disclosure.

[0024] Figure 6 is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure.

[0025] Figure 7A is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure.

[0026] Figure 7B According to one embodiment, Figure 7A VIIb-VIIb' cross-sectional view.

[0027] Figure 8 is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure.

[0028] Figure 9 is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure.

[0029] Figure 10A is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure.

[0030] Figure 10B According to one embodiment, Figure 10A A cross-sectional view of the display device taken along line Xb-Xb'.

[0031] Figure 11 is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure.

[0032] Figure 12 is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure.

[0033] Figure 13 is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The advantages and features of the present disclosure and the methods for achieving these advantages and features will become clear by reference to the exemplary embodiments described in detail below and the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure and scope of the present disclosure. Therefore, the present disclosure will be limited only by the scope of the appended claims.

[0035] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, detailed descriptions of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including," "having," and "comprising" used herein are generally intended to allow the addition of other components unless the term is used together with the term "only." Unless expressly stated otherwise, any reference to the singular may include the plural.

[0036] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0037] When terms such as "on," "above," "below," and "near" are used to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless the terms are used with the terms "immediately" or "directly."

[0038] When an element or layer is referred to as being “on” another element or layer, the element or layer may be directly on the other element or layer, or other layers or other elements may be interposed therebetween.

[0039] Although the terms "first," "second," and the like are used to describe various components, these components are not limited to these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of the present disclosure, the first component to be mentioned below may be the second component.

[0040] Throughout the specification, like reference numerals generally refer to like elements.

[0041] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the illustrated sizes and thicknesses of the components.

[0042] The features of the various embodiments of the present disclosure may be partially or entirely appended to or combined with each other, and may be technically interlocked and operated in various ways, and the embodiments may be performed independently of each other or in association with each other.

[0043] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0044] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 1 , for convenience of description, among various components of the display device 100, the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC are illustrated.

[0045] Reference Figure 1 The display device 100 includes a display panel PN having a plurality of sub-pixels SP, a gate driver GD and a data driver DD providing various signals to the display panel PN, and a timing controller TC controlling the gate driver GD and the data driver DD.

[0046] The gate driver GD provides a plurality of scan signals to the plurality of scan lines SL according to a plurality of gate control signals GCS provided from the timing controller TC. The plurality of scan signals may include a first scan signal SCAN1 and a second scan signal SCAN2. Figure 1 In the embodiment, one gate driver GD is disposed to be spaced apart from one side of the display panel PN, however the gate driver GD may be disposed in a gate-in-panel (GIP) manner, and the number of the gate drivers GD and the arrangement thereof are not limited thereto.

[0047] The data driver DD converts the image data RGB input from the timing controller TC into data voltages using reference gamma voltages according to a plurality of data control signals DCS provided from the timing controller TC. In addition, the data driver DD may provide the converted data voltages to a plurality of data lines DL.

[0048] The timing controller TC aligns externally input image data (RGB) to provide the image data to the data driver DD. The timing controller TC generates a gate control signal GCS and a data control signal DCS using externally input synchronization signals (SYNC), such as a dot clock signal, a data enable signal, and horizontal / vertical synchronization signals. Furthermore, the timing controller TC provides the generated gate control signal GCS and data control signal DCS to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0049] The display panel PN displays an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL intersect each other, and the plurality of sub-pixels SP are connected to the scan lines SL and the data lines DL, respectively. Although not shown in the drawings, the plurality of sub-pixels SP may be connected to a high-potential power line, a low-potential power line, an initialization signal line, and an emission control signal line.

[0050] The sub-pixel SP is the smallest unit constituting the screen, and each of the plurality of sub-pixels SP may include a light-emitting diode and a driving circuit for driving the light-emitting diode. The plurality of light-emitting diodes may be defined in different ways according to the type of the display panel PN. For example, when the display panel PN is an organic light-emitting display panel, the light-emitting diode may be an organic light-emitting diode including an anode, an organic layer, and a cathode. In addition, as the light-emitting diode, a quantum dot light-emitting diode (QLED) including quantum dots (QD) may also be used. In the following, although the light-emitting diode will be described under the assumption that the light-emitting diode is an organic light-emitting diode, the type of the light-emitting diode is not limited thereto.

[0051] The pixel circuit is a circuit for controlling the driving of the light emitting diode. For example, the pixel circuit may be configured to include a capacitor and a plurality of transistors, but is not limited thereto.

[0052] In the following, reference will be made to Figure 2 The pixel circuit of the sub-pixel SP is described in more detail.

[0053] Figure 2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0054] Reference Figure 2 , the pixel circuits of the plurality of sub-pixels SP include first to sixth transistors T1 , T2 , T3 , T4 , T5 , and T6 and a capacitor Cst.

[0055] The first transistor T1 is connected to the second scan line to be controlled by the second scan signal SCAN2 provided through the second scan line. In addition, the first transistor T1 can be electrically connected between the data line providing the data voltage Vdata and the capacitor Cst. When the second scan signal SCAN2 of the on-level is applied to the first transistor T1 through the second scan line, the first transistor T1 transmits the data voltage Vdata from the data line to the capacitor Cst. The first transistor T1 can be referred to as a switching transistor, which controls the timing of applying the data voltage Vdata to the capacitor Cst.

[0056] The second transistor T2 may be electrically connected between a high-potential power line supplied with a high-potential power signal EVDD and the fifth transistor T5. Furthermore, a gate electrode of the second transistor T2 may be electrically connected to a capacitor Cst. The second transistor T2 may be referred to as a drive transistor, and controls the current flowing through the light-emitting diode 120 according to a voltage applied to its gate electrode to control the brightness of the light-emitting diode 120.

[0057] The third transistor T3 may be controlled by a first scan signal SCAN1 provided through a first scan line. Depending on the types of the second transistor T2 and the third transistor T3, the third transistor T3 may be electrically connected between the gate electrode and the drain electrode or between the gate electrode and the source electrode of the second transistor T2.

[0058] The second transistor T2, serving as a driving transistor, is required to control the current flowing through the light-emitting diode 120 according to the data voltage Vdata applied to the sub-pixel SP. However, a threshold voltage deviation of the second transistor T2 provided in each sub-pixel SP may cause a brightness deviation of the light-emitting diode 120 provided in each sub-pixel SP.

[0059] At this time, the third transistor T3 is configured to compensate for the threshold voltage deviation of the second transistor T2, so that the third transistor T3 can be referred to as a compensation transistor. For example, when the first scan signal SCAN1 is applied to turn on the third transistor T3, a voltage obtained by subtracting the threshold voltage of the second transistor T2 from the high-potential power signal EVDD is applied to the gate electrode of the second transistor T2. In addition, in a state in which the high-potential power signal EVDD from which the threshold voltage is subtracted is applied to the gate electrode of the second transistor T2, the data voltage Vdata is applied to the capacitor Cst to compensate for the threshold voltage deviation of the second transistor T2.

[0060] In the embodiment, different scan signals SCAN1 and SCAN2 are applied to the third transistor T3 and the first transistor T1 from different scan lines. However, the third transistor T3 and the first transistor T1 may be connected to the same scan line and may be applied with the same scan signals SCAN1 and SCAN2, and are not limited thereto.

[0061] The fourth transistor T4 can be electrically connected to the capacitor Cst and an initialization signal line supplied with the initialization signal Vini. Furthermore, the fourth transistor T4 can be controlled by an emission control signal EM supplied via an emission control signal line. When an emission control signal EM of a conduction level is supplied via the emission control signal line, the fourth transistor T4 can initialize the voltage of the capacitor Cst or slowly discharge the data voltage Vdata supplied to the capacitor Cst to allow a current corresponding to the data voltage Vdata to flow through the light-emitting diode 120.

[0062] The fifth transistor T5 is electrically connected between the second transistor T2 and the light emitting diode 120 and can be controlled by an emission control signal EM provided via an emission control signal line. The fifth transistor T5 is turned on when the emission control signal EM is applied at a conduction level in the following state: the data voltage Vdata is applied to the capacitor Cst, and the high-potential power signal EVDD, in which the threshold voltage is compensated, is applied to the gate electrode of the second transistor T2. Therefore, current can flow through the light emitting diode 120.

[0063] The sixth transistor T6 is electrically connected between an initialization signal line to which the initialization signal Vini is supplied and an anode of the light-emitting diode 120, and is controlled by a first scan signal SCAN1 supplied via a first scan line. When the first scan signal SCAN1 of a turn-on level is supplied via the first scan line, the sixth transistor T6 may initialize the anode of the light-emitting diode 120 or a node between the second transistor T2 and the fifth transistor T5 using the initialization signal Vini.

[0064] The capacitor Cst may be a storage capacitor that stores a voltage applied to the gate electrode of the second transistor T2 serving as a driving transistor. Here, the capacitor Cst is electrically connected between the gate electrode of the second transistor T2 and the anode of the light-emitting diode 120. Therefore, the capacitor Cst may store a difference between the voltage of the gate electrode of the second transistor T2 and the voltage applied to the anode of the light-emitting diode 120.

[0065] In the following, reference will be made to Figure 3A and Figure 3B The sub-pixel SP of the display device 100 according to an exemplary embodiment of the present disclosure is described in more detail.

[0066] Figure 3A is an enlarged plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 3B According to one embodiment, Figure 3A The cross-sectional view taken along IIIb-IIIb' is shown. Figure 3A and Figure 3B The display device 100 according to the exemplary embodiment of the present disclosure includes a substrate 110, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, a passivation layer 114, a planarization layer 115, a bank 116, a high potential power line PL, a plurality of scan lines SL, a data line DL, an initialization signal line IL, an emission control signal line EL, a fifth transistor T5, a light emitting diode 120, a spacer 130, and a plurality of first patterns 140. Figure 3A In the embodiment, for the convenience of description, only the anode 121 of the light emitting diode 120 is shown. Figure 3B, for convenience of description, only the capacitor Cst of the pixel circuit and the fifth transistor T5 of the plurality of transistors T1 , T2 , T3 , T4 , T5 , and T6 are shown.

[0067] Reference Figure 3A , the plurality of sub-pixels SP are individual units that emit light, and a corresponding light-emitting diode 120 is provided in each of the plurality of sub-pixels SP. The plurality of sub-pixels SP include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 that emit light of different colors. For example, the first sub-pixel SP1 is a blue sub-pixel, the second sub-pixel SP2 is a green sub-pixel, and the third sub-pixel SP3 is a red sub-pixel.

[0068] The plurality of first sub-pixels SP1 may be arranged to form a plurality of columns. That is, the plurality of first sub-pixels SP1 may be arranged on the same column. In addition, in one embodiment, the plurality of second sub-pixels SP2 and the plurality of third sub-pixels SP3 may be arranged between the plurality of columns on which the plurality of first sub-pixels are arranged. For example, the plurality of first sub-pixels SP1 may be arranged on one column, and the second sub-pixels SP2 and the third sub-pixels SP3 may be arranged together on adjacent columns. In addition, the plurality of second sub-pixels SP2 and the plurality of third sub-pixels SP3 may be alternately arranged on the same column. In this specification, it is described that the plurality of sub-pixels SP include the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. However, the arrangement, number, and color combination of the plurality of sub-pixels SP may vary in various ways according to the design and are not limited thereto.

[0069] High-potential power lines PL extending in the column direction are provided between the plurality of sub-pixels SP. The plurality of high-potential power lines PL are wirings that transmit a high-potential power signal EVDD to each of the plurality of sub-pixels SP. Each of the plurality of high-potential power lines PL can be provided between the first sub-pixel SP1 and the second sub-pixel SP2, and between the first sub-pixel SP1 and the third sub-pixel SP3.

[0070] Similar to the multiple high-potential power lines PL, multiple data lines DL are arranged to extend along the column direction. The multiple data lines DL are wirings that transmit the data voltage Vdata to the multiple sub-pixels SP. Each of the multiple data lines DL can be arranged between the second sub-pixel SP2 and the high-potential power line PL, and between the third sub-pixel SP3 and the high-potential power line PL. However, the multiple data lines DL can also be arranged between the multiple high-potential power lines PL and the first sub-pixel SP, but are not limited thereto.

[0071] A plurality of scan lines SL extending in the row direction are provided. The plurality of scan lines SL are wirings that transmit scan signals SCAN1 and SCAN2 to the plurality of sub-pixels SP. The plurality of scan lines SL include a first scan line SL1 and a second scan line SL2. The first scan line SL1 is provided to extend in the row direction between the second sub-pixel SP2 and the third sub-pixel SP3, and the second scan line SL2 may be provided to extend in the row direction across the second sub-pixel SP2.

[0072] Similar to the multiple scan lines SL, multiple initialization signal lines IL extending along the row direction are arranged between the multiple sub-pixels SP. The multiple initialization signal lines IL are wirings that transmit the initialization signal Vini to the multiple sub-pixels SP. The multiple initialization signal lines IL can be arranged between the second sub-pixel SP2 and the third sub-pixel SP3. The multiple initialization signal lines IL can also be arranged between the first scan line SL1 and the second scan line SL2.

[0073] Similar to the plurality of scan lines SL, the plurality of emission control signal lines EL are arranged to extend in the row direction. The plurality of emission control signal lines EL are wirings that transmit emission control signals EM to the plurality of sub-pixels SP. The plurality of emission control signal lines EL may be arranged adjacent to the plurality of second scan lines SL2. The plurality of emission control signal lines EL may be arranged to extend in the row direction across the second sub-pixels SP2. The second scan lines SL2 may be arranged between the plurality of emission control signal lines EL and the plurality of initialization signal lines IL.

[0074] At the same time, the plurality of wirings can be classified into DC lines that transmit direct current (DC) signals and AC lines that transmit alternating current (AC) signals. Among the plurality of wirings, the high-potential power line PL and the initialization signal line IL that transmit the high-potential power signal EVDD and the initialization signal Vini as DC signals can be included in the DC lines. In addition, among the plurality of wirings, the scan lines SL and the data lines DL that transmit the scan signals SCAN1 and SCAN2 and the data voltage Vdata as AC signals can be included in the AC lines.

[0075] A plurality of spacers 130 are provided between the plurality of sub-pixels SP. When forming the light-emitting diodes 120 in the plurality of sub-pixels SP, a fine metal mask (FMM) may be used as a deposition mask. In this case, the plurality of spacers 130 may be provided to suppress damage that may occur due to contact with the deposition mask and to maintain a predetermined distance between the deposition mask and the substrate 110.

[0076] The plurality of first patterns 140 are disposed between the plurality of sub-pixels SP. At least a portion of the plurality of first patterns 140 may be disposed to overlap a DC line transmitting a DC signal among the plurality of wirings.

[0077] The plurality of first patterns 140 include a first portion 141 and a second portion 142. The first portion 141 extends along the column direction between the plurality of sub-pixels SP. The first portion 141 may extend along the column direction between the first sub-pixel SP1 and the second sub-pixel SP2, and between the first sub-pixel SP1 and the third sub-pixel SP3. Furthermore, at least a portion of the first portion 141 may overlap with a DC line extending along the column direction. For example, the first portion 141 extends along the column direction to overlap the high-potential power line PL, which serves as the DC line.

[0078] The second portion 142 is a portion extending in the row direction between the plurality of sub-pixels SP. The second portion 142 may be a portion extending in the row direction between the second sub-pixel SP2 and the third sub-pixel SP3, and between the first sub-pixel SP1 and the first sub-pixel SP1. In this case, the second portion 142 may extend in the row direction from the first portion 141, or may be provided separately from the first portion 141. In addition, at least a portion of the second portion 142 may overlap with a DC line extending in the row direction. For example, at least a portion of the second portion 142 extending in the row direction may be provided to overlap the initialization signal line IL, which serves as the DC line.

[0079] By providing the plurality of first patterns 140 to overlap the DC line between the plurality of sub-pixels SP, leakage current from the plurality of light emitting diodes 120 can be reduced, which will be referred to as Figure 3B Describe in more detail.

[0080] Reference Figure 3B The substrate 110 is a supporting member for supporting other components of the display device 100 and may be configured from an insulating material. For example, the substrate 110 may be formed from glass or resin. In addition, the substrate 110 may be configured to include plastic such as a polymer or polyimide (PI), or may be formed from a flexible material.

[0081] A buffer layer 111 is provided on the substrate 110. The buffer layer 111 can reduce the penetration of moisture or impurities from the substrate 110. The buffer layer 111 can be configured as a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto. However, depending on the type of substrate 110 or the type of transistor, the buffer layer 111 can be omitted, but is not limited thereto.

[0082] A fifth transistor T5 is disposed on the buffer layer 111. The fifth transistor T5 includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0083] The active layer ACT may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto. For example, when the active layer ACT is formed of an oxide semiconductor, the active layer ACT is formed of a channel region, a source region, and a drain region, and the source region and the drain region may be conductive regions, but are not limited thereto.

[0084] A gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer that insulates the active layer ACT from the gate electrode GE and may be configured of a single layer or double layers of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto.

[0085] A gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0086] An interlayer insulating layer 113 is provided on the gate electrode GE. In the interlayer insulating layer 113, contact holes are formed, through which the source electrode SE and the drain electrode DE are connected to the active layer ACT. The interlayer insulating layer 113 may be configured of a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto.

[0087] A source electrode SE and a drain electrode DE are provided on the interlayer insulating layer 113. The source electrode SE and the drain electrode DE, which are provided to be spaced apart from each other, may be electrically connected to the active layer ACT. The source electrode SE and the drain electrode DE may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0088] A high-potential power line PL and a data line DL are provided on the interlayer insulating layer 113. The high-potential power line PL and the data line DL are provided on the same layer as the source electrode SE and the drain electrode DE and are formed of the same conductive material, but are not limited thereto. For example, the high-potential power line PL and the data line DL may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0089] A passivation layer 114 is provided on the high-potential power line PL, the data line DL, the source electrode SE, and the drain electrode DE. The passivation layer 114 is an insulating layer for protecting components below the passivation layer 114. For example, the passivation layer 114 may be configured with a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto. In addition, according to exemplary embodiments, the passivation layer 114 may be omitted.

[0090] A planarization layer 115 is provided on the passivation layer 114. The planarization layer 115 is an insulating layer that planarizes the upper portion of the substrate 110. The planarization layer 115 may be formed of an organic material and, for example, may be configured of a single layer or double layers of polyimide or photoacrylic, but is not limited thereto.

[0091] A light emitting diode 120 is provided in each of the plurality of sub-pixels SP and on the planarization layer 115. The light emitting diode 120 includes an anode (anode electrode) 121, an organic layer 122, and a cathode (cathode electrode) 123.

[0092] The anode 121 is provided on the planarization layer 115. The anode 121 is electrically connected to the transistors of the pixel circuit, such as the second transistor T2 and the fifth transistor T5, so as to be provided with a driving current. The anode 121 provides holes to the organic layer 122, so that the anode 121 can be formed of a conductive material having a high work function. For example, the anode 121 can be formed of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO), but is not limited thereto.

[0093] Among them, the display device 100 can be implemented as a top emission type or a bottom emission type. When the display device 100 is a top emission type, a reflective layer formed of a metal material with excellent reflection efficiency such as aluminum (Al) or silver (Ag) can be added under the anode 121. Therefore, the light emitted from the organic layer 122 is reflected from the anode 121 to be directed to the upper direction, that is, the cathode 123. In contrast, when the display device 100 is a bottom emission type, the anode 121 can be formed only of a transparent conductive material. Hereinafter, the display device 100 according to the exemplary embodiment of the present disclosure will be described under the assumption that it is a top emission type.

[0094] A bank 116 is provided on the anode 121 and the planarization layer 115. The bank 116 is an insulating layer provided between the plurality of sub-pixels SP to partition the plurality of sub-pixels SP. The bank 116 includes an opening that exposes a portion of the anode 121. The bank 116 may be an organic insulating material provided to cover the edge or boundary of the anode 121. For example, the bank 116 may be formed of a polyimide resin, an acrylic resin, or a benzocyclobutene (BCB)-based resin, but is not limited thereto.

[0095] Spacers 130 are provided on the bank 116. Spacers 130 are provided on the bank 116 to maintain a predetermined distance from the deposition mask when forming the light-emitting diode 120. Spacers 130 can maintain a predetermined distance between the deposition mask, the bank 116 below the spacers 130, and the anode 121, thereby preventing damage caused by contact. In this case, the plurality of spacers 130 can be formed to have a shape that narrows toward the top, such as a tapered shape, to reduce the area in contact with the deposition mask.

[0096] An organic layer 122 is provided on the anode 121, the bank 116, and the spacer 130. The organic layer 122 includes a light-emitting layer and a common layer. The light-emitting layer is an organic layer that emits light of a specific color, so that different light-emitting layers can be provided on the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, or the same light-emitting layer can be provided on all of the multiple sub-pixels SP. For example, when different light-emitting layers are provided on the multiple sub-pixels SP, a blue light-emitting layer is provided in the first sub-pixel SP1, a green light-emitting layer is provided in the second sub-pixel SP2, and a red light-emitting layer can be provided in the third sub-pixel SP3. In addition, the light-emitting layers of the multiple sub-pixels SP are connected to each other to form a single layer over the multiple sub-pixels SP. For example, the light-emitting layer is provided on all of the multiple sub-pixels SP, and the light from the light-emitting layer can be converted into light of various colors with the help of a separate light conversion layer, color filter, etc.

[0097] In addition, multiple light-emitting layers emitting light of the same color may be laminated on one sub-pixel SP. For example, two blue light-emitting layers may be laminated on the first sub-pixel SP1, two green light-emitting layers may be laminated on the second sub-pixel SP2, and two red light-emitting layers may be laminated on the third sub-pixel SP3. In this case, a charge generation layer CGL (not shown) is provided between the multiple light-emitting layers to smoothly supply electrons or holes to each of the multiple light-emitting layers. In other words, the charge generation layer may be provided between the two blue light-emitting layers, between the two green light-emitting layers, and between the two red light-emitting layers.

[0098] In addition, multiple light-emitting layers emitting different colors of light may be laminated on a single sub-pixel SP. For example, a blue light-emitting layer and a yellow-green light-emitting layer may be laminated on all of the multiple sub-pixels SP, so that all of the multiple sub-pixels SP can emit white light. In this case, a charge generation layer may be provided between the blue light-emitting layer and the yellow-green light-emitting layer.

[0099] The common layer is a portion of the organic layer 122 that is provided to improve the emission efficiency of the light-emitting layer. The common layer may be formed as a single layer over the plurality of sub-pixels SP. In other words, the common layers of the plurality of sub-pixels SP are connected to form an integral structure. The common layer may include at least one of a charge generation layer, a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer, but is not limited thereto.

[0100] A cathode 123 is provided on the organic layer 122. The cathode 123 provides electrons to the organic layer 122, so that the cathode 123 can be formed of a conductive material having a low work function. The cathode 123 can be formed into a layer over the plurality of sub-pixels SP. That is, the cathodes 123 of the plurality of sub-pixels SP are connected to be formed integrally. For example, the cathode 123 can be formed of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO) or a metal alloy such as MgAg or ytterbium (Yb) alloy, and may also include a metal doping layer, but is not limited thereto. Although not shown in the figure, the cathode 123 is electrically connected to the low potential power line to be provided with a low potential power signal EVSS (see Figure 2 ).

[0101] A plurality of first patterns 140 are provided in the bank 116. The plurality of first patterns 140 may be grooves formed between the plurality of sub-pixels SP and in the bank 116. The plurality of first patterns 140 may be grooves formed from the bank 116 to the planarization layer 115 below the bank 116. However, the plurality of first patterns 140 may be formed only in the bank 116, but is not limited thereto. In addition, although Figure 3B , the plurality of first patterns 140 are shown to be V-shaped grooves; however, the plurality of first patterns 140 may be formed in various shapes, but is not limited thereto.

[0102] At least some of the plurality of first patterns 140 may be disposed to overlap with the plurality of wirings. For example, at least some of the plurality of first patterns 140 may be disposed to overlap with a DC line such as a high potential power line PL among the plurality of wirings.

[0103] The common layer of the plurality of light-emitting diodes 120 may be formed as a layer above all of the plurality of sub-pixels SP. In this case, since the light-emitting diodes 120 of the plurality of sub-pixels SP are formed to share a common layer, when the light-emitting diode 120 of a particular sub-pixel SP emits light, current may flow to the light-emitting diode 120 of an adjacent sub-pixel SP, a phenomenon known as current leakage. This current leakage phenomenon causes the light-emitting diode 120 of an undesired sub-pixel SP to emit light, resulting in color mixing between the plurality of sub-pixels SP and increased power consumption. Furthermore, the leakage current leads to visually discernible color anomalies and point defects, degrading display quality. For example, when only the first sub-pixel SP1 of the plurality of sub-pixels SP emits light, a portion of the current supplied to drive the light-emitting diode 120 of the first sub-pixel SP1 may leak to the second and third sub-pixels SP2 and SP3 adjacent to the first sub-pixel SP1 via the common layer.

[0104] Furthermore, the light-emitting layers provided for each of the plurality of sub-pixels SP have different turn-on voltages. For example, the turn-on voltage used to drive the first sub-pixel SP1, on which a blue light-emitting layer is provided, is the highest, while the turn-on voltage used to drive the third sub-pixel SP3, on which a red light-emitting layer is provided, is the lowest. In the second and third sub-pixels SP2 and SP3, which have lower turn-on voltages than the first sub-pixel SP1, which has the highest turn-on voltage, the barrier to current flow is low. Therefore, current leaking through the common layer can easily flow from the first sub-pixel SP1, which has a higher turn-on voltage, to the second and third sub-pixels SP2 and SP3, which have lower turn-on voltages. Therefore, when the first sub-pixel SP1 is driven, the second and third sub-pixels SP2 and SP3, which have lower turn-on voltages, can emit light together.

[0105] Specifically, during low-grayscale driving, the brightness of light emitted from the sub-pixel SP being driven is low, making it easier to identify light emitted from adjacent sub-pixels SP. This means that during low-grayscale driving, color anomalies and point defects caused by leakage current are more easily identified, potentially leading to significant degradation in display quality. Furthermore, when displaying white light at low grayscales, the third sub-pixel SP3, which has the lowest on-voltage, emits light first through the common layer, potentially resulting in a reddish tint in white rather than pure white.

[0106] Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, multiple first patterns 140 are provided to reduce leakage current through the common layer of the light-emitting diodes 120. First, the organic layers 122 and cathodes 123 of the multiple light-emitting diodes 120 are disposed on the bank 116 on which the multiple first patterns 140 are formed, so that the organic layers 122 and cathodes 123 are also disposed within the multiple first patterns 140. Since the organic layers 122 and cathodes 123 are deposited along the multiple first patterns 140, the length of the path through which leakage current flows can be increased. Since the common layer of the organic layer 122, which serves as a path for leakage current, is formed along the multiple first patterns 140 and the bank 116, the length of the common layer and the length of the leakage current path can be increased. Therefore, the length of the organic layer 122, which serves as a path for leakage current, is increased by the first patterns 140, which function as grooves, thereby increasing the resistance of the organic layer 122. By increasing the resistance of the organic layer 122, for example, the voltage applied to the adjacent sub-pixel is reduced to a level below the on-state voltage of the adjacent sub-pixel. Therefore, leakage current flowing to the light emitting diode 120 of the adjacent sub-pixel SP can be reduced.

[0107] Furthermore, in the display device 100 according to an exemplary embodiment of the present disclosure, leakage current carriers can be captured by capacitors formed by the cathode 123 and the DC line in the plurality of first patterns 140. Specifically, the plurality of first patterns 140 can be arranged to overlap the DC line. The portion of the cathode 123 arranged in the first pattern 140 overlapping the DC line is closer to the DC line than the portion of the cathode 123 arranged outside the first pattern 140 and not overlapping the DC line. In one embodiment, the plurality of first patterns 140 are grooves formed in the bank 116 and the planarization layer 115. Furthermore, in the first pattern 140, the cathode 123 and the DC line, for example, the cathode 123 and the high-potential power line PL or the cathode 123 and the initialization signal line IL, can form a capacitor. If the first patterns 140 are not provided, various insulating layers, such as the bank 116 and the planarization layer 115, are disposed between the cathode 123 and the DC line, for example, the high-potential power line PL or the initialization signal line IL. Consequently, the distance between the cathode 123 and the DC line increases, making it difficult to form a capacitor. However, in the display device 100 according to the exemplary embodiment of the present disclosure, the first pattern 140 is formed in the bank 116 and the planarization layer 115, so that the distance between the cathode 123 and the DC line becomes closer. Therefore, the cathode 123 and the DC line can form a capacitor. In addition, the carriers of the leakage current flowing to the adjacent sub-pixel SP are captured by the capacitor formed by the cathode 123 and the DC line, so that the leakage current flowing to the adjacent sub-pixel SP can be reduced.

[0108] Among them, when the plurality of first patterns 140 overlap with the AC line through which the AC signal of the scan line SL and the data line DL flows, a capacitor can also be formed between the cathode 123 and the AC line. However, the amplitude and direction of the AC signal vary according to time, so that the capacitor between the cathode 123 and the AC line may not be stably configured, and the carriers of the leakage current are hardly captured by the capacitor. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the plurality of first patterns 140 are arranged to overlap with the DC line such as the high-potential power line PL and the initialization signal line IL, but not with the AC line. Therefore, the carriers of the leakage current can be stably captured. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the first pattern 140 is arranged to overlap with the DC line, so that the leakage current transmitted to the adjacent sub-pixel SP can be further reduced.

[0109] Figure 4 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. Figures 1 to 3B Compared with the display device 100, Figure 4 The display device 400 and Figures 1 to 3BThe only difference between the display devices 100 is the transistors T5 and T6, and the other configurations are substantially the same, so redundant description will be omitted.

[0110] Reference Figure 4 , a first buffer layer 411a and a second buffer layer 411b are provided on the substrate 110. The first buffer layer 411a and the second buffer layer 411b can reduce the penetration of moisture or impurities from the substrate 110. The first buffer layer 411a and the second buffer layer 411b can be configured by a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx, but are not limited thereto. However, depending on the type of the substrate 110 or the type of the transistor, the first buffer layer 411a and the second buffer layer 411b can be omitted, but are not limited thereto.

[0111] A light shielding layer BSM is provided between the first buffer layer 411a and the second buffer layer 411b. The light shielding layer BSM is provided to overlap with the fifth active layer ACT5 of the fifth transistor T5 to be described below, so as to protect the fifth transistor T5 from the influence of laser light or moisture introduced from the outside, so as to reduce the deformation of the device characteristics of the fifth transistor T5. Figure 4 The light shielding layer BSM is shown to be floating, but the light shielding layer BSM may also be electrically connected to other structures, such as a plurality of wirings, but is not limited thereto.

[0112] A fifth transistor T5 is disposed on the second buffer layer 411b and includes a fifth active layer ACT5, a fifth gate electrode GE5, a fifth source electrode SE5, and a fifth drain electrode DE5.

[0113] The fifth active layer ACT5 is disposed on the second buffer layer 411b so as to overlap with the light shielding layer BSM. The fifth active layer ACT5 can be formed of low-temperature polysilicon (LTPS). Polysilicon has high mobility, resulting in low energy consumption and high reliability. Therefore, a transistor formed of polysilicon material can be applied to a driving transistor.

[0114] A first gate insulating layer 412a is disposed on the fifth active layer ACT5. The first gate insulating layer 412a is an insulating layer that insulates the fifth active layer ACT5 from the fifth gate electrode GE5 and may be configured of a single layer or double layers of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto.

[0115] A fifth gate electrode GE5 is disposed on the first gate insulating layer 412a and may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0116] A first interlayer insulating layer 413a and a second interlayer insulating layer 413b are provided on the fifth gate electrode GE5. Contact holes may be formed in the first interlayer insulating layer 413a and the second interlayer insulating layer 413b, respectively, through which the fifth source electrode SE5 and the fifth drain electrode DE5 are connected to the fifth active layer ACT5. The first interlayer insulating layer 413a and the second interlayer insulating layer 413b may be configured of a single layer or a double layer of silicon oxide SiOx or silicon nitride SiNx, but are not limited thereto.

[0117] A fifth source electrode SE5 and a fifth drain electrode DE5 are provided on the second interlayer insulating layer 413b. The fifth source electrode SE5 and the fifth drain electrode DE5, which are spaced apart from each other, may be electrically connected to the fifth active layer ACT5. The fifth source electrode SE5 and the fifth drain electrode DE5 may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0118] A passivation layer 114 is provided on the fifth source electrode SE5 and the fifth drain electrode DE5, and a connection electrode CE is provided on the passivation layer 114. The connection electrode CE is a connection member that electrically connects the anode 121 to the fifth transistor T5 and the sixth transistor T6, and is provided between the passivation layer 114 and the planarization layer 115. However, the connection electrode CE may be omitted and is not limited thereto.

[0119] The sixth transistor T6 is disposed on the first gate insulating layer 412a and includes a sixth active layer ACT6, a sixth gate electrode GE6, a sixth source electrode SE6, and a sixth drain electrode DE6.

[0120] The sixth active layer ACT6 is disposed on the first gate insulating layer 412a. The sixth active layer ACT6 may be formed of an oxide semiconductor. Oxide semiconductor materials have a band gap larger than that of silicon, so that electrons cannot cross the band gap in the off state. Therefore, oxide semiconductor materials have a low off-state current. Therefore, transistors formed of oxide semiconductor materials can be applied to switching transistors with a short on-time and a long off-time.

[0121] A first interlayer insulating layer 413a is provided on the sixth active layer ACT6, and a second gate insulating layer 412b and a sixth gate electrode GE6 are provided on the first interlayer insulating layer 413a. The second gate insulating layer 412b may be patterned in the same manner as the sixth gate electrode GE6. The second gate insulating layer 412b may be formed to correspond to the sixth gate electrode GE6, rather than being formed on the entire substrate 110. Figure 4, the first gate insulating layer 412a is formed on the entire substrate 110, and the second gate insulating layer 412b is patterned in the same manner as the sixth gate electrode GE6. However, the second gate insulating layer 412b may be provided on the entire substrate 110, or the first gate insulating layer 412a may be patterned in the same manner as the fifth gate electrode GE5, but is not limited thereto.

[0122] The sixth gate electrode GE6 may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0123] A second interlayer insulating layer 413b is provided on the sixth gate electrode GE6, and a sixth source electrode SE6 and a sixth drain electrode DE6 are provided on the second interlayer insulating layer 413b. The sixth source electrode SE6 and the sixth drain electrode DE6, which are provided to be spaced apart from each other, may be electrically connected to the sixth active layer ACT6. The sixth source electrode SE6 and the sixth drain electrode DE6 may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0124] The fifth drain electrode DE5 of the fifth transistor T5 can be connected to the sixth source electrode SE6 of the sixth transistor T6. The fifth drain electrode DE5 and the sixth source electrode SE6 can be formed integrally. Therefore, both the fifth transistor T5 and the sixth transistor T6 can be electrically connected to the anode 121 of the light emitting diode 120.

[0125] Among them, Figure 4 , it is described that the fifth active layer ACT5 of the fifth transistor T5 is formed of low-temperature polysilicon and the sixth active layer ACT6 of the sixth transistor T6 is formed of an oxide semiconductor material. However, the fifth active layer ACT5 may be formed of an oxide semiconductor material, or the sixth active layer ACT6 may be formed of low-temperature polysilicon, but is not limited thereto.

[0126] In a display device 400 according to another exemplary embodiment of the present disclosure, a plurality of transistors T1, T2, T3, T4, T5 and T6 of a pixel circuit are configured by different types to improve the performance of the pixel circuit. The pixel circuit includes a plurality of transistors T1, T2, T3, T4, T5 and T6 and a capacitor Cst, and the plurality of transistors T1, T2, T3, T4, T5 and T6 are formed by transistors of different types. For example, in some of the plurality of transistors T1, T2, T3, T4, T5 and T6, the active layer is formed by low-temperature polysilicon, and in other transistors, the active layer can be formed by an oxide semiconductor material. The transistor comprising low-temperature polysilicon has high mobility and low power consumption, so that the transistor can be applied as a driving transistor. The transistor comprising an oxide semiconductor material has a short on-time and maintains a long off-time, so that the transistor can be applied as a switching transistor. Therefore, in the display device 400 according to another exemplary embodiment of the present disclosure, considering the functions of the plurality of transistors T1, T2, T3, T4, T5, and T6 configuring the pixel circuit, the active layer may be configured of different materials to improve the performance of the pixel circuit.

[0127] Figure 5 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. Figure 4 Compared with the display device 400, Figure 5 The display device 500 further includes a dummy line DPL, but other configurations are substantially the same, and thus redundant description will be omitted.

[0128] Reference Figure 5 A passivation layer 114 is provided on the high-potential power line PL, and a dummy line DPL is provided on the passivation layer 114. The dummy line DPL is the line with the greatest distance from the substrate 110 (e.g., the line provided at the uppermost portion) among the plurality of wirings provided on the substrate 110, and is provided so as to overlap between the high-potential power line PL and the first pattern 140. Furthermore, the dummy line DPL is electrically connected to the high-potential power line PL so as to be supplied with the high-potential power signal EVDD, i.e., a DC signal, transmitted to the high-potential power line PL. Therefore, the dummy line DPL, which is provided at the uppermost portion among the plurality of wirings on the substrate 110 and electrically connected to the high-potential power line PL, can form a capacitor with the cathode 123 provided in the first pattern 140.

[0129] In a display device 500 according to another exemplary embodiment of the present disclosure, a DC signal is applied to a wiring disposed at the uppermost portion among wirings disposed on a substrate 110 to increase the capacitance of a capacitor formed between a portion of the cathode 123 in the first pattern 140 and the wiring at the uppermost portion. The DC signal may flow in some of the plurality of wirings disposed on the substrate 110. In addition, the cathode 123 disposed in the first pattern 140 overlaps with some of the DC lines through which the DC signal flows to form a capacitor. For example, a pseudo line DPL disposed at the uppermost portion among the plurality of wirings and electrically connected to the high potential power line PL may form a capacitor with the cathode 123 disposed in the first pattern 140. At this time, the shorter the distance between the two electrodes forming the capacitor, the better the capacitance of the capacitor. Therefore, the capacitance of the capacitor formed by the cathode 123 disposed in the first pattern 140 and the pseudo line DPL disposed at the uppermost portion among the wirings disposed on the substrate 110 may be greater than Figure 3B and Figure 4 The capacitor in the embodiment shown. Furthermore, when the capacitance of the capacitor increases, carriers of leakage current flowing to adjacent sub-pixels SP can be easily captured. Therefore, in a display device 500 according to another exemplary embodiment of the present disclosure, the cathode 123 provided in the first pattern 140 forms a capacitor with the uppermost wiring (e.g., a pseudo line DPL) of the wiring provided on the substrate 110 and through which a DC signal flows. Therefore, more carriers of leakage current flowing to adjacent sub-pixels SP can be captured, and visual recognition of color anomalies and point defects caused by leakage current can be reduced.

[0130] Figure 6 is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure. Figure 7A is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure. Figure 7B According to one embodiment, Figure 7A VIIb-VIIb'. Figures 1 to 3B Compared with the display device 100, Figure 6 The display device 600 and Figure 7A and Figure 7B In the display device 700, only the first patterns 640 and 740 are different, and other configurations are substantially the same, so redundant description will be omitted.

[0131] Reference Figures 6 to 7B, a plurality of first patterns 640 and 740 are provided between the plurality of sub-pixels SP. One or more first patterns 640 and 740 may be provided between the first sub-pixel SP1 and the second sub-pixel SP2, between the first sub-pixel SP1 and the third sub-pixel SP3, or between the second sub-pixel SP2 and the third sub-pixel SP3. In this case, the number of first patterns 640 and 740 provided between the plurality of sub-pixels SP may be designed in various ways taking into account the turn-on voltages of the plurality of sub-pixels SP.

[0132] For example, in Figure 6 In the display device 600, the plurality of first patterns 640 may be provided between the first sub-pixel SP1 and the second sub-pixel SP2 and between the first sub-pixel SP1 and the third sub-pixel SP3. In this case, one of the first portions 641 of the plurality of first patterns 640 between the first sub-pixel SP1 and the third sub-pixel SP3 may be provided to overlap with the high-potential power line PL, and another first portion 641 may be provided in the region between the high-potential power line PL and the first sub-pixel SP1.

[0133] The first pattern 640 among the plurality of first patterns 640, which overlaps the region between the high-potential power line PL and the third sub-pixel SP3, can increase the length of the path through which the leakage current flows. Furthermore, the first pattern 640 among the plurality of first patterns 640, which overlaps the high-potential power line PL, increases the length of the path through which the leakage current flows and forms a capacitor with the high-potential power line PL to capture carriers of the leakage current flowing to the adjacent sub-pixel SP.

[0134] Among them, Figure 6 , the two first portions 641 of the first pattern 640 are shown to be disposed only between the first sub-pixel SP1 and the second sub-pixel SP2 and between the first sub-pixel SP1 and the third sub-pixel SP3. However, one or more second portions 642 of the first pattern 640 may also be disposed between the second sub-pixel SP2 and the third sub-pixel SP3, and the arrangement and number of the plurality of first patterns 640 are not limited thereto.

[0135] Next, in Figure 7A and Figure 7B In the display device 700, a plurality of first patterns 740 may be provided between a plurality of sub-pixels SP. Specifically, the plurality of first patterns 740 (e.g., the first portions 741 of the plurality of first patterns 740) may be provided to overlap with a single high-potential power line PL provided between the plurality of sub-pixels SP. Since the plurality of first patterns 740 overlap with a single high-potential power line PL, the number of capacitors formed by the cathode 123 and the high-potential power line PL may be increased. In addition, one or more second portions 742 of the first pattern 740 may also be provided between the second sub-pixel SP2 and the third sub-pixel SP3.

[0136] Among them, although Figure 7A and Figure 7B , the plurality of first patterns 740 are shown to overlap with one high potential power line PL, however, the plurality of first patterns 740 may also be disposed to overlap with other DC lines such as the initialization signal line IL, and is not limited thereto.

[0137] In the display devices 600 and 700 according to yet another exemplary embodiment of the present disclosure, a plurality of first patterns 640 and 740 are provided between a plurality of sub-pixels SP to reduce leakage current generated during driving of the display devices 600 and 700 and flowing to the sub-pixels SP that do not emit light. Figure 6 In the display device 600, a plurality of first patterns 640 are provided between a plurality of sub-pixels SP. Some of the plurality of first patterns 640 increase the length of the path through which the leakage current flows to reduce the leakage current flowing to the adjacent sub-pixels SP. Other first patterns of the plurality of first patterns 640 overlap with a DC line such as a high potential power line PL to form a capacitor formed by the cathode 123 and the DC line, and the capacitor captures carriers of the leakage current to reduce the leakage current flowing to the adjacent sub-pixels SP. In addition, in Figure 7A and Figure 7B In the display device 700 of the present disclosure, the plurality of first patterns 740 can be arranged to overlap with a DC line, such as a high-potential power line PL, disposed between the plurality of sub-pixels SP. Since the plurality of first patterns 740 overlap with the high-potential power line PL, the number of capacitors formed by the cathode 123 and the high-potential power line PL can be increased, and more carriers of leakage current can be captured. Therefore, the plurality of first patterns 740 are arranged to overlap with a DC line to reduce leakage current flowing to adjacent sub-pixels SP. Therefore, in the display devices 600 and 700 according to another exemplary embodiment of the present disclosure, the plurality of first patterns 640 and 740 are disposed between the plurality of sub-pixels SP. Therefore, when driving one sub-pixel SP, degradation in display quality due to color mixing, dot defects, or color anomalies caused by leakage current flowing to adjacent sub-pixels SP can be reduced.

[0138] In display devices 600 and 700 according to yet another exemplary embodiment of the present disclosure, the number of first patterns 640 and 740 arranged between a plurality of subpixels SP can be designed to vary depending on the turn-on voltages of the plurality of subpixels SP. For example, leakage current can easily flow from the first subpixel SP1, which has the highest turn-on voltage, to the third subpixel SP3, which has the lowest turn-on voltage. This allows the third subpixel SP3 to emit light even when only the first subpixel SP1 needs to. Therefore, the first patterns 640 and 740 can be arranged to a maximum extent between the first subpixel SP1, which has the highest turn-on voltage, and the third subpixel SP3, which has the lowest turn-on voltage. Furthermore, the number of first patterns 640 and 740 arranged between the second subpixel SP2, which has a lower turn-on voltage than the first subpixel SP1, and the third subpixel SP3, which has the lowest turn-on voltage, is smaller than the number of first patterns 640 and 740 arranged between the first subpixel SP1 and the third subpixel SP3. Therefore, in the display devices 600 and 700 according to still another exemplary embodiment of the present disclosure, the arrangement and number of the first patterns 640 and 740 may be designed in consideration of the turn-on voltages of the plurality of sub-pixels SP.

[0139] Figure 8 is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure. Figures 1 to 3B Compared with the display device 100, Figure 8 The display device 800 and Figures 1 to 3B The only difference between the display devices 100 is the plurality of first patterns 840 , but other configurations are substantially the same, so redundant description will be omitted.

[0140] Reference Figure 8 , some of the plurality of first patterns 840 are arranged to be separated. The first portions 841 of the plurality of first patterns 840 are arranged to be separated at predetermined intervals, and the second portions 842 of the plurality of first patterns 840 are also arranged to be separated at predetermined intervals.

[0141] For example, a first portion 841 of the first pattern 840 disposed on the left side of the second sub-pixel SP2 and the third sub-pixel SP3 may be partially opened between the second sub-pixel SP2 and the first sub-pixel SP1. A first portion 841 of the first pattern 840 disposed on the right side of the second sub-pixel SP2 and the third sub-pixel SP3 may be partially opened between the third sub-pixel SP3 and the first sub-pixel SP1. In addition, a second portion 842 of the first pattern 840 disposed between the second sub-pixel SP2 and the third sub-pixel SP3 may also be partially opened.

[0142] Among them, Figure 8, the first pattern 840 is shown as being separated between the first sub-pixel SP1 and the second sub-pixel SP2, between the first sub-pixel SP1 and the third sub-pixel SP3, and between the second sub-pixel SP2 and the third sub-pixel SP3. However, the first pattern 840 may be separated at a location where a contact hole is provided or at a location overlapping with a scan line SL1 or SL2 or a data line DL through which an AC signal flows. The location where the first pattern 840 is separated is not limited thereto.

[0143] In a display device 800 according to another exemplary embodiment of the present disclosure, first patterns 840 disposed between multiple subpixels SP are partially separated, thereby reducing increases in the resistance of the cathode 123. Portions of the cathode 123 disposed within the multiple first patterns 840 form capacitors with the DC line, reducing the flow of leakage current. In other words, the resistance of the portions of the cathode 123 that overlap with the multiple first patterns 840 may increase. In this case, portions of the multiple first patterns 840 are separated to reduce the resistance of the cathode 123, thereby reducing brightness variations due to voltage drop. For example, a first portion 841 of the first pattern 840 between the first subpixel SP1 and the second subpixel SP2 is partially separated, as is a portion between the first subpixel SP1 and the third subpixel SP3. Furthermore, a second portion 842 between the second subpixel SP2 and the third subpixel SP3 is also partially separated. Therefore, in the display device 800 according to another exemplary embodiment of the present disclosure, a portion of the first pattern 840 is separated to reduce voltage drop in the cathode 123 and thus reduce brightness variations.

[0144] Figure 9 is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure. Figures 1 to 3B Compared with the display device 100, Figure 9 The display device 900 and Figures 1 to 3B The only difference between the display devices 100 is the plurality of first patterns 940 , but other configurations are substantially the same, so redundant description will be omitted.

[0145] Reference Figure 9 , a plurality of first patterns 940 are provided to respectively surround the plurality of sub-pixels SP. The first pattern 940 may be provided to surround the periphery (e.g., four sides) of the plurality of sub-pixels SP in a plan view. For example, a first portion 941 and a second portion 942 of the first pattern 940 provided around each side of each of the plurality of sub-pixels SP are connected to each other, and the first pattern 940 may be formed in a closed curve that surrounds the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0146] The first pattern 940 is arranged to surround the second sub-pixel SP2 adjacent to the first sub-pixel SP1 and the third sub-pixel SP3, surround the third sub-pixel SP3 adjacent to the second sub-pixel SP2 and the first sub-pixel SP1, and surround the first sub-pixel SP1 adjacent to the second sub-pixel SP2 and the third sub-pixel SP3. The first pattern 940 may be arranged to surround between the first sub-pixel SP1 and the second sub-pixel SP2, between the first sub-pixel SP1 and the third sub-pixel SP3, and between the second sub-pixel SP2 and the third sub-pixel SP3. Thus, the first pattern 940 may be arranged to form a grid pattern.

[0147] Among them, even in Figure 9 While the first pattern 940 is shown as surrounding all of the plurality of sub-pixels SP, the first pattern 940 may not be provided between the plurality of first sub-pixels SP1 arranged in the same column, and is not limited thereto. For example, instead of being provided between the plurality of first sub-pixels SP1 arranged in the same column, the first pattern 940 may be provided only between the first sub-pixel SP1 and the second sub-pixel SP2, and between the first sub-pixel SP1 and the third sub-pixel SP3. The plurality of first sub-pixels SP1 arranged in the same column have substantially the same on-state voltage. This means that when one of the first sub-pixels SP1 is driven, emission problems due to leakage current in the adjacent first sub-pixel SP1 are unlikely to occur. However, there may be a problem in which the second sub-pixel SP2 or the third sub-pixel SP3, which has a relatively low on-state voltage, emits light due to leakage current in the first sub-pixel SP1. Therefore, the first pattern 940 may be provided between a plurality of sub-pixels SP having different on-state voltages, but may not be provided between sub-pixels SP having substantially the same on-state voltage.

[0148] In a display device 900 according to another exemplary embodiment of the present disclosure, a first pattern 940 is provided to surround each side of a plurality of sub-pixels SP, thereby improving display quality by reducing color anomalies and point defects caused by leakage current. The first pattern 940 is provided to surround each of the plurality of sub-pixels SP, thereby reducing leakage current flowing between the plurality of sub-pixels SP having different turn-on voltages. In some of the first patterns 940 that overlap with the DC line, the cathode 123 and the DC line form a capacitor that captures carriers of the leakage current. In other first patterns 940, the length of the path through which the leakage current flows is increased to increase resistance, thereby reducing leakage current flowing to adjacent sub-pixels SP. Therefore, in the display device 900 according to another exemplary embodiment of the present disclosure, the first pattern 940 is provided to surround four sides of each of the plurality of sub-pixels SP, thereby reducing degradation of display quality due to leakage current and reducing power consumption.

[0149] Figure 10A is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure. Figure 10B According to one embodiment, Figure 10A A cross-sectional view of the display device taken along Xb-Xb'. Figures 1 to 3B Compared with the display device 100, Figure 10A and Figure 10B The display device 1000 further includes a second pattern 1050, but other configurations are substantially the same, so redundant description will be omitted.

[0150] Reference Figure 10A , a plurality of second patterns 1050 are disposed between the plurality of sub-pixels SP. The plurality of second patterns 1050 may be disposed to be spaced apart from the plurality of first patterns 1040. In addition, at least a portion of the plurality of second patterns 1050 may be disposed to overlap an AC line transmitting an AC signal.

[0151] The plurality of second patterns 1050 include a third portion 1051 and a fourth portion 1052. The third portion 1051 extends along the column direction between the plurality of sub-pixels SP. The third portion 1051 may extend along the column direction between the first sub-pixel SP1 and the second sub-pixel SP2, and between the first sub-pixel SP1 and the third sub-pixel SP3. For example, the third portion 1051 may be arranged to extend along the column direction between the first sub-pixel SP1 and the second sub-pixel SP2, and between the first sub-pixel SP1 and the third sub-pixel SP3. Only one or more third portions 1051 of the second pattern 1050 may be arranged on one side of the second sub-pixel SP2 and the third sub-pixel SP3, and one or more first portions 1041 of the first pattern 1040 may be arranged on the other side of the second sub-pixel SP2 and the third sub-pixel SP3. Alternatively, only the third portion 1051 may be arranged on one side of the second sub-pixel SP2 and the third sub-pixel SP3, or the first portion 1041 and the third portion 1051 may be arranged together on the other side of the second sub-pixel SP2 and the third sub-pixel SP3.

[0152] The fourth portion 1052 is a portion extending in the row direction between the plurality of sub-pixels SP. The fourth portion 1052 may be a portion extending in the row direction between the second sub-pixel SP2 and the third sub-pixel SP3, or between the first sub-pixel SP1. In this case, the fourth portion 1052 may extend in the row direction from the third portion 1051, or may be disposed separately from the third portion 1051. For example, the fourth portion 1052 may be disposed to extend in the row direction between the second sub-pixel SP2 and the third sub-pixel SP3. Furthermore, the fourth portion 1052 of the second pattern 1050 may be disposed between the second portion 1042 of the first pattern 1040 between the second sub-pixel SP2 and the third sub-pixel SP3. For example, the fourth portion 1052 extending from the third portion 1051 on one side of the second sub-pixel SP2 may be disposed adjacent to the second sub-pixel SP2 between the second sub-pixel SP2 and the third sub-pixel SP3. The second portion 1042 extending from the first portion 1041 on the other side of the second sub-pixel SP2 may be disposed between the fourth portion 1052 and the third sub-pixel SP3. In addition, only any one of the second portion 1042 of the first pattern 1040 and the fourth portion 1052 of the second pattern 1050 can be disposed between the second sub-pixel SP2 and the third sub-pixel SP3. For example, only the fourth portion 1052 can be disposed above the second sub-pixel SP2, and only the second portion 1042 can be disposed below the second sub-pixel SP2. However, if the plurality of second patterns 1050 and the plurality of first patterns 1040 are spaced apart from each other, the arrangement of the plurality of second patterns 1050 and the plurality of first patterns 1040 is not limited to that shown in the drawings.

[0153] At least a portion of the plurality of second patterns 1050 may be arranged to overlap with an AC line among the plurality of wirings. For example, at least a portion of the third portion 1051 of the plurality of second patterns 1050 may overlap with a data line DL extending in the column direction among the AC lines. Furthermore, at least a portion of the fourth portion 1052 of the plurality of second patterns 1050 may be arranged to overlap with a scan line SL, which is an AC line.

[0154] If the plurality of second patterns 1050 are disposed so as to overlap the DC line, the number of capacitors disposed between the cathodes 123 disposed in the plurality of first patterns 1040 and the DC line decreases, and leakage current flowing to adjacent sub-pixels SP may increase. Therefore, the plurality of second patterns 1050 may be disposed so as not to overlap the DC line.

[0155] Refer to it together Figure 10BThe second pattern 1050 is disposed on the bank 116, and the organic layer 122 and the cathode 123 of the light emitting diode 120 are disposed on the second pattern 1050. The plurality of second patterns 1050 may be disposed on the upper surface of the bank 116 to be spaced apart from the plurality of first patterns 1040 and the spacer 130.

[0156] In the plurality of second patterns 1050, the width of the upper portion may be greater than the width of the lower portion. In other words, the plurality of second patterns 1050 may be formed as reverse spacers whose width narrows from the upper portion to the lower portion. Furthermore, at least one of the common layer and the cathode 123 formed on the plurality of second patterns 1050 may be disconnected by the second pattern 1050 serving as the reverse spacer. When the common layer and the cathode 123 of the organic layer 122 are formed over the entire substrate 110, it may be difficult to deposit the organic layer 122 and the cathode 123 below the plurality of second patterns 1050 due to a shadowing effect on the plurality of second patterns 1050 serving as the reverse spacers. Consequently, the lower portions of the plurality of second patterns 1050 are blocked by the relatively wider upper portions of the plurality of second patterns 1050, making it difficult to deposit the organic layer 122 and the cathode 123 below the plurality of second patterns 1050. Consequently, at least one of the organic layer 122 and the cathode 123 may be disconnected in the plurality of second patterns 1050. Therefore, the common layer of the light emitting diode 120 and at least a portion of the cathode 123 may be electrically insulated in the plurality of second patterns 1050 .

[0157] At this point, as the organic layer 122 approaches the plurality of second patterns 1050, the resistance may increase. Specifically, the organic layer 122 may be formed with uneven thickness or partially separated in the plurality of second patterns 1050, which serve as reverse spacers, thereby increasing the resistance of the organic layer 122. Specifically, due to the shadowing effect, it is difficult to sufficiently deposit the material forming the organic layer 122 in the region adjacent to the lower portions of the plurality of second patterns 1050, resulting in the organic layer 122 being formed with a smaller thickness in the region adjacent to the lower portions of the plurality of second patterns 1050. As another example, due to the shadowing effect, it is difficult to deposit the organic layer 122 onto the side surfaces of the second patterns 1050, and a portion of the organic layer 122 may be separated. In other words, it is difficult to continuously form the organic layer 122 with uniform thickness in the plurality of second patterns 1050, thereby increasing the resistance of the organic layer 122 in the plurality of second patterns 1050. Therefore, as the organic layer 122 approaches the plurality of second patterns 1050, the resistance may increase.

[0158] The height of the plurality of second patterns 1050 may be lower than the height of the plurality of spacers 130. When the plurality of second patterns 1050 and the plurality of spacers 130 are disposed together on the upper surface of the bank 116, if the height of the plurality of second patterns 1050 is higher than the height of the plurality of spacers 130, the deposition mask comes into contact with the plurality of second patterns 1050. Therefore, it is difficult to bring the plurality of spacers 130 into contact with the deposition mask. Consequently, the distance between the deposition mask and the substrate 110 differs from the designed distance, and forming the light-emitting diodes 120 may be difficult. Therefore, the height of the plurality of second patterns 1050 is formed to be lower than the height of the plurality of spacers 130 to maintain a constant distance between the deposition mask and the substrate 110.

[0159] Among them, reference Figure 10A , the plurality of second patterns 1050 are arranged to be partially separated. The second patterns 1050 surrounding one sub-pixel SP among the plurality of sub-pixels SP may be arranged to be spaced apart from each other. The third portions 1051 of the second patterns 1050 may be arranged to be spaced apart from each other at predetermined intervals, and the fourth portions 1052 may also be arranged to be spaced apart from each other at predetermined intervals. For example, in the second pattern 1050 surrounding the first sub-pixel SP1, the third portions 1051 of the second pattern 1050 disposed on the left side of the first sub-pixel SP1 may be arranged to be spaced apart from each other.

[0160] As described above, in the second pattern 1050 as a reverse spacer, at least one of the organic layer 122 and the cathode 123 of the light-emitting diode 120 may be disconnected. If the second pattern 1050 completely surrounds the plurality of sub-pixels SP, the organic layer 122 and / or the cathode 123 are separated by the second pattern 1050, making it difficult for the plurality of light-emitting diodes 120 to emit light. Therefore, the plurality of second patterns 1050 may be arranged to surround the plurality of light-emitting diodes and form an open curve in which a portion surrounding each of the plurality of light-emitting diodes 120 is open.

[0161] For example, the third portion 1051 of the second pattern 1050, which is disposed on both sides of the second sub-pixel SP2 and the third sub-pixel SP3, may be partially open between the first sub-pixel SP1 and the second sub-pixel SP2 or between the first sub-pixel SP1 and the third sub-pixel SP3. Furthermore, the fourth portion 1052 of the second pattern 1050, which is disposed between the second sub-pixel SP2 and the third sub-pixel SP3, may also be partially open. However, the open portion of the second pattern 1050 may be designed in various ways other than those shown in the drawings and is not limited thereto.

[0162] In a display device 1000 according to another exemplary embodiment of the present disclosure, a first pattern 1040 serving as a groove and a second pattern 1050 serving as a back spacer are provided between multiple sub-pixels SP to reduce the transmission of leakage current to adjacent sub-pixels SP. The first pattern 1040 serving as a groove is provided in the bank 116 between the multiple sub-pixels SP to increase the length of the common layer, which serves as a path for leakage current to flow, thereby reducing leakage current flowing to adjacent sub-pixels SP. Furthermore, carriers of the leakage current are captured by a capacitor formed between the portion of the cathode 123 in the first pattern 1040 and the DC line, thereby reducing leakage current flowing to adjacent sub-pixels SP. Furthermore, the second pattern 1050 serving as a back spacer is provided on the bank 116 between the multiple sub-pixels SP to disconnect at least one of the common layer and the cathode 123, further reducing leakage current. Specifically, when the common layer of the organic layer 122 serving as a path for leakage current is disconnected in the second pattern 1050, the path through which leakage current flows to adjacent sub-pixels SP is blocked. Furthermore, even if the common layer of the organic layer 122 is connected in the second pattern 1050, the common layer is not deposited to have a uniform thickness, so that the resistance can be increased and the flow of leakage current can be reduced. Therefore, in the display device 1000 according to another exemplary embodiment of the present disclosure, a plurality of second patterns 1050 are provided together with the plurality of first patterns 1040. Therefore, the following problem can be reduced: when one sub-pixel SP is driven, leakage current flows to the adjacent sub-pixel SP, causing a point defect to be visually recognized due to color mixing and a reduction in color reproduction rate.

[0163] Figure 11 is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure. Figure 12 is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure. Figure 10A and Figure 10B Compared with the display device 1000, Figure 11 The display device 1100 and Figure 12 In the display device 1200 , only the plurality of first patterns 1140 and 1240 and the plurality of second patterns 1150 and 1250 are different, and other configurations are substantially the same, so redundant description will be omitted.

[0164] Reference Figure 11 ,exist Figure 11In the display device 1100, only the plurality of first patterns 1140 or only the plurality of second patterns 1150 may be arranged between the first sub-pixel SP1 and the second sub-pixel SP2, and between the first sub-pixel SP1 and the third sub-pixel SP3. For example, only the first portion 1141 of the plurality of first patterns 1140 may be arranged on one side of the first sub-pixel SP1, and only the third portion 1151 of the plurality of second patterns 1150 may be arranged on the other side of the first sub-pixel SP1. In this case, only some of the plurality of first patterns 1140 arranged between the first sub-pixel SP1 and the second sub-pixel SP2 may be separated, while the other first patterns 1140 may not be separated. Similarly, only some of the plurality of second patterns 1150 arranged between the first sub-pixel SP1 and the second sub-pixel SP2 may be separated, while the other second patterns 1150 may not be separated and extend continuously.

[0165] Reference Figure 12 ,exist Figure 12 In the display device 1200, only the plurality of first patterns 1240 or both the first pattern 1240 and the second pattern 1250 may be disposed between the first sub-pixel SP1 and the second sub-pixel SP2 and between the first sub-pixel SP1 and the third sub-pixel SP3. For example, only partially separated plurality of first patterns 1240 may be disposed on one side of the first sub-pixel SP1, and the continuously extending first pattern 1240 and partially separated second pattern 1250 may be disposed together on the other side of the first sub-pixel SP1.

[0166] In addition, refer to Figure 11 and Figure 12 ,exist Figure 11 and Figure 12 In both display devices 1100 and 1200, the first patterns 1140 and 1240 and the second patterns 1150 and 1250 are disposed together between the second subpixel SP2 and the third subpixel SP3. For example, between the second subpixel SP2 and the third subpixel SP3, the fourth portions 1152 and 1252 extending from the third portions 1151 and 1251 on one side of the second subpixel SP2 are disposed adjacent to the second subpixel SP2. Furthermore, the second portions 1142 and 1242 extending from the first portions 1141 and 1241 on the other side of the second subpixel SP2 are disposed adjacent to the third subpixel SP3. In this case, only the second patterns 1150 and 1250 disposed between the second subpixel SP2 and the third subpixel SP3 may be disposed separately.

[0167] In the display devices 1100 and 1200 according to still another exemplary embodiment of the present disclosure, a plurality of first patterns 1140 and 1240 and a plurality of second patterns 1150 and 1250 are arranged between a plurality of sub-pixels SP in various patterns to reduce leakage current flowing to adjacent sub-pixels SP generated during driving of the display device. Figure 11 In the display device 1100, only the plurality of first patterns 1140 are provided at one side of the first sub-pixel SP1, and only the plurality of second patterns 1150 are provided at the other side of the first sub-pixel SP1. In addition, the first pattern 1140 and the second pattern 1150 may be provided together between the second sub-pixel SP2 and the third sub-pixel SP3. Figure 12 In the display device 1200, a plurality of first patterns 1240 are provided at one side of the first sub-pixel SP1, and the first pattern 1240 and the second pattern 1250 are provided together at the other side of the first sub-pixel SP1. In addition, the first pattern 1240 and the second pattern 1250 may be provided together between the second sub-pixel SP2 and the third sub-pixel SP3. Figure 11 and Figure 12 In the display devices 1100 and 1200, the plurality of first patterns 1140 and 1240 are provided between the plurality of sub-pixels SP to increase the length of the path through which the leakage current flows. In addition, the carriers of the leakage current are captured, so that the transmission of the leakage current to the non-luminous sub-pixels SP can be reduced. Figure 11 and Figure 12 In the display devices 1100 and 1200 of the present disclosure, multiple second patterns 1150 and 1250 are arranged between multiple sub-pixels SP to disconnect at least a portion of the common layer of the light-emitting diode 120, which serves as a path for leakage current to flow, or to increase resistance by reducing its thickness. This further reduces the flow of leakage current. Therefore, in the display devices 1100 and 1200 according to yet another exemplary embodiment of the present disclosure, multiple first patterns 1140 and 1240 and multiple second patterns 1150 and 1250 are arranged in various patterns between multiple sub-pixels SP. This reduces leakage current transmitted to adjacent sub-pixels SP and improves display quality.

[0168] Figure 13 is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure. Figure 10A and Figure 10B Compared with the display device 1000, Figure 13 The display device 1300 and Figure 10A and Figure 10B The only difference between the display devices 1000 is the plurality of sub-pixels SP, the plurality of wirings, the plurality of first patterns 1340 and the plurality of second patterns 1350, but other configurations are substantially the same, so redundant description will be omitted.

[0169] Reference Figure 13 , the plurality of sub-pixels SP include a first sub-pixel SP1 , a second sub-pixel SP2 , and a third sub-pixel SP3 .

[0170] The plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3 may be alternately arranged on the same column or the same row. For example, the first sub-pixels SP1 and the third sub-pixels SP3 may be alternately arranged on the same column, and the first sub-pixels SP1 and the third sub-pixels SP3 may be alternately arranged on the same row.

[0171] The plurality of second subpixels SP2 may be arranged in columns and rows that are different from the columns and rows of the plurality of first subpixels SP1 and the plurality of third subpixels SP3. For example, the plurality of second subpixels SP2 may be arranged in a row, and the plurality of first subpixels SP1 and the plurality of third subpixels SP3 may be alternately arranged in rows adjacent to the aforementioned row. The plurality of second subpixels SP2 may be arranged in a column, and the plurality of first subpixels SP1 and the plurality of third subpixels SP3 may be alternately arranged in columns adjacent to the aforementioned column. The plurality of first subpixels SP1 and the second subpixels SP2 may be diagonally opposite to each other, and the plurality of third subpixels SP3 and the second subpixels SP2 may also be diagonally opposite to each other. Thus, the plurality of subpixels SP may be arranged in a lattice pattern.

[0172] Among them, Figure 13 , the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3 are arranged in the same column and the same row, and the plurality of second sub-pixels SP2 are arranged in a column and a row different from the columns and rows of the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3. However, the arrangement of the plurality of sub-pixels SP is not limited thereto.

[0173] A high-potential power line PL extending in the column direction is provided between the plurality of sub-pixels SP. The high-potential power line PL may be provided between a column on which the plurality of second sub-pixels SP2 are provided and a column on which the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3 are provided. For example, the high-potential power line PL may be provided on both sides of the plurality of second sub-pixels SP2 and on both sides of the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3.

[0174] A plurality of data lines DL extending along the column direction are arranged between the plurality of high-potential power lines PL. That is, the plurality of high-potential power lines PL and the plurality of data lines DL may be arranged alternately. Some of the plurality of data lines DL are arranged to overlap with the plurality of second sub-pixels SP2 arranged in the same column, and other of the plurality of data lines DL may be arranged to overlap with the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3 arranged in the same column.

[0175] A plurality of initialization signal lines IL extending in the row direction are provided between the plurality of sub-pixels SP. The initialization signal line IL may be provided between a row on which the plurality of second sub-pixels SP2 are provided and a row on which the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3 are provided. For example, the initialization signal line IL may be provided on both sides of the plurality of second sub-pixels SP2 and on both sides of the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3.

[0176] A plurality of scan lines SL and a plurality of emission control signal lines EL extending in the row direction are arranged between the plurality of initialization signal lines IL. For example, the first scan line SL1 among the plurality of scan lines SL is arranged to overlap with the plurality of second sub-pixels SP2, and the second scan line SL2 among the plurality of scan lines SL is arranged to overlap with the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3. In addition, the plurality of emission control signal lines EL may be arranged adjacent to the first scan line SL1 so as to overlap with the second sub-pixels SP2. Although Figure 13 , it is shown that some of the plurality of wirings are disposed between the plurality of sub-pixels SP and the other wirings overlap the plurality of sub-pixels SP, but the arrangement of the plurality of wirings is not limited thereto.

[0177] The plurality of first patterns 1340 are disposed between the plurality of sub-pixels SP. The plurality of first patterns 1340 may be disposed to correspond to the planar shape of each of the plurality of sub-pixels SP in a plan view. The plurality of first patterns 1340 may be disposed to surround each of the plurality of sub-pixels SP.

[0178] The plurality of first patterns 1340 include a first portion 1341, a second portion 1342, and a first diagonal portion 1343. The first portion 1341 extends in the column direction, the second portion 1342 extends in the row direction, and the first diagonal portion 1343 extends in the diagonal direction. Furthermore, the first portion 1341, the second portion 1342, and the first diagonal portion 1343 are connected to each other to surround the plurality of sub-pixels SP.

[0179] For example, a first portion 1341 of the first pattern 1340, which surrounds the first sub-pixel SP1, overlaps the high-potential power line PL at the left and right sides of the first sub-pixel SP1. A second portion 1342 overlaps the initialization signal line IL at the upper and lower sides of the first sub-pixel SP1. A first diagonal portion 1343 may connect the first portion 1341 and the second portion 1342. At this time, a portion of the first diagonal portion 1343 is separated to reduce the resistance of the cathode 123 and reduce the brightness deviation of the light-emitting diode 1320 due to the voltage drop phenomenon.

[0180] In addition, a first portion 1341 of a first pattern 1340 surrounding the second sub-pixel SP2 among the plurality of first patterns 1340 overlaps the high-potential power line PL on the left and right sides of the second sub-pixel SP2. A second portion 1342 overlaps the initialization signal line IL at the upper and lower sides of the second sub-pixel SP2, and a first diagonal portion 1343 may connect the first portion 1341 and the second portion 1342. In addition, a first portion 1341 of a first pattern 1340 surrounding the third sub-pixel SP3 among the plurality of first patterns 1340 overlaps the high-potential power line PL on the left and right sides of the third sub-pixel SP3. A second portion 1342 overlaps the initialization signal line IL at the upper and lower sides of the third sub-pixel SP3, and a first diagonal portion 1343 may connect the first portion 1341 and the second portion 1342. In addition, a first diagonal portion 1343 surrounding the second subpixel SP2 and a portion of the first diagonal portion 1343 surrounding the third subpixel SP3 are separated to lower the resistance of the cathode 123 and reduce brightness deviation according to a voltage drop phenomenon.

[0181] The plurality of second patterns 1350 are disposed between the plurality of sub-pixels SP. The plurality of second patterns 1350 may be disposed to be spaced apart from the plurality of first patterns 1340. The plurality of second patterns 1350 may be disposed to form closed curves in the spaces between the plurality of second sub-pixels SP2 and in the spaces between the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3.

[0182] The plurality of second patterns 1350 include a third portion 1351, a fourth portion 1352, and a second diagonal portion 1353. The third portion 1351 extends in the column direction, the fourth portion 1352 extends in the row direction, and the second diagonal portion 1353 extends in the diagonal direction. Furthermore, the third portion 1351, the fourth portion 1352, and the second diagonal portion 1353 may be arranged to be connected to each other.

[0183] For example, in the space between the second sub-pixels SP2, among the plurality of second patterns 1350, the third portions 1351 of the second patterns 1350 are arranged to be spaced apart from each other, and the fourth portion 1352 may be arranged to connect the upper and lower ends of the third portions 1351, which are spaced apart from each other. That is, the third portion 1351 and the fourth portion 1352 may form a rectangular shape. Therefore, the portion of the second pattern 1350 having a closed curve formed by the third portion 1351 and the fourth portion 1352 may be arranged in the space between the second sub-pixels SP2.

[0184] In addition, the second diagonal portion 1353 may be arranged to extend toward the second pattern 1350 arranged in a different row or column at the connection position of the third portion 1351 and the fourth portion 1352. For example, the second pattern 1350 formed by the third portion 1351 and the fourth portion 1352 is arranged in one row, and the second diagonal portion 1353 may extend toward the third portion 1351 and the fourth portion 1352 arranged in a row adjacent to the one row at the four connection positions of the third portion 1351 and the fourth portion 1352.

[0185] At this time, the second diagonal portion 1353 may connect the third portion 1351 and the fourth portion 1352 arranged in different rows or columns, or extend between the third portion 1351 and the fourth portion 1352 arranged in different rows or columns, but may not connect the third portion 1351 and the fourth portion 1352 arranged in different rows or columns. For example, the third portion 1351 and the fourth portion 1352 arranged at the upper side of one first sub-pixel SP1 and the third portion 1351 and the fourth portion 1352 arranged at the left side of one first sub-pixel SP1 may be connected by the second diagonal portion 1353. In addition, the second diagonal portion 1353 is provided between the third portion 1351 and the fourth portion 1352 arranged at the upper side of one third sub-pixel SP3 and the third portion 1351 and the fourth portion 1352 arranged at the right side of one third sub-pixel SP3. The second diagonal portion 1353 is connected to the third portion 1351 and the fourth portion 1352 provided at the upper side of the third sub-pixel SP3, and is spaced apart from the third portion 1351 and the fourth portion 1352 provided at the right side of the third sub-pixel SP3. Therefore, a portion of the second diagonal portion 1353 of the second pattern 1350 can be separated to reduce the resistance of the cathode 123 and reduce the brightness deviation due to the voltage drop phenomenon.

[0186] The spacers 1330 are disposed in the spaces between the second sub-pixels SP2 and between the first sub-pixel SP1 and the third sub-pixel SP3. In this case, the second pattern 1350 having a closed curve shape formed by the third portion 1351 and the fourth portion 1352 may not be disposed in the portion where the spacers 1330 are disposed. In other words, the plurality of first patterns 1340 and the plurality of second patterns 1350 may be disposed so as to be spaced apart from the spacers 1330.

[0187] In a display device 1300 according to another exemplary embodiment of the present disclosure, a plurality of first patterns 1340 and a plurality of second patterns 1350 are arranged between a plurality of sub-pixels SP arranged in a lattice formation to reduce the flow of leakage current. The first sub-pixels SP1 and the third sub-pixels SP3 of the plurality of sub-pixels SP may be alternately arranged in the same row and column. Furthermore, the plurality of second sub-pixels SP2 may be arranged in rows and columns different from those of the first sub-pixels SP1 and the third sub-pixels SP3. Thus, the plurality of first sub-pixels SP1, the plurality of second sub-pixels SP2, and the plurality of third sub-pixels SP3 may be arranged to form a lattice formation. In this case, the plurality of first patterns 1340 are arranged to surround the first sub-pixels SP1, the second sub-pixels SP2, and the third sub-pixels SP3, and the plurality of second patterns 1350 are arranged in the empty spaces surrounded by the first sub-pixels SP1, the second sub-pixels SP2, and the third sub-pixels SP3. Therefore, when the display device 1300 is driven, leakage current transmitted to undesired sub-pixels SP can be reduced. The multiple first patterns 1340 increase the length of the common layer, which serves as a path for leakage current to flow, thereby reducing the transmission of leakage current. The multiple second patterns 1350 disconnect at least a portion of the common layer to block the path for leakage current to flow. Therefore, in a display device 1300 according to another exemplary embodiment of the present disclosure, the multiple first patterns 1340 and the multiple second patterns 1350 are arranged between the multiple sub-pixels SP arranged in a lattice pattern. This reduces leakage current flowing to adjacent sub-pixels SP, and minimizes degradation in display quality caused by visual recognition of color anomalies or dot defects.

[0188] Exemplary embodiments of the present disclosure may also be described as follows:

[0189] According to one aspect of the present disclosure, a display device is provided. The display device includes: a substrate defining a plurality of sub-pixels; a plurality of light-emitting diodes disposed in the plurality of sub-pixels and sharing an organic layer and a cathode; a bank disposed between the plurality of light-emitting diodes and below the cathode; a plurality of wirings disposed between the bank and the substrate; and a first pattern disposed in the bank and overlapping at least one of the plurality of wirings. The cathode is disposed in the first pattern.

[0190] The display device may further include at least one insulating layer disposed between the plurality of wirings and the cathode in the first pattern. The cathode in the first pattern may overlap with any one of the plurality of wirings to form a capacitor.

[0191] Any one of the wirings forming a capacitor together with the cathode may be a DC line through which a DC signal is transmitted.

[0192] The display device may further include a second pattern disposed on the bank to be spaced apart from the first pattern.

[0193] The organic layer may include a light emitting layer and a common layer disposed in the plurality of sub-pixels, and resistance of the organic layer may increase as the organic layer approaches the second pattern.

[0194] At least any one of the light emitting layer and the common layer may be disconnected by the second pattern.

[0195] The plurality of wirings may further include an AC line through which an AC signal is transmitted, and at least a portion of the second pattern overlaps the AC line.

[0196] The first pattern and the second pattern may be disposed together between adjacent sub-pixels among the plurality of sub-pixels.

[0197] The plurality of first patterns may be disposed between adjacent sub-pixels among the plurality of sub-pixels.

[0198] The plurality of second patterns may be disposed between adjacent sub-pixels among the plurality of sub-pixels.

[0199] The first pattern may be disposed at one side of one sub-pixel among the plurality of sub-pixels, and the second pattern may be disposed at the other side of the one sub-pixel.

[0200] The first pattern may include a first portion extending in a column direction between the plurality of sub-pixels and a second portion extending in a row direction between the plurality of sub-pixels. The second pattern may include a third portion extending in a column direction between the plurality of sub-pixels and a fourth portion extending in a row direction between the plurality of sub-pixels.

[0201] The first pattern may further include a first diagonal portion extending in a direction different from that of the first and second portions, and the second pattern may further include a second diagonal portion extending in a direction different from that of the third and fourth portions.

[0202] The first pattern may be a trench extending from the bank toward the plurality of wirings, and the second pattern may be a reverse spacer disposed on the bank.

[0203] The second patterns surrounding one sub-pixel among the plurality of sub-pixels may be disposed to be spaced apart from each other.

[0204] The plurality of wirings may further include a dummy line electrically connected to the wiring overlapping the first pattern, and the dummy line may be a wiring having the greatest distance from the substrate (eg, a wiring disposed at an uppermost side) among the plurality of wirings.

[0205] The plurality of sub-pixels may include a first sub-pixel, a second sub-pixel, and a third sub-pixel emitting light of different colors, and the first sub-pixel, the second sub-pixel, and the third sub-pixel may have different turn-on voltages.

[0206] The number of the first patterns disposed between the first subpixel and the third subpixel may be different from the number of the first patterns disposed between the second subpixel and the third subpixel.

[0207] The display device may further include a second pattern disposed between the plurality of sub-pixels and on the bank. The number of second patterns disposed between the first and third sub-pixels may be different from the number of second patterns disposed between the second and third sub-pixels.

[0208] The first subpixel may be a blue subpixel, the second subpixel may be a green subpixel, and the third subpixel may be a red subpixel.

[0209] According to another aspect of the present disclosure, a display device is provided, including: a substrate in which a plurality of sub-pixels are defined; a plurality of light-emitting diodes, the plurality of light-emitting diodes are arranged in the plurality of sub-pixels, the plurality of light-emitting diodes having an organic layer shared between the plurality of light-emitting diodes and a cathode electrode shared between the plurality of light-emitting diodes; a dam, the dam being arranged between pairs of light-emitting diodes among the plurality of light-emitting diodes and below the cathode electrode; a plurality of wirings, the plurality of wirings being arranged between the dam and the substrate; and a first pattern, the first pattern passing through a thickness of the dam and overlapping with a first wiring among the plurality of wirings, wherein a first portion of the cathode electrode is arranged outside the first pattern, and a second portion of the cathode electrode is arranged in the first pattern.

[0210] The display device may further include: at least one insulating layer, at least one insulating layer being arranged between the plurality of wirings and the second portion of the cathode electrode arranged in the first pattern, wherein the second portion of the cathode electrode arranged in the first pattern overlaps with the first wiring, and a capacitor is formed between the second portion of the cathode electrode and the first wiring.

[0211] The first wiring overlapping the second portion of the cathode electrode may transmit a direct current (DC) signal.

[0212] The display device may further include: a second pattern disposed on the bank and spaced apart from the first pattern.

[0213] The organic layer may include a common layer arranged in a plurality of sub-pixels and a plurality of different light-emitting layers each emitting light of a different color, wherein the common layer is shared between the plurality of sub-pixels, wherein a first resistance of a first portion of the organic layer closer to the second pattern is greater than a second resistance of a second portion of the organic layer farther away from the second pattern than the first portion.

[0214] A portion of at least one of the light emitting layer and the common layer may be disconnected from another portion of at least one of the light emitting layer and the common layer by the second pattern.

[0215] The plurality of wirings may further include a second wiring overlapping at least a portion of the second pattern, wherein the second wiring transmits an alternating current (AC) signal.

[0216] The first pattern and the second pattern may be disposed between adjacent sub-pixels among the plurality of sub-pixels.

[0217] The plurality of first patterns may be disposed between adjacent sub-pixels among the plurality of sub-pixels.

[0218] The plurality of second patterns may be disposed between adjacent sub-pixels among the plurality of sub-pixels.

[0219] The first pattern may be disposed at a first side of a first subpixel among the plurality of subpixels, and the second pattern may be disposed at a second side of the first subpixel.

[0220] The first pattern may include: a first portion extending along a first direction between multiple sub-pixels; and a second portion extending along a second direction different from the first direction between the multiple sub-pixels, wherein the second pattern may include: a third portion extending along the first direction between the multiple sub-pixels; and a fourth portion extending along the second direction between the multiple sub-pixels.

[0221] The first pattern may further include a first diagonal portion between the first portion and the second portion, the first diagonal portion extending along a third direction different from the first direction and the second direction, wherein the second pattern may further include a second diagonal portion between the third portion and the fourth portion, the second diagonal portion extending along the third direction.

[0222] The first pattern may be a trench extending through the bank toward the first wiring, and the second pattern may be a reverse spacer disposed on the bank.

[0223] The display device may further include: a plurality of second patterns, the plurality of second patterns at least partially surrounding one sub-pixel among the plurality of sub-pixels, the plurality of second patterns being spaced apart from each other.

[0224] The display device may further include a dummy line electrically connected to the first wiring, the dummy line overlapping the first pattern and being closer to the first pattern than the first wiring.

[0225] The plurality of sub-pixels may include a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors, wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel have different turn-on voltages.

[0226] The number of the first patterns disposed between the first subpixel and the third subpixel may be different from the number of the first patterns disposed between the second subpixel and the third subpixel.

[0227] The display device may further include: second patterns arranged between the plurality of sub-pixels and on the embankment, wherein the number of second patterns arranged between the first sub-pixel and the third sub-pixel is different from the number of second patterns arranged between the second sub-pixel and the third sub-pixel.

[0228] According to another aspect of the present disclosure, a display device may be provided, comprising: a substrate in which a plurality of sub-pixels are defined; a plurality of light-emitting diodes, the plurality of light-emitting diodes being arranged in the plurality of sub-pixels, the plurality of light-emitting diodes having an organic layer shared between the plurality of light-emitting diodes and a cathode electrode shared between the plurality of light-emitting diodes; a dam, the dam being arranged between pairs of light-emitting diodes among the plurality of light-emitting diodes and below the cathode electrode; and a wiring, the wiring being arranged between the dam and the substrate, wherein a first portion of the cathode electrode overlapping with the wiring is closer to the wiring than a second portion of the cathode electrode not overlapping with the wiring.

[0229] The display device may further include a first pattern disposed through a thickness of the bank, wherein a first portion of the cathode electrode is disposed in the first pattern through the bank, and a second portion of the cathode electrode is disposed outside the first pattern.

[0230] The display device may further include: an additional first pattern passing through a thickness of the bank, wherein the cathode electrode includes a third portion disposed in the additional first pattern and overlapping the wiring overlapping the first portion of the cathode electrode.

[0231] The first pattern may be a groove extending through the bank toward the wiring.

[0232] The wiring overlapping the first portion of the cathode electrode may transmit a direct current (DC) signal.

[0233] The DC signal may be a power signal.

[0234] According to another aspect of the present disclosure, a display device is provided, including: a substrate, in which a plurality of sub-pixels are defined; a plurality of quantum dot light-emitting diodes, which are arranged in the plurality of sub-pixels and share a light-emitting layer, a common layer and a cathode; a embankment, which is arranged between the plurality of quantum dot light-emitting diodes and below the cathode; a plurality of wirings, which are arranged between the embankment and the substrate; and a first pattern, which is arranged in the embankment and overlaps with at least one of the plurality of wirings, wherein the cathode is arranged in the first pattern.

[0235] The display device may further include: a second pattern disposed on the bank to be spaced apart from the first pattern.

[0236] The common layer may include at least one of a charge generation layer, a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0237] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and the present disclosure can be implemented in many different forms without departing from the technical concepts of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concepts of the present disclosure. The scope of the technical concepts of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device comprising: a substrate having a plurality of sub-pixels defined therein; a plurality of light emitting diodes, the plurality of light emitting diodes being disposed in the plurality of sub-pixels, the plurality of light emitting diodes having an organic layer shared among the plurality of light emitting diodes and a cathode electrode shared among the plurality of light emitting diodes; a bank disposed between pairs of light-emitting diodes among the plurality of light-emitting diodes and below the cathode electrode; a plurality of wirings disposed between the bank and the substrate; as well as a first pattern, the first pattern being a groove formed between the plurality of sub-pixels, the first pattern passing through a thickness of the bank and overlapping a first wiring among the plurality of wirings; wherein a first portion of the cathode electrode is disposed outside the first pattern, and a second portion of the cathode electrode is disposed within the first pattern; Wherein, the first pattern includes: a first portion extending along a first direction between the plurality of sub-pixels; and A second portion extends between the plurality of sub-pixels along a second direction, the second direction being different from the first direction.

2. The display device according to claim 1, further comprising: at least one insulating layer disposed between the plurality of wirings and a second portion of the cathode electrode disposed in the first pattern, The second portion of the cathode electrode disposed in the first pattern overlaps with the first wiring, and a capacitor is formed between the second portion of the cathode electrode and the first wiring.

3. The display device according to claim 2, wherein: The first wiring overlapping the second portion of the cathode electrode transmits a direct current (DC) signal.

4. The display device according to claim 2, further comprising: a second pattern disposed on the bank and spaced apart from the first pattern, The second pattern is a reverse spacer disposed on the bank and having a width that narrows from an upper portion to a lower portion.

5. The display device according to claim 4, wherein The organic layer includes a common layer provided in the plurality of sub-pixels and a plurality of different light-emitting layers each emitting light of a different color, wherein the common layer is shared between the plurality of sub-pixels, The first resistance of a first portion of the organic layer closer to the second pattern is greater than the second resistance of a second portion of the organic layer farther from the second pattern than the first portion. The display device according to claim 5 , wherein: A portion of at least one of the light emitting layer and the common layer is disconnected from another portion of the at least one of the light emitting layer and the common layer by the second pattern.

7. The display device according to claim 4, wherein The plurality of wirings further includes a second wiring overlapping at least a portion of the second pattern, wherein the second wiring transmits an alternating current (AC) signal.

8. The display device according to claim 4, wherein The first pattern and the second pattern are disposed between adjacent sub-pixels among the plurality of sub-pixels.

9. The display device according to claim 4, wherein: A plurality of first patterns are disposed between adjacent sub-pixels among the plurality of sub-pixels.

10. The display device according to claim 4, wherein A plurality of second patterns are disposed between adjacent sub-pixels among the plurality of sub-pixels.

11. The display device according to claim 4, wherein The first pattern is disposed at a first side of a first subpixel among the plurality of subpixels, and the second pattern is disposed at a second side of the first subpixel.

12. The display device according to claim 4, wherein The second pattern includes: a third portion extending along the first direction between the plurality of sub-pixels; and A fourth portion extends along the second direction between the plurality of sub-pixels.

13. The display device according to claim 12, wherein: The first pattern further includes a first diagonal portion between the first portion and the second portion, the first diagonal portion extending in a third direction different from the first direction and the second direction, and The second pattern further includes a second diagonal portion between the third portion and the fourth portion, and the second diagonal portion extends along the third direction.

14. The display device according to claim 4, wherein The first pattern is a groove extending through the bank toward the first wiring.

15. The display device according to claim 14, further comprising: A plurality of second patterns at least partially surround one sub-pixel among the plurality of sub-pixels, and the plurality of second patterns are spaced apart from each other. 16 . The display device according to claim 1 , further comprising a dummy line electrically connected to the first wiring, the dummy line overlapping the first pattern and being closer to the first pattern than the first wiring.

17. The display device according to claim 1, wherein The plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors, wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel have different turn-on voltages.

18. The display device according to claim 17, wherein: The number of first patterns disposed between the first sub-pixel and the third sub-pixel is different from the number of first patterns disposed between the second sub-pixel and the third sub-pixel.

19. The display device according to claim 17, further comprising: a second pattern, the second pattern being disposed between the plurality of sub-pixels and on the bank, The number of the second patterns arranged between the first sub-pixel and the third sub-pixel is different from the number of the second patterns arranged between the second sub-pixel and the third sub-pixel.

20. A display device comprising: a substrate having a plurality of sub-pixels defined therein; a plurality of light emitting diodes, the plurality of light emitting diodes being disposed in the plurality of sub-pixels, the plurality of light emitting diodes having an organic layer shared among the plurality of light emitting diodes and a cathode electrode shared among the plurality of light emitting diodes; a bank disposed between pairs of light emitting diodes among the plurality of light emitting diodes and below the cathode electrode; a wiring provided between the bank and the substrate, and a first pattern, the first pattern being a groove formed between the plurality of sub-pixels, the first pattern passing through a thickness of the bank and overlapping the wiring; wherein a first portion of the cathode electrode overlapping with the wiring is closer to the wiring than a second portion of the cathode electrode not overlapping with the wiring, wherein the first portion of the cathode electrode is disposed in the first pattern through the bank, and the second portion of the cathode electrode is disposed outside the first pattern; Wherein, the first pattern includes: a first portion extending along a first direction between the plurality of sub-pixels; and A second portion extends between the plurality of sub-pixels along a second direction, the second direction being different from the first direction.

21. The display device according to claim 20, further comprising: and an additional first pattern extending through the thickness of the embankment, the additional first pattern being a groove formed between the plurality of sub-pixels, wherein the cathode electrode includes a third portion disposed in the additional first pattern and overlapping with a wiring that overlaps with the first portion of the cathode electrode.

22. The display device according to claim 20, wherein The first pattern is a groove extending through the bank toward the wiring.

23. The display device according to claim 20, wherein The wiring overlapping the first portion of the cathode electrode transmits a direct current (DC) signal.

24. The display device according to claim 23, wherein The DC signal is a power signal.

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