Dynamic range control circuit, audio processing chip and audio processing method thereof

Abstract

The present invention discloses a dynamic range control circuit, an audio processing chip and an audio processing method thereof, which have a first gain branch, a second gain branch and an output module. The first gain branch includes a plurality of first gain generation modules connected in series. The second gain branch includes a plurality of second gain generation modules connected in parallel. The output module is used to output target data based on the output gain of the first gain branch, the output gain of the second gain branch and the initial input data. The first gain generation module and the second gain generation module each have a separate gain generator and a gain smoothing processing module. It can be seen that in each gain generation module, different compression times and release times can be set through their respective smoothing processing modules, so that the compression times and release times of different gain generation modules are separated, which can greatly improve the tuning of the audio amplifier and the user's auditory experience.

Description

Technical Field

[0001] The present invention relates to the field of sound processing technology, and more particularly to a dynamic range control circuit, an audio processing chip and an audio processing method thereof. Background Art

[0002] Dynamic Range Control (DRC) is an algorithm commonly used for sound volume control. It performs different processing within different energy ranges. The noise removal effector (Noise Gate), expander (Expander), compressor (Compressor) and limiter are the four node modules in the system with energy levels from low to high.

[0003] During DRC processing, the input data needs to be gain adjusted and smoothed. Conventional technology only allows one gain adjustment method to be selected for each process, and there is only one smoothing module. Only one attack time or release time can be set, making it impossible to separate independent attack times or release times based on different gain settings. Summary of the Invention

[0004] In view of this, the present application provides a dynamic range control circuit, an audio processing chip and an audio processing method thereof, the scheme is as follows:

[0005] A dynamic range control circuit, comprising:

[0006] A first gain branch, the first gain branch comprising a plurality of first gain generation modules connected in series;

[0007] A second gain branch, the second gain branch comprising a plurality of second gain generating modules connected in parallel;

[0008] an output module, configured to output target data based on an output gain of the first gain branch, an output gain of the second gain branch, and initial input data;

[0009] Among them, the first gain generation module and the second gain generation module each have a separate gain generator and a gain smoothing processing module; in the same gain generation module, the gain generator is used to perform gain processing on the input signal received by the corresponding gain generation module, and the gain smoothing processing module is used to set the compression time and release time based on the output gain of the gain generator.

[0010] Preferably, in the above-mentioned dynamic range control circuit, the first gain branch is used to generate input signals of each second gain generation module based on the output gain of each first gain generation module and the amplitude of the initial input data.

[0011] Preferably, in the above dynamic range control circuit, the first gain branch has N first gain generation modules connected in series, the N first gain generation modules in series are, in sequence, the first gain generation module of the first stage to the first gain generation module of the N stage, where N is a positive integer greater than 1; the first gain generation module of the i-th stage has an i-th stage output gain, where i is a positive integer not greater than N;

[0012] If i=1, the first gain generation module of the first stage outputs the first stage output gain based on the amplitude of the initial input data;

[0013] If i>1, the i-th stage first gain generating module outputs the i-th stage output gain based on the amplitude of the initial input data and the 1st stage output gain to the (i-1)th stage output gain.

[0014] Preferably, in the above dynamic range control circuit, the first gain branch has N first gain generation modules connected in series, and the N first gain generation modules connected in series are, in sequence, the first gain generation module of the first stage to the first gain generation module of the N stage, where N is a positive integer greater than 1;

[0015] The first gain branch further includes: N-1 cascaded first adders, the N-1 first adders being sequentially from the 1st stage first adder to the N-1th stage first adder;

[0016] Among them, the first adder of the jth stage is used to calculate the sum of the output gains of all the first gain generation modules of the previous j stages and the amplitude of the initial input data as the input signal of the first gain generation module of the j+1th stage, and j is a positive integer not greater than N-1.

[0017] Preferably, in the above dynamic range control circuit, the first gain branch has N first gain generation modules connected in series, and the N first gain generation modules connected in series are, in sequence, the first gain generation module of the first stage to the first gain generation module of the N stage, where N is a positive integer greater than 1;

[0018] The first gain branch further includes: N-1 cascaded second adders, the N-1 second adders being sequentially from the first-stage second adder to the N-1-stage second adder;

[0019] Among them, the second adder of the first stage is used to calculate the sum of the output gain of the first gain generation module of the first stage and the output gain of the first gain generation module of the second stage; the second adder of the jth stage is used to calculate the sum of the output gain of the second adder of the j-1th stage and the output gain of the first gain module of the j+1th stage, where j is a positive integer greater than 1 and not greater than N-1.

[0020] Preferably, in the above dynamic range control circuit, the second gain branch includes M parallel second gain generation modules and a comparator, where M is a positive integer greater than 1;

[0021] The input signals of the second gain generation module are all the sum of the amplitude of the initial input data and the output gains of all the first gain generation modules;

[0022] The comparator is used to compare the output gains of the M second gain generation modules and select the smallest output gain as the output gain of the second gain branch.

[0023] Preferably, in the above-mentioned dynamic range control circuit, if the output gain of each gain generation module belongs to the logarithmic domain, the first gain branch is used to calculate the sum of the output gains of all first gain generation modules and the amplitude of the initial input data, and use the sum as the input signal of each second gain generation module.

[0024] Preferably, in the above-mentioned dynamic range control circuit, the output module is used to calculate the sum of the output gains of the two gain branches, calculate the linear domain value of the sum based on antilogarithmic operation, calculate the product of the linear domain value and the initial input data, and use the product as the target data.

[0025] Preferably, in the above-mentioned dynamic range control circuit, if the output gain of each gain generation module belongs to the linear domain, the first gain branch is used to calculate the product of the output gains of all first gain generation modules and use the product as the input signal of each second gain generation module.

[0026] Preferably, in the above dynamic range control circuit, the output module is used to calculate the product of the output gains of the two gain branches and the initial input data, and use the product as the target data.

[0027] Preferably, in the above dynamic range control circuit, the gain generator is a compressor, which is used to start suppressing the input signal when its input signal exceeds a first threshold value, so as to output the output gain of the gain generator to which it belongs;

[0028] The degree of suppression of the output gain relative to the input signal is related to a first proportional parameter, and the smoothness of the output gain relative to the input signal is related to a first smooth transition parameter.

[0029] Preferably, in the above-mentioned dynamic range control circuit, the gain generator is a limiter, which is used to suppress the input signal to a fixed amplitude signal with an amplitude of the second threshold when the input signal exceeds the second threshold, so as to output the output gain of the gain generator to which it belongs;

[0030] The smoothness of the output gain relative to the input signal is related to a second smooth transition parameter.

[0031] Preferably, in the above-mentioned dynamic range control circuit, the gain generator is a noise removal effector, which is used to start suppressing the input signal when its input signal is less than a third threshold value to output the output gain of the gain generator to which it belongs;

[0032] The degree of suppression of the output gain relative to the input signal is related to a second proportional parameter, and the smoothness of the output gain relative to the input signal is related to a third smooth transition parameter.

[0033] Preferably, in the above-mentioned dynamic range control circuit, the gain generator is an expander, which is used to start amplifying the input signal based on the set compensation gain and the third proportional parameter when the input signal thereof exceeds the fourth threshold value, so as to output the output gain of the gain generator to which it belongs;

[0034] The smoothness of the output gain relative to the input signal is related to a fourth smooth transition parameter.

[0035] The present invention also provides an audio processing chip, comprising:

[0036] A dynamic range control circuit as described in any one of the above.

[0037] The present invention also provides an audio processing method of an audio processing chip, wherein the dynamic range control circuit in the audio processing chip has a first gain branch and a second gain branch, the first gain branch includes a plurality of first gain generation modules connected in series, and the second gain branch includes a plurality of second gain generation modules connected in parallel;

[0038] The audio processing method comprises:

[0039] Each gain generation module performs gain processing on the input signal it obtains to form an output gain, and sets the compression time and release time based on its own output gain;

[0040] Target data is output based on the output gains of the gain generation modules at each stage and the initial input data of the dynamic range control circuit.

[0041] Preferably, in the above audio processing method, if the output gain of each gain generation module belongs to the logarithmic domain, the method of outputting the target data includes:

[0042] The sum of the output gains of the two gain branches is calculated, a linear domain value of the sum is calculated based on an antilogarithmic operation, the product of the linear domain value and the initial input data is calculated, and the product is used as the target data.

[0043] Preferably, in the above audio processing method, if the output gain of each gain generation module belongs to the linear domain, the method of outputting the target data includes:

[0044] The product of the output gains of the two gain branches and the initial input data is calculated, and the product is used as the target data.

[0045] It can be seen from the above description that the dynamic range control circuit, audio processing chip and audio processing method provided by the technical solution of the present invention have a first gain branch, a second gain branch and an output module. The first gain branch includes a plurality of first gain generation modules connected in series. The second gain branch, the second gain branch includes a plurality of second gain generation modules connected in parallel. The output module is used to output target data based on the output gain of the first gain branch, the output gain of the second gain branch and the initial input data. The first gain generation module and the second gain generation module each have a separate gain generator and a gain smoothing processing module. It can be seen that in each gain generation module, different compression times and release times can be set through their respective smoothing processing modules, so that the compression times and release times of different gain generation modules are separated, which can greatly improve the tuning of the audio power amplifier and the user's auditory experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0047] The structures, proportions, sizes, etc. depicted in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not intended to limit the conditions under which the present invention can be implemented and therefore have no substantive technical significance. Any structural modifications, changes in proportional relationships, or adjustments in size should still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and objectives that can be achieved by the present invention.

[0048] Figure 1 It is a structural diagram of a conventional DRC circuit;

[0049] Figure 2 A DRC circuit provided by an embodiment of the present invention;

[0050] Figure 3 A schematic structural diagram of a first gain branch provided by an embodiment of the present invention;

[0051] Figure 4 A schematic structural diagram of a second gain branch provided by an embodiment of the present invention;

[0052] Figure 5 A schematic structural diagram of another DRC circuit provided by an embodiment of the present invention;

[0053] Figure 6 is a gain conversion curve of the compressor in the DRC circuit according to an embodiment of the present invention;

[0054] Figure 7 is a gain conversion curve of the limiter in the DRC circuit according to an embodiment of the present invention;

[0055] Figure 8 is a gain conversion curve of the noise removal effector in the DRC circuit according to an embodiment of the present invention;

[0056] Figure 9 is a gain conversion curve of the expander in the DRC circuit according to an embodiment of the present invention;

[0057] Figure 10 A comparison diagram of input and output data in the entire DRC circuit provided by an embodiment of the present invention;

[0058] Figure 11 A flowchart of an audio processing method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0059] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0060] In the tuning and protection algorithms of digital audio amplifiers, different gain levels are required for input signals of different amplitudes to ensure that large signals do not exceed the speaker's tolerance range; the energy of small and medium signals is enhanced to increase the perceived loudness of the sound; and noise is effectively suppressed to improve the signal-to-noise ratio of the sound.

[0061] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a conventional DRC circuit. Figure 1 In the method shown, the input signal is amplitude-detected by a peak calculation module or a root mean square calculation module to obtain the real-time amplitude of the input signal. The over-interval judgment module selects gain processing through a noise removal effector, expander, compressor or limiter. The processed signal is smoothed by a smoothing processing module and then multiplied with the input signal processed by the delay module through a multiplier to generate an output signal.

[0062] The inventors discovered that Figure 1 In the method shown, each data processing process can only select one gain processing method through the interval judgment module, and each gain processing path uses the same smoothing processing module. Only one compression time and release time can be set, and the time separation and independence of compression time and release time for different gain adjustments cannot be achieved.

[0063] To address the above issues, an embodiment of the present invention provides a DRC circuit that can perform multiple corresponding processing operations on initial input data using multiple first gain generation modules connected in series and multiple second gain generation modules connected in parallel. The gain generator in any gain generation module can be any of a limiter, compressor, expander, and noise removal effector. The two gain branches implement multi-node gain adjustment, and each gain generation module has an independent gain smoothing processing module, making the timing of each gain generation module independent of each other. The DRC circuit has a simple structure and saves computational effort.

[0064] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0065] like Figure 2 As shown, Figure 2A DRC circuit is provided in an embodiment of the present invention, comprising: a first gain branch 01, wherein the first gain branch 01 includes a plurality of first gain generation modules 11 connected in series; a second gain branch 02, wherein the second gain branch 02 includes a plurality of second gain generation modules 21 connected in parallel; and an output module 12, wherein the output module 12 is configured to output target data Dout based on the output gain of the first gain branch 01, the output gain of the second gain branch 02, and initial input data Din.

[0066] Among them, the first gain generation module 11 and the second gain generation module 21 each have a separate gain generator 111 and a gain smoothing processing module 112; in the same gain generation module, the gain generator 111 is used to perform gain processing on the input signal, and the gain smoothing processing module 112 is used to set the compression time and release time of the corresponding gain generation module based on the output gain of the gain generator 111.

[0067] In the DRC circuit described in the embodiment of the present invention, the first gain branch 01 is used to generate input signals of each second gain generation module 21 based on the output gain of each first gain generation module 11 and the amplitude Adin of the initial input data Din.

[0068] In the DRC circuit described in this embodiment of the present invention, the first gain generation modules 11 in the first gain branch 01 are internally connected in series, while the second gain generation modules 21 in the second gain branch 02 are internally connected in parallel. Each gain generation module has an independent gain smoothing processing module 112. The output module 21 outputs the desired target data Dout based on the output gains of the two branches. Each gain generation module can be configured with a different compression time and release time. The separation of compression and release times for different gain generation modules provides greater flexibility and applicability in digital audio signal processing, significantly improving both the tuning of digital audio providers and the subjective listening experience of users.

[0069] In the first gain generation module 11, the gain generator (Gain Computer) 111 is any one of a limiter, a compressor, an expander, and a noise removal effector. In the second gain generation module 21, the gain generator 111 is any one of a limiter, a compressor, an expander, and a noise removal effector. The DRC circuit described in this embodiment of the present invention may include one, two, three, or four of these.

[0070] In the DRC circuit described in the embodiment of the present invention, the number of gain generation modules is not limited to four. The number of first gain generation modules 11 in the first gain branch 01 and the number of second gain generation modules 21 in the second gain branch 02 can be set based on requirements. A single gain branch can include one, two, three, or four of the following: a limiter, a compressor, an expander, and a noise removal effector. Furthermore, the cascade order of the gain generation modules in the same gain branch can be adjusted arbitrarily.

[0071] The DRC circuit structure and working principle are described below by taking the output gain of each gain generation module in the first gain branch 01 and the second gain branch 02 as an example, both of which are in the logarithmic domain (ie, the log domain).

[0072] If the output gains of each gain generation module belong to the logarithmic domain, the first gain branch 01 is used to calculate the sum of the output gains of all first gain generation modules 11 and the amplitude Adin of the initial input data Din, and use the sum as the input signal of each second gain generation module 21.

[0073] The output module 12 is used to calculate the sum of the output gains of the two gain branches, calculate the linear domain value of the sum based on antilogarithmic operation, calculate the product of the linear domain value and the initial input data Din, and use the product as the target data Dout. If the output gain of the first gain branch O1 is set to OUT1 and the output gain of the second gain branch O2 is set to OUT2, the final target data Dout is calculated as follows:

[0074] First, calculate the sum of the output gains of the two gain branches S1 = OUT1 + OUT2;

[0075] Then, the linear domain value S1' corresponding to the sum value S1 is calculated.

[0076] Finally, the target data Dout=S1'*Din is calculated.

[0077] like Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of a first gain branch provided by an embodiment of the present invention. The first gain branch 01 has N first gain generation modules 11 connected in series. The N first gain generation modules 11 are sequentially connected from the first-stage first gain generation module to the N-stage first gain generation module, where N is a positive integer greater than 1. The i-th-stage first gain generation module has an i-th-stage output gain Gain(i), where i is a positive integer not greater than N. The output gain of the first gain branch 01 is the sum of the output gains of all the first gain generation modules 11, that is, OUT1, which can be expressed as follows:

[0078] OUT1=Gain(1)+Gain(2)+…+Gain(N).

[0079] In this embodiment of the present invention, the output gain Gain and amplitude Adin are both in the log domain for illustration, while the initial input data Din is in the linear domain. Therefore, based on the above equation, the output gains of all first gain generation modules 11 are summed to form OUT1. The sum S1 of OUT1 and OUT2 is then calculated, and the linear domain value S1' corresponding to this sum S1 is calculated. The product of S1' and Din is used as the target data Dout. The unit of the log domain is dB, and summing in the log domain is equivalent to multiplication in the linear domain.

[0080] like Figure 3 As shown, the DRC circuit also includes an amplitude detection module 13 for performing amplitude detection on the initial input data Din to obtain the amplitude Adin of the initial input data Din. After the initial input data Din is input into the DRC circuit, it first passes through the amplitude detection module 13 to detect the magnitude of its amplitude Adin in real time. The amplitude detection module 13 then sends the amplitude Adin to each first gain generation module 11 in the first gain branch O1. The amplitude detection module 13 may include: a peak calculation module for detecting the peak value of the initial input data Din; and / or a root mean square calculation module for calculating the root mean square value (RMS) of the initial input data Din. The method for obtaining the amplitude Adin of the initial input data Din can be set based on demand and is not specifically limited in this embodiment of the present invention.

[0081] If i=1, the first-stage first gain generation module outputs the first-stage output gain Gain(1) based on the amplitude Adin of the initial input data Din. If i>1, the i-th-stage first gain generation module outputs the i-th-stage output gain Gain(i) based on the amplitude Adin of the initial input data Din and the first-stage output gain Gain(1) to the i-1-th-stage output gain Gain(i-1).

[0082] If the first gain branch 01 has N first gain generation modules 11 connected in series, the first gain branch 01 further includes: N-1 cascaded first adders 14, and the N-1 first adders 14 are sequentially from the first adder of the 1st stage to the first adder of the N-1th stage; wherein the first adder of the jth stage is used to calculate the sum of the output gains of all the first gain generation modules 11 of the previous j stages and the amplitude Adin of the initial input data Din as the input signal of the first gain generation module of the j+1th stage, where j is a positive integer not greater than N-1.

[0083] The sum of the output gains of all the first gain generation modules 11 in the previous stage plus the amplitude Adin of the initial input data Din is used as the input signal of the first gain generation module 11 in the next stage. For example, the input signal of the first gain generation module in the i-th stage is Gain(1)+Gain(2)+…+Gain(i-1)+Adin. Figure 3 As shown, the first adder of the first stage is used to calculate Gain(1)+Adin, which is used as the input signal of the first gain generation module of the second stage. The first adder of the second stage is used to calculate Gain(1)+Gain(2)+Adin, which is used as the input signal of the first gain generation module of the third stage. ..., the first adder of the N-1 stage is used to calculate Gain(1)+Gain(2)+...+Gain(N-1)+Adin, which is used as the input signal of the first gain generation module of the N stage. The input signal of the first gain generation module of the first stage is the amplitude Adin of the initial input data Din.

[0084] If the first gain branch 01 has N first gain generation modules 11 connected in series, the first gain branch 01 also includes: N-1 cascaded second adders 15, and the N-1 second adders 15 are sequentially from the 1st-stage second adder to the N-1th-stage second adder; wherein the 1st-stage second adder is used to calculate the sum of the output gain Gain(1) of the 1st-stage first gain generation module and the output gain Gain(2) of the 2nd-stage first gain generation module; the jth-stage second adder is used to calculate the sum of the output gain Gain(j-1) of the j-1th-stage second adder and the output gain Gain(j+1) of the j+1th-stage first gain module, where j is a positive integer greater than 1 and not greater than N-1.

[0085] If i is greater than 1, for the first gain generation module of the i-th stage, there is a corresponding second adder 15, which is used to calculate the sum of the output gain Gain(i) of the first gain generation module of the i-th stage and the output gains of all the first gain generation modules of the previous i-1 stages, that is, to calculate Gain(i)+(Gain(1)+Gain(2)+…+Gain(i-1)).

[0086] The first gain branch further includes a third adder 16, which is used to calculate the sum of the output gains of all first gain generation modules 11 and the amplitude Adin of the initial input data Din as the input signal VIN of the second gain branch O2, that is:

[0087] VIN=Gain(1)+Gain(2)+…+Gain(N)+Adin=OUT1+Adin

[0088] like Figure 4 As shown, Figure 4This is a schematic diagram of the structure of a second gain branch provided in an embodiment of the present invention. The second gain branch 02 includes M parallel second gain generation modules 21 and a comparator 22, where M is a positive integer greater than 1. The input signal of each second gain generation module 21 is the sum of the amplitude of the initial input data and the output gains of all first gain generation modules 11, that is, the input signal of each second gain generation module 21 is VIN. The comparator 22 is used to compare the output gains of the M second gain generation modules 21 and select the smallest output gain as the output gain OUT2 of the second gain branch.

[0089] In the first gain branch 01, the gain generators 111 of the first gain generation modules 11 are not completely identical. Preferably, the gain generators 111 of the first gain generation modules 11 are set to be different from each other. In the second gain branch 02, the gain generators 111 of the second gain generation modules 21 are not completely identical. Preferably, the gain generators 111 of the second gain generation modules 21 are set to be different from each other.

[0090] If the first gain branch 01 has two first gain generating modules 11 connected in series, and the second gain branch 02 has two second gain generating modules 12 connected in parallel, the structure of the DRC circuit is as follows: Figure 5 As shown, Figure 5 A structural diagram of another DRC circuit provided by an embodiment of the present invention, based on Figure 2-Figure 4 As shown, Figure 5 In the DRC circuit shown, the structure and connection of the first gain branch 01 and the second gain branch 02 can be referred to Figure 2-Figure 4 The method shown will not be repeated here.

[0091] The output module 12 includes a fourth adder 17 and a multiplier 18 . The fourth adder 17 is used to calculate OUT1 + OUT2 . The multiplier 18 is used to calculate Din* = S1 ′ as the output gain Dout of the DRC circuit.

[0092] Figure 5 In the illustrated embodiment, the two gain generators 111 in the first gain branch 01 can be set as an expander and a compressor respectively, and the two gain generators 111 in the second gain branch 02 can be set as a noise removal effector and a limiter respectively. Figure 5 In the illustrated approach, the expander and compressor are connected in series, while the limiter and noise reduction effector are connected in parallel. Each gain generator 111 has an independent gain smoothing module 112, which can be configured with different compression and release times. Separating these compression and release times significantly improves the tuning and subjective listening experience of digital audio amplifiers.

[0093] In the first gain branch 01, the output gain of the previous first gain generation module 11 and the amplitude Adin of the initial input data Din are used as the input signal of the next first gain generation module 11. The input signal of the first first gain module 11 is the amplitude Adin of the initial input data Din. Figure 5 As shown, the sum of the first-stage output gain Gain (1) and the amplitude Adin of the initial input data Din serves as the input signal to the compressor. The sum of the output gains (gains) of the first gain generation module 11 is superimposed on the output gain OUT2 of the second gain branch to obtain the sum S1. The linear domain value S1' corresponding to S1 is obtained through antilogarithmic operation. S1' is multiplied by the initial input data Din (standard value) to obtain Dout.

[0094] Dout=S1'*Din

[0095] In the second gain branch 02, the input signals of the two second gain generation modules 21 are the same, both VIN=OUT1+OUT2+Adin, and the two output gains corresponding to the two second gain generation modules 21 are GAIN3 and GAIN4 respectively. The output gain of the second gain branch 02 is the minimum value of GAIN3 and GAIN4, that is, OUT2=min(GAIN3, GAIN4).

[0096] It should be noted that the number and cascade order of the gain generators in each gain branch can be set based on demand and are not limited to the method described in the embodiment of the present invention. Any number of first gain generation modules 11 can be connected in series in the first gain branch 01. The output gain OUT1 of the first gain branch 01 is the sum of the output gains of all the first gain generation modules 11. That is, if there are N first gain generation modules 11, OUT1 is expressed as follows:

[0097] OUT1=Gain(1)+Gain(2)+…+Gain(N)

[0098] Any number of second gain generation modules 21 can be connected in parallel in the second gain branch 02. The output gain OUT2 of the second gain branch 02 is the minimum output gain selected from all the second gain generation modules 21. The minimum output gain among all the parallel second gain generation modules 21 is used as the output gain OUT2 of the second gain branch 02. That is, if there are M second gain generation modules 21, OUT2 is expressed as follows:

[0099] OUT2=min(GAIN1,GAIN2,…,GAINM)

[0100] The above description uses the example of the output gain Gain and amplitude Adin of each level in the log domain to illustrate the implementation of the DRC circuit in the embodiment of the present invention. Obviously, the DRC circuit implementation corresponding to the linear domain can be obtained by making corresponding substitutions based on the log domain.

[0101] If the output gains of the various gain generation modules belong to the linear domain, the first gain branch 01 is used to calculate the product of the output gains of all the first gain generation modules 11 and use the product as the input signal of each of the second gain generation modules 21 .

[0102] The output module 12 is used to calculate the product of the output gains of the two gain branches and the initial input data, and use the product as the target data Dout.

[0103] That is to say, based on the linear domain conditions of the output gain Gain and amplitude Adin, if the output gain of each gain generation module belongs to the linear domain:

[0104] OUT1=Gain(1)*Gain(2)*…*Gain(N)

[0105] OUT2=min(GAIN1,GAIN2,…,GAINM)

[0106] Dout=Din*OUT1*OUT2

[0107] The following describes the working principles of the limiter, compressor, expander, and noise removal effector in the DRC circuit and a comparison of their input and output gains.

[0108] The gain generator 111 is a compressor, including three parameters: a first threshold Threshold1, a first proportional parameter Ratio1, and a first smooth transition parameter Knee1. The compressor is used to start suppressing the input signal when its input signal exceeds the first threshold Threshold1, so as to output the output gain of the gain generator 111 to which it belongs; wherein, the degree of suppression of the output gain relative to the input signal is related to the first proportional parameter Ratio1, and the smoothness of the output gain relative to the input signal is related to the first smooth transition parameter Knee1. The first proportional parameter Ratio1 represents the slope of the suppressed input signal. The larger the first proportional parameter Ratio1, the greater the degree of suppression. The first smooth transition parameter Knee1 represents the smooth transition between the signal being unsuppressed and the signal being suppressed, ensuring that the subjective listening effect of the processed signal does not feel harsh.

[0109] like Figure 6 As shown, Figure 6The gain conversion curve of the compressor in the DRC circuit according to the embodiment of the present invention is shown in FIG. The horizontal axis is the input amplitude and the vertical axis is the output amplitude. C1 represents the input signal whose amplitude changes from -100dB to 0dB. C2 represents the output gain after the compressor is processed. Figure 6 It can be seen that when the input signal is less than the first threshold Threshold1, the amplitudes of the input signal and the output gain are the same, and C1 and C2 coincide. When the input signal is greater than the first threshold Threshold1, the output gain is proportionally compressed relative to the input signal at the slope of the first proportional parameter Ratio1. Near the first threshold Threshold1, the output gain has a smooth transition portion produced by processing with the first smooth transition parameter Knee1.

[0110] The gain generator 111 is a limiter, including two parameters: a second threshold Threshold2 and a second smooth transition parameter Knee2. The limiter is used to suppress the input signal to a fixed amplitude signal with an amplitude of the second threshold Threshold2 when the input signal exceeds the second threshold Threshold2, so as to output the output gain of the gain generator 111 to which it belongs; wherein the smoothness of the output gain relative to the input signal is related to the second smooth transition parameter Knee2. The second threshold Threshold2 represents the threshold for triggering the limiter function. When the threshold is exceeded, the limiter forcibly suppresses the input signal to a fixed amplitude signal with an amplitude of the second threshold Threshold2. The second smooth transition parameter Knee2 represents the smooth transition between the signal being suppressed and the signal being suppressed, ensuring that the subjective listening effect of the processed signal does not feel harsh.

[0111] like Figure 7 As shown, Figure 7 The gain conversion curve of the limiter in the DRC circuit according to the embodiment of the present invention is shown in FIG. The horizontal axis is the input amplitude and the vertical axis is the output amplitude. D1 represents the input signal whose amplitude changes from -100dB to 0dB. D2 represents the output gain after the limiter processing. Figure 7 It can be seen that when the input signal is less than the second threshold Threshold2, the amplitudes of the input signal and the output gain are the same, and D1 and D2 coincide. When the input signal is greater than the second threshold Threshold2, the output gain is compressed into a signal of a fixed amplitude. Near the second threshold Threshold2, the output gain has a smooth transition portion produced by the second smooth transition parameter Knee2.

[0112] The gain generator 111 is a noise removal effector and includes four parameters: a third threshold value, Threshold 3, a second ratio parameter, Ratio 2, a third smoothing parameter, Knee 3, and a noise floor. When the input signal falls below the third threshold value, Threshold 3, the noise removal effector begins suppressing the input signal to output the output gain of the gain generator 111. The degree of suppression of the output gain relative to the input signal is related to the second ratio parameter, Ratio 2, and the smoothness of the output gain relative to the input signal is related to the third smoothing parameter, Knee 3. The amplitude of the output gain is not less than a set minimum output gain amplitude. The third threshold value, Threshold 3, triggers the noise removal effector function. Below this threshold, the noise removal effector begins suppressing the output gain. The second ratio parameter, Ratio 2, indicates the slope of the suppressed input signal; a larger ratio, Ratio 2, indicates a greater degree of suppression. The third smoothing parameter, Knee 3, indicates the smooth transition between the signal being suppressed and the signal being suppressed. The noise floor indicates the minimum output gain amplitude to which the signal can be processed.

[0113] like Figure 8 As shown, Figure 8 The gain conversion curve of the noise removal effector in the DRC circuit according to the embodiment of the present invention is shown in FIG. The horizontal axis is the input amplitude and the vertical axis is the output amplitude. E1 represents the input signal, whose amplitude changes from -100dB to 0dB. E2 represents the output gain after being processed by the noise removal effector. Figure 8 As can be seen, when the input signal amplitude is less than the third threshold, Threshold3, the output gain begins to decrease according to the slope of the second proportional parameter, Ratio2. When the output gain is reduced to the Noisefloor, that is, to -100dB, the output gain remains unchanged at the Noisefloor. When the input signal exceeds the third threshold, Threshold3, the input signal and the output gain remain the same. Near the third threshold, Threshold3, the output gain undergoes a smooth transition, generated by the third smoothing parameter, Knee3.

[0114] The gain generator 111 is an expander and includes four parameters: a fourth threshold, Threshold 4, a makeup gain, MakeupGain, a fourth smooth transition parameter, Knee 4, and a third ratio parameter, Ratio 3. When the input signal exceeds the fourth threshold, Threshold 4, the expander begins amplifying the input signal based on the set makeup gain, MakeupGain, and the third ratio parameter, Ratio 3, to output the output gain of the gain generator 111 to which it belongs. The smoothness of the output gain relative to the input signal is related to the fourth smooth transition parameter, Knee 4. The fourth threshold, Threshold 4, represents the threshold that triggers the expander function. When this threshold is exceeded, the expander begins amplifying the input signal. The makeup gain, MakeupGain, represents the gain at which the input signal is amplified. The fourth smooth transition parameter, Knee 4, represents the smooth transition between the signal being unamplified and amplified. The third ratio parameter, Ratio 3, indicates that the input signal is gradually amplified at a certain slope until it reaches a gain equal to the makeup gain, MakeupGain.

[0115] like Figure 9 As shown, Figure 9 The gain conversion curve of the expander in the DRC circuit according to the embodiment of the present invention is shown in FIG. The horizontal axis is the input amplitude and the vertical axis is the output amplitude. F1 represents the input signal whose amplitude changes from -100dB to 0dB. F2 represents the output gain after being processed by the expander. Figure 9 As can be seen, when the input signal amplitude is less than the fourth threshold, Threshold 4, the output gain amplitude is the same as the input signal amplitude, with F1 and F2 overlapping. When the input signal exceeds Threshold 4, the output gain amplitude gradually increases relative to the input signal amplitude at the slope of the third proportional parameter, Ratio 3, until the increase reaches a compensation gain, MakeupGain. At this point, a fourth smoothing parameter, Knee 4, is applied to ensure a smooth transition at the turning point of the output gain amplitude.

[0116] like Figure 10 As shown, Figure 10 This is a comparison diagram of input and output data in the entire DRC circuit provided by an embodiment of the present invention, without considering the impact of the compression time and release time set by the gain smoothing processing module on the gain adjustment. The horizontal axis is the input amplitude, the vertical axis is the output amplitude, G1 represents the input signal, and G2 represents the output gain of the DRC processing in the multi-node DRC circuit.

[0117] Depend on Figure 10It can be seen that some input signals of different amplitudes are processed by the noise removal effector, some are processed by the expander, some are processed by the compressor, and some are processed by the limiter. In addition, the number of noise removal effectors, expanders, compressors and limiters is not limited, and they are mixed in series and parallel in an unlimited order in the DRC circuit. Therefore, the DRC circuit structure is simple and the computational complexity is low, and the functions of multi-node (unlimited number of nodes) noise removal effectors, expanders, compressors and limiters are realized. The noise removal effector, expander, compressor and limiter all have separate gain smoothing processing modules, so that their compression time and release time are independent of each other relative to other gain generators. In the tuning of the digital audio power amplifier, the sound signal can be processed in layers and at different speeds, which greatly improves the subjective listening effect of the sound signal.

[0118] From the above description, it can be seen that the DRC circuit described in the embodiment of the present invention has multiple gain generation modules mixed in series and parallel, one gain generation module corresponds to one node, and an internal multi-node series and parallel mixed single-stage DRC circuit is constructed. The compression time and release time of each gain generation module are independent of each other, the structure is simple, and the calculation amount is saved.

[0119] Based on the above embodiments, another embodiment of the present invention further provides an audio processing chip, which includes the DRC circuit described in any of the above embodiments. The gain generation modules in the two gain branches can set the compression time and the release time separately. The compression time and release time of each gain generation module are independent of each other, the structure is simple, and the calculation amount is saved.

[0120] Based on the above embodiments, another embodiment of the present invention further provides an audio processing method, wherein the audio processing chip is the audio processing chip described in the above embodiments, and the dynamic range control circuit in the audio processing chip has a first gain branch and a second gain branch, wherein the first gain branch includes a plurality of first gain generation modules connected in series, and the second gain branch includes a plurality of second gain generation modules connected in parallel;

[0121] The audio processing method is as follows Figure 11 As shown, Figure 11 A flowchart of an audio processing method provided by an embodiment of the present invention includes:

[0122] Step S11: Each gain generation module performs gain processing on the input signal obtained by itself to form an output gain, and sets the compression time and release time based on its own output gain;

[0123] Step S12: outputting target data based on the output gains of the gain generation modules at each level and the initial input data of the dynamic range control circuit.

[0124] In the audio processing method described in an embodiment of the present invention, if the output gain of each gain generation module belongs to the logarithmic domain, the method of outputting the target data includes: calculating the sum of the output gains of the two gain branches, calculating the linear domain value of the sum based on antilogarithmic operation, calculating the product of the linear domain value and the initial input data, and using the product as the target data.

[0125] In the audio processing method described in an embodiment of the present invention, if the output gain of each gain generation module belongs to the linear domain, the method of outputting the target data includes: calculating the product of the output gains of two gain branches and the initial input data, and using the product as the target data.

[0126] The audio processing method of the embodiment of the present invention can set the compression time and the release time separately through the gain generation modules in the two gain branches. The compression time and release time of each gain generation module are independent of each other, the structure is simple, and the calculation amount is saved.

[0127] The various embodiments in this specification are described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0128] It should be noted that in the description of the present invention, it should be understood that the terms "upper," "lower," "top," "bottom," "inner," "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of the present invention and simplify the description. They do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally located component.

[0129] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the aforementioned elements.

[0130] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A dynamic range control circuit, characterized in that: include: A first gain branch, the first gain branch comprising a plurality of first gain generation modules connected in series; A second gain branch, wherein the second gain branch includes a plurality of second gain generation modules connected in parallel; an output module, configured to output target data based on an output gain of the first gain branch, an output gain of the second gain branch, and initial input data; Among them, the first gain generation module and the second gain generation module each have a separate gain generator and a gain smoothing processing module; in the same gain generation module, the gain generator is used to perform gain processing on the input signal received by the corresponding gain generation module, and the gain smoothing processing module is used to set the compression time and release time based on the output gain of the gain generator.

2. The dynamic range control circuit according to claim 1, wherein: The first gain branch is used to generate input signals of each second gain generation module based on the output gain of each first gain generation module and the amplitude of the initial input data.

3. The dynamic range control circuit according to claim 1, wherein: The first gain branch has N first gain generation modules connected in series, the N first gain generation modules being sequentially from the first-stage first gain generation module to the N-stage first gain generation module, where N is a positive integer greater than 1; the i-th stage first gain generation module has an i-th stage output gain, where i is a positive integer not greater than N; If i=1, the first gain generation module of the first stage outputs the first stage output gain based on the amplitude of the initial input data; If i>1, the i-th stage first gain generating module outputs the i-th stage output gain based on the amplitude of the initial input data and the 1st stage output gain to the (i-1)th stage output gain.

4. The dynamic range control circuit according to claim 1, wherein: The first gain branch has N first gain generation modules connected in series, and the N first gain generation modules connected in series are sequentially a first gain generation module of the first stage to a first gain generation module of the N stage, where N is a positive integer greater than 1; The first gain branch further includes: N-1 cascaded first adders, the N-1 first adders being sequentially from the 1st stage first adder to the N-1th stage first adder; Among them, the first adder of the jth stage is used to calculate the sum of the output gains of all the first gain generation modules of the previous j stages and the amplitude of the initial input data as the input signal of the first gain generation module of the j+1th stage, and j is a positive integer not greater than N-1.

5. The dynamic range control circuit according to claim 1, wherein: The first gain branch has N first gain generation modules connected in series, and the N first gain generation modules connected in series are sequentially a first gain generation module of the first stage to a first gain generation module of the N stage, where N is a positive integer greater than 1; The first gain branch further includes: N-1 cascaded second adders, the N-1 second adders being sequentially from the first-stage second adder to the N-1-stage second adder; Among them, the second adder of the first stage is used to calculate the sum of the output gain of the first gain generation module of the first stage and the output gain of the first gain generation module of the second stage; the second adder of the jth stage is used to calculate the sum of the output gain of the second adder of the j-1th stage and the output gain of the first gain module of the j+1th stage, where j is a positive integer greater than 1 and not greater than N-1.

6. The dynamic range control circuit according to claim 1, wherein: The second gain branch includes M parallel second gain generation modules and a comparator, where M is a positive integer greater than 1; The input signals of the second gain generating module are the amplitude of the initial input data and the sum of the output gains of all the first gain generating modules; The comparator is used to compare the output gains of the M second gain generation modules and select the smallest output gain as the output gain of the second gain branch.

7. The dynamic range control circuit according to claim 2, wherein: If the output gains of the various gain generation modules belong to the logarithmic domain, the first gain branch is used to calculate the sum of the output gains of all the first gain generation modules and the amplitude of the initial input data, and use the sum as the input signal of each of the second gain generation modules.

8. The dynamic range control circuit according to claim 7, wherein: The output module is used to calculate the sum of the output gains of the two gain branches, calculate the linear domain value of the sum based on antilogarithmic operation, calculate the product of the linear domain value and the initial input data, and use the product as the target data.

9. The dynamic range control circuit according to claim 2, wherein: If the output gains of the various gain generation modules belong to the linear domain, the first gain branch is used to calculate the product of the output gains of all the first gain generation modules, and use the product as the input signal of each of the second gain generation modules.

10. The dynamic range control circuit according to claim 9, wherein: The output module is used to calculate the product of the output gains of the two gain branches and the initial input data, and use the product as the target data.

11. The dynamic range control circuit according to any one of claims 1 to 10, characterized in that: The gain generator is a compressor, configured to start suppressing the input signal when the input signal exceeds a first threshold value, so as to output the output gain of the gain generator to which it belongs; The degree of suppression of the output gain relative to the input signal is related to a first proportional parameter, and the smoothness of the output gain relative to the input signal is related to a first smooth transition parameter.

12. The dynamic range control circuit according to any one of claims 1 to 10, characterized in that: The gain generator is a limiter, configured to, when its input signal exceeds a second threshold, suppress the input signal to a fixed amplitude signal having an amplitude of the second threshold, so as to output the output gain of the gain generator to which it belongs; The smoothness of the output gain relative to the input signal is related to a second smooth transition parameter.

13. The dynamic range control circuit according to any one of claims 1 to 10, characterized in that: The gain generator is a noise removal effector, configured to, when its input signal is less than a third threshold, start suppressing the input signal to output the output gain of the gain generator to which it belongs; The degree of suppression of the output gain relative to the input signal is related to a second proportional parameter, and the smoothness of the output gain relative to the input signal is related to a third smooth transition parameter.

14. The dynamic range control circuit according to any one of claims 1 to 10, characterized in that: The gain generator is an expander, configured to start amplifying the input signal based on a set compensation gain and a third proportional parameter when its input signal exceeds a fourth threshold, so as to output the output gain of the gain generator to which it belongs; The smoothness of the output gain relative to the input signal is related to a fourth smooth transition parameter.

15. An audio processing chip, characterized in that: include: The dynamic range control circuit according to any one of claims 1 to 14.

16. An audio processing method for an audio processing chip, characterized in that: The dynamic range control circuit in the audio processing chip comprises a first gain branch and a second gain branch, wherein the first gain branch comprises a plurality of first gain generation modules connected in series, and the second gain branch comprises a plurality of second gain generation modules connected in parallel; The audio processing method comprises: Each gain generation module performs gain processing on the input signal it obtains to form an output gain, and sets the compression time and release time based on its own output gain; Target data is output based on the output gains of the gain generation modules at each stage and the initial input data of the dynamic range control circuit.

17. The audio processing method according to claim 16, characterized in that: If the output gains of the gain generation modules belong to the logarithmic domain, the method of outputting the target data includes: The sum of the output gains of the two gain branches is calculated, a linear domain value of the sum is calculated based on an antilogarithmic operation, the product of the linear domain value and the initial input data is calculated, and the product is used as the target data.

18. The audio processing method according to claim 16, characterized in that: If the output gains of the gain generation modules belong to the linear domain, the method of outputting the target data includes: The product of the output gains of the two gain branches and the initial input data is calculated, and the product is used as the target data.

Images