De-glitch clock divider circuit, method and terminal

Abstract

This invention provides a de-glitching clock divider circuit, method, and terminal, including a first trigger module for counting an input reference clock based on an input division factor to output first count data; a second trigger module for generating an intermediate clock signal based on the division factor and the reference clock, and processing the first count data based on the intermediate clock signal to output second count data; a combination circuit connected to the output of the second trigger module to process the second count data and output an intermediate output signal; a third trigger module for outputting a second-level asynchronous reset signal based on the intermediate clock signal; and a fourth trigger module, whose reset terminal is connected to the output of the third trigger module, and which generates a divided clock based on the first count data and the reference clock. The frequency divider circuit of this invention not only increases the upper limit of the circuit's operating clock frequency but also improves clock stability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital circuit, and particularly relates to a deburring clock frequency division circuit, method and terminal. BACKGROUND

[0002] A complete digital system design often needs to use multiple clocks. The traditional clock frequency division generally uses a phase-locked loop (PLL) to generate clocks of different frequencies, but it cannot achieve arbitrary frequency division and requires a certain switching time for frequency switching.

[0003] And at present, when the digital clock frequency division module performs odd frequency division on the input clock, the digital clock frequency division module often uses the rising and falling edges of the input clock to perform timing logic processing on the clock at the same time, so that only half a clock cycle of margin is left for timing constraints at a certain position of the circuit to meet the requirement of establishing the hold time. When the clock frequency becomes faster, timing violations are easily generated, which affects the stability of the clock.

[0004] Therefore, it is necessary to provide a new deburring clock frequency division circuit, method and terminal to solve the above problems in the prior art. SUMMARY

[0005] The present application aims to provide a deburring clock frequency division circuit, method and terminal, so that the margin left for timing constraints is restored to one clock cycle, the upper limit of the circuit operating clock frequency is improved, and the stability of the clock is improved.

[0006] To achieve the above-mentioned purpose, the deburring clock frequency division circuit comprises:

[0007] A first trigger module is configured to count a reference clock input according to a frequency division coefficient signal input to output first count data;

[0008] A second trigger module is connected to the output end of the first trigger module, configured to generate an intermediate clock signal according to the frequency division coefficient signal and the reference clock, and process the first count data according to the intermediate clock signal to output second count data;

[0009] A combination circuit is connected to the output end of the second trigger module to process the second count data and output an intermediate output signal;

[0010] A third trigger module is connected to the output end of the combination circuit, configured to output a second level asynchronous reset signal according to the intermediate output signal and the intermediate clock signal;

[0011] A fourth trigger module is connected with the output terminal of the third trigger module and the output terminal of the first trigger module, and the reset terminal of the fourth trigger module is connected with the output terminal of the third trigger module, and the fourth trigger module generates a frequency-divided clock according to the first count data and the reference clock.

[0012] The burr-removing clock frequency-dividing circuit has the advantages that: the first trigger module counts the input reference clock according to the frequency-dividing coefficient signal to output first count data, and the second trigger module processes the first count data according to the generated intermediate clock signal to output second count data, the processing logic of the combination circuit is arranged after the second trigger module outputting the second count data, so that the margin of six time sequence constraints is restored from half a period to one period in the process of clock frequency division, the upper limit of the clock frequency during the working of the whole circuit is effectively improved, and the fourth trigger module is used to output the final frequency-divided clock, so that the stability of the output clock is effectively improved.

[0013] Optionally, the combination circuit comprises a first adder, a third comparator, a second adder and an inverter, one input terminal of the first adder is connected with the output terminal of the second trigger module, the other input terminal of the first adder inputs a first level, the output terminal of the first adder is connected with one input terminal of the third comparator, one input terminal of the second adder inputs the frequency-dividing coefficient signal, the other input terminal inputs the first level, the output terminal of the second adder is connected with the other input terminal of the third comparator, the output terminal of the third comparator is connected with the input terminal of the inverter, and the output terminal of the inverter is connected with the input terminal of the third trigger module.

[0014] Optionally, the first trigger module comprises a third adder, a first comparator, a selector and a first flip-flop, one input terminal of the third adder and one input terminal of the first comparator are both connected with the output terminal of the first flip-flop, the other input terminal of the third adder inputs a first level, the output terminal of the third adder is connected with one input terminal of the selector, the other input terminal of the selector inputs a first selection signal, the other input terminal of the first comparator inputs the frequency-dividing coefficient signal, the output terminal of the first comparator is connected with the selection signal input terminal of the selector, the output terminal of the selector is connected with the data input terminal of the first flip-flop, the output terminal of the first flip-flop is also connected with the input terminal of the second trigger module and the input terminal of the fourth trigger module, and the clock input terminal of the first flip-flop inputs the reference clock.

[0015] The second trigger module includes a second flip-flop and an XOR gate. The data input terminal of the second flip-flop is connected to the output terminal of the first flip-flop. The two input terminals of the XOR gate are respectively input to the frequency division coefficient signal and the reference clock. The XOR gate outputs an intermediate clock signal according to the frequency division coefficient signal and the reference clock. The output terminal of the XOR gate is connected to the clock input terminal of the second flip-flop and the clock input terminal of the third trigger module.

[0016] The third trigger module includes a third trigger, the data input terminal of which is connected to the output terminal of the inverter, the clock input terminal of which is connected to the output terminal of the XOR gate, and the output terminal of which is connected to the fourth trigger module.

[0017] The fourth trigger module includes a second comparator, an OR gate, and a fourth trigger module. One input of the second comparator is connected to the output of the first flip-flop, and the other input of the second comparator receives the frequency division coefficient signal. The output of the second comparator is connected to one input of the OR gate, and the other input of the OR gate is connected to the output of the fourth flip-flop. The output of the OR gate is connected to the data input of the fourth flip-flop. The clock input of the fourth flip-flop receives the reference clock. The output of the third flip-flop is connected to the reset input of the fourth flip-flop, and the output of the fourth flip-flop outputs the frequency division clock.

[0018] Optionally, the first flip-flop, the second flip-flop, and the third flip-flop all receive the same reset signal.

[0019] The present invention also provides a de-glitch clock division method, comprising:

[0020] Input a frequency division coefficient signal and a reference clock to the first trigger module to count the reference clock according to the frequency division coefficient signal to obtain first count data;

[0021] The reference clock and the frequency division coefficient signal are input into the second trigger module to generate an intermediate clock signal, and the first counting data is input into the second trigger module to generate second counting data according to the intermediate clock signal;

[0022] The second counting data is input to the combinational circuit and an intermediate output signal is generated. The intermediate output signal is input to the third trigger module, and the intermediate clock signal is input to the clock input terminal of the third trigger module and a second-level asynchronous reset signal is output.

[0023] The first counting data and the reference clock are input to the fourth trigger module to output a frequency-divided clock.

[0024] The beneficial effects of the de-glitching clock division method described in this invention are as follows: the first trigger module counts the input reference clock according to the division coefficient signal to output the first count data, and the second trigger module processes the first count data according to the generated intermediate clock signal to output the second count data. By setting the processing logic of the combinational circuit after the second trigger module that outputs the second count data, the margin of the six timing constraints of the entire circuit is restored from half a cycle to a full cycle during the clock division process, which effectively improves the upper limit of the clock frequency when the entire circuit is working. Moreover, the use of the fourth trigger module to output the final divided clock effectively improves the stability of the output clock.

[0025] Optionally, the step of inputting the second counting data to the combinational circuit and generating an intermediate output signal includes:

[0026] The first counting data is input to one input terminal of the first adder, and a first level is input to the other input terminal of the first adder to generate a first addition signal through the first adder;

[0027] The frequency division coefficient signal is input to one input terminal of the second adder, and a first level signal is input to the other input terminal of the second adder to generate the second addition signal;

[0028] The first addition signal is input to one input of the third comparator, and the second addition signal is input to the other input of the third comparator, so that the third comparator outputs an intermediate processing signal.

[0029] The intermediate processing signal is input to an inverter for processing and to generate the intermediate output signal.

[0030] Optionally, the step of inputting the reference clock and the frequency division coefficient signal into the second trigger module to generate an intermediate clock signal, and inputting the first counting data into the second trigger module to generate second counting data according to the intermediate clock signal, includes:

[0031] The frequency division coefficient signal and the reference clock are respectively input to the two input terminals of the XOR gate to generate an intermediate clock signal;

[0032] The intermediate clock signal is input to the clock input terminal of the second flip-flop, and the first counting data is input to the data input terminal of the second flip-flop, so as to count the intermediate clock signal according to the frequency division coefficient signal to generate the second counting data.

[0033] Optionally, inputting the first counting data and the reference clock to the fourth trigger module to output a frequency-divided clock includes:

[0034] The frequency division coefficient signal and the first counting data are input to the second comparator to generate a rising edge signal based on the magnitude of the first counting data and the frequency division coefficient signal;

[0035] The rising edge signal is input to an OR gate, and the frequency-divided clock is output according to the rising edge of the reference clock and the rising edge signal.

[0036] The present invention further provides a terminal, which includes the above-described de-glitch clock divider circuit. Attached Figure Description

[0037] Figure 1 This is a circuit diagram of the de-glitch clock divider circuit described in an embodiment of the present invention;

[0038] Figure 2 This is a timing diagram of the de-glitch clock divider circuit described in an embodiment of the present invention;

[0039] Figure 3 This is a flowchart of the de-glitch clock division method described in an embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but do not exclude other elements or objects.

[0041] To address the problems existing in the prior art, embodiments of the present invention provide a glitching clock divider circuit, comprising:

[0042] The first trigger module 1 is used to count the input reference clock according to the input frequency division coefficient signal to output the first count data;

[0043] The second trigger module 2 is connected to the output terminal of the first trigger module 1, and is used to generate an intermediate clock signal according to the frequency division coefficient signal and the reference clock, and process the first counting data according to the intermediate clock signal to output the second counting data.

[0044] The combination circuit 5 is connected to the output terminal of the second trigger module 2 to process the second counting data and output an intermediate output signal;

[0045] The third trigger module 3 is connected to the output terminal of the combined circuit 5 and is used to output a second-level asynchronous reset signal to the intermediate output signal according to the intermediate clock signal.

[0046] The fourth trigger module 4 is connected to the output terminal of the third trigger module 3 and the output terminal of the first trigger module 1, and the reset terminal of the fourth trigger module 4 is connected to the output terminal of the third trigger module 3, and generates a frequency division clock based on the first counting data and the reference clock.

[0047] In the circuit described above, by inputting the frequency division coefficient signal and the reference clock signal into the first trigger module 1, the first trigger module 1 counts the reference clock signal according to the frequency division coefficient signal, thereby outputting first count data. Then, the first count data is input into the second trigger module 2, along with the frequency division coefficient signal and the reference clock signal, to generate an intermediate clock signal. The second trigger module 2 then counts the intermediate clock signal according to the frequency division coefficient signal, thereby obtaining second count data. Since no combinational logic circuit is added between the first trigger module 1 and the second trigger module 2, the processing timing between the two trigger modules is faster. This improves efficiency. The second counting data is then output to the combinational circuit 5. The combinational logic of the combinational circuit 5 processes the second counting data to output an intermediate output signal to the third trigger module 3. The output second-level asynchronous reset signal is used as the reset signal for the fourth trigger module 4. Then, the fourth trigger module 4 outputs the final frequency-divided clock based on the first counting data and the reference clock. In the above process, the margin left for timing constraints is changed from half a clock cycle to one clock cycle, which effectively improves the highest operating frequency of the entire circuit. At the same time, the use of the fourth trigger module 4 to replace the traditional combinational logic circuit to output the frequency-divided clock achieves glitches and improves the stability of the clock.

[0048] In some embodiments, the combination circuit 5 includes a first adder 501, a third comparator 502, a second adder 503, and an inverter 504. One input terminal of the first adder 501 is connected to the output terminal of the second trigger module 2, and the other input terminal of the first adder 501 receives a first level. The output terminal of the first adder 501 is connected to one input terminal of the third comparator 502. One input terminal of the second adder 503 receives the frequency division coefficient signal, and the other input terminal receives the first level. The output terminal of the second adder 503 is connected to the other input terminal of the third comparator 502. The output terminal of the third comparator 502 is connected to the input terminal of the inverter 504, and the output terminal of the inverter 504 is connected to the input terminal of the third trigger module 3.

[0049] The combinational circuit 5 performs combinational logic processing on the second counting data output by the second trigger module 2. During the processing, since the combinational circuit 5 is located between the second trigger module 2 and the third trigger module 3, and the timing interval between the second trigger module 2 and the third trigger module 3 is periodic, the combinational circuit 5 has more time constraints during data processing, which improves data processing efficiency. It also increases the time constraint margin in the entire circuit from half a cycle to one cycle, thereby increasing the highest operating frequency of the circuit.

[0050] The third comparator 502 will only generate a valid output signal when the input signals at both input terminals are the same.

[0051] In some other embodiments, the circuit structure of the de-glitch clock divider circuit is as follows. The de-glitch clock divider circuit will now be described with the example of the first level being high, the second level being low, and the second level asynchronous reset signal being a low level asynchronous reset signal.

[0052] The first trigger module 1 includes a third adder 101, a first comparator 102, a selector 103, and a first flip-flop 104. One input terminal of the third adder 101 and one input terminal of the first comparator 102 are both connected to the output terminal of the first flip-flop 104. The other input terminal of the third adder 101 receives a high level input. The output terminal of the third adder 101 is connected to one input terminal of the selector 103. The other input terminal of the selector 103 receives a first selection signal h1. The other input terminal of the first comparator 102 receives a frequency division coefficient signal. The output terminal of the first comparator 102 is connected to the selection signal input terminal of the selector 103. The output terminal of the selector 103 is connected to the data input terminal of the first flip-flop 104. The output terminal of the first flip-flop 104 is also connected to the input terminals of the second trigger module 2 and the fourth trigger module 4. The clock input terminal of the first flip-flop 104 receives the reference clock.

[0053] The second trigger module 2 includes a second flip-flop 201 and an XOR gate 202. The data input terminal of the second flip-flop 201 is connected to the output terminal of the first flip-flop 104. The two input terminals of the XOR gate 202 are respectively input to the frequency division coefficient signal and the reference clock. The XOR gate 202 outputs an intermediate clock signal according to the frequency division coefficient signal and the reference clock. The output terminal of the XOR gate 202 is connected to the clock input terminal of the second flip-flop 201 and the clock input terminal of the third trigger module 3.

[0054] It should be noted that in this embodiment, the XOR gate 202 can also be replaced by a selector to obtain the corresponding output signal. Specifically, when a selector is used instead of the XOR gate 202, the output of the selector is determined according to the frequency division coefficient signal and the reference clock clk_in. When the frequency division coefficient signal is high level 1, the intermediate clock clk_neg of the selector output is the inverse of the input reference clock clk_in, that is, when the input reference clock clk_in = 1, the output intermediate clock clk_neg = 0, and when the input reference clock clk_in = 0, the output intermediate clock clk_neg = 1. When the frequency division coefficient signal is low level 0, the intermediate clock clk_neg of the selector output is the same as the input reference clock clk_in, which will not be elaborated here.

[0055] The third trigger module 3 includes a third trigger 301. The data input terminal of the third trigger 301 is connected to the output terminal of the inverter 504. The clock input terminal of the third trigger 301 is connected to the output terminal of the XOR gate 202. The output terminal of the third trigger 301 is connected to the fourth trigger module 4.

[0056] The fourth trigger module 4 includes a second comparator 401, an OR gate 402, and a fourth trigger module 403. One input of the second comparator 401 is connected to the output of the first flip-flop 104, and the other input of the second comparator 401 receives the frequency division coefficient signal. The output of the second comparator 401 is connected to one input of the OR gate 402, and the other input of the OR gate 402 is connected to the output of the fourth flip-flop 403. The output of the OR gate 402 is connected to the data input of the fourth flip-flop 403. The clock input of the fourth flip-flop 403 receives the reference clock. The output of the third flip-flop 301 is connected to the reset input of the fourth flip-flop 403, and the output of the fourth flip-flop 403 outputs the frequency division clock.

[0057] In the above circuit, taking odd-number frequency division by 3 as an example, the odd-number frequency division coefficient div[9:0] is input to another input terminal of the first comparator 102, and the reference clock clk_in is input to the clock input terminal of the first flip-flop 104. After the combinational logic composed of the third adder 101, the first comparator 102 and the selector 103 forms an output signal to be output to the data input terminal of the first flip-flop 104. Thus, the first flip-flop 104 counts the input reference clock clk_in according to the frequency division coefficient signal and outputs the first count data counter. The first selection signal h1 is high level 1. When counter≥div, the selector 103 selects the output 1 to the input terminal of the first flip-flop 104. That is, the output of the first flip-flop 104 cycles between 1 and the frequency division coefficient div. Its timing reference Figure 2 At position A in the diagram, after inputting the first count data `counter` and the frequency division coefficient signal to the two input terminals of the second comparator 401, the second comparator 401 outputs a rising edge signal `rise_edge`. This rising edge signal `rise_edge` marks when the final output frequency division clock `clk_out` goes high. Specifically, when the first count data `counter` is greater than or equal to the frequency division coefficient `div`, the rising edge signal `rise_edge` outputs a high level. Its timing reference is... Figure 2 Position B in the diagram.

[0058] After inputting the frequency division coefficient signal and the reference clock clk_in to the two input terminals of the XOR gate 202, the XOR gate 202 outputs an intermediate clock clk_neg. Since the frequency division coefficient div is odd, the intermediate clock clk_neg and the reference clock clk_in are exactly in reverse. The intermediate clock clk_neg is then input to the clock input terminal of the second flip-flop 201 as the clock signal, while the first counting data counter is output to the data input terminal of the second flip-flop 201. The second flip-flop 201 processes the data, thus counting the intermediate clock clk_neg at the rising edge with a period equal to the frequency division coefficient div, and outputting the second counting data counter_neg. Its timing reference... Figure 2 The position of label C in the text.

[0059] After the second counting data `counter_neg` is output to the first adder 501, the frequency division coefficient signal is input to one input of the second adder 503, and a high-level signal is input to the other input of the second adder 503, thereby outputting the second addition signal `half`. The two inputs of the first adder 501 are respectively input to the second counting data `counter_neg` and the high-level signal, and output the first addition signal. After the first addition signal and the second addition signal `half` are respectively input to the two inputs of the third comparator 502, the third comparator 502 outputs an intermediate processing signal. This intermediate processing signal is processed by the inverter 504 and outputs an intermediate output signal, which is then input to the third flip-flop 3. The data input terminal of 01 is simultaneously connected to the clock input terminal of the third flip-flop 301 via the intermediate clock clk_neg. The third flip-flop 301 outputs a second-level asynchronous reset signal fail_edge. The second-level asynchronous reset signal fail_edge is the output of the third flip-flop 303, triggered by the rising edge of the intermediate clock clk_neg. It marks when the divided clock clk_out goes low, determined by the second counting data counter_neg and the second addition signal half, where half = (div + 1) / 2. When the second counting data counter_neg + 1 and the second addition signal half are equal, the second-level asynchronous reset signal fail_edge goes low. Its timing reference is... Figure 2The label D is used in the diagram; then, the second-level asynchronous reset signal fail_edge is input to the reset input of the fourth flip-flop 403, so that the second-level asynchronous reset signal fail_edge is used as the reset signal of the fourth flip-flop 403. The output of the fourth flip-flop 403 is the frequency-divided clock clk_out. The trigger edge is when the reference clock clk_in is at the rising edge, and when the second-level asynchronous reset signal fail_edge is at the falling edge, the frequency-divided clock clk_out is triggered to go low. Its timing reference... Figure 2 The position is indicated by label E; after the rising edge of the reference clock clk_in is triggered, if the sampled rising edge signal rise_edge is at a high level, the frequency divider clock clk_out is triggered to go high, and its timing reference... Figure 2 The label F is located at position F. Therefore, based on the division factor signal and the reference clock clk_in, clock division is performed and the divided clock clk_out is output. Through the above circuit, the timing constraint margin is increased from half a cycle to one cycle, and the reference clock... Figure 2 In traditional frequency division methods, the timing constraint margin is the interval S0 between the rising edge of the reference clock clk_in and the rising edge of the intermediate clock clk_neg. However, the timing constraint margin of the frequency division circuit in this scheme is the interval S1 between the two rising edges of the intermediate clock clk_neg. Obviously, the frequency division circuit in this scheme improves the timing constraint margin. Moreover, the final use of a flip-flop to output the divided clock clk_out improves the clock stability and achieves the effect of de-glitching.

[0060] In some embodiments, the first trigger 104, the second trigger 201, and the third trigger 303 all receive the same reset signal rst_n.

[0061] It should be noted that in the glitch-reducing clock divider circuit of the scheme, the first level can also be set to low level and the second level to high level. In this case, the second addition signal half = (div + 0) / 2. In the rest of the process, the rising edge trigger, rising edge sampling and rising edge signal are adjusted to the falling edge trigger, falling edge sampling and falling edge signal. The other contents related to the first level and the second level are adjusted according to the first level being low level and the second level being high level. Since both implementation methods are based on the glitch-reducing clock divider circuit in this scheme, their working principles and processes are basically similar, and will not be described in detail here.

[0062] This invention also discloses a de-glitch clock division method, referring to... Figure 3 It includes the following steps:

[0063] S301. Input the frequency division coefficient signal and the reference clock to the first trigger module to count the reference clock according to the frequency division coefficient signal to obtain the first counting data.

[0064] The first trigger module processes the frequency division coefficient signal and the reference clock, so that the first trigger module counts the input reference clock clk_in with the frequency division coefficient div as the period and outputs the first count data counter.

[0065] S302. Input the reference clock and the frequency division coefficient signal into the second trigger module to generate an intermediate clock signal, and input the first counting data into the second trigger module to generate second counting data according to the intermediate clock signal.

[0066] In some embodiments, the above process includes:

[0067] The frequency division coefficient signal and the reference clock are respectively input to the two input terminals of the XOR gate to generate an intermediate clock signal;

[0068] The intermediate clock signal is input to the clock input terminal of the second flip-flop, and the first counting data is input to the data input terminal of the second flip-flop, so as to count the intermediate clock signal according to the frequency division coefficient signal to generate the second counting data.

[0069] An intermediate clock signal is generated by inputting the frequency division coefficient signal and the reference clock to the two input terminals of an XOR gate, thereby making the output intermediate clock clk_neg inversely related to the reference clock clk_in. Then, the intermediate clock signal is input to the clock input terminal of the second flip-flop, and the first count data counter is input to the data input terminal of the second flip-flop, so that the second flip-flop counts the intermediate clock clk_neg by the frequency division coefficient div on the rising edge of the intermediate clock clk_neg to output the second count data counter_neg.

[0070] S303. Input the second counting data to the combination circuit and generate an intermediate output signal. Input the intermediate output signal to the third trigger module and input the intermediate clock signal to the clock input terminal of the third trigger module and output a second-level asynchronous reset signal.

[0071] In some embodiments, inputting the second counting data to the combinational circuit and generating an intermediate output signal includes:

[0072] The first counting data is input to one input terminal of the first adder, and a first level is input to the other input terminal of the first adder to generate a first addition signal through the first adder;

[0073] The frequency division coefficient signal is input to one input terminal of the second adder, and a first level signal is input to the other input terminal of the second adder to generate the second addition signal;

[0074] The first addition signal is input to one input of the third comparator, and the second addition signal is input to the other input of the third comparator, so that the third comparator outputs an intermediate processing signal.

[0075] The intermediate processing signal is input to an inverter for processing and to generate the intermediate output signal.

[0076] Then, the intermediate output signal is input to the data input terminal of the third flip-flop 301, and the intermediate clock clk_neg is input to the clock input terminal of the third flip-flop 303, so that the third flip-flop 301 outputs the second level asynchronous reset signal fail_edge according to the second counting data counter_neg and the intermediate clock clk_neg.

[0077] S304. Input the first counting data and the reference clock to the fourth trigger module to output the frequency division clock.

[0078] In some embodiments, inputting the first counting data and the reference clock to the fourth trigger module to output a frequency-divided clock includes:

[0079] The frequency division coefficient signal and the first counting data are input to the second comparator to generate a rising edge signal rise_edge based on the magnitude of the first counting data and the frequency division coefficient signal.

[0080] The rising edge signal rise_edge is input to an OR gate, and the second level asynchronous reset signal fail_edge is input to the reset input terminal of the fourth flip-flop 403, so that the frequency division clock clk_out is output according to the high and low levels of the rising edge signal rise_edge and the second level asynchronous reset signal fail_edge.

[0081] The present invention also discloses a terminal, which includes the aforementioned de-glitch clock divider circuit.

[0082] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A deburring clock division circuit, comprising: The application relates to a frequency divider. The application relates to a frequency divider. The application relates to a frequency divider. The application relates to a frequency divider. The application relates to a frequency divider. The application relates to a frequency divider. The application relates to a frequency divider.

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The third trigger module comprises a third flip-flop, a data input end of the third flip-flop is connected with an output end of the inverter, a clock input end of the third flip-flop is connected with an output end of the XOR gate, and an output end of the third flip-flop is connected with the fourth trigger module; The fourth trigger module comprises a second comparator, an OR gate and a fourth flip-flop, one input end of the second comparator is connected with an output end of the first flip-flop, another input end of the second comparator inputs the frequency division coefficient signal, an output end of the second comparator is connected with one input end of the OR gate, another input end of the OR gate is connected with an output end of the fourth flip-flop, an output end of the OR gate is connected with a data input end of the fourth flip-flop, a clock input end of the fourth flip-flop inputs the reference clock, an output end of the third flip-flop is connected with a reset input end of the fourth flip-flop, and an output end of the fourth flip-flop outputs the frequency division clock.

3. The de-burring clock division circuit of claim 2, wherein, The first flip-flop, the second flip-flop and the third flip-flop all input the same reset signal.

4. A deburring clock division method applied to the deburring clock division circuit according to any one of claims 1 to 3, characterized by, Comprise: input a frequency division coefficient signal and a reference clock to a first trigger module to count the reference clock according to the frequency division coefficient signal to obtain first counting data; input the reference clock and the frequency division coefficient signal to a second trigger module to generate an intermediate clock signal, and input the first counting data to the second trigger module to generate second counting data according to the intermediate clock signal; input the second counting data to a combination circuit to generate an intermediate output signal, input the intermediate output signal to a third trigger module, and input the intermediate clock signal to a clock input end of the third trigger module to output a second level asynchronous reset signal; input the first counting data and the reference clock to a fourth trigger module to output a frequency division clock; wherein the inputting the second counting data to the combination circuit to generate the intermediate output signal comprises: input the first counting data to one input end of a first adder, and input a first level to another input end of the first adder to generate a first addition signal through the first adder; input the frequency division coefficient signal to one input end of a second adder, and input a first level signal to another input end of the second adder to generate a second addition signal; input the first addition signal to one input end of a third comparator, and input the second addition signal to another input end of the third comparator to output an intermediate processing signal through the third comparator; input the intermediate processing signal to an inverter for processing to generate the intermediate output signal.

5. The deburring clock division method of claim 4, wherein, The inputting the reference clock and the frequency division coefficient signal to the second trigger module to generate the intermediate clock signal, and the inputting the first counting data to the second trigger module to generate the second counting data according to the intermediate clock signal comprises: input the frequency division coefficient signal and the reference clock to two input ends of an XOR gate respectively to generate the intermediate clock signal; The intermediate clock signal is input to a clock input end of a second flip-flop, and the first count data is input to a data input end of the second flip-flop, so as to generate the second count data by counting the intermediate clock signal according to the frequency division coefficient signal.

6. The deburring clock division method of claim 4, wherein, The inputting of the first count data and the reference clock to the fourth trigger module to output a frequency division clock comprises: The frequency division coefficient signal and the first count data are input to a second comparator, so as to generate a rising edge signal according to the size of the first count data and the frequency division coefficient signal; The rising edge signal is input to an OR gate, and the frequency division clock is output according to the rising edge of the reference clock and the rising edge signal.

7. A terminal, characterized by comprising: The terminal comprises the deburring clock frequency division circuit according to any one of claims 1 to 3.

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