Cryptographic data communication device

Abstract

In one embodiment, a data communications apparatus includes a circuit for connecting to a network and configured to receive a sequence of data packets from a remote device via the network, the sequence including data blocks, a plurality of data blocks having block boundaries that are not aligned with payload boundaries of the packets, and a packet processing circuit to cryptographically process the data blocks using a block ciphertext so as to write corresponding cryptographically processed data blocks to a memory while simultaneously storing segments of corresponding data blocks in the received data blocks in the memory, such that the packet processing circuit stores a first segment of a data block of a first packet in the memory until a second packet is received, and then cryptographically processes the first segment and the second segment together so as to write the corresponding cryptographically processed data block to the memory.

Description

[0001] Related application information

[0002] This application claims priority to Israel Patent Application S / N 276,538 filed on August 5, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to computer systems and, in particular but not exclusively, to cryptographic processing in data communications devices. Background Art

[0004] Solid-state drives (SSDs) are large-capacity storage devices that use integrated circuit memory (usually NAND-based flash memory) to store data while providing an interface that emulates a traditional hard disk drive (HDD). Compared with HDDs, SSDs have faster access speeds, lower latency, and greater resistance to environmental interference. Therefore, SSDs are gradually replacing HDDs in many storage applications.

[0005] Because SSDs were originally designed to replace HDDs, they typically use the same types of input / output (I / O) buses and protocols as HDDs, such as SATA, SAS, and Fibre Channel. Subsequently, SSDs were connected directly to the host computer's peripheral component interface bus (such as PCI NVM Express (NVMe) defines the register interface, command set, and feature set for PCI Express SSDs.

[0006] Advanced network interface controllers (NICs) are designed to support remote direct memory access (RDMA) operations in which the NIC transfers data from the memory of one computer to the memory of another computer via direct memory access without involving the central processing unit (CPU) of the target computer. Although RDMA is commonly used to transfer data to and from host memory (RAM), many attempts to adapt RDMA functionality to write data directly to and read data from SSDs have been described in the patent literature. For example, U.S. Patent Application Publication 2008 / 0313364 describes a method for remote direct memory access to solid-state storage devices that is said to allow direct access between the memories of clients connected to such devices via a network. Similarly, U.S. Patent Application Publication 2011 / 0246597 describes a system in which a network interface component of a server can access a solid-state storage module of a server via a network storage access link that bypasses the central processing unit (CPU) and main memory of the server. Summary of the invention

[0007] According to an embodiment of the present disclosure, the present invention provides a data communication device, including a network interface, which includes one or more ports for connecting to a packet data network, and is configured to receive a data packet sequence from a remote device through the packet data network via the one or more ports in response to a data transmission request, the received sequence includes received data blocks, multiple received data blocks have block boundaries that are not aligned with the payload boundaries of the packets, so that corresponding data blocks in the received data blocks are divided into two corresponding segments in consecutive corresponding packets contained in the sequence, and a packet processing circuit, which is configured to use block ciphertext to perform cryptographic processing on the received data blocks so as to write the corresponding cryptographically processed data blocks into a memory, and at the same time save the segments of the corresponding data blocks in the received data blocks in the memory, so that the packet processing circuit stores the first segment of a corresponding received data block of the first packet in the memory until a second packet is received via the network interface, and then cryptographically processes the first segment and the second segment together so as to write the corresponding cryptographically processed data block into the memory.

[0008] Further according to an embodiment of the present disclosure, the device includes a host interface, which is configured to be connected to a host computer having a processing unit, and the processing unit is configured to manage the implementation of the data transfer request, wherein the packet processing circuit is configured to cryptographically process the received data block using the block ciphertext so that the corresponding cryptographically processed data block is written to the host computer via the host interface, and at the same time, the segment of the corresponding data block in the received data block is saved in the memory, so that the packet processing circuit stores the first segment of the data block of the corresponding received first packet in the memory until the second packet is received via the network interface, and then cryptographically processes the first segment and the second segment together so that the corresponding cryptographically processed data block is written to the host computer via the host interface.

[0009] Further according to an embodiment of the present disclosure, the group processing circuit is configured to find that the second segment is a partial block, retrieve the first segment from the memory, and in response to the second segment being a partial block, cryptographically process the first segment and the second segment together as a whole block using the block ciphertext.

[0010] In addition, according to an embodiment of the present disclosure, each of the packets includes an entire data block for cryptographic processing by the block ciphertext.

[0011] In addition, according to an embodiment of the present disclosure, the group processing circuit is configured to read the cryptographic parameters registered by the processing unit in the memory, the cryptographic parameters including an initial key and an initial value, calculate a first key in response to the initial key and the initial value, cryptographically process a first block of received data blocks in response to the first key, calculate an update value in response to the initial value and the size of the first block, calculate a second key in response to the initial key and the update value, cryptographically process a second block of received data blocks in response to the second key, and write the cryptographically processed first block and second block into the memory.

[0012] Further in accordance with an embodiment of the present disclosure, the update value indicates a storage location of the second block.

[0013] Furthermore, according to an embodiment of the present disclosure, the packet processing circuit is configured to encrypt the received data block using the block ciphertext so as to write the corresponding ciphertext data block into the memory.

[0014] In addition, according to an embodiment of the present disclosure, the packet processing circuit is configured to calculate a corresponding signature of the received data block or the ciphertext data block; and write the calculated signature into the memory.

[0015] Furthermore, according to an embodiment of the present disclosure, the packet processing circuit is configured to decrypt the received data block using the block ciphertext so as to write the corresponding plaintext data block into the memory.

[0016] Further according to an embodiment of the present disclosure, the packet processing circuit is configured to authenticate the corresponding signature of the received data block or the plaintext data block; in response to the corresponding signature being authenticated, write the corresponding data block in the plaintext data block into the memory.

[0017] According to another embodiment of the present disclosure, a data communication device is also provided, including a network interface, which includes one or more ports for connecting to a packet data network, and is configured to receive a data packet sequence from a remote device through the packet data network via the one or more ports in response to a data transmission request, the received sequence including a received data block, a data packet processing circuit, which is configured to read cryptographic parameters from a memory in which a processing unit registers the parameters, the cryptographic parameters including an initial key and an initial value, calculate a first key in response to the initial key and the initial value, cryptographically process a first block of the received data blocks in response to the first key, calculate an update value in response to the initial value and the size of the first block, calculate a second key in response to the initial key and the update value, cryptographically process a second block of the received data blocks in response to the second key, and write the cryptographically processed first and second blocks into the memory.

[0018] According to another embodiment of the present disclosure, a data communication device is also provided, including a packet processing circuit, which is configured to receive data from a memory in response to a data transmission request, and to perform cryptographic processing on the received data in units of data blocks using block ciphertext so as to add corresponding cryptographically processed data blocks to a sequence of data packets, the sequence including corresponding cryptographically processed data blocks having block boundaries that are not aligned with payload boundaries of corresponding packets, so that the corresponding cryptographically processed data blocks are divided into two corresponding segments contained in consecutive corresponding packets in the sequence, and a network interface, which includes one or more ports for connecting to a packet data network, and is configured to send the sequence of data packets to a remote device via the one or more ports through the packet data network.

[0019] Further according to an embodiment of the present disclosure, the apparatus comprises a host interface configured to be connected to a host computer comprising a processing unit configured to manage implementation of a data transfer request, wherein the packet processing circuit is configured to receive the data from the host computer via the host interface in response to the data transfer request.

[0020] In addition, according to an embodiment of the present disclosure, the group processing circuit is configured to receive a first data block from the memory, find that the first data block includes a first partial block, in response to finding that the first data block includes the first partial block, request a first additional data block from the memory, use the block ciphertext to cryptographically process the first partial block and the first additional data block as a whole block, generate a first cryptographically processed data block, divide the first cryptographically processed data block into the first segment and the second segment, add the first segment to the first group, and store the second segment in the memory until the second group is processed by the group processing circuit.

[0021] In addition, according to an embodiment of the present disclosure, the group processing circuit is configured to find a second segment stored in the memory, request a second data block from the memory in response to the found second segment, find that the second data block includes a second partial block, request an additional second data block from the memory in response to finding that the second data block includes the second partial block, use the block ciphertext to cryptographically process the second data block without the second partial block to generate at least one second cryptographically processed data block, use the block ciphertext to cryptographically process the second partial block and the additional second data block as a whole block to generate an additional second cryptographically processed data block, divide the additional second cryptographically processed data block into a third and a fourth segment, add the second segment, the at least one second cryptographically processed data block and the third segment to the second group, and store the fourth segment in the memory until the third group is processed by the data group processing circuit.

[0022] Further in accordance with an embodiment of the present disclosure, each of the packets includes a corresponding complete cryptographically processed data block.

[0023] Further according to an embodiment of the present disclosure, the group processing circuit is configured to read the cryptographic parameters registered by the processing unit in the memory, the cryptographic parameters including an initial key and an initial value, calculate a first key in response to the initial key and the initial value, perform cryptographic processing on a first block of the received data blocks in response to the first key, calculate an update value in response to the initial value and the size of the first block, calculate a second key in response to the initial key and the update value and perform cryptographic processing on a second block of the received data blocks in response to the second key.

[0024] In addition, according to an embodiment of the present disclosure, the update value indicates a storage location of the second block.

[0025] Furthermore, according to an embodiment of the present disclosure, the packet processing circuit is configured to encrypt a received data block using the block ciphertext so as to add a corresponding ciphertext data block to the data packet sequence.

[0026] Further according to an embodiment of the present disclosure, the packet processing circuit is configured to: calculate a corresponding signature of the received data block or the ciphertext data block; and add the calculated signature to the data packet sequence.

[0027] Furthermore, according to an embodiment of the present disclosure, the packet processing circuit is configured to decrypt the received data block using the block ciphertext so as to add the corresponding plaintext data block to the data packet sequence.

[0028] In addition, according to an embodiment of the present disclosure, the packet processing circuit is configured to: authenticate the corresponding signature of the received data block or the plaintext data block; in response to the corresponding signature being authenticated, add the corresponding plaintext data block to the data packet sequence.

[0029] According to another embodiment of the present disclosure, a data communication device is also provided, including a packet processing circuit, which is configured to receive data from a memory in response to a data transmission request, read the cryptographic parameters registered by the processing unit in the memory, the cryptographic parameters including an initial key and an initial value, calculate a first key in response to the initial key and the initial value, perform cryptographic processing on a first block of received data blocks in response to the first key, calculate an update value in response to the initial value and the size of the first block, calculate a second key in response to the initial key and the update value, perform cryptographic processing on a second block of received data blocks in response to the second key, and pack the first and second blocks into at least one packet; and a network interface, which includes one or more ports for connecting to a packet data network and is configured to send the at least one packet to a remote device through the packet data network via the one or more ports. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The present invention will be understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a block diagram of a data communications system constructed and operated in accordance with an embodiment of the present invention;

[0032] Figure 2 is included in Figure 1 A flowchart of the steps in a method of sending cryptographically processed data blocks to a remote device in a grouped form in a system;

[0033] Figure 3 is included in Figure 1 A flowchart of steps in a method of cryptographically processing a data block sent in a first packet in a system;

[0034] Figure 4 It is shown Figure 3 a block diagram of a method of a flowchart;

[0035] Figure 5 is included in Figure 1 A flowchart of steps in a method of cryptographically processing a data block sent in a second packet in a system;

[0036] Figure 6 It is shown Figure 5 a block diagram of a method of a flowchart;

[0037] Figure 7is included in Figure 1 A flowchart of the steps in a key calculation method in a system;

[0038] Figure 8 is included in Figure 1 A flowchart of the steps in a method for performing cryptographic processing on a received grouped data block in a system;

[0039] Fig. 9 is included in Figure 1 A flowchart of the steps in a method for performing cryptographic processing on a data block of a first group in a system;

[0040] Fig.10 It is shown Fig. 9 a flow chart of the method;

[0041] Fig.11 is included in Figure 1 A flowchart of the steps in a method of performing cryptographic processing on a data block of a second group in a system; and

[0042] Fig.12 It is shown Fig.11 A flow chart of the method is a block diagram. DETAILED DESCRIPTION

[0043] Overview

[0044] Data can be stored in encrypted form in a storage device using a self-encrypting disk to protect data at rest. When an authorized entity retrieves data from a storage device, such as based on an RDMA request, the data can be decrypted by the storage device. Encryption and decryption of storage devices can be inefficient and involve additional latency.

[0045] One solution is to perform encryption of the data to be stored (and / or decryption of data retrieved from memory) in a data communication device such as a network interface controller (NIC). Encryption and / or decryption can be performed as part of a packet processing pipeline. For example, data retrieved from a local storage device to be sent to a remote device can be decrypted in the NIC and then packaged to be sent to the remote device over the network. Data received from a local host for storage in a remote storage device can be encrypted in the NIC and then packaged to be sent to the remote storage device over the network. In another example, packets received from a remote device for storage in a local storage device can be encrypted in the NIC for storage in the local storage device. Packets received from a remote storage device can be decrypted in the NIC for transmission to the local host.

[0046] Data stored in a storage device may be stored in blocks of a size defined by the storage device, for example, in blocks of 512 or 520 bytes. However, when data is encrypted using a block ciphertext (e.g., using AES or any suitable block ciphertext), the block size of the block ciphertext (e.g., 16 bytes) may not align with the size of the storage block. Additionally, the packets used to transmit data across a network may not conform to the block ciphertext size or the block size used by the storage device. In some applications, the payload size of the packet may be fixed or dynamic. The above creates a problem when performing encryption and decryption in the NIC, which generally processes data based on packet size.

[0047] Embodiments of the present invention solve the above problems by providing a data communication device that detects a partial data block in data received from a memory (e.g., from a host memory of a host computer) and requests additional data so that the entire block fits into a size that a block ciphertext can be processed (e.g., encrypted or decrypted) by a block ciphertext. Some of the ciphertext-processed data blocks may not be aligned with a packet boundary of a packet to which the ciphertext-processed data blocks are to be added. Therefore, the misaligned blocks are divided into segments, one of which is included in one packet and the other is included in a subsequent packet.

[0048] When the data communication device receives a packet, the packet may similarly include one or more partial data blocks. The data communication device cryptographically processes (e.g., encrypts or decrypts) the entire data block that conforms to the block ciphertext size and writes the cryptographically processed entire data block to a memory (e.g., to a host memory of a host computer). The partial block may be stored in the memory until the next packet is received. The stored partial block is then retrieved from the memory and cryptographically processed (e.g., encrypted or decrypted) with the partial block from the next packet so that the entire data block that conforms to the block ciphertext size is cryptographically processed and written to the memory (e.g., to the host memory or the host computer).

[0049] In some embodiments, cryptographic processing may include calculating a signature of an encrypted block or a block to be encrypted. The calculated signature may be stored (in memory) or sent (to a remote device) with the encrypted block.

[0050] In some implementations, the cryptographic process may include authenticating a signature associated with a decrypted block or block to be decrypted. Providing a decrypted block (eg, a plaintext block) to a memory or remote device may be contingent on the signature of the authenticated block.

[0051] In some embodiments, the blocks are cryptographically processed according to cryptographic parameters registered in a memory (e.g., a host memory) by a processing unit, such as a central processing unit (CPU) or a graphics processing unit (GPU) of the host. The GPU can be configured to implement graphics rendering to perform various operations related to generating pixel data based on graphics data provided by the central processing unit (CPU). The GPU is used to generate three-dimensional (3D) graphics objects and two-dimensional (2D) graphics objects for various applications, including feature films, computer games, virtual reality (VR) and augmented reality (AR) experiences, mechanical design, etc.

[0052] The cryptographic parameters may include a block size, an initial value, and an initial key for the block ciphertext. The key for cryptographically processing the initial block may be calculated based on the initial value and the initial key. The initial value is generally updated for subsequent blocks, such as the size of the block. For example, if the initial value is 2000, then based on a 16-byte block size, the update value for the next block may be equal to 2016. The key for cryptographically processing subsequent blocks may be calculated based on the update value and the initial key. In some embodiments, the update value indicates the storage location of the current block being cryptographically processed. In some embodiments, the update value may include two values, for example, one value indicating a storage block number and another value indicating a location within the storage block.

[0053] The terms "scrambled" and "encrypted", in all their grammatical forms, are used interchangeably in this specification and claims to refer to any suitable scrambling and / or encryption method for scrambling and / or encrypting a data stream, and / or any other suitable method intended to render a data stream incomprehensible except to its intended recipient. Well-known types of scrambling or encryption include, but are not limited to, DES, 3DES, and AES (e.g., XTS-AES). Similarly, the terms "descrambled" and "decrypted", in all their grammatical forms, are used throughout this specification and claims to refer to the opposite of all grammatical forms of "scrambled" and "encrypted".

[0054] Block ciphers may use any suitable encryption / decryption type and / or mode and may process blocks of any suitable size.

[0055] System Description

[0056] Reference now Figure 1 , which is a block diagram of a data communication system 10 constructed and operated in accordance with an embodiment of the present invention. The data communication system 10 includes a data communication apparatus 12, a remote device 14, a host 16, and at least one storage device 18.

[0057] The data communication apparatus 12 includes a network interface 20 including one or more ports 22 for connecting to a packet data network 24. The remote device 14 is connected to the data communication apparatus 12 through the packet data network 24.

[0058] The data communication apparatus 12 also includes a host interface 26 that is configured to be connected to the host computer 16 via a suitable connection. The data communication apparatus 12 also includes a packet processing circuit 28 that processes data packets received from the remote device 14 or any other remote device via the network interface 20, and processes and packages the data for transmission to the remote device 14 or any other remote device via the network interface 20. By way of example only, the packet processing circuit 28 includes a block cipher 36 for performing cryptographic processing such as encryption, decryption, signature generation, and authentication.

[0059] In practice, some or all of the functions of the packet processing circuit 28 may be combined in a single physical component, or alternatively, implemented using multiple physical components. These physical components may include hard-wired or programmable devices, or a combination of both. In some embodiments, at least some of the functions of the packet processing circuit 28 may be performed by a programmable processor under the control of suitable software. For example, the software may be downloaded to the device in electronic form over a network. Alternatively or additionally, the software may be stored in a tangible, non-transitory computer-readable storage medium, such as an optical, magnetic or electronic memory.

[0060] The host computer 16 includes an interface 30, a memory 32, and a processing unit 34. The interface 30 connects the host computer 16 to the data communication device 12 via the host interface 26. The memory 32 stores data used by the processing unit 34 and optionally used by the data communication device 12. For example, the data communication device 12 can write data to the memory 32 and read data from the memory 32. In some embodiments, the data communication device 12 may include its own memory in which it stores data, while other data is optionally stored in the memory 32. The processing unit 34 may be locally connected to the storage device 18-1.

[0061] The remote device 14 may be locally connected to the storage device 18 - 2 .

[0062] The processing unit 34 is configured to manage the implementation of data transfer requests. The data transfer request may originate from the remote device 14 or from the host computer 16 or from any other suitable device. The data transfer request may include any one or more of the following: a request from the remote device 14 (or any suitable device) to store data in the storage device 18-1; a request from the remote device 14 (or any suitable device) to retrieve data from the storage device 18-1; a request from the host computer 16 to store data in the storage device 18-2; and a request from the host computer 16 to read data from the storage device 18-2. The data transfer request may include the transfer of data to or from another remote device via the data communication device 12 with or without the participation of the processing unit 34 of the host 16. In some embodiments, the data communication device 12 may include its own processing unit or array of processing units to handle the data transfer request. The processing unit 34 may satisfy the data transfer request according to any suitable protocol, such as RDMA.

[0063] In practice, some or all of the functions of processing unit 34 may be combined in a single physical component, or alternatively, implemented using multiple physical components. These physical components may include hardwired or programmable devices, or a combination of both. In some embodiments, at least some of the functions of processing unit 34 may be performed by a programmable processor (e.g., a CPU or GPU) under the control of suitable software. For example, the software may be downloaded to the device in electronic form over a network. Alternatively or additionally, the software may be stored in a tangible, non-temporary computer-readable storage medium, such as an optical, magnetic, or electronic memory.

[0064] Reference now Figure 2 , which is a flow chart 50, including Figure 1 The system 10 is sent to the remote device 14 in the form of a packet ( Figure 1 ) steps in a method for cryptographically processing a data block. Also referenced is Figure 1 .

[0065] The packet processing circuit 28 is configured to receive (block 52) data from the memory 32 (or any other suitable memory). The data may be provided in the memory 32 in response to a data transfer request from the remote device 14 and / or the data communication apparatus 12. In some embodiments, the packet processing circuit 28 is configured to receive data from the host computer 16 via the memory 32 through the host interface 26 in response to the data transfer request. In some embodiments, the data is read from the storage device 18-1 and written to the memory 32, and the data communication apparatus 12 reads the data therefrom.

[0066] The packet processing circuit 28 is configured to cryptographically process the received data in units of data blocks using the block ciphertext 36 (block 54) so ​​as to add the corresponding cryptographically processed data blocks to the sequence of data packets. The sequence of packets may include some cryptographically processed data blocks whose block boundaries are not aligned with (i.e., straddle) the payload boundaries of the corresponding packets, such that some cryptographically processed data blocks are divided into two corresponding segments, which are included in consecutive packets in the sequence. For example, the cryptographically processed data block may be divided into a portion of the cryptographically processed data block placed in one packet and another portion of the cryptographically processed data block placed in another (adjacent) packet.

[0067] A packet typically includes an entire cryptographically processed data block and may also include one or more partial data blocks. For example, some packets may include one partial block (at the beginning or end of the packet payload), some packets may include two partial blocks (one at the beginning of the packet payload and one at the end of the packet payload), and some packets may include an entire data block without any partial data blocks in the packet payload.

[0068] The processing of some data blocks will refer to Figures 3 to 6 Describe in more detail.

[0069] The steps of block 54 may include one or more sub-steps of blocks 56 - 62 described in more detail below.

[0070] If the received data block is plaintext, the packet processing circuit 28 is configured to encrypt (block 56) the received data block using the block ciphertext 36 so as to add the corresponding ciphertext data block to the sequence of data packets. The packet processing circuit 28 is optionally configured to calculate (block 58) a corresponding signature for the received data block or ciphertext data block. The steps of blocks 56 and 58 may be performed in any order. For example, the signature may be calculated based on the plaintext block or the ciphertext block. Figure 7 The calculation of the key is described in more detail.

[0071] If the received data block is ciphertext, the packet processing circuit 28 is optionally configured to authenticate (block 60) the corresponding signature of the received data block or plaintext data block (i.e., after decryption). The packet processing circuit 28 is configured to decrypt (block 62) the received data block using the block ciphertext 36 so as to add the corresponding plaintext data block to the sequence of data packets. The steps of blocks 60 and 62 may be performed in any order. For example, a plaintext block or a ciphertext block may be used to authenticate a signature.

[0072] The packet processing circuit 28 is configured to add (block 64) the cryptographically processed data blocks to their respective packets, with some of the blocks being divided between consecutive respective packets. In some embodiments, the packet processing circuit 28 is configured to add the calculated signature to the sequence of data packets. In some embodiments, the packet processing circuit 28 is configured to add the corresponding plaintext data blocks to the sequence of data packets in response to the corresponding signature being authenticated. In other words, the plaintext data blocks for which the corresponding signatures are successfully authenticated are added to the packets, while the plaintext data blocks for which the corresponding signatures are not successfully authenticated are not added to the packets.

[0073] The network interface 20 is configured to send (block 66 ) the sequence of data packets to the remote device 14 over the packet data network 24 via the one or more ports 22 .

[0074] Reference now Figure 3 and Figure 4 . Figure 3 is a flow chart 100, comprising Figure 1 Steps in a method of cryptographically processing a data block sent in a packet P1 in a system 10. Figure 4 It is shown Figure 3 100 is a block diagram 118 of the method of flowchart 100, illustrating the data flow between the memory 32 and the network interface 20. Also refer to Figure 1 .

[0075] The packet processing circuit 28 is configured to receive (block 102, Figure 4 The packet processing circuit 28 is configured to detect (block 104) that the data block A includes a portion of the block B. The packet processing circuit 28 is configured to respond to the detection that the data block A includes the portion of the block B request (block 106, Figure 4 The arrow 122 in FIG. 1 ) comes from an additional data block C of the memory controller (not shown) of the memory 32 .

[0076] The data packet processing circuit 28 is configured for cryptographic processing (block 108, Figure 4 The block processing circuit 28 is configured to perform cryptographic processing on the partial block B and the additional data block C together as a whole block using the block ciphertext 36 (block 110, Figure 4 ), a cryptographically processed data block E is generated. The packet processing circuit 28 is configured to divide (block 112) the cryptographically processed data block E into segments S1 and S2.

[0077] The data packet processing circuit 28 is configured to add to the packet P1 (block 114, Figure 4 The arrow 128 in FIG. 128 ) blocks A' and segment S1, which are then forwarded ( Figure 4The packet processing circuit 28 is configured to store the segment S2 (block 116, Figure 4 130) in memory 32 (or any suitable memory) until packet P2 is processed by packet processing circuit 28, as shown in reference Figure 5 and Figure 6 A more detailed description.

[0078] Reference now Figure 5 and Figure 6 . Figure 5 is a flow chart 150, including Figure 1 Steps in a method of cryptographically processing a data block sent in packet P2 in system 10. Figure 6 It is shown Figure 5 A flowchart of the method of block diagram 170 is provided. Also refer to Figure 1 .

[0079] The packet processing circuit 28 is configured to find (block 152, Figure 6 The packet processing circuit 28 is configured to request (block 154, arrow 172) the segment S2 stored in the memory 32 (or any suitable memory) from the memory controller. Figure 6 The packet processing circuit 28 may be configured to adjust the size of the data block F in response to the segment S2 being found. For example, if the packet processing circuit 28 normally requests data blocks of a size suitable for addition to a packet, the packet processing circuit 28 may adjust its request to reduce the size of the data block request by the size of the segment S2 (i.e., the requested size will be equal to the general packet size minus the size of the segment S2).

[0080] The packet processing circuitry 28 is configured to discover (block 156) that the data block F includes a partial block G. In some cases, the data block may include an integer number of blocks without a partial block. The packet processing circuitry 28 is configured to request (block 158, Figure 6 Arrow 176) appends data block H.

[0081] The packet processing circuit 28 is configured to use the block ciphertext 36 cryptographic processing (block 160, Figure 6 The entire block of data block F (i.e., data block F without partial block G) is processed by the block processing circuit 28 (block 162, arrow 178) to produce a cryptographically processed data block F'. The block processing circuit 28 is configured to process the partial block G and the additional data block H together as a whole block cipher using the block ciphertext 36 (block 162, Figure 6 ), generates an additional cryptographically processed data block K.

[0082] The group processing circuit 28 is configured to divide (block 164) the cryptographically processed data block K into segments S3 and S4. The group processing circuit 28 is configured to divide (block 166, Figure 6 The segment S2, the cryptographically processed data block F' and the segment S3 are added to the packet P2, which is then forwarded ( Figure 6 The packet processing circuit 28 is configured to store (block 168, arrow 186) in the memory 32 (or any suitable memory). Figure 6 Arrow 184) segment S4 until packet P3 is processed by the packet processing circuit 28, etc.

[0083] Reference now Figure 7 , which includes Figure 1 Flowchart 200 of steps in a key calculation method in system 10. Also refer to Figure 1 The steps described below may be used for key calculation whether the data communication device 12 is processing packets received via the packet data network 24 or packets to be transmitted via the packet data network 24 .

[0084] The processing unit 34 of the host computer 16 or another processing unit (e.g., in the data communication device 12) is configured to register cryptographic parameters in the memory 32 (or any suitable memory), for example, in response to a data transfer request. The cryptographic parameters may include an initial key K, an initial value V, and a block size of the block ciphertext 36. The cryptographic parameters may be registered in the memory 32 along with other parameters, for example, as part of an M key.

[0085] The packet processing circuitry 28 is configured to read (block 202) cryptographic parameters registered in the memory 32 (or any suitable memory).

[0086] The packet processing circuitry 28 is configured to calculate (block 204) a key K1 in response to the initial key K and the initial value V. The calculation may be based on any suitable key modification algorithm, for example, combining K and V using an XOR operation, or encrypting V using K. The packet processing circuitry 28 is configured to cryptographically process a block B1 of the received data blocks in response to the key K1 (block 206).

[0087] The packet processing circuit 28 is configured to calculate (block 208) an update value V1 in response to the initial value V and the size of the block B1 or any other suitable value. The update value V1 may indicate the storage location of the block B2. For example, if the initial value V is 2000, then based on a block size of 16 bytes, the update value V1 for the next block may be equal to 2016. The key for cryptographically processing subsequent blocks may be calculated based on the update value and the initial key K or a key used for previous encryption (e.g., K1). In some embodiments, the update value indicates the storage location (in the storage device 18-1 or the storage device 18-2) of the block to be cryptographically processed. In some embodiments, the update value may include two values, for example, one value indicating a storage block number (i.e., a block reference of a data block in one of the storage devices 18) and another value indicating a location in the storage block.

[0088] The packet processing circuit 28 is configured to calculate (block 210) a key K2 in response to the initial key K (or key K1) and the update value V1. The packet processing circuit 28 is configured to cryptographically process (block 212) a block B2 of the received data blocks in response to the key K2.

[0089] For the subsequent block B n , the packet processing circuit 28 is configured to respond to the previously updated value V n-1 and the previous block B n-1 (or any suitable value) to calculate (block 214) a new update value V n . Update the value V n Block B can be indicated n The packet processing circuit 28 is configured to respond to the initial key K (or K n-1 ) and update value V n To calculate (block 216) the key K n The packet processing circuit 28 is configured to respond to the key K n Cryptographic Processing (Block 218) Block B n The steps of blocks 214 - 218 may be repeated for subsequent blocks (arrow 220 ).

[0090] Reference now Figure 8 , which is a flow chart 300, including Figure 1 The steps in the method of cryptographically processing a received packet data block in the system 10. Also refer to Figure 1 .

[0091] The network interface 20 of the data communication device 12 is configured to receive (block 302) a sequence of data packets from the remote device 14 via the port 22 through the packet data network 24 in response to a data transmission request. The received sequence of data packets includes received data blocks. Some received data blocks have block boundaries that are not aligned with (i.e., straddle) the payload boundary of at least one packet, so that the corresponding received data blocks are divided into two corresponding segments contained in consecutive corresponding packets in the sequence. For example, a portion of the data block can be arranged in one packet and another portion of the data block can be arranged in another (adjacent) packet to divide the data block. The packet generally includes the entire data block and may also include one or more partial data blocks. For example, some packets may include one partial block (at the beginning or end of the packet payload), some packets may include two partial blocks (one at the beginning of the packet payload and one at the end of the packet payload), and some packets may include the entire data block without any partial data blocks.

[0092] The packet processing circuitry 28 is configured to cryptographically process the received data blocks using the block ciphertext 36 (block 304) so ​​as to write the corresponding cryptographically processed data blocks to the memory 32 (or any suitable memory) while maintaining some segments of the received data blocks in the memory 32, such that the packet processing circuitry 28 stores the segment S1 of the corresponding received data block B1 of the packet P1 in the memory 32 (or any suitable memory) until the packet P2 (including the segment of the data block B1) is received via the network interface 20, and then cryptographically processes the segments S1 and S2 together so as to write the corresponding cryptographically processed data blocks to the memory 32 (or any suitable memory). The processing of the partial data blocks will refer to FIG. Figure 9-12 Each data packet also typically includes an entire data block for cryptographic processing by block ciphertext 36.

[0093] In some embodiments, the packet processing circuit 28 is configured to cryptographically process the received data blocks using the block ciphertext 36 so as to write the corresponding cryptographically processed data blocks to the memory 32 of the host computer 16 via the host interface 26, while maintaining the segments of the corresponding received data blocks in the memory 32 (or any suitable memory), so that the packet processing circuit 28 stores the segment S1 in the memory 32 (or any suitable memory) until the packet P2 is received via the network interface 20, and then cryptographically processes the segments S1 and S2 together so as to write the corresponding cryptographically processed data blocks to the memory 32 of the host computer 16 via the host interface 26.

[0094] The steps of block 304 may include one or more sub-steps of blocks 30 - 312 described in more detail below.

[0095] If the received data block is plaintext, the packet processing circuit 28 is configured to encrypt (block 306) the received data block using the block ciphertext 36 so as to write the corresponding ciphertext data block to the memory 32 (or any suitable memory). The packet processing circuit 28 is optionally configured to calculate (block 308) a corresponding signature for the received data block or ciphertext data block. The steps of blocks 306 and 308 may be performed in any order. For example, the signature may be calculated based on the plaintext block or the ciphertext block. The above reference Figure 7 The calculation of the key is described in more detail.

[0096] If the received data block is ciphertext, the packet processing circuit 28 is optionally configured to authenticate (block 310) the corresponding signature of the received data block or the plaintext data block (i.e., after decryption). The packet processing circuit 28 is configured to decrypt (block 312) the received data block using the block ciphertext 36 to write the corresponding plaintext data block to the memory 32 (or any suitable memory). The steps of blocks 310 and 312 may be performed in any order. For example, a plaintext block or a ciphertext block may be used to authenticate the signature.

[0097] The packet processing circuit 28 is configured to write (block 314) the cryptographically processed data block and the optionally calculated signature to the memory 32 (or any suitable memory). In some embodiments, the packet processing circuit 28 is configured to write the corresponding plaintext data block to the memory 32 in response to the corresponding signature being authenticated. In other words, the plaintext data block whose corresponding signature has been successfully authenticated is written to the memory 32, while the plaintext data block whose corresponding signature has not been successfully authenticated is not written to the memory 32.

[0098] Reference now Fig. 9 and Fig.10 . Fig. 9 is a flow chart 400, including Figure 1 The steps in the method of performing cryptographic processing on the data block of the first group in the system 10. Fig.10 It is shown Fig. 9 A flowchart of the method of block diagram 412. Also refer to Figure 1 .

[0099] The packet processing circuit 28 is configured to receive (block 402, Fig.10 The packet processing circuit 28 is configured to detect (block 404) that a portion of the packet P1 includes a partial block (segment S1). The packet processing circuit 28 is configured to store (block 406, Fig.10 The packet processing circuit 28 is configured to cryptographically process the entire block M of the packet P1 (block 408, Fig.10The block processing circuit 28 is configured to write the cryptographically processed block M' into (block 410, Fig.10 Arrow 422) memory 32 (or any suitable memory).

[0100] Reference now Fig.11 and Fig.12 . Fig.11 is included in Figure 1 Flowchart 430 of the steps in a method of cryptographically processing a data block of group P2 in system 10. Fig.12 It is shown Fig.11 A flowchart of the method of block diagram 450 is also shown. Figure 1 .

[0101] The packet processing circuit 28 is configured to receive (block 432, Fig.12 The packet processing circuit 28 is configured to detect (block 434) that the packet P2 includes an initial partial block (segment S2) and a final partial block (segment S3). The packet processing circuit 28 is configured to store (block 436, Fig.12 The packet processing circuit 28 is configured to retrieve (block 438, arrow 456) segment S3 from memory in response to finding segment S2 in packet P2. Fig.12 458) segment S1.

[0102] The block processing circuitry 28 is configured to responsively detect that the segment S2 is a partial block using the block ciphertext 36 as a whole block together with the ciphertext (block 440, Fig.12 The block processing circuit 28 is configured to perform cryptographic processing on the entire block N of the packet P2 (block 442, Fig.12 The block processing circuit 28 is configured to write the cryptographically processed blocks C' and M' into (block 444, Fig.12 Arrow 464) memory 32 (or any suitable memory).

[0103] For the sake of clarity, various features of the invention described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, various features of the invention described in the context of a single embodiment may also be provided separately or in any suitable sub-combination.

[0104] The above embodiments are cited by way of example, and the present invention is not limited by what is specifically shown and described above. On the contrary, the scope of the present invention includes the combination and sub-combination of the various features described above, as well as changes and modifications that those skilled in the art would think of after reading the foregoing description and that are not disclosed in the prior art.

Claims

1. A data communication device, comprising: a network interface comprising one or more ports for connecting to a packet data network and configured to receive, in response to a data transmission request, a sequence of data packets from a remote device over the packet data network via the one or more ports, the received sequence comprising received data blocks, a plurality of received data blocks having block boundaries that are not aligned with payload boundaries of the packets such that respective ones of the received data blocks are divided into two respective segments contained in consecutive respective packets in the sequence; and a packet processing circuit configured to cryptographically process the received data blocks using the block ciphertext so as to write the corresponding cryptographically processed data blocks to a memory while simultaneously storing segments of corresponding ones of the received data blocks in the memory, such that the packet processing circuit stores a first segment of a corresponding one of the received data blocks of a first packet in the memory until a second packet is received via the network interface, and then cryptographically processes the first segment together with the second segment so as to write the corresponding cryptographically processed data block to the memory, The packet processing circuit is configured to: finding that the second segment is a partial block; and The first segment is retrieved from the memory, and in response to the second segment being a partial block, the first segment and the second segment are cryptographically processed together as a whole block using the block ciphertext.

2. The apparatus of claim 1 , further comprising a host interface, the host interface being configured to connect to a host computer having a processing unit, the processing unit being configured to manage implementation of the data transfer request, wherein the packet processing circuit is configured to cryptographically process the received data block using the block ciphertext so as to write the corresponding cryptographically processed data block to the host computer via the host interface, while simultaneously storing the segment of the corresponding data block in the received data block in the memory, so that the packet processing circuit stores the first segment of the data block corresponding to the first received packet in the memory until the second packet is received via the network interface, and then cryptographically processes the first segment and the second segment together so as to write the corresponding cryptographically processed data block to the host computer via the host interface.

3. The apparatus of claim 1, wherein each of the data packets includes an entire data block for cryptographic processing by the block ciphertext.

4. The apparatus according to claim 1, wherein the packet processing circuit is configured to: reading cryptographic parameters registered by the processing unit in the memory, the cryptographic parameters including an initial key and an initial value; calculating a first key in response to the initial key and the initial value; cryptographically processing a first one of the received data blocks in response to the first key; calculating an updated value in response to the initial value and a size of the first block; calculating a second key in response to the initial key and the update value; cryptographically processing a second block of the received data blocks in response to the second key; as well as The cryptographically processed first and second blocks are written to the memory. The apparatus of claim 4 , wherein the update value indicates a storage location of the second block.

6. The apparatus of claim 1, wherein the packet processing circuit is configured to encrypt a received data block using the block ciphertext so as to write a corresponding ciphertext data block into the memory.

7. The apparatus according to claim 6, wherein the packet processing circuit is configured to: calculate a corresponding signature of the received data block or the ciphertext data block; and write the calculated signature into the memory.

8. The apparatus of claim 1, wherein the packet processing circuit is configured to decrypt a received data block using the block ciphertext so as to write a corresponding plaintext data block to the memory.

9. The apparatus according to claim 8, wherein the packet processing circuit is configured to: authenticate the corresponding signature of the received data block or the plaintext data block; and write the corresponding plaintext data block in the plaintext data block into the memory in response to the corresponding signature being authenticated.

10. A data communication device, comprising: a network interface comprising one or more ports for connecting to a packet data network and configured to receive a sequence of data packets from a remote device over the packet data network via the one or more ports in response to a data transmission request, the received sequence comprising a received data block; A data packet processing circuit, wherein the data packet processing circuit is configured to: Reading the cryptographic parameters from a memory for registering cryptographic parameters of the processing unit, the cryptographic parameters including an initial key and an initial value; calculating a first key in response to the initial key and the initial value; cryptographically processing a first one of the received data blocks in response to the first key; calculating an updated value in response to the initial value and a size of the first block; calculating a second key in response to the initial key and the update value; cryptographically processing a second block of the received data blocks in response to the second key; as well as writing the cryptographically processed first and second blocks to the memory, and wherein: a received data block from said received data blocks having a block boundary that is not aligned with a payload boundary of said packet such that the corresponding received data block is divided into two corresponding segments contained in consecutive corresponding packets in said sequence; and The data packet processing circuit is configured to cryptographically process the received data blocks using block ciphertexts so as to write the corresponding cryptographically processed data blocks into a memory, while simultaneously storing segments in the received data blocks in the memory, such that the data packet processing circuit stores a first segment of a corresponding received data block of a first packet into the memory until a second packet is received via the network interface, and then cryptographically processes the first segment and the second segment together so as to write the corresponding cryptographically processed data blocks into the memory.

11. A data communication device, comprising: A packet processing circuit, the packet processing circuit being configured to: receiving data from the memory in response to a data transfer request; as well as cryptographically processing the received data in units of data blocks using a block ciphertext so as to add corresponding cryptographically processed data blocks to a sequence of data packets, the sequence including corresponding cryptographically processed data blocks having block boundaries that are not aligned with payload boundaries of corresponding packets, such that the corresponding cryptographically processed data blocks are divided into two corresponding segments contained in consecutive corresponding packets in the sequence; and a network interface comprising one or more ports for connecting to a packet data network and configured to send the sequence of data packets to a remote device over the packet data network via the one or more ports, wherein the packet processing circuit is configured to: receiving a first data block from the memory; finding that the first data block includes a first partial block; In response to finding that the first data block includes the first partial block, requesting a first additional data block from the memory; Using the block ciphertext, cryptographically process the first partial block and the first additional data block together as a whole block to generate a first cryptographically processed data block; dividing the first cryptographically processed data block into a first segment and a second segment; adding the first segment to a first group; and The second segment is stored in the memory until a second packet is processed by the packet processing circuit.

12. The apparatus of claim 11 , further comprising a host interface configured to connect to a host computer comprising a processing unit configured to manage implementation of data transfer requests, wherein the packet processing circuit is configured to receive the data from the host computer via the host interface in response to the data transfer request.

13. The apparatus of claim 11, wherein the packet processing circuit is configured to: finding a second segment stored in the memory; In response to the found second segment, requesting a second data block from the memory; finding that the second data block includes a second partial block; In response to finding that the second data block includes the second partial block, requesting an additional second data block from the memory; cryptographically processing the second data block without the second partial block using the block ciphertext to generate at least one second cryptographically processed data block; cryptographically processing the second partial block and the additional second data block together as a whole block using the block ciphertext to generate an additional second cryptographically processed data block; dividing the additional second cryptographically processed data block into a third segment and a fourth segment; adding the second segment, the at least one second cryptographically processed data block, and the third segment to the second packet; and The fourth segment is stored in the memory until a third packet is processed by the data packet processing circuit.

14. The apparatus of claim 11, wherein each of the packets comprises a corresponding complete cryptographically processed block of data.

15. The apparatus of claim 11, wherein the packet processing circuit is configured to: reading cryptographic parameters registered by the processing unit in the memory, the cryptographic parameters including an initial key and an initial value; calculating a first key in response to the initial key and the initial value; cryptographically processing a first one of the received data blocks in response to the first key; calculating an updated value in response to the initial value and a size of the first block; calculating a second key in response to the initial key and the update value; and A second one of the received data blocks is cryptographically processed in response to the second key. The apparatus of claim 15 , wherein the update value indicates a storage location of the second block.

17. The apparatus of claim 11, wherein the packet processing circuit is configured to encrypt a received data block using the block ciphertext so as to add a corresponding ciphertext data block to the sequence of data packets.

18. The apparatus according to claim 17, wherein the packet processing circuit is configured to: calculate a corresponding signature of the received data block or the ciphertext data block; and add the calculated signature to the data packet sequence.

19. The apparatus of claim 11, wherein the packet processing circuit is configured to decrypt a received data block using the block ciphertext to add a corresponding plaintext data block to the sequence of data packets.

20. The apparatus of claim 19, wherein the packet processing circuit is configured to: authenticate a corresponding signature of a received data block or the plaintext data block; and in response to the corresponding signature being authenticated, add the corresponding plaintext data block to the data packet sequence.

21. A data communication device, comprising: A packet processing circuit, the packet processing circuit being configured to: receiving data from the memory in response to a data transfer request; cryptographically processing the received data in units of data blocks using a block ciphertext so as to add corresponding cryptographically processed data blocks to a sequence of data packets, the sequence including corresponding cryptographically processed data blocks having block boundaries that are not aligned with payload boundaries of corresponding packets, such that the corresponding cryptographically processed data blocks are divided into two corresponding segments contained in consecutive corresponding packets in the sequence; reading cryptographic parameters registered by the processing unit in the memory, the cryptographic parameters including an initial key and an initial value; calculating a first key in response to the initial key and the initial value; cryptographically processing a first one of the received data blocks in response to the first key; calculating an updated value in response to the initial value and a size of the first block; calculating a second key in response to the initial key and the update value; cryptographically processing a second block of the received data blocks in response to the second key; as well as Packing the first block and the second block into at least one packet; and A network interface comprises one or more ports for connecting to a packet data network and is configured to send the at least one packet to a remote device over the packet data network via the one or more ports.

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