A method for threshold voltage tuning via selective deposition of high-k metal gate (HKMG) film stacks.

Abstract

A method for microfabrication of a three-dimensional transistor stack with a gate-all-around field-effect transistor device. Channels are suspended between source and drain regions. Each channel is selectively deposited with a material layer designed to adjust the threshold voltage of the channel. These layers can be oxides, high-k materials, work function materials, and metallizations. The three-dimensional transistor stack forms an array of high-threshold-voltage devices and low-threshold-voltage devices in a single package.

Description

[0001] Cross-references to related applications

[0002] This invention claims priority to U.S. Provisional Application 62 / 872,943, filed July 11, 2019, entitled “Method for Threshold Voltage Tuning Through Selective Deposition of High-K Metal Gate (HKMG) Film Stacks”, the entirety of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to microelectronic devices, including semiconductor devices, transistors, and integrated circuits, including methods of microfabrication and methods of adjusting transistor threshold voltage (V) through selective deposition processes. t The method. Background Technology

[0004] The fabrication of semiconductor devices (especially at the microscale) requires various manufacturing processes, such as film deposition, etch mask creation, patterning, material etching and removal, and doping. These processes are repeated to form the desired semiconductor device element on a substrate. Historically, transistors have been fabricated in a plane using microfabrication, with wiring / metallization formed above the active device plane, and thus the transistor is characterized as a two-dimensional (2D) circuit or 2D fabrication. Scaling has greatly increased the number of transistors per unit area in 2D circuits, but as scaling moves into the single-digit nanometer semiconductor device fabrication node, scaling is facing greater challenges. Semiconductor device manufacturers have expressed a demand for three-dimensional (3D) semiconductor circuits with transistors stacked on top of each other.

[0005] 3D integration—the vertical stacking of multiple devices—aims to overcome the scaling limitations experienced in planar devices by increasing transistor density volumetrically rather than area. While the flash memory industry has successfully demonstrated and implemented device stacking through the adoption of 3D nanometers, its application to randomized logic designs is substantially more challenging.

[0006] Threshold voltage (V) t Threshold voltage (VLV) is the minimum voltage required to activate a transistor within a CMOS (Complementary Metal-Oxide-Semiconductor) device. As CMOS devices shrink, the number of different threshold voltages used in a given design increases. Using different threshold voltages allows designers to optimize specific parts of the chip to operate with higher performance or lower power as needed. A typical device manufactured in a standard foundry at the N5 technology node can incorporate up to five different threshold voltages, which requires significant complexity in the chip manufacturing process.

[0007] There are several different methods to "tune" or create a threshold voltage (V). t One approach is to use channel doping to achieve different threshold voltages. Since the device size and channel width have been scaled down by nearly 50 angstroms for leading-edge FinFET devices, and the channel height for nanowire / nanosheet devices is also close to 50 angstroms, considering the significant reduction in mobility with smaller-sized coupled doped channels, channel doping is no longer a viable option for V1. t A poor choice for tuning. For such small channel dimensions, a single dopant atom can negatively impact device performance. Furthermore, the variability of the dopant within the channel is statistically difficult to control, and these atomic-scale variations can significantly affect the device's threshold voltage. Therefore, the application of channel doping can generate multiple undesirable Vth values ​​in the corresponding device. t Adjust the "flavor" or value.

[0008] V of CMOS devices t Other tuning methods have been implemented through work function metal (WFM) stack engineering, such as by adding multiple stacked metal films around the channel or by increasing the thickness of the WFM stack. Because the work function of the WFM stack is highly dependent on the thickness variation within each film of the WFM stack, complex integration processes have been developed that use etch-stop layers (ESLs) and atomic layer deposition (ALO) of the work function metal (WFM), multiple masking steps using expensive photolithography operations, and wet etching to impart controlled variations within the WFM stack to control the threshold voltage. This approach has become the dominant method for threshold voltage tuning at existing technology nodes, but it comes with increased integration and fabrication complexity in attempting to achieve multiple threshold voltage requirements.

[0009] Therefore, one object of this disclosure is to provide a method for adjusting the threshold voltage (V) through a selective deposition process. t Methods and systems for this purpose. Such processes can be used across FINFET, nanowire / nanosheet, complementary FET, and vertical FET devices. Summary of the Invention

[0010] Various aspects of this disclosure describe methods for adjusting the transistor threshold voltage (V) via a selective deposition process. t The method.

[0011] An exemplary embodiment describes a method of microfabrication. A substrate having channels for a gate-all-around (GAU) field-effect transistor device is used. The channels comprise a vertical stack of channels positioned adjacent to each other, wherein individual channels extend horizontally between source and drain regions in the vertical stack. In the vertical stack of channels, at least one channel is positioned above a second channel. The channels include at least four specified channel types, including high-voltage PMOS channels, high-voltage NMOS channels, low-voltage PMOS channels, and low-voltage NMOS channels.

[0012] In an exemplary embodiment, a first high-k dielectric is selectively deposited around an uncovered channel comprising a high-voltage PMOS channel, a high-voltage NMOS channel, a low-voltage PMOS channel, and a low-voltage NMOS channel. While the high-voltage and low-voltage PMOS channels are covered, a first work function metal is selectively deposited on the high-voltage and low-voltage NMOS channels. While the high-voltage and low-voltage NMOS channels are covered, a second work function metal is selectively deposited on the high-voltage and low-voltage PMOS channels. While the low-voltage PMOS and low-voltage NMOS channels are covered, a third work function metal is selectively deposited on the high-voltage PMOS and high-voltage NMOS channels. After the work function metals are deposited, conductive metal material is deposited on the high-voltage PMOS channels, high-voltage NMOS channels, low-voltage PMOS channels, and low-voltage NMOS channels.

[0013] Another exemplary embodiment describes a method for vertically stacking microfabricated nanochannels, each vertical stack having a different voltage threshold.

[0014] Another exemplary embodiment describes a three-dimensional transistor stack comprising: a substrate having channels for a gate-all-around field-effect transistor device, the channels comprising a vertical stack of channels positioned adjacent to each other, wherein each channel extends horizontally between source and drain regions, wherein in each vertical stack of channels, at least one channel is positioned above a second channel; and a first vertical stack of high-voltage NMOS channels, wherein each channel comprises a first high-k dielectric, a first work function metal, a third work function metal, and a conductive metal. The structure comprises: a second vertical stack of low-voltage NMOS channels, wherein each channel is surrounded by a first high-k dielectric, a first work function metal, and a conductive metal material; a third vertical stack of high-voltage PMOS channels, wherein each channel is surrounded by a first high-k dielectric, a second work function metal, a third work function metal, and a conductive metal material; a fourth vertical stack of low-voltage PMOS channels, wherein each channel is surrounded by a first high-k dielectric, a second work function metal, and a conductive metal material; a capping material on the conductive metal material; and input gate contacts connected to the conductive metal material.

[0015] For clarity, the different steps described herein have been presented. Generally, these steps can be performed in any suitable order. Furthermore, while each of the different features, techniques, configurations, etc., described herein may be discussed in different places within this disclosure, it is intended that each of the concepts can be performed independently of or in combination with each other. Therefore, the invention can be practiced and contemplated in many different ways.

[0016] The foregoing general description of the illustrative embodiments and the following detailed description are merely exemplary aspects of the teachings of this disclosure and are not restrictive. Attached Figure Description

[0017] As the present disclosure and its many accompanying advantages become better understood by referring to the following detailed description taken in conjunction with the accompanying drawings, a more comprehensive understanding of the present disclosure and its many accompanying advantages can be readily obtained, in which:

[0018] Figure 1 It is the cross section intercepted through the common gate after the nanosheet is released under high threshold voltage and low threshold voltage conditions.

[0019] Figure 2 The growth of an interfacial silicon oxide layer around the silicon nanosheet channel is shown.

[0020] Figure 3 Atomic layer deposition of a high-k film on the interface layer of silicon nanosheets is shown.

[0021] Figure 4Isotropic deposition of TiN cap on top of a high-k film is depicted.

[0022] Figure 5 An isotropic deposition of a TaN etch-stop layer on top of a TiN capping film is depicted.

[0023] Figure 6 Isotropic deposition of TiN work function metal across NMOS and PMOS gates is depicted.

[0024] Figure 7 The patterning of the filling material is shown.

[0025] Figure 8 It shows the result from V t The opening portion of the mask is used for wet etching to remove the TiN work function metal.

[0026] Figure 9 The TiN work function metal is shown only in the high threshold voltage PMOS gate.

[0027] Figure 10 An isotropic deposition of TaN on top of both the NMOS and PMOS gates is depicted.

[0028] Figure 11 The patterning of the filling material is shown.

[0029] Figure 12 Wet etching of a selectively applied TaN etch-stop layer on a high-k film for low-threshold voltage NMOS gates and low-threshold voltage PMOS gates is depicted.

[0030] Figure 13 The removal of the filler material is shown, which exposes the TaN layer retained for high threshold voltage NMOS gates and high threshold voltage PMOS gates.

[0031] Figure 14 The isotropic deposition of NMOS work function metal on top of NMOS and PMOS gates is depicted.

[0032] Figure 15 The patterning of the filling material is shown.

[0033] Figure 16 The wet etching of the NMOS work function metal from a low threshold voltage PMOS gate is shown.

[0034] Figure 17 The removal of the spin-coated carbon patterned filler layer is shown, which demonstrates how the NMOS work function metal is removed from the low threshold voltage PMOS gate while remaining on other gates.

[0035] Figure 18The isotropic deposition of lining material prior to the deposition of a high-conductivity metallic filler to complete the HKMG stack is depicted.

[0036] Figure 19 The HKMG structure is shown by filling it with a highly conductive metallic material.

[0037] Figure 20 The diagram illustrates the trenching of HKMG metal within the gate, the formation of the SiN cap, and the formation of the input gate contacts to the common gate.

[0038] Figure 21 The cross-sections are taken through the common gate after the nanosheet is released under high threshold voltage conditions (left) and low threshold voltage conditions (right).

[0039] Figure 22 Selective deposition of high-k dielectrics is shown directly on exposed nanosheets or nanowires within alternative gate trenches.

[0040] Figure 23 Selective deposition of TiN capping on top of a high-k film is shown.

[0041] Figure 24 The patterning of the filling material is shown.

[0042] Figure 25 Selective deposition of NMOS work function metals is shown across both high and low threshold voltage conditions.

[0043] Figure 26 The device is shown after the filler material has been removed.

[0044] Figure 27 Patterning of the fill material is depicted to effectively keep the NMOS gate “blocked” and TiN capping metal is used for PMOS to keep the gate open.

[0045] Figure 28 Selective deposition of PMOS work function metals across both high and low threshold voltage conditions is depicted.

[0046] Figure 29 The removal of the filler material is described.

[0047] Figure 30 The patterning of the filling material is shown.

[0048] Figure 31 Selective deposition of additional NMOS work function metals under two high threshold voltage conditions across two NMOS transistors is shown.

[0049] Figure 32 The removal of the filler material is shown.

[0050] Figure 33 The isotropic deposition of lining material prior to the deposition of a high-conductivity metallic filler to complete the HKMG stack is shown.

[0051] Figure 34 The HKMG structure is shown by filling it with a highly conductive metallic material.

[0052] Figure 35 The diagram illustrates the recess of HKMG metal within the gate, the formation of the SiN cap, and the subsequent formation of the input gate contacts to the common gate. Detailed Implementation

[0053] In the accompanying drawings, similar reference numerals designate the same or corresponding parts throughout several views. Furthermore, as used herein, unless otherwise stated, the terms "a" (one), "an" (an), etc., generally carry the meaning of "one or more". Unless otherwise stated or illustrated as a schematic structure or flowchart, the drawings are generally drawn to scale.

[0054] In addition, the terms “approximately,” “about,” “about,” and similar terms generally refer to a range of identified values ​​that include 20%, 10%, or preferably 5%, and any values ​​in between.

[0055] Various aspects of this disclosure relate to methods for vertically stacking microfabricated nanochannels and to three-dimensional transistor stacks comprising channels with different voltage thresholds, each vertical stack having a different voltage threshold.

[0056] A multi-gate MOSFET is a metal-oxide-semiconductor field-effect transistor that incorporates more than one gate into a single device. Multiple gates can be controlled by a single gate electrode, where multiple gate surfaces function electrically as a single gate, or they can be controlled by independent gate electrodes.

[0057] FinFET (Fin Field-Effect Transistor) is a non-planar transistor or "2D" transistor. A variant of the conventional MOSFET, FinFET is characterized by a thin silicon "fin" inversion channel on top of the substrate, allowing the gate to form two contact points: the left and right sides of the fin. The thickness of the fin (measured from the source to the drain) determines the effective channel length of the device. The wrap-around gate structure provides better electrical control of the channel, reduces leakage current, and overcomes other short-channel effects.

[0058] A gate-all-around (GAA) FET (abbreviated as GAAFET) is conceptually similar to a FinFET, except that the gate material surrounds the channel region on all sides. Depending on the design, a gate-all-around FET can have two or four active gates. A gate-all-around FET can utilize silicon nanowire stacks, where the gates are stacked entirely around the silicon nanowires.

[0059] The gate-all-around assembly is similar to a MOSFET, where the gate is sandwiched between the source and drain and has fins similar to those of a FinFET. However, unlike a conventional FinFET where the fins are placed vertically, a FinFET is turned on on its side with a gate-all-around configuration.

[0060] A gate-all-around FET can incorporate three or more nanowires. The nanowires forming the channel are suspended and extend from the source to the drain. A high-k / metal gate structure that controls the flow of current fills the gap between the source and drain.

[0061] A typical high-k metal gate (HKMG) integration process for FinFET CMOS devices includes: (a) removing polycrystalline or amorphous silicon through a wet etching process within the replacement gate; (b) removing the chemical oxide protecting the FIN structure within the replacement gate; (c) forming an interface silicon oxide layer on the cleaned FIN, wherein the interface oxide can be 8 to 12 angstroms thick for the core logic portion of current prior art devices, and much thicker than 12 angstroms for the high-voltage portions of the chip (e.g., at the input and output regions); and (d) depositing a high-k (HK) dielectric material (e.g., hafnium oxide (HfO)) on the interface layer through an atomic layer deposition process, wherein the thickness of the high-k film can be... (e) Depositing a titanium nitride (TiN) capping layer on the HK film via atomic layer deposition or conformal chemical vapor deposition (CVD); (f) Depositing an etch stop layer such as tantalum nitride (TaN) via atomic layer deposition or conformal CVD deposition; (g) Depositing polycrystalline or amorphous silicon into the alternative gate via chemical vapor deposition (CVD) or physical vapor deposition (PVD); (h) High-temperature annealing to drive the reliability of the HK film; (i) Removing the polycrystalline or amorphous silicon filler from the alternative gate; (j) Depositing a p-type work function metal across the NMOS and PMOS gates via atomic layer deposition or conformal CVD, wherein conventional p The work function metal includes TiN; (k) using a filler material such as spin-coated carbon (SOC) to block the NMOS gate and PMOS gate; (i) patterning a "blocking" mask that only turns on the NMOS portion of the alternative gate while blocking the PMOS portion; (m) once the NMOS portion of the alternative gate is turned on and the SOC material is etched away from the NMOS portion of the alternative gate, the TiN is wet-etched, wherein the underlying TaN etch stop layer (ESL) prevents any removal of the TiN cap deposited on top of the HK. Optionally, a second wet etching can be used to selectively remove the TaN without etching the underlying TiN; (n) subsequently from the PMOS portion of the alternative gate... The process involves removing the SOC to open both the NMOS and PMOS portions; (o) then depositing an n-type work function metal such as TiAl, TiAlN, or TiAlC across the NMOS and PMOS gates using atomic layer deposition or conformal CVD; (p) then depositing a liner material such as TiN or TaN within the NMOS and PMOS gates using atomic layer deposition or conformal CVD as a means of providing good barrier and adhesion for subsequent deposition of a highly conductive filler metal barrier layer such as tungsten, cobalt, ruthenium, or even aluminum or aluminum coalloys within the alternative gate trenches, and using wet etching to remove the metal and barrier film, wherein the alternative gate trenches are opened by means of a topologically patterned mask.Patterned masks cannot be used for atomic layer deposition of work functions and barrier metal processes because the deposition process itself is isotropic and deposits not only along the channel and within the sidewalls of the surrogate gate, but also along the topological barrier mask. This makes it difficult to remove the barrier mask pattern without first removing the deposition completed around the intended channel. By incorporating the topological barrier mask pattern into the wet etching process, selectivity can be added to the subtractive metal etching process, in which the desired film can be removed without interfering with the patterned barrier mask.

[0062] This approach to threshold voltage tuning presents challenges when multiple threshold voltages are required. In the examples above, both NMOS and PMOS have a single threshold voltage. For the case of two different threshold voltages for NMOS and PMOS, process integration becomes more extensive when tuning is achieved using work function metal stacking and thickness. NMOS devices with low threshold voltage conditions resemble the NMOS from the examples above, where the n-type work function metal is deposited directly on a TiN cap covered by an HK film. For high threshold voltage conditions in NMOS, the work function metal stack can be included within V... t The TaN barrier layer is not wet-etched during the tuning step. For the low-voltage condition of PMOS, the work function metal stack looks similar to the previous example, where TaN is deposited on a TiN cap covering HK, and then the work function metal, titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), or aluminum-doped titanium carbide (TiAlC), is deposited on TiN. The high-threshold voltage PMOS work function metal stack can contain an unremoved TaN barrier layer, a deposition of TiN on some type of continuous TiN without any TaN ESL, or even multiple pairs of TaN / TiN depositions from integration, which will again have a final n-type work function metal deposited on top. This addition of a single additional threshold voltage condition to both NMOS and PMOS will drive an increase in the etch stop layer deposition step, the photolithographic “block” patterning process, and several additional wet etch steps to remove the unwanted film from the low threshold voltage condition. The integration process can be optimized to reduce the number of associated block and etch steps that are removed, which is at high V t The work function metal stack comes at the cost of a large amount of additional metal, especially for PMOS gates.

[0063] The figures below illustrate the integration of NMOS and PMOS under two threshold voltage conditions. Each step sequence shows two separate sequences parallel to each other, with the left-handed sequence showing the high threshold voltage integration and the right-handed sequence showing the low threshold voltage integration. In both sequences, the high-k metal gate (HKMG) shown is the common gate, which includes the PMOS gate on the left-handed side of each individual image and the NMOS gate on the right-handed side of each individual image.

[0064] Figure 1 A cross-section is shown taken through the plane of the common gate of the all-around gate transistor block after the nanosheets are released under high threshold voltage conditions 110 and low threshold voltage conditions 120. The common gate will be processed to have a high-voltage PMOS stack (114), a high-voltage NMOS stack (116), a low-voltage PMOS stack, and a low-voltage NMOS stack. The stacks comprise vertical stacks of channels positioned adjacent to each other (see, for example, 112a, 112b, 112c of stack 114), in which each channel extends horizontally between the source / drain regions. In the vertical stack, at least one channel (e.g., 112c) is positioned above a second channel (112b). The final processed stack will include at least four specified channel types, including a high-voltage PMOS channel 114, a high-voltage NMOS channel 116, a low-voltage PMOS channel 124, and a low-voltage NMOS channel 126.

[0065] Figure 2 An interfacial silicon oxide layer (one shown as 230) grown on the outer surface of each silicon nanosheet channel is illustrated. Item 232 represents the lower silicon block, which is the unetched portion of the gate structure. Each channel stack is isolated from adjacent channel stacks by a dielectric material, not shown for clarity.

[0066] Figure 3 Atomic layer deposition of a high-k film 334 on the interface layer of a silicon nanosheet is shown. Since the high-k deposition of hafnium oxide is performed via atomic layer deposition, the deposit will cover the sidewalls and bottom of the substituted gate trench with a thickness equal to the thickness of the deposition around the nanosheet. Any deposition of a dipole-forming material (e.g., alumina or hafnium oxide) will be completed in situ or as a secondary deposition following the high-k film.

[0067] Figure 4 The isotropic deposition of TiN cap 435 on top of a high-k film 334 is depicted, followed by a subsequent annealing process.

[0068] Figure 5 The isotropic deposition of a TaN etch stop layer 536 on top of a TiN capping film 435 is shown. This layer will be used to prevent removal of the TiN capping film during subsequent metal removal for threshold voltage tuning, wherein the additional TiN serves as the work function metal.

[0069] Figure 6 Isotropic deposition of TiN work function metal 638 across NMOS and PMOS gates is shown.

[0070] Figure 7Patterning of filler material 740, such as spin-coated carbon (SOC), is shown to effectively keep the high threshold voltage PMOS gate 714 “blocked” and open the TiN work function metal for the low threshold voltage PMOS 724 and all NMOS gates (716, 726) to be removed by wet etching.

[0071] Figure 8 It shows the result from V t The mask opening is wet-etched after removing the TiN work function metal 638. The TaN layer 536 is an etch stop layer that prevents the removal of the TiN cap 435 over the high-k film 334. In an alternative embodiment, after this step, the wet etching can then be modified to focus on removing the selectively TiN 536 from TiN 435 to remove the etch stop layer as a means of reducing the total HKMG stack thickness. However, in this integration scheme, the TaN stop layer is retained to reduce Vk applied in subsequent integration processes. t Methods for adjusting the number of masks.

[0072] Figure 9 A high-voltage PMOS gate 914 with the SOC filler material 740 removed is depicted, thus showing the TiN work function metal 638 that is only retained within the high threshold voltage PMOS gate 914 and stripped away anywhere else.

[0073] Figure 10 Isotropic deposition of TaN 1044 on both NMOS and PMOS gates is depicted to provide an etch stop layer to protect the TiN work function metal of the high threshold voltage PMOS gate. Note that the deposition in both the NMOS and low threshold voltage PMOS gates effectively increases the amount of TaN deposited on these gates. Also note that, because these are isotropic depositions, whether by atomic layer deposition or conformal chemical vapor deposition, the deposition along the sidewalls and bottom of the alternative gate trench reflects what is deposited on the actual channel.

[0074] Figure 11 Selective patterning of filler materials such as spin-coated carbon (SOC) 1146 is shown to effectively keep the high threshold voltage PMOS gate 1114 and NMOS gate 1116 “blocked”. The low threshold voltage PMOS gate 1124 and NMOS gate 1126 are turned on to remove the TaN etch stop layer metal 1044 by wet etching.

[0075] Figure 12 Wet etching of a selective TaN etch stop layer 1044 on a high-k film 334 of a low-threshold voltage PMOS gate 1224 and an NMOS gate 1226 is depicted.

[0076] Figure 13 The removal of filler material 1146 is depicted, which exposes TiN work function material 638 for high threshold voltage PMOS gate 1314 and TaN 1044 for high threshold voltage NMOS gate 1316.

[0077] Figure 14 The isotropic deposition of NMOS work function metal 1448 (TiAlN shown here as an example) on top of the NMOS gate and PMOS gate is shown.

[0078] Figure 15 Patterning of a filler material such as spin-coated carbon (SOC) 1550 is shown to effectively keep the high threshold voltage PMOS gate 1514 and NMOS gate 1516, as well as the low threshold voltage NMOS 1526, "blocked". The low threshold voltage PMOS gate 1524 is turned on to remove the NMOS work function metal 1448 (hypothetically TiAlN here) by wet etching.

[0079] Figure 16 The wet etching of the work function metal 1448 (assumed to be TiAlN in this case) from the low threshold voltage PMOS gate 1624 is shown.

[0080] Figure 17 The removal of the spin-coated carbon patterned filler layer 1650 is shown, which shows that the NMOS work function metal 1448 (here assumed to be TiAlN) has been removed from the low threshold voltage PMOS gate 1724, exposing the TaN layer 536, while remaining on both the low threshold voltage NMOS gate 1726 and the high threshold voltage NMOS gate 1716 and PMOS gate 1714.

[0081] Figure 18 The isotropic deposition of liner material 1852 is shown before depositing a high-conductivity metallic filler to complete the HKMG stack. The liner will be deposited on the sidewalls of the trenches and around the nanowire channels. The liner is very thin (approximately 1 nm), so it does not significantly increase the thickness of the trench walls and the substrate. For cases using high-conductivity fillers (such as tungsten or cobalt), TiN or TaN is typically used as the liner material. Ruthenium can be used as a high-conductivity filler, in which case a liner material may not be necessary, but extensive physical simulations are required because ruthenium tends to be a p-type metal.

[0082] Figure 19The HKMG structure is depicted by filling a high-conductivity (HC) metallic material 1954 (assumed to be tungsten in this example). The HC metallic material fills all the open spaces within the transistor (gate), thus filling the sides of the trench and the nanowires. Note that for the case of lateral nanosheets with high threshold voltage conditions, the work function metal begins to fuse between adjacent nanosheets and the surrogate gate trench substrate. Despite conservative estimates for the liner / stop layer / work function thickness and the final 15 nm vertical spacing between the stacked nanosheets, the actual fusion is worse.

[0083] Figure 20 The image depicts the trenches of the HKMG metal stack within the gate, the formation of the SiN cap 2056, and the subsequent formation of the input gate contact 2058 to the common gate. The two stacks on the left show the high threshold voltage cases for PMOS 2014 and NMOS 2016. The two stacks on the right show the low threshold voltage cases for PMOS 2024 and NMOS 2026. Note the nanowires of the high-voltage PMOS stack 2014 (…). Figure 2 212a, b, c) are fused with the bottom wall, which may lead to high-voltage stack failure.

[0084] The integration process includes several additional steps for forming a simple NMOS / PMOS work function metal stack: (a) removing polysilicon or amorphous silicon within the alternative gate via a wet etching process; (b) removing the chemical oxide protecting the FIN structure within the alternative gate; (c) forming an interface silicon oxide layer on the cleaned FIN, wherein for current prior art devices of the core logic portion, the interface oxide can be approximately 8 to 12 angstroms thick, and for high-voltage portions of the chip such as input and output (I / O) portions, it can be much thicker than 12 angstroms; and (d) depositing a high-k (HK) dielectric material on the interface layer via an atomic layer deposition process, e.g. For example, HfO, where the thickness of the high-k film can vary from 10 Å to 20 Å in the core logic section; (e) depositing a TiN capping layer on the HK film by atomic layer deposition or conformal CVD deposition; (f) depositing an etch stop layer, such as TaN, by atomic layer deposition or conformal CVD deposition; (g) depositing polycrystalline or amorphous silicon into the alternative gate by chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes; (h) high-temperature annealing to improve the reliability of the HK film; (i) removing polycrystalline or amorphous silicon filler from the alternative gate; (j) depositing p-type work function metal across the NMOS and PMOS gates by atomic layer deposition or conformal CVD.

[0085] Common p-type work function metals include TiN; (k) using filler materials such as spin-coated carbon (SOC) to block NMOS and PMOS gates; (i) patterning will block the low V of the PMOS.t Simultaneously, only the NMOS portion and the high V of the alternative gate are turned on. t The "blocking" mask for the PMOS section (additional step); (m) once the NMOS section with the alternative gate is turned on and low V t PMOS section (additional steps) and only from the NMOS section with the alternative gate and low V t In the PMOS portion (additional step), the SOC material is etched away, and then TiN is wet-etched, wherein the underlying TaN etch stop layer (ESL) prevents any removal of the TiN cap deposited on top of HK. Optionally, a second wet etching can be used to selectively remove TaN without etching the underlying TiN; (n) the SOC is then removed from the PMOS portion with the alternative gate to open the NMOS portion and the PMOS portion.

[0086] Additional steps include: (n+1) a second ESL, such as TaNA, can then be deposited by atomic layer deposition or conformal CVD; (n+2) blocking the high threshold voltage portions of the NMOS and PMOS gates by filling a material such as spin-coated carbon (SOC) and topologically patterning a blocking mask, which only opens the low V values ​​of the NMOS and PMOS. t Partial; (n+3) wet etching removal of V t The TiN in the open region of the tuning mask is selectively replaced by TaN. In cases where multiple TaN films are on top of each other, two TaN films are removed by wet etching; for regions containing TaN+TiN+TaN, only the topmost TaN film is removed; (n+4) high V values ​​are removed from both the SOC and the NMOS and PMOS gates. t Partial topological patterning material.

[0087] The integration process continues: (o) an n-type work function metal, such as TiAl, TiAlN, or TiAlC, is then deposited across the NMOS and PMOS gates using atomic layer deposition or conformal CVD; (p) a liner material, such as TiN or TaN, is then deposited within the NMOS and PMOS gates by atomic layer deposition or conformal CVD as a means of providing good barrier and adhesion for subsequent deposition of highly conductive filler metals, such as tungsten, cobalt, ruthenium, or even aluminum or aluminum coalloys.

[0088] One problem with threshold voltage tuning using only work function metal stacking and thickness is that the total HKMG stack thickness becomes excessive, and the integration process becomes relatively complex, even for NMOS and PMOS with only two V values. t The conditions are similar. Typically, a TaN etch stop layer of at least 10 to 20 angstroms is required to achieve the desired high V for PMOS. tThe repeated TiN / TaN stacking significantly increases the thickness of the HKMG stack. A larger work function metal stack can ultimately limit the FIN spacing, and indirectly limit the p / n junction and distance between the FINs and any gate cuts. The FIN spacing typically coincides with the critical metal spacing, so any increase in FIN spacing to accommodate a larger HKMG stack, whether compensated for by increasing the critical metal spacing or by adding additional tracks in the critical metal layer, can result in a larger standard cell size. Typically, the etch stop layer used has much lower conductivity than the final gate fill metal, so utilizing the added ESL to occupy most of the HKMG stack will limit how much highly conductive fill metal can be used, significantly increasing the gate resistance. Conversely, an alternative is to reduce the number of FINs in the design, which will reduce the drive current and negatively impact device performance.

[0089] A second problem with this approach is that further increasing the number of available threshold voltages will increase the deposition of additional ESL layers, so for the highest threshold voltage conditions, there may not be enough space to prevent the metal from merging between adjacent FIN structures or between FIN and diced structures within the gate. With the addition of more threshold voltage conditions, integration becomes significantly more complex in terms of the number of required lithography block steps and the number of etch stop layer (ESL) films. To accommodate the increased number of films and the impact on gate resistance associated with placing a lower-conductivity metal within the open transistor body, direct etching of atomic layers of the work function metal must be considered to selectively etch certain crystalline orientations of the work function metal relative to the desired crystal structure. The risk of this approach is driven by thickness variations, especially when transitioning from FINFETs to nanosheet devices. In nanosheet devices, this etching must be highly isotropic and capable of etching the typically very wide bottom portion of the nanosheet relative to the top and side portions to control the threshold voltage.

[0090] This issue is not isolated from FinFET devices, but it also applies to nanowires and nanosheets, as well as complementary FET devices, where transistors are stacked on top of each other either in a common-gate configuration where NMOS and PMOS coexist within the same common gate, or in a split-gate configuration where NMOS and PMOS gates are stacked on top of each other but separated by a dielectric film, or in a stacked transistor configuration. For nanowire and nanosheet processes, the concern is not the Fin-to-FIN fusion of metals within the work function metal stack, but rather the fusion of one nanowire or nanosheet into another in the vertical direction. Whether it's a FinFET or a nanowire / nanosheet, once any fusion of a particular metal film exists between two adjacent channels, or even if the available spacing between adjacent channels is significantly reduced, subsequent deposition of the next metal in the stack is prevented from being deposited onto the channels as intended.

[0091] U.S. Patent Publication 2019 / 0172828, entitled "Semiconductor Apparatus Having Stacked Gates and Method of Manufacture Thereof," which is incorporated herein by reference in its entirety, describes a technique in which a work function metal stack is deposited by atomic layer selective deposition or CVD selective deposition to expose a channel material, which may be silicon, silicon-germanium (SiGe), or germanium. An interfacial silicon oxide layer can then be created at the interface between the channel material and the high-k selectively deposited film. This process can then be repeated, wherein other metal-containing films can be selectively deposited on the surface of other metal-containing films or conductive materials. These additional selectively deposited films may include dipole forming materials for high-k films such as hafnium oxide or aluminum oxide, capping materials for high-k films such as TiN, work function metals such as TiN, TiON, TiAl, TiAlN, TiC, and TiAlC, etch stop layers such as TaN, and even lining materials such as TiN and TaN to help fill high-conductivity filler metals such as aluminum, tungsten, cobalt, or ruthenium.

[0092] Self-assembled monolayers (SAMs) are one-molecule-thick layers of material that are bound to a surface in an ordered manner due to physical or chemical forces during the deposition process. Silanes can be formed into SAMs through solution or vapor deposition processes. Most commonly, chlorosilanes or alkoxysilanes are used. Once deposition occurs, chemical (ethylene oxide or Si-OM) bonds are formed with the surface, providing permanent modification to the substrate.

[0093] In one aspect of this disclosure, a self-assembled monolayer (SAM) is selectively attached to a dielectric film (such as a low-k spacer) to form the outer boundary of a typical alternative gate after polycrystalline or amorphous silicon has been pulled from the alternative gate. Because the self-assembled monolayer prevents deposition along the sidewalls of the open alternative gate trench, a high-k metal oxide film, such as hafnium oxide, can be selectively deposited around the channel material.

[0094] The application of selective deposition offers several benefits and features. The process provides a mechanism for forming “split gates” for complementary FET (CFET) devices, and an architecture in which NMOS and PMOS devices within the complementary device are stacked laterally or vertically on top of each other, as opposed to the side-by-side stacking done in conventional CMOS devices. Gate resistance is reduced by selectively depositing these materials only along the channel and then occupying the “released” or removed metal volume with a higher-conductivity metal such as tungsten, aluminum, cobalt, or ruthenium, by removing the liner layer, barrier layer, etch stop layer, and work function metal deposition along the sidewalls of the alternative gate trench. Features include reduced contact polycrystalline pitch (CPP) or gate pitch, where selective deposition allows for a smaller Lg (gate length) because no work function metal, liner layer, barrier layer, or etch stop layer is deposited at the interface between the inner sidewall of the alternative gate and the end of the gate channel within the gate structure, thus allowing for a smaller physical alternative gate size. Benefits include reduced FET capacitance, where dielectric-selective deposition of low-k materials (e.g., silicon oxide, SiOCH, SiCN, SiOCN, or SiOC) can be performed on the sidewalls of the alternative gate trench, thereby increasing the size of the gate spacer without changing the physical gate size, or combining this with a conductor-selective deposition process on conductors without changing the actual gate length (Lg). More detailed descriptions of these techniques can be found in the cited disclosures.

[0095] Various aspects of this disclosure include the ability to adjust the threshold voltage (V) of the channel through a selective deposition process. t This process can be used across FinFET, nanowire / nanosheet, complementary FET, and vertical FET devices. Both nanowires and nanosheets can be considered "nanochannels" or gate-all-around channels, meaning channels with gate stacks around the entire cross-section of the channel. The channel cross-section can be circular, square, rectangular, rounded, etc. The implementation uses nanosheet devices as a demonstration method, but this is non-limiting and can be applied to additional device architectures and designs, as well as any nanochannel.

[0096] The implementation methods include methods for manufacturing semiconductor devices and integration processes.

[0097] In one implementation, the threshold voltage of a prior art CMOS device is controlled by a high-k metal gate (HKMG) stack for each desired threshold voltage condition of the PMOS and NMOS transistors. Due to the reduction in channel size, current prior art devices do not wish to rely on channel doping. Hereinafter, the HKMG stack may include several components or layers. These layers may include: (a) an interface oxide layer; (b) a high-k dielectric film having an in-situ dipole forming material; (c) a capping layer; (d) a separate dipole forming layer on the high-k dielectric layer; (e) an etch stop layer; (f) NMOS work function metals and PMOS work function metals; (f) a liner material; and (g) a high-conductivity metal filler.

[0098] In another embodiment, thickness variation is achieved by adjusting the thickness of the work function metal and combining a metal stack containing a work function metal of a specific thickness with the introduction of a second metal on top (the latter method is typically used to set a higher threshold voltage for PMOS transistors).

[0099] The variability in thickness itself can lead to significant threshold voltage shifts, which is why the conventional approach to setting the unique work function thickness for threshold voltage tuning is done through an “addition and subtraction” process, in which the work function is deposited by atomic layer deposition or a highly controlled chemical vapor deposition process, followed by the deposition of some type of etch stop layer, another metal layer is deposited on top of the etch stop layer, and the second metal film is removed from the desired lower threshold voltage condition.

[0100] However, aspects of this disclosure integrate selective deposition atomic layer deposition or selective deposition chemical vapor deposition processes into the "addition" method, wherein a set work function metal thickness can be applied across all threshold voltage conditions, and additional work function metal can be deposited at higher threshold voltage conditions via a general photolithography process. Therefore, an etch stop layer is not required.

[0101] Furthermore, selective deposition methods for threshold voltage adjustment allow a wide range of different threshold voltages to be incorporated into CMOS designs, even with existing-scale dimensions. This can be achieved through the selective deposition process described herein, or by creating a blocking mask to turn on each NMOS and PMOS one at a time for each threshold voltage condition, and growing a portion or the entire HKMG stack on a single processing tool for each threshold voltage condition in a single time. Once a threshold voltage “HKMG stack” is complete, the photolithographic blocking material can be removed, and the process can then be repeated, where a new blocking mask is patterned to turn on the next threshold voltage condition.

[0102] Removing the etch stop layer in the add-and-subtract methods for threshold voltage tuning as described herein offers several advantages and features. The low-conductivity film of the HKMG stack can be replaced with a high-conductivity metal filler, such as tungsten, aluminum, cobalt, or ruthenium. This reduces the total number of films required to surround the gate channel. For device performance, it is desirable to stack nanowires / nanofa sheets as close as possible. However, this relatively dense stacking is often limited by the amount of metal film surrounding the channel, such that at some point, metal from the close-packed deposition will begin to fuse between two adjacent overlapping nanowires / nanofa sheets and affect transistor performance. Therefore, in such an "add-and-subtract" approach, the addition of multiple threshold voltages is greatly limited because higher threshold voltage conditions will include multiple etch stop layers in the stack. Subsequent etch stop layer removal steps, such as selective wet etching, can be employed in conventional processes, but these additional removal steps further increase process complexity and require sufficient selectivity to avoid etching either the capping or work function metal during the process.

[0103] Another benefit is a method to reduce the total HKMG stack thickness while increasing the number of available threshold voltages. This allows for a reduction in the lateral spacing of the nanowires and nanosheets, which can provide significant transistor performance benefits. Another benefit is a method to reduce any possibility of fused metal before the final high-conductivity metal fills to higher threshold voltage conditions. This provides better electrostatic control for individual channels.

[0104] Another aspect of this disclosure provides an integrated process that reduces the total number of photolithographic masking steps used. A common work function thickness for both low and higher threshold voltages can be deposited in a single step, and different threshold voltage conditions can be subsequently enabled to perform additional selective deposition, thus making the selective deposition method only "additional". The additional photolithographic masking steps can be minimized by allowing the addition of NMOS work function material on top of the NMOS work function metal to achieve the PMOS threshold voltage. The figure below illustrates how removing the subtracted etching steps can significantly reduce the step sequence.

[0105] The step sequence savings are achieved by bypassing existing "addition and subtraction" methods, which employ deposition, etch stop layer deposition, and second work function metal deposition on atomic layer deposition or chemical vapor deposition tools for work function metals, followed by removal from the corresponding tools and transfer to a wet etching tool to remove the second work function metal from low threshold voltage conditions, wherein this sequence is repeated for each increase in the number of threshold voltage conditions. For the selective deposition process of this disclosure, all depositions within a common threshold voltage can be performed sequentially within the same deposition tool.

[0106] Because the work function thickness in this paper can be controlled with great accuracy during selective deposition and with precision similar to atomic layer deposition (ALD), this method of setting the threshold voltage not only provides a significant increase in the number of threshold voltages available while maintaining a consistent or low HKMG stack thickness around the channel, but also provides finer increments of the threshold voltage that are now possible within the design presented in this paper.

[0107] The described features and benefits are based on threshold voltage conditions for two NMOS and two PMOS. Therefore, the benefits of the technique described herein are amplified when there are more than two threshold voltage conditions for NMOS and PMOS. Thus, multiple threshold voltages can be implemented for each of the NMOS and PMOS. The application of threshold voltage conditions can be limited to single-channel stacks, two-channel stacks, three-channel stacks, or four-channel stacks, for example... Figure 1 The disclosure includes both high-voltage PMOS and NMOS channels and low-voltage PMOS and NMOS channels. The selective threshold voltage technology of this disclosure is not limited to one, two, three, or four stacked channels and can be applied to multiple channels as needed.

[0108] An example implementation is shown below. For ease of description, this implementation is a single example to keep the total mask count the same as that processed by current prior art, but illustrates the use of selective deposition methods to reduce complexity and the total HKMG stack thickness. As will be understood, there can be many variations in target masking and deposition.

[0109] To overcome the issue of fusion thickness, selective deposition is used to bypass some etch stop layers. For ease of description, this implementation is a single example to keep the total mask count the same as the previously described current prior art processes, but illustrates a selective deposition method utilizing this disclosure to reduce complexity and decrease the total HKMG stack thickness. As will be understood, there can be many variations in target masking and deposition.

[0110] Figure 21 The cross-sections are captured through the common gates after the nanosheets are released under high threshold voltage conditions 2110 and low threshold voltage conditions 2120. Each common gate consists of a PMOS gate (2114, 2124) on the left and an NMOS stack (2116, 2126) on the right.

[0111] Figure 22 The selective deposition of a high-k dielectric 2232 (hypothetically hafnium oxide in this case) directly on exposed nanosheets or nanowires within an alternative gate trench is shown. An interfacial silicon oxide layer can be grown at the interface between the hafnium oxide and the nanowire / nanosheet structure, and the high-k film can also be in-situ doped with dipole-forming material.

[0112] Figure 23 The selective deposition of a TiN cap 2334 on top of a high-k film is illustrated, followed by a subsequent annealing process. Since all threshold voltage tuning is accomplished through selective deposition, rather than the "add and subtract" process typically used for high-side devices, etch-stop layers such as low-conductivity TaN, which occupy a significant volume across the entire HKMG stack, are no longer required. Removing these low-conductivity films allows for a significant improvement in overall gate resistance, particularly for CFET devices where gates are stacked on top of each other and may require a common gate contact connection to M1.

[0113] Figure 24 Patterning of filler materials such as spin-coated carbon 2440 (SOC) is shown to effectively keep the PMOS gate “blocked” (both high and low threshold conditions) and the TiN capping metal 2334 for the NMOS gate “on” (both high and low threshold conditions).

[0114] Figure 25 Selective deposition of NMOS work function metal 2538 across high and low threshold voltage conditions is illustrated. The SOC 2440 “blocks” the surfaces of the PMOS gates (2514, 2524), preventing any deposition along these nanowires / nanofalves. In this case, NMOS work function metal 2538 of common thickness is deposited under both threshold voltage conditions, with the aim of adding additional work function thickness to the high threshold voltage condition later during integration. This approach minimizes the total number of threshold voltage lithography modules, which is necessary in the process, as a means of reducing overall complexity and cost. Alternatively, for a very high number of threshold voltage conditions, each individual threshold voltage condition can be turned on one at a time for the required HKMG stack deposition, and then turned off for each individual V… t Tuning conditions repeat. V can be adjusted according to the designer's requirements. t Optimize for V by considering the number of "flavors," the total cost and efficiency required for the integration process. t The combination of tunable selective deposition capabilities.

[0115] Figure 26 The HKMG stack after removing the SOC filler material 2440 is shown.

[0116] Figure 27 Patterning of filler material 2740, such as spin-coated carbon (SOC), is shown to effectively keep the NMOS gate (both high threshold condition 2716 and NMOS low threshold condition 2726) "blocked" and the TiN capping metal 2334 (both high threshold condition 2714 and PMOS low threshold condition 2724) for the PMOS gate open.

[0117] Figure 28 Selective deposition of PMOS work function metal 2858 across high threshold voltage condition 2814 and low threshold voltage condition 2824 is depicted. The SOC 2740 “blocks” the surface of the NMOS gates (2816, 2826), preventing any deposition along these nanowires / nanofalves. A common thickness of PMOS work function metal, preferably TiN, is deposited under both threshold voltage conditions (2814, 2824) with the aim of adding additional work function thickness to the high threshold voltage condition later during integration. This approach minimizes the total number of threshold voltage lithography modules, which is necessary in the process, as a means of reducing overall complexity and cost. Alternatively, for a very high number of threshold voltage conditions, each individual threshold voltage condition can be turned on one at a time for the required HKMG stack deposition, and then turned off for each individual V... t Tuning conditions repeat. V can be adjusted according to the designer's requirements. t Optimize for V by considering the number of "flavors," the total cost and efficiency required for the integration process. t The combination of tunable selective deposition capabilities.

[0118] Figure 29 The HKMG stack after removing the SOC filler material 2740 is shown.

[0119] Figure 30 Patterning of filler materials such as spin-coated carbon 3040 (SOC) is shown to effectively keep the low threshold voltage conditions of both NMOS 3026 and PMOS 3024 “blocked” while the high threshold voltage conditions of both NMOS 3016 and PMOS 3014 are turned on within the alternative gate trench.

[0120] Figure 31 The selective deposition of additional NMOS work function metal 3138 across a stack of PMOS 3114 and NMOS 3116 is depicted to illustrate high threshold voltage conditions. In this way, NMOS threshold voltage adjustment can be easily achieved through the thickness difference of the work function metal, while the combined stacking of PMOS work function metal and NMOS work function metal 3138 of the PMOS transistor will be used for threshold voltage tuning of the PMOS gate.

[0121] Figure 32 The HKMG stack after the removal of SOC filler material 3040 is shown.

[0122] Figure 33The isotropic deposition of liner material 3352 prior to the deposition of a high-conductivity metallic filler to complete the HKMG stack is shown. For cases using high-conductivity fillers (e.g., tungsten or cobalt), TiN or TaN is typically used as the liner material. In this case, selective deposition of the TiN liner is not used because it acts as a "glue" layer for subsequent metal filling; therefore, the liner should be deposited isotropically within the trench. Ruthenium can be used as a high-conductivity filler, and a liner material may not be necessary in this case; however, due to ruthenium's tendency to act as a p-type metal, extensive physical simulations are required.

[0123] Figure 34 The HKMG structure is depicted by filling a high-conductivity metal material 3454 (assumed to be tungsten in this example). The high-conductivity metal material fills all unoccupied areas within the trench and surrounds the nanowire channel. Note that in the case of lateral nanosheets with high threshold voltage conditions, the work function metal no longer begins to fuse between adjacent nanosheets and the substrate of the alternative gate trench, as isotropically deposited in the case of HKMG stacks. Therefore, the ability to tune the threshold voltage by adjusting the thickness of the work function metal without requiring multiple etch-stop layers reduces the overall HKMG stack thickness around the channel, thus providing a means to reduce the lateral spacing of the nanowire / nanofe, which can provide performance benefits to the transistor and improve electrostatics for the individual channels under high threshold voltage conditions.

[0124] Figure 35 The diagram depicts the groove filled with HKMG metal within the gate, the formation of the SiN cap 3556, and the subsequent formation of the input gate contact 3558 to the common gate. The left side shows the high threshold voltage cases for the PMOS 3514 (left-handed) and NMOS 3516 (right-handed). The right side shows the low threshold voltage cases for the PMOS 3524 (left-handed) and NMOS 3526 (right-handed).

[0125] Figure 20 High-voltage PMOS nanowires 2012a-c and Figure 35 A comparison of the high-voltage PMOS nanowires 3512a-c shows Figures 21 to 35 The implementation method described herein improves the isolation of each nanowire.

[0126] Figures 21 to 35 The implementation provides gates surrounding nanowire / nanosheet transistor stacks, having PMOS high-voltage stacks and NMOS high-voltage stacks as well as PMOS low-voltage stacks and NMOS low-voltage stacks, each stack having a different threshold voltage V. t .

[0127] Figures 21 to 35A claimed first embodiment is described. The first embodiment describes a microfabrication method comprising: receiving a substrate having channels for a gate-all-around field-effect transistor device, the channels comprising a vertical stack of channels positioned adjacent to each other, wherein each channel extends horizontally between source and drain regions in the vertical stack of channels, wherein for each vertical stack of channels, at least one channel is positioned above a second channel, the channels comprising at least four specified channel types, including a high-voltage PMOS channel, a high-voltage NMOS channel, a low-voltage PMOS channel, and a low-voltage NMOS channel; selectively depositing a first high-k dielectric around the uncovered channels including the high-voltage PMOS channel, the high-voltage NMOS channel, the low-voltage PMOS channel, and the low-voltage NMOS channel; and depositing a first high-k dielectric around the high-voltage PMOS channel and the low-voltage NMOS channel. With the voltage PMOS channel covered, a first work function metal is selectively deposited on each high-voltage NMOS channel and each low-voltage NMOS channel; with the high-voltage NMOS channel and the low-voltage NMOS channel covered, a second work function metal is selectively deposited on each high-voltage PMOS channel and each low-voltage PMOS channel; with the low-voltage PMOS channel and the low-voltage NMOS channel covered, a third work function metal is selectively deposited on each high-voltage PMOS channel and each high-voltage NMOS channel; and after depositing the first work function metal, the second work function metal, and the third work function metal, a conductive metal material is deposited on the high-voltage PMOS channel, the high-voltage NMOS channel, the low-voltage PMOS channel, and the low-voltage NMOS channel.

[0128] The method further includes: covering a portion of a high-voltage NMOS channel and selectively depositing a second high-k dielectric on the uncovered portion of the high-voltage NMOS channel to induce different threshold voltages in the high-voltage NMOS channel, wherein the second high-k dielectric is made of the same or different material from the first high-k dielectric.

[0129] The method further includes: covering a portion of a high-voltage PMOS channel and selectively depositing a second high-k dielectric on the uncovered portion of the high-voltage PMOS channel to induce different threshold voltages in the high-voltage PMOS channel, wherein the second high-k dielectric is made of the same or different material from the first high-k dielectric.

[0130] The method further includes: covering a portion of a high-voltage NMOS channel and selectively depositing a specific work function metal on the uncovered portion of the high-voltage NMOS channel to induce different threshold voltages in the high-voltage NMOS channel.

[0131] The method further includes: selectively depositing a first capping material on the first high-k dielectric after depositing the first high-k dielectric.

[0132] The method further includes, wherein depositing a first high-k dielectric around an uncovered channel comprises: depositing the first high-k dielectric on all sides of a cross-section of the uncovered channel, but not on the sidewalls of the alternative gate.

[0133] The method further includes forming high-voltage channels with different gate stack thicknesses, thereby causing different threshold voltages in the high-voltage channels.

[0134] The method further includes forming low-voltage channels with different gate stack thicknesses, thereby causing different threshold voltages in the low-voltage channels.

[0135] The method further includes selectively depositing a first titanium nitride (TiN) capping material on the first high-k dielectric after depositing the first high-k dielectric.

[0136] The method further includes annealing the vertical stack of channels after depositing the first capping material, and annealing the vertical stack of channels after depositing the first titanium nitride capping material.

[0137] The method further includes, wherein covering a portion of the high-voltage NMOS channel comprises: patterning a filler material around a portion of the high-voltage NMOS channel, wherein the filler material is spin-coated carbon and the filler material is removed after selectively depositing a first high-k dielectric on the uncovered portion of the high-voltage NMOS channel.

[0138] The method further includes: covering the high-voltage PMOS channel and the low-voltage PMOS channel with a filler material before selectively depositing a first work function metal on each high-voltage NMOS channel and each low-voltage NMOS channel; and removing the filler material by wet etching after selectively depositing the first work function metal on each high-voltage NMOS channel and each low-voltage NMOS channel; covering the high-voltage NMOS channel and the low-voltage NMOS channel with a filler material before selectively depositing a second work function metal on each high-voltage PMOS channel and each low-voltage PMOS channel; and removing the filler material by wet etching after selectively depositing the second work function metal on each high-voltage PMOS channel and each low-voltage PMOS channel; and covering the low-voltage PMOS channel and the low-voltage NMOS channel with a filler material by wet etching before selectively depositing a third work function metal on each high-voltage PMOS channel and each high-voltage NMOS channel; and removing the filler material after selectively depositing the third work function metal on each high-voltage PMOS channel and each high-voltage NMOS channel.

[0139] The method further includes: isotropically depositing a liner material on a high-voltage PMOS channel, a high-voltage NMOS channel, a low-voltage PMOS channel, and a low-voltage NMOS channel prior to depositing a conductive metal material; selectively depositing each work function metal by one of atomic layer selective deposition (ALD) or chemical vapor selective deposition (CVD); selecting a liner material from the group consisting of tantalum nitride (TaN) and titanium nitride (TiN); selecting a conductive metal material from the group consisting of tungsten, cobalt, ruthenium, aluminum, and aluminum alloys; and selecting a work function metal from the group consisting of titanium nitride (TiN), titanium oxynitride (TiON), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), titanium carbide (TiC), and aluminum-doped titanium carbide (TiAlC).

[0140] about Figures 21 to 35A second embodiment is illustrated. The second embodiment describes a method for vertically stacking microfabrication nanochannels, wherein each vertical stack has a different voltage threshold. The method includes: receiving a substrate having channels for a gate-all-around field-effect transistor device, the channels comprising vertically stacked nanochannels positioned adjacent to each other, wherein each nanochannel extends horizontally between a source region and a drain region, wherein for each vertical stack of channels, at least one nanochannel is positioned above a second nanochannel. The channel includes at least four specified nanochannel types, including high-voltage PMOS nanochannels, high-voltage NMOS nanochannels, low-voltage PMOS nanochannels, and low-voltage NMOS nanochannels; a high-k film is deposited on each nanochannel; a titanium nitride (TiN) capping layer is selectively deposited on the high-k film; the substrate is annealed; a first filler material is patterned on the vertical stack of high-voltage PMOS nanochannels and low-voltage PMOS nanochannels; and an NMOS work function metal is selectively deposited on the TiN capping layer of the high-voltage NMOS nanochannels and low-voltage NMOS nanochannels. The process involves: removing the first filler material from the vertical stack of high-voltage and low-voltage PMOS nanochannels; patterning the second filler material on the vertical stack of high-voltage and low-voltage NMOS nanochannels; selectively depositing PMOS work function metal on the TiN capping layer of the high-voltage and low-voltage NMOS nanochannels; removing the second filler material from the vertical stack of high-voltage and low-voltage NMOS nanochannels; and patterning the second filler material on the vertical stack of low-voltage PMOS and NMOS nanochannels. The third filler material is patterned; NMOS work function metal is selectively deposited on the vertical stack of PMOS high-voltage nanochannels and NMOS high-voltage nanochannels; the third filler material is patterned from the vertical stack of PMOS low-voltage nanochannels and NMOS low-voltage nanochannels; each vertical stack is filled with a high-conductivity metal material; a first silicon nitride (SiN) cap is formed on the high-voltage stack, and a second silicon nitride (SiN) cap is formed on the low-voltage stack; a first input gate contact is formed in the first silicon nitride cap and a second input gate contact is formed in the second silicon nitride cap.

[0141] The method of the second embodiment includes selectively depositing each work function metal by one of atomic layer selective deposition (ALD) or chemical vapor selective deposition (CVD).

[0142] about Figures 21 to 35A third embodiment is shown. The third embodiment describes a three-dimensional transistor stack comprising: a substrate with vertically stacked channels for a gate-all-around field-effect transistor device, the vertically stacked channels being positioned adjacent to each other, wherein each channel extends horizontally between a source region and a drain region, wherein in each vertically stacked channel, at least one channel is positioned above a second channel; and a first vertically stacked high-voltage NMOS channels, wherein each channel is composed of a first high-k dielectric, a first work function metal, a third work function metal, and a conductive metal material. The structure comprises: a second vertical stack of low-voltage NMOS channels, wherein each channel is surrounded by a first high-k dielectric, a first work function metal, and a conductive metal material; a third vertical stack of high-voltage PMOS channels, wherein each channel is surrounded by a first high-k dielectric, a second work function metal, a third work function metal, and a conductive metal material; a fourth vertical stack of low-voltage PMOS channels, wherein each channel is surrounded by a first high-k dielectric, a second work function metal, and a conductive metal material; a capping material on the conductive metal material; and input gate contacts connected to the conductive metal material.

[0143] Obviously, many modifications and variations of this disclosure are possible based on the above teachings. Therefore, it should be understood that the invention can be practiced in ways other than those specifically described herein, within the scope of the appended claims.

[0144] In the foregoing description, specific details, such as the particular geometry of the processing system and the description of the various components and processes used herein, have been set forth. However, it should be understood that the techniques described herein can be practiced in other embodiments departing from these specific details, and such details are for illustrative purposes and not for limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, specific figures, materials, and configurations have been set forth for illustrative purposes to provide a thorough understanding. However, embodiments can be practiced without such specific details. Components having substantially the same functional construction are indicated by the same reference numerals, and therefore any redundant description may be omitted.

[0145] Various techniques have been described as multiple discrete operations to aid in understanding the various implementations. The order of description should not be interpreted as implying that these operations are necessarily sequential. In fact, these operations do not need to be performed in the presented order. The described operations may be performed in a different order than the described implementation. Various additional operations may be performed in additional implementations and / or the described operations may be omitted.

[0146] As used herein, “substrate” or “target substrate” generally refers to the object being processed according to the invention. A substrate may include any material portion or structure of a device—particularly a semiconductor or other electronic device—and may be, for example, a base substrate structure such as a semiconductor wafer, a photomask, or a layer (e.g., a thin film) situated on or superimposed on a base substrate structure. Therefore, the substrate is not limited to any particular base structure, underlying or overlay layer, patterned or unpatterned, but is contemplated to include any such layer or base structure, and any combination of layers and / or base structures. This description may refer to specific types of substrates, but this is for illustrative purposes only.

[0147] Many variations can be made to the operation of the techniques described above while still achieving the same objectives of the invention. Such variations are intended to be covered by the scope of this disclosure. Therefore, the foregoing description of embodiments of the invention is not intended to be restrictive. Rather, any limitations on embodiments of the invention are set forth in the appended claims.

Claims

1. A method for microfabrication, the method comprising: A substrate receiving a channel for a gate-all-around field-effect transistor device, the channel comprising a vertical stack of channels positioned adjacent to each other, wherein each channel extends horizontally between a source region and a drain region in the vertical stack of channels, wherein for each vertical stack of channels, at least one channel is positioned above a second channel, the channels comprising at least four specified channel types, including a high-voltage PMOS channel, a high-voltage NMOS channel, a low-voltage PMOS channel, and a low-voltage NMOS channel; A first high-k dielectric is selectively deposited around the uncovered channel, which includes a high-voltage PMOS channel, a high-voltage NMOS channel, a low-voltage PMOS channel, and a low-voltage NMOS channel. When the high-voltage PMOS channel and the low-voltage PMOS channel are covered, a first work function metal is selectively deposited on each high-voltage NMOS channel and each low-voltage NMOS channel; When the high-voltage NMOS channel and the low-voltage NMOS channel are covered, a second work function metal is selectively deposited on each high-voltage PMOS channel and each low-voltage PMOS channel; When the low-voltage PMOS channel and the low-voltage NMOS channel are covered, a third work function metal is selectively deposited on each high-voltage PMOS channel and each high-voltage NMOS channel; and After depositing the first work function metal, the second work function metal, and the third work function metal, conductive metal materials are deposited on the high-voltage PMOS channel, the high-voltage NMOS channel, the low-voltage PMOS channel, and the low-voltage NMOS channel.

2. The method according to claim 1, further comprising: A portion of the high-voltage NMOS channel is covered, and a second high-k dielectric is selectively deposited on the uncovered portion of the high-voltage NMOS channel to generate different threshold voltages in the high-voltage NMOS channel, wherein the second high-k dielectric is made of the same or different material as the first high-k dielectric.

3. The method according to claim 2, further comprising: A portion of the high-voltage PMOS channel is covered, and a second high-k dielectric is selectively deposited on the uncovered portion of the high-voltage PMOS channel to generate different threshold voltages in the high-voltage PMOS channel, wherein the second high-k dielectric is made of the same or different material as the first high-k dielectric.

4. The method according to claim 1, further comprising: A portion of the high-voltage NMOS channel is covered, and a specific work function metal is selectively deposited on the uncovered portion of the high-voltage NMOS channel to generate different threshold voltages in the high-voltage NMOS channel.

5. The method according to claim 1, further comprising: After depositing the first high-k dielectric, a first capping material is selectively deposited on the first high-k dielectric.

6. The method according to claim 1, wherein, Depositing the first high-k dielectric around the uncovered channel includes depositing the first high-k dielectric on all sides of the cross-section of the uncovered channel, but not on the sidewalls of the alternative gate.

7. The method according to claim 1, further comprising: High-voltage channels with different gate stack thicknesses are formed, thereby generating different threshold voltages in the high-voltage channels.

8. The method according to claim 1, further comprising: Low-voltage channels with different gate stack thicknesses are formed, thereby generating different threshold voltages in the low-voltage channels.

9. The method according to claim 1, further comprising: After depositing the first high-k dielectric, a first titanium nitride (TiN) capping material is selectively deposited on the first high-k dielectric.

10. The method of claim 5, further comprising: The vertical stack of the channels is annealed after the first capping material is deposited.

11. The method of claim 9, further comprising: The vertical stack of the channels is annealed after the first titanium nitride capping material is deposited.

12. The method according to claim 3, wherein, Covering a portion of the high-voltage NMOS channel includes patterning a filler material around the portion of the high-voltage NMOS channel, wherein the filler material is spin-coated carbon.

13. The method of claim 12, further comprising: The filler material is removed after selectively depositing the first high-k dielectric on the high-voltage NMOS channel.

14. The method according to claim 1, further comprising: Before selectively depositing the first work function metal on each high-voltage NMOS channel and each low-voltage NMOS channel, the high-voltage PMOS channel and the low-voltage PMOS channel are covered with a filler material, and after selectively depositing the first work function metal on each high-voltage NMOS channel and each low-voltage NMOS channel, the filler material is removed by wet etching. Before selectively depositing the second work function metal on each high-voltage PMOS channel and each low-voltage PMOS channel, the high-voltage NMOS channel and the low-voltage NMOS channel are covered with a filler material, and after selectively depositing the second work function metal on each high-voltage PMOS channel and each low-voltage PMOS channel, the filler material is removed by wet etching. as well as Before selectively depositing the third work function metal on each high-voltage PMOS channel and each high-voltage NMOS channel, the low-voltage PMOS channel and the low-voltage NMOS channel are covered with the filler material by wet etching, and after selectively depositing the third work function metal on each high-voltage PMOS channel and each high-voltage NMOS channel, the filler material is removed.

15. The method according to claim 1, further comprising: Before depositing the conductive metal material, a liner material is isotropically deposited on the high-voltage PMOS channel, the high-voltage NMOS channel, the low-voltage PMOS channel, and the low-voltage NMOS channel.

16. The method according to claim 1, further comprising: Each work function metal is selectively deposited using either atomic layer selective deposition (ALD) or chemical vapor selective deposition (CVD).

17. The method of claim 15, further comprising: The lining material is selected from the group consisting of tantalum nitride (TaN) and titanium nitride (TiN); The conductive metal material is selected from the group consisting of tungsten, cobalt, ruthenium, aluminum, and aluminum alloys; as well as Select work function metals from the group consisting of titanium nitride (TiN), titanium oxynitride (TiON), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), titanium carbide (TiC), and aluminum-doped titanium carbide (TiAlC).

18. A method for vertically stacking microfabricated nanochannels, each vertical stack having a different voltage threshold, the method comprising: A substrate receiving a channel for a gate-all-around field-effect transistor device, the channel comprising a vertical stack of nanochannels positioned adjacent to each other, wherein each nanochannel extends horizontally between a source region and a drain region, wherein for each vertical stack of nanochannels, at least one nanochannel is positioned above a second nanochannel, the nanochannels comprising at least four specified nanochannel types, including a high-voltage PMOS nanochannel, a high-voltage NMOS nanochannel, a low-voltage PMOS nanochannel, and a low-voltage NMOS nanochannel; Deposit a high-k film on each nanochannel; Titanium nitride (TiN) capping layer is selectively deposited on the high-k film; The substrate is annealed; The first filler material is patterned on a vertical stack of high-voltage PMOS nanochannels and low-voltage PMOS nanochannels; NMOS work function metals are selectively deposited on the TiN capping layers of high-voltage NMOS nanochannels and low-voltage NMOS nanochannels; Remove the first filler material from the vertical stack of high-voltage PMOS nanochannels and low-voltage PMOS nanochannels; The second filler material is patterned on a vertical stack of high-voltage NMOS nanochannels and low-voltage NMOS nanochannels; PMOS work function metal is selectively deposited on the TiN capping layer of the high-voltage NMOS nanochannel and the low-voltage NMOS nanochannel; Remove the second filler material from the vertical stack of high-voltage NMOS nanochannels and low-voltage NMOS nanochannels; A third filler material is patterned on a vertical stack of low-voltage PMOS nanochannels and low-voltage NMOS nanochannels. NMOS work function metal is selectively deposited on a vertical stack of high-voltage PMOS nanochannels and high-voltage NMOS nanochannels; The third filler material is patterned based on the vertical stacking of low-voltage PMOS nanochannels and low-voltage NMOS nanochannels. Fill each vertical stack with lining material; Each vertical stack is filled with a high-conductivity metallic material; A first silicon nitride (SiN) cap is formed on the vertical stack of a high-voltage PMOS nanochannel and a high-voltage NMOS nanochannel, and a second silicon nitride (SiN) cap is formed on the vertical stack of a low-voltage PMOS nanochannel and a low-voltage NMOS nanochannel; and A first input gate contact is formed in a first silicon nitride cap, and a second input gate contact is formed in a second silicon nitride cap.

19. The method of claim 18, further comprising: Each work function metal is selectively deposited using either atomic layer selective deposition (ALD) or chemical vapor selective deposition (CVD).

20. A three-dimensional transistor stack, comprising: A substrate having vertically stacked channels for a gate-all-around field-effect transistor device, the vertically stacked channels being positioned adjacent to each other, wherein each channel extends horizontally between source and drain regions in the vertical stack of channels, wherein, In each vertical stack of channels, at least one channel is positioned above the second channel; A first vertical stack of high-voltage NMOS channels, wherein each channel is surrounded by a first high-k dielectric, a first work function metal, a third work function metal, and a conductive metal material; A second vertical stack of low-voltage NMOS channels, wherein each channel is surrounded by the first high-k dielectric, the first work function metal, and a conductive metal material; A third vertical stack of high-voltage PMOS channels, wherein each channel is surrounded by a first high-k dielectric, a second work function metal, a third work function metal, and a conductive metal material; A fourth vertical stack of low-voltage PMOS channels, wherein each channel is surrounded by a first high-k dielectric, a second work function metal, and a conductive metal material; The sealing material on the conductive metal material; and The input gate contact is connected to the conductive metal material.

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