Processor-oriented data transfer instruction implementation method and system

Abstract

The application provides a processor-oriented data transfer instruction implementation method and system, and the method comprises the following steps: step S1: a RISC special processor decodes a read memory instruction, and data of a specific length byte is moved from a memory to a plurality of specified registers according to a memory address and a register first address given in the instruction; step S2: the RISC special processor decodes a write memory instruction, and data of a specific length byte is moved from a register to a specified memory address according to a memory address and a register first address given in the instruction. The application realizes fast moving operation of multiple data, has the advantages of flexible addressing mode, and thus improves the operation efficiency of the multiple data transfer instruction, which is beneficial to the multiple data moving operation in the application of the special processor, especially in the field of network processor, and the instruction greatly improves the operation efficiency of the special processor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular, to a processor-oriented data transfer instruction implementation method and system, and especially to a processor-oriented multi-data transfer instruction implementation method. BACKGROUND

[0002] In the early development of computer, the cost of memory is high, so it is desired to implement as many computer operations as possible by as few instructions as possible to reduce the memory resources consumed by the computer program, which leads to the formation of CISC design style, that is, to increase the complexity and function of instructions to improve the performance of computer. The processor based on CISC architecture has strong ability to process high-level language, so the code amount is small, but in order to cope with different computer operations, the hardware design complexity is usually high. With the development of computer technology, statistical data shows that the usage rate of various instructions in the program under CISC architecture is quite different (more than 80% of the instructions are rarely used in the program), which leads to the emergence of RISC architecture. RISC is the abbreviation of Reduced Instruction Set Computer, which simplifies the structure of the processor by reducing the number of instructions, standardizing the instruction format, simplifying the addressing mode and using a large number of register operations on the basis of CISC architecture, thereby greatly improving the performance, parallel processing capability and cost performance of the processor.

[0003] In RISC architecture, Load / Store instruction structure is adopted, which reduces the memory-memory operation instructions set in CISC architecture. In RISC instruction system, only Load / Store instructions can access memory, and other instructions operate data between registers. Since the processor can complete the read and write operations of the register in a single cycle, it well balances the speed difference between CPU and memory access, and improves the running efficiency of the processor. However, the traditional RISC instruction set has poor flexibility and small data throughput, and cannot take full advantage of the performance of the high-speed bus between memory and processor. On the other hand, with the development of technology, higher and higher requirements are put forward for data communication and processing speed, especially in the field of specific embedded special-purpose processors, such as network processors, a large amount of data exchange usually occurs in a short time, so the traditional Load / Store instruction cannot meet the real-time requirements caused thereby. In order to solve this problem, a high-speed multi-data access instruction structure is proposed, which extends the Load / Store in RISC instruction set. The extension provides a flexible multi-data transfer operation, which improves the access speed and flexibility of the processor to data, and further realizes fast response, high-speed external hardware control and special-purpose data processing operation, so as to be suitable for the design of special-purpose processor with strong real-time performance.

[0004] A dynamic reconfigurable instruction computer processor composed of a dynamic reconfigurable integrated circuit is disclosed in the patent document with publication number CN101364214A. The dynamic reconfigurable integrated circuit is connected to a configuration circuit, a user data input / output circuit, a random memory, a keyboard, a mouse, and a display of the dynamic reconfigurable integrated circuit. The dynamic reconfigurable integrated circuit includes a plurality of reconfigurable units, each of which is composed of an SRAM reconfigurable circuit with a configuration queue and a configuration clock. When the configuration clock of the corresponding configuration unit permits, the configuration unit is configured, i.e., the corresponding instruction is updated. When the configuration clock is disabled, the configuration unit is not configured with data for updating, and the original configuration is retained, i.e., the original reconfigurable instruction is retained.

[0005] Computer instruction: a command that can be directly recognized by a computer to complete a specific operation. It usually includes an operation code and an operand. The operation code determines the operation to be completed, and the operand indicates the data participating in the operation and its unit address and other information.

[0006] Register relative addressing: the address of the operand is composed of two parts, one of which exists in the CPU register, and the other exists in the computer instruction. The sum of the two is the address of the operand.

[0007] Base index addressing: the address of the operand is composed of two parts, both of which exist in the CPU register. The sum of the two is the address of the operand. Among them, the address stored in one register is the base, and the address stored in the other register is the index.

[0008] ASIC: Application Specific Integrated Circuit, which refers to an integrated circuit designed and manufactured according to the requirements of a specific user and the needs of a specific electronic system.

[0009] CISC architecture: Complex Instruction Set Computer architecture, which means that in the CISC architecture, the instruction format and length are usually variable, the number of instructions is relatively large, and the instruction execution period is not fixed.

[0010] RISC architecture: Reduced Instrucion Set Computer architecture, which means that in the RISC architecture, the instruction format and length are usually fixed, the number of instructions is relatively small, and most instructions can be executed within one cycle.

[0011] Harvard structure: refers to the storage of instructions and data in different memories, and the two memories are independently addressed and accessed, thereby avoiding the blocking of instructions and data during CPU operation.

[0012] The Load / Store instructions in the proposed RISC instruction set are either of small data throughput, which cannot bring the performance of high-speed bus into play, or of poor flexibility, which cannot meet the needs of special processors. With the development of technology, higher and higher requirements are put forward for data communication and processing speed, especially in the field of special embedded processors, such as network processors, in which a large amount of uncertain data exchange usually occurs in a short time, so the traditional Load / Store instructions cannot meet the real-time requirements caused thereby. Therefore, a technical solution is needed to improve the above technical problems. SUMMARY

[0013] In view of the defects in the prior art, the purpose of the present application is to provide a processor-oriented data transfer instruction implementation method and system.

[0014] According to the processor-oriented data transfer instruction implementation method provided by the present application, the method comprises the following steps:

[0015] Step S1: The RISC special processor decodes a read memory instruction, and moves data of a specific length byte from the memory to a specified plurality of registers according to the memory address and the register first address given in the instruction;

[0016] Step S2: The RISC special processor decodes a write memory instruction, and moves data of a specific length byte from the register to a specified memory address according to the memory address and the register first address given in the instruction.

[0017] Preferably, based on the RISC architecture, the load / Store instruction in the RISC is extended, and the memory addressing mode adopts register relative addressing and base address index addressing.

[0018] Preferably, lmr and smr are used to indicate the read memory and write memory instructions respectively, wherein l and s respectively represent load and store, m represents a plurality of byte access operations, and r represents that the memory base address comes from the register.

[0019] Preferably, two instructions are obtained: lmr reg.m.i, reg.n(A), B and smr reg.m.i, reg.n(A), B; wherein reg.m represents the first register to be read and written, i is the i-th byte in the corresponding register as the read / write starting position, Value(reg.n)+A is the first address of the memory to be accessed, Value(reg.n) represents the value in the corresponding register, A is an address offset, which comes from a register or an immediate number; and B is the number of bytes to be accessed, which comes from a register or an immediate number.

[0020] Preferably, the bit field width of the operation code lmr / smr is 4, corresponding to Bit[3:0] in the instruction code; the bit field width of the operand reg.m.i is 7, corresponding to Bit[31:25] in the instruction code.

[0021] Preferably, the bit field width of the operand reg.n is 5, corresponding to Bit[24:20] in the instruction code; the bit field width of the operands A and B is 8, corresponding to Bit[19:12] and Bit[11:4] in the instruction code respectively.

[0022] Preferably, the operand reg.m.i adopts byte addressing mode; reg.n adopts the value of a 32-bit register as base address to maximize the addressing space; A and B can adopt single-byte value or the value in a 32-bit register and an immediate number, increasing the addressing space or the byte range of the move.

[0023] Preferably, reg.n in the technical solution is replaced by con.n, thereby introducing two new instructions lmc reg.m.i,con.n(A),B and smc reg.m.i,con.n(A),B; wherein, c in the instruction represents that the memory start address comes from the constant table, and con.n represents that the memory start address comes from the nth item in the constant table.

[0024] Preferably, the 32-bit RISC CPU is of Harvard structure, and the instruction is implemented by pipeline, which is divided into five stages:

[0025] Instruction fetch: the processor saves the content in the instruction memory into the instruction register;

[0026] Decoding: the multi-data operation instruction is decoded to distinguish different instructions and determine the accessed registers and memory base address, offset address and the accessed byte number;

[0027] Execution: the actual memory start address is calculated according to the memory base address and the offset address;

[0028] Memory access: the bus is requested according to the decoded instruction to perform the multi-data move operation;

[0029] Write back: for the load type instruction, the returned data in the memory is written into the register.

[0030] The application also provides a processor-oriented data transfer instruction implementation system, which comprises the following modules:

[0031] Module M1: the RISC special-purpose processor decodes the read memory instruction to move the data of a specific length byte from the memory to the specified multiple registers according to the memory address and the register start address given in the instruction;

[0032] Module M2: RISC special processor decodes the write memory instruction, and moves the data of specific length bytes from the register to the specified memory address according to the memory address and the register first address given in the instruction.

[0033] Compared with the prior art, the present application has the following beneficial effects:

[0034] 1. The present application provides an instruction extension suitable for RISC special processor, and realizes the fast moving operation of multiple data;

[0035] 2. The present application provides a feasible instruction field division scheme, which has the advantages of large addressing range and flexible addressing mode, thereby improving the operation efficiency of the multiple data transfer instruction, which is beneficial to the multiple data moving operation in the application of special processor, especially in the field of network processor, which usually needs to move a large amount of data in sequence quickly, and the instruction will greatly improve the operation efficiency of the special processor;

[0036] 3. The present application introduces a constant table register, and by introducing the constant table register, the instruction operation efficiency and data processing speed are further improved, and the efficiency improvement comes from the fact that in the RISC architecture, the memory base addresses corresponding to different devices are usually fixed, and the register base addresses with high usage rate are stored in the constant table register, so that the values of the general registers do not need to be set when the multiple data moving instruction is executed, the number of instructions is reduced, and the instruction operation efficiency and data processing speed of the special processor are improved. BRIEF DESCRIPTION OF DRAWINGS

[0037] Other characteristics, objects and advantages of the present application will become more apparent from the following detailed description of the non-limiting embodiments with reference to the accompanying drawings:

[0038] Figure 1 Fig. 1 is a schematic diagram of the RISC top-level module structure of the present application;

[0039] Figure 2 Fig. 4 is a diagram showing the meanings of various fields in the assembly instruction of the present application;

[0040] Figure 3 Fig. 5 is a diagram of a feasible instruction bit field division scheme of the present application. DETAILED DESCRIPTION

[0041] The present application will be described in detail below with reference to specific embodiments. The following embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any form. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present application. These all belong to the protection scope of the present application.

[0042] ReferenceFigure 1 and Figure 2 To address this technical problem, a high-speed, multi-data-movement instruction structure is proposed, extending the Load / Store instruction in the traditional RISC instruction set. This extension improves the processor's data access speed, enabling rapid response, high-speed external hardware control, and dedicated data processing operations, thus making it suitable for real-time dedicated processor designs. This invention analyzes the data communication rate requirements in the Ethernet domain and the data access methods of traditional RISC CPUs, and extends the Load / Store instruction in the RISC CPU instruction set based on reduced instruction set computing frameworks such as MIPS, PowerPC, and ARM.

[0043] The operation implemented by the computer instructions in this invention addresses the need for greater flexibility and throughput in accessing memory data within the field of embedded dedicated processors. Based on this, this invention provides a feasible multi-data transfer instruction. Figure 1 A schematic diagram of the RISC top-level module structure corresponding to this invention is given, and the corresponding computer operations are as follows:

[0044] When the dedicated processor decodes the memory read instruction, it will move data of a specific length of bytes from memory to multiple specified registers according to the memory address and register start address given in the instruction. The registers, memory addresses, and byte lengths in the instruction are all flexible and variable, and the instruction execution cycle is flexible and variable according to the number of bytes moved.

[0045] When the dedicated processor decodes a write memory instruction, it will move a specific length of bytes of data from the register to the specified memory address according to the memory address and register starting address given in the instruction. The register, memory address, and byte length in the instruction are all flexible and variable, and the instruction execution cycle is flexible and variable according to the number of bytes moved.

[0046] Based on the RISC architecture and extended from the RISC load / store instructions, this invention employs register-relative addressing and base-indexed addressing for memory addressing to enable flexible multi-data transfer operations. This invention provides a naming convention for assembly instructions: using lmr and smr to indicate read and write memory instructions respectively, where l and s represent load and store, m represents multiple byte access operations, and r indicates that the memory base address comes from a register. This results in two instructions: lmrreg.mi,reg.n(A),B and smr reg.mi,reg.n(A),B. Figure 2The meanings of the different fields are summarized. Here, reg.m represents the first register to be read or written, i corresponds to the i-th byte in the register as the starting position for reading or writing, Value(reg.n)+A is the starting address of the memory to be accessed, Value(reg.n) represents the value in the corresponding register, A is the address offset, from a register or an immediate value, and B is the number of bytes to be accessed, from a register or an immediate value.

[0047] This invention provides an instruction bit field partitioning scheme for extended instructions in 32-bit RISC dedicated processors, such as... Figure 3 As shown, specifically: the bit field width of the opcode lmr / smr is 4, corresponding to Bit[3:0] in the instruction code; the bit field width of the operand reg.mi is 7, corresponding to Bit[31:25] in the instruction code; the bit field width of the operand reg.n is 5, corresponding to Bit[24:20] in the instruction code; the bit field widths of operands A and B are 8, corresponding to Bit[19:12] and Bit[11:4] in the instruction code, respectively. In the feasible instruction field partitioning scheme provided by this invention, the operand reg.mi adopts byte addressing, increasing flexibility; reg.n uses the value of a 32-bit register as the base address to maximize the addressing space; A and B can use single-byte values ​​or values ​​in 32-bit registers and immediate values, increasing the addressing space or the range of bytes to be moved, while also having high flexibility. For specific implementation methods, please refer to... Figure 3 .

[0048] Considering that in practical applications, the memory base addresses corresponding to different peripherals are usually fixed, this invention proposes introducing a constant table in a dedicated processor to accelerate the execution efficiency of extended instructions. Specifically, the implementation scheme replaces `reg.n` with `con.n`, thereby introducing two new instructions: `lmc reg.mi,con.n(A),B` and `smcreg.mi,con.n(A),B`. Here, `c` in the instructions represents that the memory starting address comes from the constant table. In the specific implementation, specific values ​​can be filled into the constant table as needed to facilitate assembly program calls. `con.n` represents that the memory starting address comes from the nth item in the constant table. At this point, Figure 3 The opcode in the table will be determined by lmc and smc, while the values ​​of bits 20 to 24 in the bit field will indicate the nth entry in the constant table, with the rest remaining unchanged. According to Figure 3 As shown, the instruction domain partitioning scheme of this invention supports a maximum of 32 constant table registers. Thus far, this invention provides four multiple data shift instructions for dedicated processors, summarized as follows:

[0049] lmr reg.mi,reg.n(A),B;

[0050] smr reg.mi,reg.n(A),B;

[0051] lmc reg.mi,con.n(A),B;

[0052] smc reg.mi,con.n(A),B.

[0053] Reference Figure 3 This invention provides a specific circuit embodiment. The 32-bit RISC CPU in this embodiment is assumed to be a Harvard architecture, with instructions implemented using a pipelined architecture, consisting of 5 stages:

[0054] Instruction fetch: The processor saves the contents of the instruction memory into the instruction register;

[0055] Decoding: Decode the multi-data operation instructions of the present invention to distinguish different instructions and determine the accessed registers and memory base addresses, offset addresses and the number of bytes accessed;

[0056] Execution: Calculate the actual starting address of memory based on the base address and offset address;

[0057] Memory access: Initiating a request to the bus based on the decoded instructions to perform multiple data transfer operations;

[0058] Write-back: For load-type instructions, the data returned from memory is written to a register.

[0059] The present invention also provides a processor-oriented data transfer instruction implementation system, the system comprising the following modules: Module M1: a RISC dedicated processor decodes a read memory instruction, and moves data of a specific length of bytes from memory to multiple specified registers according to the memory address and register starting address given in the instruction; Module M2: a RISC dedicated processor decodes a write memory instruction, and moves data of a specific length of bytes from registers to a specified memory address according to the memory address and register starting address given in the instruction.

[0060] This invention provides an instruction extension suitable for RISC dedicated processors, enabling fast multi-data transfer operations. It also provides a feasible instruction domain partitioning scheme with advantages such as a large addressing range and flexible addressing modes, thereby improving the operational efficiency of multi-data transfer instructions. This is beneficial for multi-data transfer operations in dedicated processor applications, especially in the field of network processors, where rapid sequential transfer of large amounts of data is often required. This instruction will significantly improve the operational efficiency of dedicated processors.

[0061] This invention introduces a constant table register, which further improves instruction execution efficiency and data processing speed. This efficiency improvement comes from the fact that, under the RISC architecture, the memory base address corresponding to different devices is usually fixed. By storing the base address of the frequently used register in the constant table register, the value of the general-purpose register does not need to be set when executing multiple data transfer instructions, reducing the number of instructions and thus improving the instruction execution efficiency and data processing speed of the dedicated processor.

[0062] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0063] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A method for implementing processor-oriented data transfer instructions, characterized in that, The method includes the following steps: Step S1: The RISC dedicated processor decodes the memory read instruction and moves data of a specific length of bytes from memory to multiple specified registers according to the memory address and register starting address given in the instruction; Step S2: The RISC dedicated processor decodes the memory write instruction and moves data of a specific length of bytes from the register to the specified memory address according to the memory address and register starting address given in the instruction; Based on the RISC architecture, it extends the load / Store instruction in RISC and adopts register-relative addressing and base-indexed addressing for memory addressing. The instructions for reading and writing memory are indicated by lmr and smr, respectively. Here, l and s represent load and store, respectively, m represents multiple byte access operations, and r represents that the memory base address comes from a register. Two instructions are obtained: `lmr reg.mi,reg.n(A),B` and `smr reg.mi,reg.n(A),B`; where `reg.m` represents the first register to be read or written, `i` corresponds to the i-th byte in the register as the start position for reading or writing, `Value(reg.n)+A` is the starting address of the memory to be accessed, `Value(reg.n)` represents the value in the corresponding register, `A` is the address offset, which comes from the register or an immediate value; and `B` is the number of bytes to be accessed, which comes from the register or an immediate value. The bit field width of the opcode lmr / smr is 4, corresponding to Bit[3:0] in the instruction code; the bit field width of the operand reg.mi is 7, corresponding to Bit[31:25] in the instruction code; The bit field width of operand reg.n is 5, corresponding to Bit[24:20] in the instruction code; the bit field width of operands A and B is 8, corresponding to Bit[19:12] and Bit[11:4] in the instruction code, respectively.

2. The processor-oriented data transfer instruction implementation method according to claim 1, characterized in that, The operand reg.mi uses byte addressing. reg.n uses the value of a 32-bit register as the base address to maximize the address space; A and B can use a single-byte value or a value in a 32-bit register and an immediate value, increasing the address space or the range of bytes that can be moved.

3. The processor-oriented data transfer instruction implementation method according to claim 2, characterized in that, The technical solution replaces reg.n with con.n, thereby introducing two new instructions lmc reg.mi,con.n(A),B and smcreg.mi,con.n(A),B; where 'c' in the instructions represents that the memory starting address comes from the constant table, and 'con.n' represents that the memory starting address comes from the nth item in the constant table.

4. The processor-oriented data transfer instruction implementation method according to claim 3, characterized in that, The 32-bit RISC CPU uses the Harvard architecture, and its instructions are implemented using a pipelined system with five stages. Instruction fetch: The processor saves the contents of the instruction memory into the instruction register; Decoding: Decode the multi-data operation instructions of the present invention to distinguish different instructions and determine the accessed registers and memory base addresses, offset addresses and the number of bytes accessed; Execution: Calculate the actual starting address of memory based on the base address and offset address; Memory access: Initiating a request to the bus based on the decoded instructions to perform multiple data transfer operations; Write-back: For load-type instructions, the data returned from memory is written to a register.

5. A system for implementing the processor-oriented data transfer instruction implementation method of claim 1, characterized in that, The system includes the following modules: Module M1: The RISC dedicated processor decodes the memory read instruction and moves data of a specific length in bytes from memory to multiple specified registers according to the memory address and register starting address given in the instruction; Module M2: The RISC dedicated processor decodes the write memory instruction and moves data of a specific length from the register to the specified memory address based on the memory address and register starting address given in the instruction.

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