A data processing method, apparatus and system

Abstract

The embodiment of the application provides a data processing method, device and system. In the method, in the sending direction, data of a target instance stored in a host register is written into a first storage area of a first memory corresponding to the target instance, and the data of the target instance is transmitted by using a target FlexE management channel; when the first storage area is full, data in the first storage area is read as target data; the target data is inserted into a position of the target FlexE management channel in an OH frame; and the OH frame after the insertion is sent. By using the technical solution provided in the embodiment of the application, the problem that message data cannot be accurately parsed due to the CPU interruption in the task running process is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a data processing method, device and system. BACKGROUND

[0002] FlexE (Flexible Ethernet) technology is a flexible Ethernet interface standard defined by OIF (Optical Internetworking Forum), which is an interface technology for implementing service isolation and network slicing of a bearer network.

[0003] The FlexE management channel is a transmission channel for user-defined applications in a FlexE OH (Overhead) frame. In the sending direction, a CPU (Central Processing Unit) writes a data block of a message into a host register, reads the data block from the host register as a data block of the FlexE management channel, inserts the data block into the OH frame, and sends the OH frame. In the receiving direction, the data block of the FlexE management channel is extracted from the OH frame and written into the host register, and the CPU reads the data block from the host register and processes it.

[0004] The FlexE management channel cannot be interrupted during the sending or receiving of a message, but it may be randomly interrupted by the CPU during task execution, which cannot guarantee the continuous sending and receiving of message data, and thus the message data cannot be accurately parsed. SUMMARY

[0005] The embodiments of the present application aim to provide a data processing method, device and system to solve the problem that message data cannot be accurately parsed due to interruption by the CPU during task execution. The specific technical solutions are as follows:

[0006] In a first aspect, the embodiments of the present application provide a data processing method, which comprises:

[0007] writing data of a target instance stored in a host register into a first storage area of a first memory corresponding to the target instance, wherein the data of the target instance is transmitted by a target FlexE management channel;

[0008] reading data from the first storage area as target data when the first storage area is full;

[0009] inserting the target data into a position of the target FlexE management channel in an OH frame;

[0010] sending the OH frame after the insertion.

[0011] In a second aspect, an embodiment of the present application provides a data processing method, the method comprising:

[0012] extracting target data from a position of a target FlexE management channel in a received OH frame, the target FlexE management channel being used to transmit data of a target instance;

[0013] writing the target data into a second memory corresponding to the target instance;

[0014] when an amount of data stored in the second memory is greater than or equal to a preset data amount, writing the data stored in the second memory into a host register;

[0015] processing the data stored in the host register.

[0016] In a third aspect, an embodiment of the present application provides a data processing apparatus, the apparatus comprising: a host write module, an encoding module, a first memory, and a storage reading module;

[0017] the host write module is configured to read data of a target instance stored in a host register, the data of the target instance being transmitted by using a target FlexE management channel;

[0018] the encoding module is configured to encode the data read by the host write module, and write the data obtained after encoding into a first storage area of the first memory;

[0019] the storage reading module is configured to read data from the first storage area as target data when the first storage area is full, insert the target data into a position of the target FlexE management channel in an OH frame, and send the OH frame after inserting the data.

[0020] In a fourth aspect, an embodiment of the present application provides a data processing apparatus, the apparatus comprising: a host reading module, a decoding module, a second memory, and a storage writing module;

[0021] the storage writing module is configured to extract target data from a position of a target FlexE management channel in a received OH frame, the target FlexE management channel being used to transmit data of a target instance, and write the target data into the second memory corresponding to the target instance;

[0022] the decoding module is configured to read data from the second memory when an amount of data stored in the second memory is greater than or equal to a preset data amount, and decode the read data;

[0023] The host reading module is configured to write the decoded data into a host register, so that the CPU processes the data stored in the host register.

[0024] In a fifth aspect, the embodiments of the present application provide a data processing system, including the data processing apparatus provided in the third aspect and the data processing apparatus provided in the fourth aspect.

[0025] The embodiments of the present application have the following beneficial effects:

[0026] In the technical scheme provided by the embodiments of the present application, after the data is written into the host register, the data is written into the corresponding memory before the data is sent, or the data is written into the corresponding memory before the data is written into the host register after the data is received. In this case, even if the task is interrupted by the CPU during the running process, no data is written into the host register, but in the sending direction, enough data is stored in the corresponding memory, and during the period of time when the CPU is interrupted, the data can be continuously read from the memory, thereby ensuring the continuous sending of the packet data, and in the receiving direction, the corresponding data can be continuously written into the corresponding memory, and after the interruption is restored, the corresponding data can be read to write into the host register, thereby ensuring that the packet data can be accurately parsed, and the problem that the packet data cannot be accurately parsed due to the interruption of the CPU during the running process of the task is solved.

[0027] Of course, implementing any product or method of the present application does not necessarily require all the advantages described above. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only some embodiments of the present application, and other embodiments can be obtained by those skilled in the art based on these drawings.

[0029] Figure 1 A schematic diagram for the deployment of FlexE management channel;

[0030] Figure 2 The first flowchart of the data processing method provided by the embodiments of the present application;

[0031] Figure 3 The second flowchart of the data processing method provided by the embodiments of the present application;

[0032] Figure 4 The third flowchart of the data processing method provided by the embodiments of the present application;

[0033] Figure 5This is a fourth flowchart illustrating the data processing method provided in the embodiments of this application;

[0034] Figure 6 This is a schematic flowchart of data processing in the transmission direction provided in an embodiment of this application;

[0035] Figure 7 A fifth flowchart illustrating the data processing method provided in this application embodiment;

[0036] Figure 8 A sixth flowchart illustrating the data processing method provided in this application embodiment;

[0037] Figure 9 A seventh flowchart illustrating the data processing method provided in the embodiments of this application;

[0038] Figure 10 This is a schematic flowchart of data processing in the receiving direction provided in an embodiment of this application;

[0039] Figure 11 A schematic diagram illustrating the mapping relationship between FlexE instances and RAM provided in this application embodiment;

[0040] Figure 12a A schematic diagram illustrating different RAM mappings to different FlexE instances provided in this application embodiment;

[0041] Figure 12b A schematic diagram illustrating different RAM mappings to the same FlexE instance provided in an embodiment of this application;

[0042] Figure 13 This is a first structural schematic diagram of a data processing apparatus provided in an embodiment of this application;

[0043] Figure 14 This is a second structural schematic diagram of a data processing apparatus provided in an embodiment of this application;

[0044] Figure 15 This is a schematic diagram of the structure of a data processing system provided in an embodiment of this application. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0046] For ease of understanding, the terms appearing in the embodiments of this application are explained below.

[0047] FlexE: The implementation agreement of FlexE provides a general mechanism to support various Ethernet MAC (Media Access Control) rates, which can or can not correspond to any existing Ethernet PHY (Physics) rate, and can specifically include MAC rates higher than the PHY rate carrying FlexE, and MAC rates lower than the PHY rate carrying FlexE. Among them, the MAC rate higher than the PHY rate is implemented by binding one or more PHY rates, and the MAC rate lower than the PHY rate is implemented by sub-rate and channelization. This can be regarded as a generalization of the Multi-Link Gearbox implementation agreement, which removes the restriction on the number of bound PHYs and the corresponding constraints of FlexE Clients to Ethernet rates.

[0048] FlexE Group: A FlexE group includes 1 to n 100G FlexE instances or 50G FlexE instances, which are carried by a group of 1 to m bound Ethernet PHYs. FlexE groups are supported by one or more bound 50GBASE-R PHYs, one or more bound 100GBASE-R PHYs, one or more bound 200GBASE-R PHYs, or one or more 400GBASE-R PHYs.

[0049] FlexE instance: is an information unit, divided into 50G FlexE instance or 100G FlexE instance, composed of FlexE Client data capable of carrying 50G or 100G capacity and its related overhead. 50G FlexE instance is carried only by 50G BASE-R PHY. 100G FlexE instance can be carried by 100G BASE-R PHY, 200GBASE-R PHY or 400GBASE-R PHY.

[0050] FlexE Client data: is an Ethernet flow based on MAC rate, which can or can not correspond to any PHY rate. The FlexE Client MAC rate supported by the FlexE group is 10, 40 and m×25Gb / s. The FlexE Client MAC rate supported by the FlexE group can support all or a subset of these FlexE Client MAC rates, such as m×25Gb / s.

[0051] FlexE Shim layer: is the layer of FlexE Client which maps or demaps FlexE group bearer. FlexE mapping refers to mapping FlexE Client data to FlexE group data in the transmission direction; FlexE demapping refers to parsing FlexE Client data from FlexE group data in the receiving direction.

[0052] FlexE Overhead (OH) frame: an in-band management channel provided for the FlexE Shim layer, supporting the transmission of configuration information and management information between two FlexE interfaces to be connected, and realizing automatic negotiation and establishment of the link. It can be understood that one FlexE OH is the OH of one FlexE instance.

[0053] FlexE management channel: a transmission channel in the FlexE OH frame that can be used for user-defined applications.

[0054] FlexE management channel includes segment management channel, synchronization message channel and Shim-to-Shim channel. In the FlexE OH frame, the deployment of the FlexE management channel is as shown in Figure 1 , the FlexE OH frame includes 8 blocks, among which block 4-5 are defined as segment management channels by the FlexE protocol, block 6 is defined as a synchronization message channel by the FlexE protocol, and block 6-8 or block 7-8 are defined as Shim-to-Shim channels by the FlexE protocol.

[0055] The segment management channel occupies two data blocks (such as block 4 and block 5 in Figure 1 ) of each FlexE OH frame. The total capacity of the segment management channel is about: the bandwidth of the segment management channel corresponding to each 100G BASE-R, 200G BASE-R or 400G BASE-R bearer of 100G FlexE instance is 1.222Mb / s; the bandwidth of the segment management channel corresponding to each 50G BASE-R bearer of 50G FlexE instance is 0.611Mb / s.

[0056] The Shim-to-Shim channel occupies two data blocks (such as block 7 and block 8 in Figure 1 ) or three data blocks (such as block 6, block 7 and block 8 in Figure 1 ) of each FlexE OH frame.

[0057] For the FlexE group not configured to provide the synchronization message channel, the Shim-to-Shim channel occupies the blocks 6-8 of the FlexE OH frame. The total capacity of the Shim-to-Shim channel in this configuration is about: 1.833 Mb / s for the 100G FlexE instance corresponding to the Shim-to-Shim channel of each 100GBASE-R, 200G BASE-R or 400G BASE-R bearer; and 0.916 Mb / s for the 50G FlexE instance corresponding to the Shim-to-Shim channel of each 50G BASE-R bearer.

[0058] For the FlexE group configured to provide the synchronization message channel, the Shim-to-Shim channel only occupies the blocks 7-8 of the FlexE OH frame. At this time, the total capacity of the Shim-to-Shim channel is the same as the total capacity of the segment management channel.

[0059] The only restriction of the FlexE management channel is that each 66B data block is a legal format according to [802.3] clause 82. The protocol used on the FlexE management channel can be Ethernet-based, using a combination of data and control blocks, or any other application-specific format using only data blocks.

[0060] In the current router product, the synchronization message channel is used to carry the 1588 function of FlexE, and the segment management channel and the Shim-to-Shim channel support other applications, such as supporting the application of DCN (Data communication network) and LLDP (Link Layer Discovery Protocol) protocol on the FlexE physical port, and the FlexE management channel can send LLDP packets and OSPF packets.

[0061] For the use of the FlexE management channel, the FlexE standard protocol only describes its definition and basic application scenarios, and does not specify the specific processing flow and implementation. For the chip supporting the FlexE function, the host-reg interface for writing and reading the blocks 4-8 in the OH frame is provided. According to the actual application, in the sending direction, the CPU processes the packet data at the link layer and the physical layer, writes it into the host-reg, and reads the data block from the host-reg and inserts it into the corresponding block in the FlexE OH frame; in the receiving direction, the corresponding block is extracted from the FlexE OH frame, written into the host-reg, and then analyzed at the physical layer and the link layer to provide to the CPU for processing.

[0062] Take 100G as an example, each 66B block in the FlexE OH frame needs about 100us (microsecond) to send or receive. During the sending process of the link layer, the interrupt cannot occur, because if the interrupt occurs, the data written in the host register is empty, the block inserted in the FlexE OH frame is empty, or the block extracted from the FlexE OH frame is empty, the data read from the host register is empty, which causes the receiving end to receive the empty block, and causes the message data to be unable to be accurately parsed. However, during the task running process, the sending process is randomly interrupted by the CPU hardware, and the us-level continuous writing and reading of data from the host register cannot be strictly guaranteed.

[0063] In order to guarantee the us-level continuous writing and reading of data from the host register, the CPU core is exclusively allocated to the specific task, and in the case of fixed CPU capability, the processing capability of other tasks is seriously squeezed.

[0064] To solve the above problems, the embodiment of the present application provides a data processing method. In the method, after the data is written into the host register, the data is written into the corresponding memory before the data is sent, or the data is written into the corresponding memory before the data is written into the host register after the data is received. In this case, even if the task is interrupted by the CPU during the task running process, no data is written into the host register, but in the sending direction, enough data is stored in the corresponding memory, and during the interruption period of the CPU, the data can be continuously read from the memory, and the continuous sending of the message data is guaranteed, and in the receiving direction, the corresponding data can be continuously written into the corresponding memory, and after the interruption is restored, the corresponding data can be read to write into the host register, and then the message data can be accurately parsed, thereby solving the problem that the message data cannot be accurately parsed due to the interruption of the CPU during the task running process.

[0065] In addition, in the embodiment of the present application, the CPU core does not need to be exclusively allocated to the specific task, and the processing capability of other tasks will not be squeezed, thereby guaranteeing the normal processing of various tasks.

[0066] The data processing method provided by the embodiment of the present application will be described in detail below through specific embodiments.

[0067] Referring to Figure 2 , Figure 2 The first flowchart of the data processing method provided by the embodiment of the present application is shown. For the convenience of understanding, the electronic device is taken as an execution subject for description, and the electronic device is not limited. The method comprises the following steps:

[0068] Step S21, write the data of the target instance stored in the host register into the first storage area of the first memory corresponding to the target instance, and the data of the target instance is transmitted by the target FlexE management channel.

[0069] In the embodiment of the application, the target instance can be any FlexE instance, in the sending direction, the memory corresponding to the target instance is the first storage area, and the target FlexE management channel can be a segment management channel, a synchronization message channel or a Shim-to-Shim channel. The data of one FlexE instance can be understood as the data of one packet. The host register (such as host_reg) contains a set of registers for CPU (such as software) to operate packet data, parameter setting and state acquisition, etc.

[0070] The upper application program (such as CPU) in the electronic device writes the data of the target instance into the host register, and other hardware in the electronic device reads the data from the host register and writes the read data into the first storage area of the first memory.

[0071] In the embodiment of the application, the upper application program can perform 64B / 66B encoding processing on the data of the target instance, and write the obtained 64B / 66B data block after encoding into the host register; other hardware directly reads the 64B / 66B data block from the host register and writes the read 64B / 66B data block into the first storage area of the first memory.

[0072] In order to reduce the occupation of CPU resources and reduce the utilization rate of CPU, the upper application program can directly write the data of the target instance into the host register; other hardware reads the data from the host register, performs 64B / 66B encoding processing on the read data, and writes the obtained 64B / 66B data block after encoding into the first storage area of the first memory. The specific processing process will be described below, and will not be described in detail.

[0073] Step S22, when the first storage area is full, read the data from the first storage area as target data.

[0074] In the embodiment of the application, the electronic device continuously reads data from the host register and continuously writes data into the first storage area. When the first storage area is full, the data is read from the first storage area, and the read data is used as target data.

[0075] Step S23, insert the target data into the position of the target FlexE management channel in the OH frame.

[0076] In this embodiment, if the target FlexE management channel is a segment management channel, then the target FlexE management channel is located in blocks 4-5 of the OH frame; if the target FlexE management channel is a synchronization message channel, then the target FlexE management channel is located in block 6 of the OH frame; if the target FlexE management channel is a Shim-to-Shim channel, then the target FlexE management channel is located in blocks 6-8 or blocks 7-8 of the OH frame.

[0077] After the electronic device reads the target data, it inserts the target data into the target FlexE management channel position in the OH frame.

[0078] Step S24: Send the OH frame after inserting the data.

[0079] After the target data is input into the OH frame, the electronic device sends an OH frame with the inserted data, thereby enabling the transmission of the target instance's data through the target FlexE management channel.

[0080] In the technical solution provided in this application embodiment, data is written to the corresponding memory after being written to the host register and before being sent. In this case, even if the task is interrupted by the CPU during execution and no more data is written to the host register, sufficient data is stored in the corresponding memory in the transmission direction. During the period of CPU interruption, data can be continuously read from the memory, ensuring continuous transmission of message data. This, in turn, ensures that the message data can be accurately parsed, solving the problem that message data cannot be accurately parsed due to CPU interruption during task execution.

[0081] based on Figure 2 The flowchart shown in this application also provides a data processing method, such as... Figure 3 As shown, the method may include steps S31-S36, wherein steps S34-S36 are the same as steps S22-S24 described above, and will not be repeated here. Steps S31-S33 are one implementation of step S21.

[0082] Step S31: Read the data of the target instance from the host register as the raw data.

[0083] Step S32: Encode the original data using a preset encoder to obtain encoded data.

[0084] In this embodiment of the application, the data encoding algorithm can be either a 64B encoding algorithm or a 66B encoding algorithm, and there is no limitation on the latter.

[0085] Step S33, write the encoded data into the first storage area of the first memory corresponding to the target instance.

[0086] In the embodiment of the present application, the upper-layer application program of the electronic device does not encode the data, but directly writes the data into the host register. When reading the data from the host register, the data is encoded by using the preset encoder. In this case, the encoding of the data is implemented by using other hardware than the upper-layer application program, and the encoding of the data is offloaded to the hardware other than the CPU, thereby reducing the processing burden of the CPU, reducing the occupation of the CPU resources, and reducing the utilization rate of the CPU.

[0087] In order to further solve the problem that the message data cannot be accurately parsed due to the interruption of the CPU during the task running, in an embodiment of the present application, the first memory corresponding to the target instance further includes a second storage area in the sending direction. The first memory includes the first storage area and the second storage area, which can be understood as that one memory is divided into two areas A and B, facilitating the ping-pong operation of software and hardware.

[0088] Based on this, the embodiment of the present application further provides a data processing method, as shown in Figure 4 The method can include steps S41-S46, wherein steps S41-S44 are the same as steps S21-S24, which will not be described here.

[0089] Step S45, when the first storage area is full, write the data of the target instance stored in the host register subsequently into the second storage area of the first memory.

[0090] In the embodiment of the present application, when the first storage area is full, the electronic device performs step S42 to read the data from the first storage area as target data to send the data of the target instance through the target FlexE management channel; at the same time, the electronic device performs step S45 to continue reading the data from the host register and write the read data into the second storage area.

[0091] Step S46, when the second storage area is full and the data sending in the first storage area is completed, read the data from the second storage area as target data.

[0092] The electronic device continuously reads the data from the host register and continuously writes the data into the second storage area. When the second storage area is full and the data sending in the first storage area is not completed, step S42 is continuously performed to read the data from the first storage area as target data; if the data sending in the first storage area is completed, the data is read from the second storage area as target data, and then step S43 is performed to send the data of the target instance through the target FlexE management channel.

[0093] In addition, in a case where the second storage area is full and data transmission in the first storage area is completed, the electronic device can write data of a target instance stored subsequently in the host register into the first storage area.

[0094] In the technical solution provided in the embodiments of the present application, ping-pong operation of software and hardware is performed through the first storage area and the second storage area. In this case, even if the CPU is interrupted for a long time, since sufficient data is stored in the first storage area and the second storage area, it can be ensured that the target FlexE management channel of the OH frame does not transmit empty blocks, and the problem that message data cannot be accurately parsed due to interruption of the CPU during task running is further solved.

[0095] In an embodiment of the present application, in order to reduce the probability of data insertion disorder in the OH frame, when data transmission in the first storage area is in progress, the electronic device will not write data of a target instance stored in the host register into the first storage area of the first memory; after data transmission in the first storage area is completed, the electronic device re-executes step S21 to write data of the target instance stored in the host register into the first storage area, that is, re-reads data of the target instance from the host register and writes the read data into the first storage area.

[0096] In an embodiment of the present application, the embodiments of the present application further provide a data processing method, as shown in Figure 5 The method comprises steps S51-S55, wherein steps S53-S55 are the same as steps S22-S24 described above, and will not be described here again. Steps S51-S52 are an implementation manner of step S21.

[0097] Step S51: taking a first address of the first storage area of the first memory corresponding to the target instance, which is not written with data, as a target address.

[0098] In the embodiments of the present application, the address bit width and the data bit width of the first storage area can be set according to actual needs. In an example, the address bit width of the first storage area can be 64, such as an address range of 0-63, and the data bit width of the first storage area is the size of a data block, such as 64 bits or 66 bits.

[0099] Step S52: writing data of the target instance stored in the host register into the target address, and re-executing step S51 until the first storage area is full.

[0100] Taking the address range of the first storage area as 0-63, the electronic device takes the first address 0 in the first storage area which has not been written as a target address, reads the data of the target instance from the host register, and writes the read data to the address 0 of the first storage area. When the data is successfully written to the address 0, the electronic device takes the first address 1 in the first storage area which has not been written as a target address, reads the data of the target instance from the host register, and writes the read data to the address 1 of the first storage area. The cycle continues until the data is successfully written to the address 63, that is, the first storage area is full.

[0101] In the technical solution provided in the embodiments of the present application, the first storage area is successfully filled through steps S51-S52, so that the duration of the CPU interruption during the task running is delayed to the duration of sending all the data in the first storage area, thereby solving the problem that the message data cannot be accurately parsed due to the CPU interruption during the task running.

[0102] In the embodiments of the present application, if the second storage area is configured in the electronic device, the address bit width and the data bit width of the second storage area can be set according to actual needs. The addresses of the first storage area and the second storage area can be continuous, for example, the address bit width of the first storage area can be 64, for example, the address range is 0-63, and the address bit width of the second storage area can be 64, for example, the address range is 64-127.

[0103] In the embodiments of the present application, the process of writing data into the second storage area by the electronic device is similar to the process of writing data into the first storage area described above, and details can be referred to the related description above, which will not be repeated here.

[0104] The data processing provided in the embodiments of the present application will be described in detail below in combination with the data processing flow in the sending direction shown in FIG. 6. Figure 6

[0105] Step S61: detecting whether the storage state of the RAM is a storable state. If yes, step S62 is performed, and if not, the waiting continues, and step S61 is re-executed.

[0106] The RAM includes the first storage area and / or the second storage area. The storage state of the RAM can be represented by a txok state. If the value of the txok state is true, the CPU determines that the storage state of the RAM is a storable state, otherwise, the CPU determines that the storage state of the RAM is an un-storable state.

[0107] ​For example, when the first storage area is empty or the data in the first storage area has been sent, the first storage area is in a storable state, and the hardware generates an interrupt signal. For example, when the first storage area and the second storage area are both empty or the data in the first storage area and the second storage area has been sent, the RAM is in a storable state, and the hardware generates an interrupt signal.

[0108] The CPU polls or responds to the interrupt signal to detect whether the storage state of the RAM is in a storable state. If it is determined that the storage state of the RAM is in a storable state, it indicates that the data in the current RAM has been sent, and the CPU can write data into the RAM to perform step S62.

[0109] In step S62, data is written into the RAM address through the host interface.

[0110] The address range of the first storage area is 0-63, and the address range of the second storage area is 64-127.

[0111] In step S63, it is determined whether the data in the current RAM address is written successfully. If yes, step S64 is performed, and if no, the waiting is continued and step S63 is performed again.

[0112] Each RAM address can write one data block, and when data is written into each RAM address, step S63 is repeatedly performed to ensure that the data in the RAM address is written successfully, and the data writing of the next RAM address can be performed after the data writing is successful.

[0113] In step S64, it is determined whether the RAM is full. If yes, step S65 is performed, and if no, the waiting is continued and step S62 is performed again to write data into the next RAM address.

[0114] In the embodiment of the application, after the data in the current RAM address is written successfully, it is determined whether the RAM is full, that is, whether the message data in the RAM is written completely. If the RAM is full, that is, the message data in the RAM is written completely, step S65 is performed.

[0115] In the embodiment of the application, when the first storage area is full and the second storage area is in a storable state, the address of the second storage area is selected to write data; when the address of the second storage area is full and the first storage area is in a storable state, the address of the first storage area is selected to write data. The above process is repeated.

[0116] In step S65, the RAM text request position is set.

[0117] The RAM text request bit can be represented by a RAM tx request. After the CPU sets the RAM text request bit, the RAM data sending process is started, as described above in steps S22-S24, and the packet data is transmitted through the FlexE management channel.

[0118] In step S66, it is determined whether the data of a packet is sent. If yes, the process ends. If no, the process returns to step S61.

[0119] Steps S61-S66 are relatively simple, and details can be found in the above Figures 2-5 description of the related part.

[0120] Corresponding to the data processing method in the sending direction described above, the present embodiment also provides a data processing method in the receiving direction, as shown in Figure 7 FIG. 6. The method includes the following steps.

[0121] In step S71, target data is extracted from the position of the target FlexE management channel in the received OH frame. The target FlexE management channel is used to transmit data of a target instance.

[0122] In the present embodiment, the target instance can be any FlexE instance. In the receiving direction, the memory corresponding to the target instance is a second memory, which is a FIFO (First Input First Output) memory. The target FlexE management channel can be a segment management channel, a synchronization message channel, or a Shim-to-Shim channel. The data of one FlexE instance can be understood as the data of one packet.

[0123] The hardware of the electronic device receives the OH frame and extracts data from the position of the target FlexE management channel in the OH frame as target data. The target data is the data of the target instance.

[0124] In step S72, the target data is written into the second memory corresponding to the target instance.

[0125] In step S73, when the amount of data stored in the second memory is greater than or equal to a preset data amount, the data stored in the second memory is written into the host register.

[0126] The preset data amount can be understood as the depth of the second memory. The preset data amount can be set according to the processing capability of the CPU. For example, if the processing capability of the CPU is weak, and there is data in the second memory, the CPU needs to be notified to read and process the data, and the preset data amount is set to a small value; if the processing capability of the CPU is strong, the preset data amount can be set to a large value, in which case the CPU reads and processes the data in batches, thereby reducing the number of times of interrupting the CPU. By flexibly configuring the preset data amount, the technical solution provided in the embodiments of the present application can adapt to the processing capability of different CPUs, thereby expanding the application range of the technical solution provided in the embodiments of the present application.

[0127] In the embodiments of the present application, when the amount of data stored in the second memory is greater than or equal to the preset data amount, the second memory can generate an interrupt signal, and the interrupt signal is transmitted to the CPU, to notify the CPU that the data in the second memory can be read.

[0128] In the embodiments of the present application, the CPU can also check the current depth of the second memory in a polling manner. When the amount of data stored in the second memory is greater than or equal to the preset data amount, that is, the current depth of the second memory is greater than or equal to the preset data amount, a corresponding reading operation is performed.

[0129] In the process in which the hardware of the electronic device writes the data stored in the second memory into the host register, the data in the second memory can be read and directly written into the host register. Since the data stored in the second memory is the data extracted from the OH frame, that is, 64B / 66B encoded data, after the CPU reads the data from the host register, the read data needs to be first decoded by 64B / 66B to obtain decoded data, and then the decoded data is processed.

[0130] In order to reduce the occupation of CPU resources and the utilization rate of the CPU, in the process in which the hardware of the electronic device writes the data stored in the second memory into the host register, the data in the second memory can be read, the read data can be decoded by 64B / 66B to obtain decoded data, and the decoded data can be written into the host register. In this case, the CPU can read the data from the host register and directly process the read data. The specific processing process will be described below, and will not be described in detail.

[0131] In step S74, the data stored in the host register is processed.

[0132] In the technical solution provided in this application embodiment, after receiving data and before writing the data to the host register, the data is written to the corresponding memory. In this case, even if the task is interrupted by the CPU during execution and no more data is written to the host register, data can still be continuously written to the corresponding memory in the receiving direction. After the interrupt is resumed, the corresponding data can be read and written to the host register, thereby ensuring that the message data can be accurately parsed and solving the problem that the message data cannot be accurately parsed due to the CPU interruption during task execution.

[0133] based on Figure 7 The flowchart shown in this application also provides a data processing method, such as... Figure 8 As shown, the method may include steps S81-S86, wherein steps S81-S82 and S86 are the same as steps S71-S72 and S74 described above, and will not be repeated here. Steps S83-S85 are one implementation of step S73.

[0134] Step S83: When the amount of data stored in the second memory is greater than or equal to the preset amount of data, read the data of the target instance from the second memory as the original data.

[0135] Step S84: Use a preset decoder to decode the original data to obtain decoded data.

[0136] In this embodiment of the application, the data encoding algorithm can be either a 64B encoding algorithm or a 66B encoding algorithm, and correspondingly, the data decoding algorithm can be either a 64B decoding algorithm or a 66B decoding algorithm, without limitation.

[0137] Step S85: Write the decoded data into the host register.

[0138] In this embodiment, the electronic device decodes the data using a preset encoder and writes the decoded data into the host register. The upper-layer application (such as the CPU) of the electronic device does not need to decode the data and can directly process the data read from the host register. In this case, the data decoding is implemented by other hardware outside the upper-layer application, offloading the data decoding to hardware other than the CPU, reducing the CPU's processing burden, reducing the occupation of CPU resources, and reducing CPU utilization.

[0139] based on Figure 7 The flowchart shown in this application also provides a data processing method, such as... Figure 9As shown, the method can include steps S91-S95, wherein steps S91-S92 and S95 are the same as steps S71-S72 and S74 described above, and will not be repeated here. Steps S93-S94 are an implementation of step S73.

[0140] Step S93, when the amount of data stored in the second memory is greater than or equal to the preset data amount, the first address of the unread data in the second memory is taken as the target address.

[0141] Step S94, reading data from the target address and writing the read data into the host register, and re-executing step S93 until the second memory is read out completely.

[0142] Taking the address range of the second memory as 0-63, the electronic device takes the first address (address 0) of the unread data in the second memory as the target address, reads the data of the target instance from address 0, and writes the read data into the host register. When the data is successfully read out from address 0, if the second memory is not empty, i.e., the second memory still stores data, the electronic device takes the first address 1 of the unread data as the target address, reads the data of the target instance from address 1, and writes the read data into the host register. This cycle continues until the second memory is read out completely, i.e., the second memory is empty, and then step S96 is executed.

[0143] In the technical solution provided by the embodiment of the application, through steps S93-S94, the second memory is successfully written into the host register, so that the duration of the task running process interrupted by the CPU is delayed to the duration of the amount of data stored in the second memory from empty to the preset data amount, solving the problem that the packet data cannot be accurately parsed due to the task running process being interrupted by the CPU.

[0144] The data processing provided by the embodiment of the application will be described in detail below in combination with the data processing flow in the receiving direction shown in the figure. Figure 10

[0145] Step S101, determining whether the read state of the FIFO is a readable state. If yes, step S102 is executed, and if not, the waiting continues and step S101 is re-executed.

[0146] The FIFO includes the second memory. The read state of the FIFO can be represented by the txok state.

[0147] In the embodiment of the application, when the amount of data stored in the second memory is greater than or equal to the preset data amount, the second memory can generate an interrupt signal, and the interrupt signal is transmitted to the CPU to notify the CPU that the data in the second memory can be read. ​

[0148] In the embodiment of the present application, the CPU can also check the current depth of the second memory in a polling manner. When the amount of data stored in the second memory is greater than or equal to the preset data amount, that is, the current depth of the second memory is greater than or equal to the preset data amount, the corresponding reading operation is performed.

[0149] The CPU determines that the reading state of the FIFO is a readable state and performs step S102 in response to the interruption or the polling detection that the amount of data stored in the second memory is greater than or equal to the preset data amount.

[0150] In step S102, data is read into the FIFO address.

[0151] In step S103, it is determined whether the data of the current FIFO address is read successfully. If yes, step S104 is performed, and if not, the waiting is continued and step S103 is re-executed.

[0152] One data block can be written into each FIFO address. When the data of each FIFO address is read, step S103 is repeatedly executed to ensure that the data of the FIFO address is read successfully, and the data of the next FIFO address can be read only after the data of the FIFO address is read successfully.

[0153] In step S104, it is determined whether the FIFO is empty. If yes, step S105 is performed, and if not, the waiting is continued and step S102 is re-executed to write the data of the next FIFO address.

[0154] In the embodiment of the present application, after the data of the current FIFO address is read successfully, it is determined whether the FIFO is empty, that is, whether the message data in the FIFO is read completely. If the FIFO is empty, that is, the message data in the FIFO is read completely, step S105 is performed.

[0155] In step S105, the read data is processed, and step S101 is re-executed.

[0156] Steps S101-S105 are relatively simple, and the related descriptions of steps S101-S105 can be referred to the above description of the related part. Figures 7-9

[0157] In the technical scheme provided by the embodiment of the present application, for the case of supporting multiple FlexE instances, the RAM (the first memory or the second memory) can be mapped to multiple FlexE instances, as shown in FIG. 1. Figure 11 Figure 11 In the embodiment of the present application, each RAM (Random Access Memory) can represent the first memory or the second memory. Specifically, different RAMs can be mapped to different FlexE instances, and different RAMs can also be mapped to the same FlexE instance.​​

[0158] For example, the first memory can correspond to other instances in addition to the target instance; and the target instance can correspond to other memories in addition to the first memory.

[0159] For example, the second memory can correspond to other instances in addition to the target instance; and the target instance can correspond to other memories in addition to the second memory.

[0160] For example, as shown in (1) and (2) of FIG. 6, RAM0 is mapped to block4~5 of the FlexE management channel of the OH frame of instance0, and RAM1 is mapped to block6~8 of the FlexE management channel of the OH frame of instance1; as shown in (3) of FIG. 6, RAM0 is mapped to block4~5 of the FlexE management channel of the OH frame of instance0, and RAM1 is mapped to block6~8 of the FlexE management channel of the OH frame of instance0. Figure 12a Figure 12b For example, as shown in (1) and (2) of FIG. 6, RAM0 is mapped to block4~5 of the FlexE management channel of the OH frame of instance0, and RAM1 is mapped to block6~8 of the FlexE management channel of the OH frame of instance1; as shown in (3) of FIG. 6, RAM0 is mapped to block4~5 of the FlexE management channel of the OH frame of instance0, and RAM1 is mapped to block6~8 of the FlexE management channel of the OH frame of instance0.

[0161] In the above manner, the mapping relationship between the memory and the FlexE instance is configured, which facilitates the flexible application and full use of the RAM resource by the user, allows multiple FlexE management channels to be mapped on the same RAM, reduces the number of RAMs deployed in the electronic device on the basis of supporting the same number of FlexE management channels, and reduces the circuit area and chip cost.

[0162] In addition, in the embodiments of the present application, the mapping relationship between the memory and the FlexE instance can be flexibly configured to realize the configurability of the block of the FlexE management channel in the OH frame. As described above, different RAMs can be mapped to different FlexE instances, different RAMs can be mapped to the same FlexE instance, and even the same RAM can be mapped to multiple blocks of the FlexE management channel of the same FlexE instance, which provides flexibility for the diversified application of the upper application program and provides the possibility for the interworking of the FlexE management channel.

[0163] Corresponding to the above data processing method, the embodiments of the present application also provide a data processing device, as shown in FIG. 13, which comprises a host write module 131, an encoding module 132, a first memory 133, and a storage reading module 134. Figure 13

[0164] The host write module 131 is used to store the data of the target instance from the host register, and the data of the target instance is transmitted by the target FlexE management channel.

[0165] ​​The encoding module 132 is configured to encode the data read by the host write module, and write the encoded data into a first storage area of the first memory 133;

[0166] The storage reading module 134 is configured to read the data from the first storage area as target data when the first storage area is full, insert the target data into a position of a target FlexE management channel in an OH frame, and send the OH frame after the insertion.

[0167] Optionally, the encoding module 132 is further configured to encode the data subsequently read by the host write module after the first storage area is full, and write the encoded data into a second storage area of the first memory 133.

[0168] The storage reading module 134 is further configured to read the data from the second storage area as target data when the second storage area is full and the data in the first storage area is sent.

[0169] Optionally, the encoding module 132 is further configured to encode the data read by the host write module 131 after the data in the first storage area is sent, and write the encoded data into the first storage area of the first memory 133.

[0170] Optionally, the encoding module 132 is specifically configured to:

[0171] take the first address of the first storage area of the first memory corresponding to the target instance and not written with data as a target address;

[0172] encode the data read by the host write module 131, write the encoded data into the target address, and re-perform the step of taking the first address of the first storage area of the first memory corresponding to the target instance and not written with data as the target address until the first storage area is full.

[0173] Optionally, the first memory further corresponds to other instances, and / or the target instance further corresponds to other memories.

[0174] In the technical scheme provided by the embodiments of the present application, after the data is written into the host register, the data is written into the corresponding memory before being sent. In this case, even if the task is interrupted by the CPU during the running process, no data is written into the host register, but in the sending direction, enough data is stored in the corresponding memory, and during the period of time when the CPU is interrupted, the data can be continuously read from the memory, thereby ensuring the continuous sending of the packet data, and further ensuring that the packet data can be accurately parsed, thereby solving the problem that the packet data cannot be accurately parsed due to the interruption of the CPU during the running of the task.

[0175] Corresponding to the data processing method, the embodiment of the application further provides a data processing device, as shown in the figure, the device comprises: a host reading module 141, a decoding module 142, a second memory 143 and a storage writing module 144. Figure 14 The storage writing module 144 is used for extracting target data from the position of the target FlexE management channel in the received OH frame, the target FlexE management channel being used for transmitting data of a target instance; and writing the target data into the second memory 143 corresponding to the target instance.

[0176] The storage writing module 144 is used for extracting target data from the position of the target FlexE management channel in the received OH frame, the target FlexE management channel being used for transmitting data of a target instance; and writing the target data into the second memory 143 corresponding to the target instance.

[0177] The decoding module 142 is used for reading data from the second memory 143 and decoding the read data when the amount of data stored in the second memory 143 is greater than or equal to a preset data amount.

[0178] The host reading module 141 is used for writing the decoded data into a host register, so that the CPU processes the data stored in the host register.

[0179] Optionally, the decoding module 142 can be specifically used for:

[0180] Taking the first address of the unread data in the second memory 143 as a target address;

[0181] Reading data from the target address and decoding the read data;

[0182] When the data reading from the target address is successful, if it is detected that the second memory 143 is not empty, the step of taking the first address of the unread data in the second memory 143 as the target address is re-executed until the second memory 143 is empty.

[0183] Optionally, the second memory also corresponds to other instances; and / or, the target instance also corresponds to other memories.

[0184] In the technical scheme provided by the embodiment of the application, after receiving data, the data is written into the corresponding memory before being written into the host register. In this case, even if the task is interrupted by the CPU during running, no data is written into the host register, but the data can be continuously written into the corresponding memory in the receiving direction, and the corresponding data can be read after the interruption is restored to be written into the host register, thereby ensuring that the packet data can be accurately parsed, and solving the problem that the packet data cannot be accurately parsed due to the interruption of the task by the CPU during running.

[0185] Corresponding to the data processing method, the embodiment of the application further provides a data processing system, as shown in the figure, Figure 15As shown, the system comprises a host write module 151, an encoding module 152, a first memory 153, a memory reading module 154, a host reading module 155, a decoding module 156, a second memory 157, and a memory writing module 158.

[0186] The host write module 151 is configured to store data of a target instance from a host register, and the data of the target instance is transmitted by using a target FlexE management channel.

[0187] The encoding module 152 is configured to encode the data read by the host write module, and write the encoded data into a first storage area of the first memory 153.

[0188] The memory reading module 154 is configured to read data from the first storage area as target data when the first storage area is full, insert the target data into a position of the target FlexE management channel in an OH frame, and send the OH frame after the insertion.

[0189] The memory writing module 158 is configured to extract target data from the position of the target FlexE management channel in the received OH frame, and write the target data into the second memory 157 corresponding to the target instance.

[0190] The decoding module 156 is configured to read data from the second memory 157 when the amount of data stored in the second memory 157 is greater than or equal to a preset data amount, and decode the read data.

[0191] The host reading module 155 is configured to write the decoded data into the host register, so that the CPU processes the data stored in the host register.

[0192] In the embodiment of the application, in the sending direction, the host write module 151 can be referred to as HOST_WR_CTRL, which is configured to respond to a message data sending write operation of software, the encoding module 152 is configured to perform 64B / 66B encoding processing on a data block, and after the encoding is completed, the data block is written into the first memory 153. The first memory 153 can be divided into two areas A and B, i.e., the first storage area and the second storage area, which can be used for ping-pong operation of software and hardware. The memory reading module 154 can be referred to as SRAM_RD_CTRL, which is configured to insert the full data in the first memory 153 into a FlexE OH frame, and after the data in the first memory 153 is completely sent, an interrupt signal is triggered to the host, which is configured to notify the software to continue to write the to-be-sent data into the first memory 153.

[0193] In the receiving direction, the storage reading module 154 can be referred to as FIFO_WR_CTRL, used to extract data from the FlexE OH frame, and write the extracted data into the corresponding second storage 157, which will generate an interrupt signal to the host according to the set threshold (such as the above-mentioned preset data amount), used to inform the software that the FIFO data can be read out. The decoding module 156 is used to perform 64B / 66B decoding processing on the data block, and write the decoded data into the host register through the host reading module 155, so that the software processes the data stored in the host register.

[0194] In the technical scheme provided by the embodiments of the present application, after writing the data into the host register, before sending the data, or after receiving the data, before writing the data into the host register, the data is written into the corresponding storage. In this case, even if the task is interrupted by the CPU during the running process, no data is written into the host register, but in the sending direction, enough data is stored in the corresponding storage, and during the period of CPU interruption, the data can be continuously read from the storage, thereby ensuring the continuous sending of the packet data, and in the receiving direction, the corresponding data can be continuously written into the corresponding storage, and after the interruption is restored, the corresponding data can be read to write into the host register, thereby ensuring that the packet data can be accurately parsed, and the problem that the packet data cannot be accurately parsed due to the interruption of the task by the CPU during the running process is solved.

[0195] In the embodiments of the present application, the above-mentioned data processing system can be centrally deployed on one electronic device, or distributedly deployed on different electronic devices, and no limitation is made in this regard.

[0196] In the embodiments described above, all or some of the steps can be implemented by hardware, software, firmware or any combination thereof. When implemented by software, all or some of the steps can be implemented in the form of one or more computer programs or program elements. The computer programs reside (at least temporarily) in a memory of a computer during execution. The memory can be a RAM memory, a flash memory, a ROM memory, an EPROM memory, or any other suitable memory. The memory can be integral to or separate from the computer. The computer programs can be written in any suitable programming language, such as C, C++, Java, Visual Basic, etc. The computer programs can be written in assembly or machine language, if desired. The computer programs can be distributed over network coupled file servers, or can be distributed by any other suitable means.

[0197] It is to be understood that the terminology “first”, “second”, etc. is used in this document only to distinguish one entity or operation from another entity or operation, and does not necessarily imply or suggest any such actual relationship or order between the entities or operations. Also, the terms “comprises”, “comprising”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by an occurrence of the phrase “comprises a” does not exclude the existence of additional identical elements in the process, method, article, or apparatus including the element.

[0198] Each of the embodiments in the present specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other. Each of the embodiments focuses on the difference from other embodiments. In particular, for the device and system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the description of the method embodiments.

[0199] The above merely provides the preferred embodiment of the present application, and not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A data processing method, characterized by, The method is applied to other hardware except CPU in an electronic device, and the method comprises the following steps: writing data of a target instance stored in a host register into a first storage area of a first memory corresponding to the target instance, wherein the data of the target instance is transmitted by a target FlexE management channel, and the data of the target instance is written into the host register by a CPU in the electronic device; after the first storage area is full, reading data from the first storage area as target data; inserting the target data into a position of the target FlexE management channel in an overhead (OH) frame; sending the OH frame after the insertion, so that other hardware except the CPU in an electronic device receiving the OH frame extracts the target data from the position of the target FlexE management channel in the received OH frame, writes the target data into a second memory corresponding to the target instance, and when the amount of data stored in the second memory is greater than or equal to a preset data amount, writes the data stored in the second memory into a host register, and a CPU in the electronic device receiving the OH frame processes the data stored in the host register.

2. The method of claim 1, wherein, The step of writing the data of the target instance stored in the host register into the first storage area of the first memory corresponding to the target instance comprises the following steps: reading the data of the target instance from the host register as original data; encoding the original data by using a preset encoder to obtain encoded data; writing the encoded data into the first storage area corresponding to the target instance.

3. The method of claim 1, wherein, The method further comprises the following steps: after the first storage area is full, writing data of a target instance subsequently stored in the host register into a second storage area of the first memory; after the second storage area is full and the data in the first storage area is sent, reading data from the second storage area as target data.

4. The method of claim 1, wherein, The method further comprises the following steps: after the data in the first storage area is sent, re-executing the step of writing the data of the target instance stored in the host register into the first storage area of the first memory corresponding to the target instance.

5. The method of claim 1, wherein, The step of writing the data of the target instance stored in the host register into the first storage area of the first memory corresponding to the target instance comprises the following steps: taking a first address in the first storage area of the first memory corresponding to the target instance which is not written as a target address; writing the data of the target instance stored in the host register into the target address, and re-executing the step of taking the first address in the first storage area of the first memory corresponding to the target instance which is not written as the target address until the first storage area is full.

6. The method according to any one of claims 1 to 5, characterized in that, The first memory also corresponds to other instances, and / or the target instance also corresponds to other memories.

7. The method of claim 1, wherein, The step of writing the data stored in the second memory into the host register comprises the following steps: reading the data of the target instance from the second memory as original data; decoding the original data by using a preset decoder to obtain decoded data; writing the decoded data into the host register.

8. The method of claim 1, wherein, The step of writing the data stored in the second memory into a host register comprises: reading data from the target address and writing the read data into a host register; when the data reading from the target address is successful, if it is detected that the second memory is not empty, the step of taking the first address of the unread data in the second memory as a target address is re-executed; if it is detected that the second memory is empty, the step of processing the data stored in the host register is executed. The second memory also corresponds to other instances; and / or, the target instance also corresponds to other memories.

9. The method of claim 1, 7 or 8, wherein, The first data processing device applied to other hardware except CPU in the electronic device sending OH frames and the second data processing device applied to other hardware except CPU in the electronic device receiving OH frames, the first data processing device comprises: a host write module, an encoding module, a first memory and a storage reading module; the second data processing device comprises: a host reading module, a decoding module, a second memory and a storage write module; 10. A data processing apparatus, characterized by, The host write module is used for reading the data of a target instance stored in a host register, the data of the target instance is transmitted by a target FlexE management channel, and the data of the target instance is written into the host register by a CPU in the electronic device. The encoding module is used for encoding the data read by the host write module and writing the encoded data into a first storage area of the first memory. The storage reading module is used for reading data from the first storage area as target data when the first storage area is full, inserting the target data into a position of the target FlexE management channel in an overhead header OH frame, and sending the OH frame after the insertion of data. The storage write module is used for extracting target data from a position of a target FlexE management channel in a received overhead header OH frame, the target FlexE management channel being used for transmitting data of a target instance, and writing the target data into the second memory corresponding to the target instance. The decoding module is used for reading data from the second memory and decoding the read data when the amount of data stored in the second memory is greater than or equal to a preset data amount. The host reading module is used for writing the decoded data into a host register, so that a CPU in the electronic device processes the data stored in the host register. The encoding module is also used for encoding data subsequently read by the host write module after the first storage area is full, and writing the encoded data into a second storage area of the first memory.

11. The apparatus of claim 10, wherein, The storage reading module is also used for reading data from the second storage area as target data when the second storage area is full and the data in the first storage area is sent. ​ 12. The apparatus of claim 10, wherein, The encoding module is further configured to encode data read by the host write module after the data in the first storage area is sent, and write the encoded data into the first storage area.

13. The apparatus of claim 10, wherein, The encoding module is specifically configured to: take a first address of the first storage area of the first memory corresponding to the target instance and not written with data as a target address; encode the data read by the host write module, write the encoded data into the target address, and re-perform the step of taking the first address of the first storage area of the first memory corresponding to the target instance and not written with data as the target address until the first storage area is full.

14. The apparatus of claim 10, wherein, The step of writing the data stored in the second memory into the host register comprises: taking a first address of the second memory and not read with data as a target address; reading data from the target address and decoding the read data; after the data is successfully read from the target address, if it is detected that the second memory is not empty, re-performing the step of taking the first address of the second memory and not read with data as the target address until the second memory is empty.

15. A data processing system, characterized by The data processing device of any one of claims 10-14. The data processing device of any one of claims 10-14.

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