Memory testing method, device and electronic device

Abstract

The present invention relates to the technical field of memory testing, and specifically to a memory testing method, device, and electronic device. The method includes obtaining a faulty physical address of a target memory and a preset address offset; determining a faulty physical address range based on the faulty physical address and the preset address offset; setting the attributes of all physical addresses within the faulty physical address range to locked; converting the faulty physical address range into a virtual address range; and performing a memory test on the target memory based on the virtual address range. By using the faulty physical address to screen the test objects in the target memory and only testing the faulty physical address range without the need for overall testing, the memory testing range is narrowed. Moreover, due to memory fault coupling and multiple write fault manifestations, memory faults occur in adjacent row and column ranges. Therefore, testing the faulty physical address range can ensure the reliability of the test results.

Description

Technical Field

[0001] The present invention relates to the technical field of memory testing, and in particular to a memory testing method, device and electronic device. Background Art

[0002] Memory is a precision high-speed server component, with diverse and complex types of faults. With the update of memory speed and the improvement of manufacturing process technology, the particles are made more and more precisely, and the single memory capacity is getting larger and larger. For example, the latest 128G DDR4 with a 12-14nm process. Precision is accompanied by an increase in interference type faults. For some of these types of faults, some need to be excited by a specific sensitization sequence, and some need to be excited by repeated high-intensity reading and writing. In production testing, memory faults are difficult to detect and reproduce.

[0003] The prior art performs read-write pressure testing on all virtual addresses of the memory on the server through the memtest algorithm. Since all virtual addresses are tested, a complete fault reproduction test takes a long time. A complete test of a 32G memory takes nearly half an hour, and the fault reproduction time is long and the efficiency is low. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a memory testing method, device and electronic device to solve the problem of low efficiency of memory testing.

[0005] According to a first aspect, an embodiment of the present invention provides a memory testing method, including:

[0006] Obtain the fault physical address of the target memory and a preset address offset;

[0007] Based on the fault physical address and the preset address offset, determine the fault physical address range;

[0008] Set the attributes of all physical addresses within the fault physical address range to locked;

[0009] Convert the fault physical address range into a virtual address range;

[0010] Perform memory testing on the target memory based on the virtual address range.

[0011] The memory test method provided by the embodiments of the present invention screens test objects in the target memory by using faulty physical addresses, and only tests the faulty physical address range without the need for overall testing, thereby narrowing the memory test range. Moreover, due to memory fault coupling and multiple write fault manifestations, memory faults occur in adjacent row and column ranges. Therefore, a faulty physical address range is determined from the faulty physical address, and testing the faulty physical address range can ensure the reliability of the test results. At the same time, setting the attributes of all physical addresses within the faulty address range to locked can prevent the operating system from mapping these faulty physical addresses during the test, resulting in the failure of subsequent virtual address range mapping and ensuring the normal progress of the test.

[0012] In combination with the first aspect, in the first embodiment of the first aspect, the conversion of the faulty physical address range into a virtual address range includes:

[0013] Converting the faulty physical address range into a target physical address range recognizable by the operating system;

[0014] Converting the target physical address range into the virtual address range.

[0015] The memory test method provided by the embodiments of the present invention converts the faulty physical address range into a virtual address range recognizable by the operating system, so that memory read and write can replace I / O read and write to obtain higher performance and improve test efficiency.

[0016] In combination with the first embodiment of the first aspect, in the second embodiment of the first aspect, the conversion of the target physical address range into the virtual address range includes:

[0017] Obtaining CPU type and topology information;

[0018] Based on the CPU type and topology information, converting the target physical address range into the virtual address range.

[0019] The memory test method provided by the embodiments of the present invention accurately converts the virtual address range by obtaining the CPU type and topology information, ensuring the reliability of the virtual address range conversion.

[0020] In combination with the first aspect, before the step of obtaining the faulty physical address of the target memory and the preset address offset in the third embodiment of the first aspect, it further includes:

[0021] Turning off memory interleaving to make the physical addresses of the target memory continuous.

[0022] The memory test method provided by the embodiments of the present invention needs to turn off interleaving to ensure the continuity of the physical memory addresses because, in the memory interleaving mode, the memory addresses are discrete and not suitable for continuous reading and writing.

[0023] Combined with the third implementation manner of the first aspect, in the fourth implementation manner of the first aspect, the turning off of the memory interleaving includes:

[0024] Invoking and modifying the BIOS configuration file to turn off the memory interleaving, and restarting the target memory.

[0025] The memory test method provided by the embodiments of the present invention realizes the automatic turning off of the memory interleaving by automatically invoking the BIOS configuration file, and restarts the target memory to ensure the availability of the memory after turning off the memory interleaving.

[0026] Combined with the first aspect, in the fifth implementation manner of the first aspect, the memory testing of the target memory based on the virtual address range includes:

[0027] Obtaining the quantity of the target memory to start threads corresponding one by one to the target memory;

[0028] Performing memory testing on the corresponding target memory based on each thread.

[0029] The memory test method provided by the embodiments of the present invention realizes the parallelism of the memory testing through the threads corresponding one by one to the target memory, improving the testing efficiency.

[0030] Combined with the fifth implementation manner of the first aspect, in the sixth implementation manner of the first aspect, the performing memory testing on the corresponding target memory based on each thread includes:

[0031] Obtaining the virtual address range corresponding to each failed physical address in each target memory;

[0032] Performing cyclic memory testing on each virtual address range based on the corresponding thread.

[0033] According to the second aspect, the embodiments of the present invention further provide a memory test device, including:

[0034] An obtaining module, configured to obtain the failed physical addresses of the target memory and a preset address offset;

[0035] A determining module, configured to determine a failed physical address range based on the failed physical addresses and the preset address offset;

[0036] A setting module, configured to set the attributes of all physical addresses within the failed physical address range to locked;

[0037] A conversion module, configured to convert the range of the faulty physical addresses into a range of virtual addresses;

[0038] A test module, configured to perform a memory test on the target memory based on the range of virtual addresses.

[0039] The memory test device provided by the embodiments of the present invention screens the test objects in the target memory by using the faulty physical addresses, and only performs tests on the range of faulty physical addresses without the need for overall testing, thereby narrowing the memory test range. Moreover, due to the memory fault coupling and the manifestation of multiple write faults, the memory faults occur in adjacent row and column ranges. Therefore, the range of faulty physical addresses is determined from the faulty physical addresses, and performing tests on the range of faulty physical addresses can ensure the reliability of the test results. At the same time, setting the attributes of all physical addresses within the range of faulty addresses to locked can prevent the operating system from mapping these faulty physical addresses during the test, resulting in the invalidation of subsequent virtual address range mapping, and ensuring the normal progress of the test.

[0040] According to a third aspect, an embodiment of the present invention provides an electronic device, including: a memory and a processor, where the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to execute the memory test method described in the first aspect or any one of the embodiments of the first aspect.

[0041] According to a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, where the computer-readable storage medium stores computer instructions, and the computer instructions are used to cause the computer to execute the memory test method described in the first aspect or any one of the embodiments of the first aspect. Description of the Drawings

[0042] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 is a flowchart of the memory test method according to an embodiment of the present invention;

[0044] Figure 2 is a flowchart of the memory test method according to an embodiment of the present invention;

[0045] Figure 3 is a flowchart of the memory test method according to an embodiment of the present invention;

[0046] Figure 4 It is a structural block diagram of a memory test device according to an embodiment of the present invention;

[0047] Figure 5 It is a schematic diagram of the hardware structure of a sub-device provided by an embodiment of the present invention. Detailed implementation manners

[0048] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0049] The memory test method provided by the embodiments of the present invention records the physical addresses of faults, narrows the memory test range, so as to achieve the effect of shortening the fault reproduction time. For example, for 32G of memory, in the prior art, in order to meet the requirements of fault reproduction, it is necessary to run full 32G. Now, only the fault physical address ranges corresponding to each fault physical address need to be run, and the fault reproduction time is shortened by more than a hundred times. Due to the huge improvement in test efficiency, high-complexity algorithms can be used to increase the fault reproduction probability; in addition, within a short time, the number of test loops of the executed algorithms is increased, and theoretically, the reproduction probability can be increased; based on the physical addresses of faults in the memory, the positions of faulty memories can be accurately determined.

[0050] According to an embodiment of the present invention, an embodiment of a memory test method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order from that here.

[0051] In this embodiment, a memory test method is provided, which can be used in electronic devices such as servers, computers, and tablets. Figure 1 It is a flowchart of the memory test method according to an embodiment of the present invention, as Figure 1 shown, and the process includes the following steps:

[0052] S11, obtain the physical addresses of faults of the target memory and a preset address offset.

[0053] If a failure occurs during the operation of the memory, the SPD in the memory will record the physical address of the failure, which is called the failure physical address. Since the failure characteristic state of the memory is a coupling fault: if and only if unit j is in a specific state y (y ∈ {0, 1}), unit i is always a certain value x (x ∈ {0, 1}), then unit i is coupled to unit j. The coupling relationship is not necessarily symmetric, that is to say, if unit i is coupled to unit j, it is not necessarily the case that unit j is also coupled to unit i. That is, the memory failure coupling and multiple write failure manifestations cause the memory failure to occur in the adjacent row and column ranges. Therefore, a preset address offset needs to be set to perform subsequent memory detection based on the failure physical address in combination with this preset address offset. Generally, there are 64 bits per row. Therefore, 20M above and below the failure physical address is sufficient to include the failed units affected by the coupling. Of course, the specific value of the address offset can be set according to actual needs, and no limitation is imposed on it here.

[0054] Among them, for each target memory, the number of its failure physical addresses can be one, two or more, and so on. Correspondingly, for the electronic device, the number of target memories that can be tested simultaneously is set according to actual needs, and no limitation is imposed on it here.

[0055] S12. Based on the failure physical address and the preset address offset, determine the failure physical address range.

[0056] After the electronic device obtains the failure physical address, it adds the preset address offset to the failure physical address to determine the failure physical address range. Among them, the failure physical address is used as the base address, and on this basis, after offsetting the preset address offset up and down, the failure physical address range is determined.

[0057] Corresponding to each failure physical address, the electronic device can obtain the corresponding failure physical address range. For example, if there are 4 target memories and each target memory corresponds to 2 failure physical addresses, then each target memory corresponds to 2 failure physical address ranges.

[0058] S13. Set the attributes of all physical addresses within the failure physical address range to locked.

[0059] The physical address attributes are determined by the hardware BIOS and passed to the operating system through the E820 table. Then, the operating system performs corresponding operations based on the attributes of each physical address. Among them, the physical address attributes include Usable, Reserved, ACPI data, and ACPI NVS. Specifically, Usable: indicates the physical address that has been mapped to physical memory; Reserved: indicates that these intervals are not mapped anywhere and cannot be used as RAM, but the Kernel can decide to map this interval to other places, such as PCI devices. By reading / proc / iomem, you can view the mapping of the physical address space and know how these reserved spaces are further allocated to different devices for use; ACPI data: indicates the RAM space mapped to store ACPI data, and the operating system should read the ACPI Table into this interval; ACPI NVS: indicates the non-volatile storage space mapped to store ACPI data, which cannot be used by the operating system. The attributes of the physical address are set in the BIOS, and the attributes of the physical address are passed to the operating system OS through the E820 table.

[0060] After the electronic device determines the range of faulty physical addresses, it sets the attributes of all physical addresses within this range to locked. In this way, the operating system will not allocate this range of faulty physical addresses to other processes or the system itself, which can avoid the failure of the virtual address range conversion in S14. Setting the attributes of the faulty physical addresses to reserved means that these intervals are not mapped anywhere and cannot be used as RAM. Therefore, setting the address segment with the reserved attribute will not affect the system's use, and it can be used to run memory algorithm read and write tests to stimulate the faulty unit.

[0061] S14, convert the range of faulty physical addresses to a range of virtual addresses.

[0062] The electronic device maps each physical address within the range of faulty physical addresses to a virtual address in sequence to determine the corresponding range of virtual addresses.

[0063] S15, perform a memory test on the target memory based on the range of virtual addresses.

[0064] The electronic device uses a memory test algorithm to perform a memory test on the range of virtual addresses, that is, to reproduce the fault through a stress test. Among them, the memory test algorithm can adopt some algorithms with high complexity, such as Data Retention, MarchSD, etc.

[0065] The specific details of this step will be described in detail below.

[0066] The memory test method provided in this embodiment screens the test objects in the target memory by using the faulty physical addresses, and only tests the range of faulty physical addresses without the need for overall testing, thus narrowing the memory test scope. Moreover, due to memory fault coupling and the manifestation of multiple write faults, memory faults occur in adjacent row and column ranges. Therefore, the range of faulty physical addresses is determined from the faulty physical addresses, and testing the range of faulty physical addresses can ensure the reliability of the test results. At the same time, setting the attributes of all physical addresses within the faulty address range to locked can prevent the operating system from mapping these faulty physical addresses during the test, resulting in the invalidation of subsequent virtual address range mapping and ensuring the normal progress of the test.

[0067] In this embodiment, a memory test method is provided, which can be used in electronic devices such as servers, computers, and tablet computers. Figure 2 It is a flowchart of the memory test method according to an embodiment of the present invention, as Figure 2 shown. The process includes the following steps:

[0068] S21, obtain the faulty physical addresses of the target memory and a preset address offset.

[0069] For details, please refer to Figure 1 S11 in the shown embodiment, which will not be elaborated here.

[0070] S22, based on the faulty physical addresses and the preset address offset, determine the range of faulty physical addresses.

[0071] For details, please refer to Figure 1 S12 in the shown embodiment, which will not be elaborated here.

[0072] S23, set the attributes of all physical addresses within the range of faulty physical addresses to locked.

[0073] For details, please refer to Figure 1 S13 in the shown embodiment, which will not be elaborated here.

[0074] S24, convert the range of faulty physical addresses into a range of virtual addresses.

[0075] Specifically, the above S24 includes:

[0076] S241, convert the range of faulty physical addresses into a range of target physical addresses recognizable by the operating system.

[0077] Since the failed physical address is represented in the form of rows and columns when recorded, that is, the failed physical address row and col recorded by the SPD. However, the physical address recognizable by the operating system is represented in other forms. For example, 0x28F0000000. Therefore, the electronic device needs to convert the failed physical address range into the target physical address range based on the corresponding relationship. Among them, the corresponding relationship is determined by the hardware of the memory. For example, which physical address in the operating system does the first row and the first column of the memory physical address correspond to. Based on this, the electronic device can convert the entire failed physical address range into the target physical address range recognizable by the operating system.

[0078] S242, convert the target physical address range into a virtual address range.

[0079] After the electronic device determines the target physical address range, it converts it into a virtual address range. Among them, the virtual address range can be obtained by mapping with the mmap function.

[0080] In some alternative embodiments of this embodiment, the above S242 may include:

[0081] (1) Obtain the CPU type and topology information.

[0082] (2) Based on the CPU type and topology information, convert the target physical address range into a virtual address range.

[0083] Obtain the CPU type. For example, intel, AMD, ARM, and intel has several generations of platforms such as the Skylake and Icelake platforms. Obtain the logical cores under their CPUs to establish thread binding. The electronic device uses the mmap function to map the target physical address range into a virtual address range based on the CPU type and topology information. Among them, the purpose of mapping is to use the mmap function to map the / dev / mem file to improve the test memory address read and write speed and thus improve the test efficiency.

[0084] By obtaining the CPU type and topology information to accurately convert the virtual address range, the reliability of the virtual address range conversion is ensured.

[0085] S25, perform a memory test on the target memory based on the virtual address range.

[0086] For details, please refer to Figure 1 S15 in the illustrated embodiment, which will not be elaborated here.

[0087] The memory test method provided in this embodiment converts the failed physical address range into a virtual address range recognizable by the operating system, so that memory read and write can replace I / O read and write to obtain higher performance and improve test efficiency.

[0088] In this embodiment, a memory testing method is provided, which can be used in electronic devices such as servers, computers, and tablets. Figure 3 It is a flowchart of the memory testing method according to an embodiment of the present invention, as Figure 3 shown. The process includes the following steps:

[0089] S31. Turn off memory interleaving so that the physical addresses of the target memory are continuous.

[0090] Before testing, the electronic device calls and modifies the BIOS configuration file through a corresponding script to turn off interleaving, and then restarts the target memory to take effect. Alternatively, it can also be manually turned off through the BIOS interface when the server and computer are started.

[0091] S32. Obtain the faulty physical address of the target memory and a preset address offset.

[0092] For details, please refer to Figure 1 S11 of the embodiment shown, which will not be elaborated here.

[0093] S33. Based on the faulty physical address and the preset address offset, determine the faulty physical address range.

[0094] For details, please refer to Figure 1 S12 of the embodiment shown, which will not be elaborated here.

[0095] S34. Set the attributes of all physical addresses within the faulty physical address range to locked.

[0096] For details, please refer to Figure 1 S13 of the embodiment shown, which will not be elaborated here.

[0097] S35. Convert the faulty physical address range into a virtual address range.

[0098] For details, please refer to Figure 2 S24 of the embodiment shown, which will not be elaborated here.

[0099] S36. Perform a memory test on the target memory based on the virtual address range.

[0100] Specifically, the above S36 includes:

[0101] S361. Obtain the number of target memories to start threads corresponding one by one to the target memories.

[0102] The number of target memories can be automatically obtained by the electronic device, or can be set by the user on the interaction interface provided by the electronic device, or can also be obtained by the electronic device through other means, and no limitation is made thereto.

[0103] After determining the number of target memories, the electronic device starts the corresponding number of threads to perform parallel tests on each target memory.

[0104] S362. Perform memory tests on the corresponding target memories based on each thread.

[0105] The threads correspond to the target memories one by one. The memory tests for the corresponding target memories can be independently completed within each thread. That is, for the virtual address range determined for the faulty physical address of the target memory, the corresponding memory algorithm is used to perform memory tests on the virtual address range.

[0106] In some optional implementation manners of this embodiment, the above S362 may include:

[0107] (1) Obtain the virtual address range corresponding to each faulty physical address in each target memory.

[0108] (2) Perform cyclic memory tests on each virtual address range based on the corresponding thread.

[0109] As described above, for each target memory, there may be at least one faulty physical address. For each faulty physical address, there is a corresponding virtual address range. In the same thread, cyclic tests are performed on the virtual address range corresponding to the target memory, so as to implement a stress and strengthening test on the target memory. That is, the electronic device tests multiple faulty target memories in parallel at the same time, and a single target memory serially tests the virtual address ranges corresponding to 3 SPD faulty physical addresses.

[0110] As an optional implementation manner of this embodiment, ECC and MCE detections are performed while performing memory tests to determine whether there are errors and thus determine whether the memory has failed.

[0111] In the memory test method provided in this embodiment, since in the memory interleaving mode, the memory addresses are discrete and not suitable for continuous reading and writing, it is necessary to turn off the interleaving to ensure the continuity of the memory physical addresses. The parallelism of memory tests is achieved through threads corresponding to the target memories one by one, improving the test efficiency.

[0112] This memory test method automatically obtains the SPD faulty physical addresses, determines whether there are faulty memory modules in the server, and automatically creates threads according to the number of faulty memory modules to perform parallel tests on all memory modules. Each single memory is serially strengthened and tightened tested according to the SPD faulty physical addresses. That is, based on the SPD fault address records, the memory test range is reduced to achieve the effect of shortening the fault recurrence time. For example, for a 32G memory, originally it needed to run full 32G for recurrence, now it only needs to run 20M for each fault, and the fault recurrence time is shortened by more than a hundred times.

[0113] Furthermore, with a huge improvement in test efficiency, algorithms with high complexity, such as Data Retention and March SD, can be introduced into the memory fault reproduction test. Additionally, increasing the number of test loops of the executed algorithms within a short period can increase the reproduction probability.

[0114] Furthermore, this test method is based on the actual physical address of the fault, and can accurately determine the location of the faulty memory.

[0115] In this embodiment, a memory test device is further provided. This device is used to implement the above-mentioned embodiments and preferred implementation manners, and those that have been described will not be repeated here. As used hereinafter, the term "module" can be a combination of software and / or hardware that can achieve a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware is also possible and contemplated.

[0116] This embodiment provides a memory test device, as Figure 4 shown, including:

[0117] An acquisition module 41, configured to acquire the physical address of the fault of the target memory and a preset address offset;

[0118] A determination module 42, configured to determine a physical address range of the fault based on the physical address of the fault and the preset address offset;

[0119] A setting module 43, configured to set the attributes of all physical addresses within the physical address range of the fault to locked;

[0120] A conversion module 44, configured to convert the physical address range of the fault into a virtual address range;

[0121] A test module 45, configured to perform a memory test on the target memory based on the virtual address range.

[0122] The memory test device in this embodiment is presented in the form of functional units. Here, the unit refers to an ASIC circuit, a processor and a memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0123] The further functional descriptions of the above-mentioned respective modules are the same as those in the corresponding embodiments above, and will not be repeated here.

[0124] This embodiment of the present invention further provides an electronic device, having the above-mentioned Figure 4 shown memory test device.

[0125] Please refer to Figure 5 , Figure 5It is a schematic structural diagram of an electronic device provided by an alternative embodiment of the present invention. As Figure 5 shown, the electronic device may include: at least one processor 51, such as a CPU (Central Processing Unit), at least one communication interface 53, a memory 54, and at least one communication bus 52. Among them, the communication bus 52 is used to realize the connection and communication between these components. Among them, the communication interface 53 may include a display screen (Display) and a keyboard (Keyboard). Optionally, the communication interface 53 may further include a standard wired interface and a wireless interface. The memory 54 may be a high-speed RAM memory (Random Access Memory, volatile random access memory), or a non-volatile memory, such as at least one disk memory. Optionally, the memory 54 may further be at least one storage device located far from the aforementioned processor 51. Among them, the processor 51 may be combined with Figure 4 the device described, and an application program is stored in the memory 54, and the processor 51 calls the program code stored in the memory 54 to execute any of the above method steps.

[0126] Among them, the communication bus 52 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The communication bus 52 may be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, Figure 5 only a thick line is used to represent it in the figure, but it does not mean that there is only one bus or one type of bus.

[0127] Among them, the memory 54 may include a volatile memory (English: volatile memory), such as a random access memory (English: random-access memory, abbreviation: RAM); the memory may also include a non-volatile memory (English: non-volatile memory), such as a flash memory (English: flash memory), a hard disk (English: hard disk drive, abbreviation: HDD) or a solid-state drive (English: solid-state drive, abbreviation: SSD); the memory 54 may further include a combination of the above types of memories.

[0128] Among them, the processor 51 can be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP.

[0129] Among them, the processor 51 may further include a hardware chip. The above-mentioned hardware chip can be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The above-mentioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0130] Optionally, the memory 54 is further configured to store program instructions. The processor 51 can call the program instructions to implement the memory test method as shown in any embodiment of the present application.

[0131] The embodiment of the present invention further provides a non-transitory computer storage medium. The computer storage medium stores computer-executable instructions, and the computer-executable instructions can execute the memory test method in any of the above method embodiments. Among them, the storage medium can be a magnetic disk, an optical disc, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above types of memories.

[0132] Although the embodiments of the present invention are described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A memory testing method, characterized in that, including: Obtaining a faulty physical address of a target memory and a preset address offset; Determining a faulty physical address range based on the faulty physical address and the preset address offset; Setting the attributes of all physical addresses within the faulty physical address range to locked; Converting the faulty physical address range into a virtual address range; Performing a memory test on the target memory based on the virtual address range.

2. The method according to claim 1, characterized in that, The converting the faulty physical address range into a virtual address range includes: Converting the faulty physical address range into a target physical address range recognizable by an operating system; Converting the target physical address range into the virtual address range.

3. The method according to claim 2, characterized in that, The converting the target physical address range into the virtual address range includes: Obtaining CPU type and topology information; Converting the target physical address range into the virtual address range based on the CPU type and topology information.

4. The method according to claim 1, characterized in that, Before the step of obtaining the faulty physical address of the target memory and the preset address offset, it further includes: Turning off memory interleaving to make the physical addresses of the target memory continuous.

5. The method according to claim 4, characterized in that, The turning off memory interleaving includes: Invoking and modifying a BIOS configuration file to turn off memory interleaving and restarting the target memory.

6. The method according to claim 1, characterized in that, The performing a memory test on the target memory based on the virtual address range includes: Obtaining the quantity of the target memory to start threads corresponding one by one to the target memory; Performing a memory test on the corresponding target memory based on each of the threads.

7. The method according to claim 6, characterized in that, The performing a memory test on the corresponding target memory based on each of the threads includes: Obtaining the virtual address range corresponding to each faulty physical address in each target memory; Performing a loop memory test on each of the virtual address ranges based on the corresponding thread.

8. A memory testing device, characterized in that, including: An obtaining module, configured to obtain a faulty physical address of a target memory and a preset address offset; A determining module, configured to determine a faulty physical address range based on the faulty physical address and the preset address offset; A setting module, configured to set the attributes of all physical addresses within the faulty physical address range to locked; A converting module, configured to convert the faulty physical address range into a virtual address range; A testing module, configured to perform a memory test on the target memory based on the virtual address range.

9. An electronic device, characterized in that, including: A memory and a processor, the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to execute the memory test method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions, and the computer instructions are used to cause a computer to execute the memory test method according to any one of claims 1-7.

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