Apparatus and Method for Adaptive Retention Voltage in a Volatile Memory

Abstract

An integrated circuit (IC) includes a plurality of volatile memory (VM) blocks and a power gating control circuit configured to control power gating for each of the plurality of VM blocks. The IC includes a power mode controller circuit configured to select a power mode, and in response to selecting a retention mode as the power mode, the power mode controller circuit gates the supply voltage to each block in a selected subset from the plurality of VM blocks and allows a retention voltage to power each VM block in the remaining subset of the plurality of VM blocks external to the selected subset. The IC includes a voltage controller circuit configured to determine a voltage level of the retention voltage based on a minimum retention voltage required for each VM block in the remaining subset.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices, and more particularly, to adjusting retention voltages for volatile memory blocks. Background Art

[0002] A semiconductor device can switch to a low-power mode in which the circuitry is in a non-active state, but the circuit state is retained in volatile memory so that the device does not completely power off. The low-power mode can save time and effort by allowing a user to resume from the point where they interrupted before entering the low-power mode, without requiring a full power-off / power-on cycle and loss of data from the previous session. The voltage level during state retention is lower than the active level to reduce power consumption. In existing low-power state retention solutions for retaining states in volatile memory, such as in a microcontroller, the retention voltage level is based on the maximum storage capacity of the volatile memory to be retained. The leakage current is proportional to the voltage level applied to the bit cells in the memory device.

[0003] The leakage current of an array of a large number of memory cells, including volatile memory bit cells such as greater than 1 megabyte, will be a specific value at the retention voltage, which allows proper operation over the process, voltage, and temperature (PVT) variation ranges of all bit cells. The retention voltage is determined by the probability of bit cell failure, which occurs when the supplied voltage is insufficient to retain the data stored by the bit cell. This failure probability is proportional to the number of bit cells in the retention mode. However, when the storage capacity of the volatile memory is reduced to a smaller amount (e.g., 32 kilobytes), the retention voltage can be reduced, thereby reducing the leakage current. Generally, the retention voltage is selected for the worst case, which includes a large number of bit cells in the retention mode. Summary of the Invention

[0004] According to a first aspect of the present invention, there is provided an integrated circuit, comprising:

[0005] a plurality of volatile memory (VM) blocks;

[0006] a power gating control circuit configured to control power gating for each of the plurality of VM blocks;

[0007] a power mode controller circuit configured to select a power mode for the integrated circuit, wherein in response to the power mode controller circuit selecting the retention mode as the power mode, the power gating control circuit gates the supply voltage for each block in a selected subset from the plurality of VM blocks and allows the retention voltage to power each VM block in the remaining subset of the plurality of VM blocks external to the selected subset; and

[0008] A voltage controller circuit configured to determine a voltage level of the retention voltage based on a minimum retention voltage required for each VM block in the remaining subset.

[0009] According to one or more embodiments, the integrated circuit further includes: a storage circuit coupled to the voltage controller circuit, the storage circuit being configured to store a corresponding minimum retention voltage for each VM block of the plurality of VM blocks.

[0010] According to one or more embodiments, the voltage controller circuit is configured to determine the voltage level of the retention voltage by selecting a maximum value of the minimum retention voltages corresponding to the remaining subset of VM blocks.

[0011] According to one or more embodiments, the voltage level of the retention voltage includes a tolerance voltage in addition to a voltage required to maintain a state in the remaining subset of the VM blocks.

[0012] According to one or more embodiments, the integrated circuit further includes: a voltage regulator configured to provide a corresponding supply voltage to each VM block of the plurality of blocks, wherein the voltage controller circuit is configured to indicate the voltage level of the retention voltage to the voltage regulator.

[0013] According to one or more embodiments, the voltage regulator provides the voltage level of the retention voltage indicated by the voltage controller circuit as the corresponding supply voltage during the retention mode.

[0014] According to one or more embodiments, the voltage regulator is configured to provide one of a set of predetermined regulated voltages as the corresponding supply voltage during the retention mode, wherein the voltage controller circuit is configured to indicate the voltage level of the retention voltage by selecting one of the set of predetermined regulated voltages.

[0015] According to one or more embodiments, the integrated circuit includes a static random access memory (SRAM), wherein the SRAM is divided into a plurality of NV memory blocks.

[0016] According to one or more embodiments, the voltage controller circuit is configured to determine the voltage level of the retention voltage based on a total number of VM blocks in the remaining subset.

[0017] According to one or more embodiments, in response to the power mode controller circuit selecting the active mode as the power mode, the power gate control circuit allows an operating supply voltage to power each VM block in a second selected subset of the plurality of VM blocks.

[0018] According to one or more embodiments, in response to the power mode controller circuit selecting the active mode as the power mode, the power gating control circuit further gates the power to one or more of the plurality of VM blocks outside the second selected subset.

[0019] According to one or more embodiments, in response to the power mode controller circuit selecting the active mode as the power mode, the power gating control circuit further allows a second retention voltage to power one or more of the plurality of VM blocks outside the second selected subset.

[0020] According to a second aspect of the present invention, there is provided an integrated circuit, comprising:

[0021] A volatile memory, the volatile memory being divided into a plurality of blocks;

[0022] A voltage regulator configured to provide a supply voltage to each of the plurality of blocks;

[0023] A power gating control circuit configured to control the power gating of the supply voltage to each of the plurality of blocks;

[0024] A power mode controller configured to select a power mode for the integrated circuit, wherein in response to selecting the retention mode, the power gating control circuit blocks the supply voltage from powering each block in a selected subset of the plurality of blocks and allows the supply voltage to power each block in the remaining subset of the plurality of blocks outside the selected subset; and

[0025] A voltage controller circuit configured to instruct the voltage regulator to retain a voltage level to provide the retained voltage level as the supply voltage during the retention mode, wherein the voltage controller is configured to determine the retained voltage level based on the minimum retained voltage level required for each block in the remaining subset.

[0026] According to one or more embodiments, the integrated circuit further comprises: a storage circuit coupled to the voltage controller circuit, the storage circuit being configured to store a corresponding minimum retained voltage level for each block in the remaining subset.

[0027] According to one or more embodiments, the voltage controller circuit is configured to select the maximum value of the minimum retained voltage levels corresponding to the blocks in the remaining subset and to indicate the retained voltage level based on the selected maximum value.

[0028] According to one or more embodiments, the voltage regulator is configured to provide one of a set of predetermined regulated voltages as the supply voltage, wherein the voltage controller circuit is configured to indicate the retention voltage level by selecting one of the set of predetermined regulated voltages.

[0029] According to one or more embodiments, the non-volatile memory is characterized as a static random access memory (SRAM).

[0030] According to another aspect of the present invention, a method is provided, including:

[0031] Entering a data retention mode of a volatile memory, wherein the volatile memory is divided into a plurality of blocks;

[0032] In response to entering the data retention mode, selecting a retention subset of the plurality of blocks, wherein in the data retention mode, each block in the retention subset is powered by a retention voltage, and in the data retention mode, each block in the plurality of blocks not in the retention subset is powered off; and

[0033] Determining a voltage level of the retention voltage provided to each block in the retention subset during the retention mode based on a minimum retention voltage required for each block in the retention subset.

[0034] According to one or more embodiments, the determining includes: selecting a maximum value of the minimum retention voltages required for the blocks of the retention subset; and setting the voltage level of the retention voltage based on the selected maximum value.

[0035] According to one or more embodiments, the determining further includes: accessing a storage circuit configured to store a corresponding minimum retention voltage for each block of the plurality of blocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The present disclosure is illustrated by way of example and is not limited by the accompanying drawings, in which like reference numerals indicate like elements. Elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0037] Figure 1 A block diagram showing components of a processing system according to a selected embodiment of the present invention.

[0038] Figure 2 A block diagram showing components of a processing system according to a selected embodiment of the present invention. DETAILED DESCRIPTION

[0039] Embodiments of systems and methods are disclosed, in which the minimum voltage level required to retain data in a block of a volatile memory is determined for each block based on the number of bit cells in the block. Once entering a low-power mode where it is required to retain data in at least some of the blocks, the maximum value of the minimum voltage levels of a group of blocks in the retention mode is selected as the retention voltage for all the blocks in the group. In existing known systems, the retention voltage is selected based on the total storage capacity of the memory in the entire volatile memory device, even though the largest block may not be among those blocks having data to be retained during the low-power mode. Blocks having fewer memory cells require a smaller retention voltage. By selecting the retention voltage based on the storage capacity of the volatile memory to be retained in the largest block in a block subset, the leakage current can be significantly reduced, even reduced by an exponential factor, thereby reducing power consumption.

[0040] Figure 1 A block diagram showing components for controlling the retention voltage of volatile memory blocks having different numbers of bit cells in a processing system according to a selected embodiment of the present invention is shown. The components include a power mode controller circuit 102, a memory controller circuit 103 having a power gating control circuit 104, a volatile memory device 105 having a bit cell array grouped into blocks 106, 108, 110, a voltage control / regulator circuit 112, and a storage circuit 116 for storing values of the minimum retention mode voltage (Vmin,k) requirements of the volatile memory blocks 106, 108, 110.

[0041] The power mode controller circuit 102 receives an operation mode as an input from another device, such as from a master processing core (not shown). The processing system typically implements an active operation mode and one or more reduced-power modes, in the active operation mode all required circuitry is powered to provide full functional capabilities, and the one or more reduced-power modes implement various levels of simplified functionality. The implementation of the reduced-power modes is intended to reduce power consumption and conserve available power, especially in battery-powered devices.

[0042] The power mode controller circuit 102 correlates the operating mode with one or more voltage levels required to provide the functionality enabled in each operating mode. When a circuit is not needed in a particular mode, the voltage level in the active or reduced power mode can also be "off". The required voltage levels are output to the memory controller circuit 103 and the voltage controller / regulator circuit 112. For example, the power controller 102 can signal the memory controller circuit 103 and the voltage control / regulator circuit 112 to provide the active mode voltage levels for the full operability of the memory device 105. At one or more levels of the low power mode, although the memory device 105 does not have the full operability to write and read data into the bit cells in the memory blocks 106, 108, 110, the contents of at least some of the blocks 106, 108, 110 in the memory device 105 are retained. The voltage controller / regulator circuit 112 receives the required voltage level signals from the power mode controller circuit 102 and supplies the corresponding regulated voltages to one or more of the blocks 106, 108, 110 based on whether full functionality or a lower power operable state is enabled, in which the contents of one or more volatile memory blocks among the volatile memory blocks 106, 108, 110 are retained despite limited functionality.

[0043] The blocks 106, 108, 110 can each include a different number of bit cells and can thus have different Vmin requirements for retaining state information during the low power retention mode. Also, the number of blocks 106, 108, 110 in the retention mode can vary depending on the selected power mode. The minimum retention voltage Vmin for each of the blocks 106, 108, 110 is tracked and stored. The minimum retention voltage may or may not vary with the number of bit cells in the block. For example, due to a tail bit, the Vmin of a small block may be higher than that of a larger block. The power mode controller circuit 102 uses this information to determine the maximum Vmin of the blocks 106, 108, 110 selected to be in the retention mode. If the Vmin of each block is stored, the Vmin (i.e., the maximum value) of any combination of these blocks can be calculated even if there is an abnormal tail bit somewhere. Information about the lowest voltage level required to retain the data in each of the blocks 106, 108, 110 is stored in the volatile memory block retention mode Vmin requirement circuit 116. The relationship between the size of each of the blocks 106, 108, 110 and the minimum retention voltage of the block can be hard-coded or implemented as a look-up table in a register. Alternatively, the Vmin information for each of the blocks 106, 108, 110 can be determined and generated by software executed by a state machine in a central processing unit, a digital signal processor, or other suitable hardware, firmware, or software or a combination thereof.

[0044] It can be found that the memory storage capacity retained in the memory device 105 starts as the total storage capacity of the memory and then subtracts the memory storage capacity that is power gated. Power gating prevents current from flowing into the unused blocks 106, 108, 110 to reduce power consumption. The power gating control circuit 104 generates a control signal that is provided to a power gating device (not shown) in the memory device 105. Some of the blocks 106, 108, 110 can be power gated, and the data stored in the power gated blocks can be transferred to a retention register such as a flip-flop (not shown). Other blocks among the blocks 106, 108, 110 that are not power gated or are in the active mode can retain the content in the bit cells during the specified low-power mode.

[0045] The power mode controller circuit 102 can be implemented by dedicated hardware that can be controlled by a central processing unit. The power mode controller circuit 102 controls the power states of the multiple volatile memory blocks 106, 108, 110 according to the power mode of the device in which the power mode controller circuit 102 is implemented. In the active mode, some of the memory blocks among the memory blocks 106, 108, 110 can be in a fully operable mode, while other memory blocks among the memory blocks 106, 108, 110 can be in a retention mode or power gated. The voltage controller / regulator 112 supplies a regulated voltage to each of the blocks 106, 108, 110 that are not power gated. When the power mode controller circuit 102 selects the active mode as the power mode, the power gating control circuit 104 allows an operating supply voltage to be provided to each of the blocks 106, 108, 110 in the active mode, while a retention voltage is provided to each of the blocks 106, 108, 110 in the retention mode.

[0046] In some low-power states, when retaining the information in the memory device 105, some of the memory blocks among the memory blocks 106, 108, 110 may be in the retention mode, while other memory blocks among the memory blocks 106, 108, 110 may be power gated. Whenever one or more of the memory blocks 106, 108, 110 are placed in the retention mode, the supply voltage level from the voltage controller / regulator 112 is adjusted based on the memory blocks 106, 108, 110 in the power gated state. When the memory blocks 106, 108, 110 return from the retention mode to the active mode, the supply voltage increases to the active mode level.

[0047] Thus, in the lower power mode, the power mode controller circuit 102 provides a signal indicating that the power level to be used is lower than the power level used during the fully operable or active mode. The memory controller 103 determines which of the memory blocks 106, 108, 110 are power gated and which of the memory blocks 106, 108, 110 are in the retention mode. The register settings in the power mode controller 102 are used to program the power states of the memory blocks 106, 108, 110, and based on this information, the power mode controller 102 uses the Vmin requirements 116 of the blocks 106, 108, 110 in the retention mode to determine the retention voltage to be provided to the voltage controller / regulator circuit 112. When more than one of the memory blocks 106, 108, 110 are in the retention mode, the Vmin voltage of the block with the maximum Vmin voltage of all the blocks in the retention mode can be selected as the retention voltage for all the memory blocks 106, 108, 110 in the retention mode. Additionally, an additional voltage tolerance or voltage guard band can be added to the selected Vmin to help ensure the contents of the retention blocks 106, 108, 110.

[0048] In the case where the total number of bit cells in each of the blocks 106, 108, 110 in the retention mode is less than the total number of bit cells of the block with the maximum number of bit cells that can be set to the retention mode, the retention voltage will be lower than the retention voltage in previously known systems, where all blocks in the retention mode use the retention voltage of the block with the highest total number of bit cells regardless of whether they are currently in the retention mode. Thus, compared to the systems and devices implementing embodiments of the present invention, previously known systems use a higher retention voltage than required, resulting in higher leakage current and power consumption.

[0049] Reference Figure 2 , which shows a simplified block diagram illustrating an example of a multi-core processing system 200 that can be used to implement embodiments of the present invention. The processing system 200 includes one or more processor cores 202, 204, 206, a system switch fabric 208, a power mode controller circuit 102, a voltage controller / regulator circuit 112, a memory controller circuit 103, a memory device 105, a volatile memory block retention mode Vmin requirement storage device 116, peripherals 216, a network port 226, and an input / output (I / O) port 228. The switch fabric 208 communicatively couples all the illustrated components 102, 103, and 202 - 128 of the multi-core processing system 200.

[0050] The processing cores 202, 204, 206 include computer processor circuitry capable of executing functions that can be implemented as software instructions, hardware circuitry, firmware, or a combination of software, hardware, and firmware. Operations and functions can be executed under the control of an operating system. One or more instances of software application code can be executed simultaneously. The application code executed by the processing cores 202, 204, 206 can access data and instructions in the memory 105 via the system switching fabric 208 and the memory controller 103. The processing cores 202, 204, 206 can be complex instruction set computing (CISC) microprocessors, reduced instruction set computing (RISC) microprocessors, very long instruction word (VLIW) microprocessors, processors implementing other instruction sets, or processors implementing a combination of instruction sets. Additionally or alternatively, the processing cores 202, 204, 206 can be one or more dedicated processors, such as application specific integrated circuits (ASICs), cellular or baseband processors, field programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, graphics processors, network processors, communication processors, cryptographic processors, coprocessors, embedded processors, or any other type of logic capable of processing instructions.

[0051] The processing system 200 can also include one or more network ports 226 configurable to connect to one or more networks, which can also be accessed by one or more remote nodes. The remote nodes can include other application processors, devices, or sensors that can exchange information with the processing system 200.

[0052] The system switching fabric 208 routes requests and responses between the CPUs 202, 204, 206 and the power mode controller 102, the peripheral interface 216, the memory controller 103, and the I / O device 228.

[0053] One or more peripheral interfaces 216 are communicatively coupled to the system switching fabric 208. The peripheral interface 216 can include circuitry, for example, for performing power management, flash management, interconnect management, USB, and other PHY type tasks. A variety of peripheral devices (not shown), such as sensors, field programmable gate arrays, external integrated circuits, mice, keyboards, printers, display monitors, external memory drives, cameras, and lights, can be coupled to the processing system 200 via the peripheral interface 216.

[0054] Memory device 105 may include one or more volatile storage (or memory) devices such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or other types of volatile storage devices. Additionally or alternatively, memory device 105 may include non-volatile memory such as read only memory (ROM), electrically erasable programmable ROM, flash memory, magnetic RAM, resistive RAM, etc. In any form, memory device 105 may store information including sequences of instructions to be executed by a processing device or any other device. For example, executable code and / or data in, including but not limited to, an operating system, device drivers, firmware (e.g., input / output basic system or BIOS), and / or application programs may be loaded into the memory and executed by processor cores 202, 204, 206.

[0055] It should now be appreciated that power consumption can be reduced by adjusting the level of the retention voltage (Vmin) in all blocks in retention mode and in unused power-gated blocks to the maximum Vmin, which is beneficial for saving energy and extending the charge life of battery-powered devices.

[0056] In some embodiments, an integrated circuit may include: a plurality of volatile memory (VM) blocks (106, 108, 110); a power gating control circuit (104) configured to control power gating of each of the plurality of VM blocks; a power mode controller circuit (102) configured to select a power mode for the integrated circuit, wherein in response to the power mode controller circuit selecting the retention mode as the power mode, the power gating control circuit gates the supply voltage for each block in a selected subset (N-k) from the plurality of VM blocks and allows the retention voltage to power each VM block in the remaining subset (k) of the plurality of VM blocks outside the selected subset; and a voltage controller circuit configured to determine a voltage level of the retention voltage based on a minimum retention voltage (Vmin,k) required for each VM block in the remaining subset.

[0057] In some aspects, the integrated circuit may additionally include a storage circuit (116) coupled to the voltage controller circuit and configured to store a corresponding minimum retention voltage for each of the plurality of VM blocks.

[0058] In other aspects, the voltage controller circuit may be configured to determine the voltage level of the retention voltage by selecting a maximum value (Max{Vmin,k}) of the minimum retention voltages corresponding to the remaining subset of VM blocks.

[0059] In another aspect, the voltage level of the retention voltage can include a (guard-banded) tolerance voltage in addition to the voltage required to maintain the states in the VM blocks of the remaining subsets.

[0060] In another aspect, the integrated circuit can further include a voltage regulator (112) configured to supply a corresponding supply voltage to each VM block among the plurality of blocks, wherein the voltage controller circuit is configured to indicate the voltage level of the retention voltage to the voltage regulator.

[0061] In another aspect, the voltage regulator can provide, during the retention mode, the voltage level of the retention voltage indicated by the voltage controller circuit as the corresponding supply voltage (e.g., the voltage controller indicates the required precise retention level).

[0062] In another aspect, the voltage regulator can be configured to provide, during the retention mode, one of a set of predetermined regulated voltages as the corresponding supply voltage. The voltage controller circuit can be configured to indicate the voltage level of the retention voltage by selecting one of the set of predetermined regulated voltages (e.g., the voltage regulator can output only a limited number of voltages, and the controller selects the voltage that is closest (and greater) to the voltage it needs).

[0063] In another aspect, the integrated circuit can include a static random access memory (SRAM), wherein the SRAM is divided into a plurality of NV memory blocks.

[0064] In another aspect, the voltage controller circuit can be configured to determine the voltage level of the retention voltage based on the total number of VM blocks in the remaining subsets.

[0065] In another aspect, in response to the power mode controller circuit selecting the active mode as the power mode, the power gating control circuit can allow the operating supply voltage to power each VM block in the second selected subset of the plurality of VM blocks (the blocks in the active state).

[0066] In another aspect, in response to the power mode controller circuit selecting the active mode as the power mode, the power gating control circuit can further gate the power to one or more VM blocks among the plurality of VM blocks outside the second selected subset (the active VM blocks and the power-gated VM blocks).

[0067] In another aspect, in response to the power mode controller circuit selecting the active mode as the power mode, the power gating control circuit further allows a second retention voltage to power one or more VM blocks among the plurality of VM blocks outside the second selected subset (including the active VM blocks and the VM blocks in the retention mode).

[0068] In other embodiments, an integrated circuit may include a volatile memory divided into multiple blocks, a voltage regulator configured to provide a supply voltage to each of the multiple blocks, a power gate control circuit configured to control power gating of the supply voltage for each of the multiple blocks, and a power mode controller configured to select a power mode for the integrated circuit. In response to selecting a retention mode, the power gate control circuit blocks the supply voltage from powering each block in a selected subset of the multiple blocks and allows the supply voltage to power each block in the remaining subset of the multiple blocks external to the selected subset. The voltage controller circuit may be configured to instruct the voltage regulator to indicate a retention voltage level to provide the retention voltage level as the supply voltage during the retention mode. The voltage controller is configured to determine the retention voltage level based on the minimum retention voltage level required for each block in the remaining subset.

[0069] In another aspect, the integrated circuit may include a storage circuit coupled to the voltage controller circuit, the storage circuit being configured to store a corresponding minimum retention voltage level for each block in the remaining subset.

[0070] In another aspect, the voltage controller circuit may be configured to select the maximum value of the minimum retention voltage levels corresponding to the blocks in the remaining subset and to indicate the retention voltage level based on the selected maximum value.

[0071] In another aspect, the voltage regulator may be configured to provide one of a set of predetermined regulated voltages as the supply voltage. The voltage controller circuit may be configured to indicate the retention voltage level by selecting one of the predetermined regulated voltages from the set of predetermined regulated voltages.

[0072] In another aspect, the non-volatile memory may be characterized as a static random access memory (SRAM).

[0073] In another embodiment, a method may include entering a data retention mode of a volatile memory, where the volatile memory is divided into multiple blocks. In response to entering the data retention mode, a retention subset of the multiple blocks is selected, where in the data retention mode, each block in the retention subset is maintained powered by a retention voltage, and in the data retention mode, each block in the multiple blocks not in the retention subset is powered off. A voltage level of the retention voltage provided to each block in the retention subset during the retention mode is determined based on the minimum retention voltage required for each block in the retention subset.

[0074] In another aspect, determining the voltage level of the retention voltage provided to each block in the retention subset during the retention mode may include selecting the maximum value of the minimum retention voltages required for the blocks in the retention subset and setting the voltage level of the retention voltage based on the selected maximum value.

[0075] In another aspect, determining the voltage level of the retention voltage provided to each block in the retention subset during the retention mode can further include accessing a storage circuit configured to store a corresponding minimum retention voltage for each of a plurality of blocks.

[0076] Since the devices implementing the present disclosure are mostly composed of electronic components and circuits known to those skilled in the art, the circuit details will not be explained to a greater extent than necessary as shown above in order to understand and appreciate the basic concepts of the present disclosure and in order not to obscure or deviate from the teachings of the present disclosure.

[0077] Although the present disclosure has been described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the appended claims. For example, the components for implementing Vmin for memory blocks 106, 108, 110 in the retention mode can be used in any type of device that uses a volatile memory device and implements a low power mode. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive, and it is intended that all such modifications be included within the scope of the present disclosure. It is not intended that any advantages, benefits, or problem solutions described herein with respect to specific embodiments be construed as critical, required, or essential features or elements of any or all claims.

[0078] As used herein, the term "coupled" is not intended to be limited to direct coupling or mechanical coupling.

[0079] Furthermore, as used herein, the term "a" or "an" is defined as one or more than one. Also, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that another claim element introduced by the indefinite article "a" or "an" limits any particular claim containing such introduced claim element to a disclosure containing only one such element, even when the same claim includes the introductory phrase "one or more" or "at least one" and an indefinite article such as "a" or "an". The same applies to the use of definite articles.

[0080] Unless otherwise stated, terms such as "first" and "second" are used arbitrarily to distinguish the elements so described. Thus, these terms are not necessarily intended to indicate a temporal or other precedence of such elements.

Claims

1. An integrated circuit, characterized in that, Comprising: A plurality of volatile memory (VM) blocks; A power gating control circuit configured to control the power gating of each of the plurality of VM blocks; A power mode controller circuit configured to select a power mode for the integrated circuit, wherein in response to the power mode controller circuit selecting a retention mode as the power mode, the power gating control circuit gates the supply voltage to each block in a selected subset from the plurality of VM blocks and allows a retention voltage to power each VM block in the remaining subset of the plurality of VM blocks external to the selected subset; A voltage controller circuit configured to determine a voltage level of the retention voltage based on a minimum retention voltage required for each VM block in the remaining subset; And A voltage regulator configured to provide a corresponding supply voltage to each VM block in the plurality of blocks, wherein the voltage controller circuit is configured to indicate the voltage level of the retention voltage to the voltage regulator.

2. The integrated circuit according to claim 1, wherein Further comprising: A storage circuit coupled to the voltage controller circuit and configured to store a corresponding minimum retention voltage for each VM block in the plurality of VM blocks.

3. The integrated circuit according to claim 2, wherein The voltage controller circuit is configured to determine the voltage level of the retention voltage by selecting a maximum value of the minimum retention voltages corresponding to the remaining subset of VM blocks.

4. The integrated circuit according to claim 3, wherein, The voltage level of the retention voltage includes a tolerance voltage in addition to the voltage required to maintain the state in the remaining subset of the VM blocks.

5. The integrated circuit according to claim 1, wherein, The voltage regulator provides the voltage level of the retention voltage indicated by the voltage controller circuit as the corresponding supply voltage during the retention mode.

6. The integrated circuit according to claim 1, characterized in that, The voltage regulator is configured to provide one of a set of predetermined regulated voltages as the corresponding supply voltage during the retention mode, wherein the voltage controller circuit is configured to indicate the voltage level of the retention voltage by selecting one of the set of predetermined regulated voltages.

7. The integrated circuit according to claim 1, characterized in that, The integrated circuit includes a static random access memory (SRAM), wherein the SRAM is divided into a plurality of NV memory blocks.

8. An integrated circuit, characterized in that, Comprising: A volatile memory divided into a plurality of blocks; A voltage regulator configured to provide a supply voltage to each of the plurality of blocks; A power gating control circuit configured to control the power gating of the supply voltage to each of the plurality of blocks; A power mode controller configured to select a power mode for the integrated circuit, wherein in response to selecting a retention mode, the power gating control circuit prevents the supply voltage from powering each block in a selected subset of the plurality of blocks and allows the supply voltage to power each block in the remaining subset of the plurality of blocks external to the selected subset; And A voltage controller circuit configured to indicate to the voltage regulator a retention voltage level to provide the retention voltage level as the supply voltage during the retention mode, wherein the voltage controller is configured to determine the retention voltage level based on the minimum retention voltage level required by each block in the remaining subset.

9. A method for retention voltage in a volatile memory, characterized in that, Comprising: Entering a data retention mode of a volatile memory, wherein the volatile memory is divided into a plurality of blocks; In response to entering the data retention mode, selecting a retention subset of the plurality of blocks, wherein in the data retention mode, each block in the retention subset is powered by a retention voltage, and in the data retention mode, each block in the plurality of blocks not in the retention subset is powered off; Determining a voltage level of the retention voltage provided to each block in the retention subset during the retention mode based on the minimum retention voltage required by each block in the retention subset, and indicating the voltage level of the retention voltage to a voltage regulator; And Providing a corresponding supply voltage to each block in the plurality of blocks by a voltage regulator.

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