Testing system including storage devices

Abstract

This invention relates to a test system including a storage device. The technology includes a test system comprising: a storage device configured to store initial setting values ​​for performing normal operation; and a test device configured to generate a set of operation commands including test values ​​as results of test operations performed by the storage device, and configured to send the set of operation commands to the storage device. The storage device performs an operation based on the set of operation commands by using the test values, replaces the initial setting values ​​with the operation values ​​generated as a result of the operation, and stores the operation values.

Description

Technical Field

[0001] This disclosure relates to a test system including storage devices, and more specifically to a test system including storage devices, all of which include operating components. Background Technology

[0002] The storage device may include an array of storage cells in which data is stored, peripheral circuitry configured to program, read or erase the storage cells included in the array of storage cells, and control circuitry capable of controlling the peripheral circuitry based on commands.

[0003] During the manufacturing process of the storage device, various initial settings for performing programming, reading, and erasing operations are stored in the storage device. For example, the initial settings may be default values ​​for the initial programming voltage, step voltage, and pass voltage.

[0004] After the storage device is manufactured, testing can be performed on it, and the test results can be reflected in the initial settings stored in the storage device. A testing device can be used for this purpose.

[0005] In order to reflect the test result value in the initial setting value, the test device can perform a read operation to obtain the initial setting value from the storage device, an operation to operate the initial setting value and the test result value, and a storage operation to store the operation-required setting value in the storage device.

[0006] However, when there are multiple storage devices that need to reflect the test values, the operation time for reflecting the test values ​​will increase because the above operations need to be performed on each storage device. Summary of the Invention

[0007] A testing system according to one embodiment of the present disclosure includes: a storage device configured to store initial settings for performing normal operation; and a testing device configured to generate a set of operation commands including test values ​​as the result of test operations performed by the storage device, and configured to send the set of operation commands to the storage device, wherein the storage device performs an operation based on the set of operation commands by using the test values, replaces the initial settings with operation values ​​generated as the result of the operation, and stores the operation values.

[0008] A test system according to another embodiment of this disclosure includes: a command generator configured to output operation commands based on different operation enable signals; an address selector configured to output the address of a register in which an initial setting value to be changed is stored; a merging circuit configured to output a set of operation commands including the operation commands, the address, and the test value when a test value is received; and a storage device configured to generate an operation value by performing an operation based on the set of operation commands, and configured to replace the initial setting value stored in the register with the operation value. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating a test system according to one embodiment of the present disclosure.

[0010] Figure 2 This is a diagram illustrating a test apparatus according to one embodiment of the present disclosure.

[0011] Figure 3 This is a diagram illustrating a command generator according to one embodiment of the present disclosure.

[0012] Figure 4 This is a diagram illustrating an address selector according to one embodiment of the present disclosure.

[0013] Figure 5 This is a diagram illustrating a storage device according to one embodiment of the present disclosure.

[0014] Figure 6 This is a diagram specifically illustrating a control circuit according to one embodiment of the present disclosure.

[0015] Figure 7 This is a diagram illustrating an operational method of control logic according to an embodiment of the present disclosure.

[0016] Figure 8 This is a diagram illustrating a register group according to one embodiment of the present disclosure.

[0017] Figure 9 This is a diagram illustrating a method of operating on values ​​stored in a register according to one embodiment of the present disclosure.

[0018] Figure 10 This is a diagram illustrating a register group according to another embodiment of the present disclosure.

[0019] Figure 11 This is a diagram illustrating a method of operating on values ​​stored in a register according to another embodiment of the present disclosure.

[0020] Figure 12This is a diagram illustrating a storage system based on conventional methods.

[0021] Figure 13 and Figure 14 This is a diagram illustrating the operation method of a test system according to one embodiment of the present disclosure.

[0022] Figure 15 This is a diagram illustrating the method of reflecting test result values ​​on dies manufactured in different wafers.

[0023] Figure 16 This is a diagram illustrating a method for reflecting the same test result value on different packaged chips.

[0024] Figure 17 This is a diagram illustrating the methods for reflecting different test result values ​​on different packaged chips. Detailed Implementation

[0025] Various embodiments of this disclosure will be described below with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0026] It should be understood that although the terms "first," "second," "third," etc., are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, a first element in some embodiments may be referred to as a second element in other embodiments.

[0027] Furthermore, it should be understood that when a component is referred to as "connected" or "linked" to another component, it can be directly connected or linked to the other component, or there may be intermediate components. Conversely, when a component is referred to as "directly connected" or "directly linked" to another component, there are no intermediate components.

[0028] One embodiment of this disclosure provides a testing system that can quickly manipulate test result values ​​and initial setting values, and quickly store the operation values ​​generated by the operation in a storage device.

[0029] According to this technology, multiple storage devices operate on test values ​​and initial setting values ​​according to a set of operation commands output from a test device, and independently store the operation values ​​generated by the operation. Therefore, the time required to change the initial setting values ​​stored in multiple storage devices can be shortened.

[0030] Figure 1 This is a diagram illustrating a test system according to one embodiment of the present disclosure.

[0031] Reference Figure 1The test system 1000 may include multiple storage devices MD1 to MDn (n is a positive integer) and a test device 2000. Although Figure 1 Multiple storage devices MD1 to MDn are shown, but one storage device can be connected to the test device 2000.

[0032] Storage devices MD1 to MDn can be devices capable of storing data, and can be composed of non-volatile or volatile storage devices. Non-volatile storage devices can be devices that retain stored data even when the power is cut off, while volatile storage devices can be devices whose stored data will be corrupted when the power is cut off.

[0033] The test device 2000 can output an operation command set OP_CMDs based on the first operation enable signal 1OP_EN to the m-th operation enable signal mOP_EN (m is a positive integer), the set value type information S_INFO, and the test value T_VAL. The test device 2000 may not operate on the test value T_VAL, but may output the operation command set OP_CMDs containing the test value T_VAL.

[0034] Storage devices MD1 to MDn can simultaneously execute operations on the initial setting value and the test value T_VAL based on the operation command set OP_CMDs, and then simultaneously store the operation value. The initial setting values ​​stored in different storage devices MD1 to MDn can be different from each other or they can be the same as each other. On the other hand, some initial setting values ​​can be the same as each other, while the remaining values ​​can be different from each other.

[0035] Since the test apparatus 2000 according to this embodiment can perform operations without independence, while the storage devices MD1 to MDn can perform operations independently, the time required for the operation of reflecting the test value T_VAL on the storage devices MD1 to MDn can be shortened.

[0036] Figure 2 This is a diagram illustrating a test apparatus according to one embodiment of the present disclosure.

[0037] Reference Figure 2 The test apparatus 2000 may include a command generator 2100, an address selector 2200, and a merging circuit 2300.

[0038] Command generator 2100 can output an operation command OP_CMD corresponding to the selected operation based on the first operation enable signal 1OP_EN to the m-th operation enable signal mOP_EN. The corresponding first operation enable signals 1OP_EN to the m-th operation enable signal mOP_EN can be signals corresponding to different operations. Here, the operation can be a logical operation, such as AND, OR, or XOR operations. For example, the first operation enable signal 1OP_EN can be a signal corresponding to an AND logical operation, and the second operation enable signal 2OP_EN can be a signal corresponding to an OR logical operation. Optionally, the operation can be an arithmetic operation, such as an addition operation, a subtraction operation, a multiplication operation, or a division operation. Command generator 2100 can output an operation command OP_CMD corresponding to the selected logical operation based on the input first operation enable signals 1OP_EN to the m-th operation enable signal mOP_EN. The first operation enable signals 1OP_EN to the m-th operation enable signal mOP_EN can be signals that select different logical operations, and can be determined based on the result of a test operation. For example, when it is necessary to perform an AND operation on the initial setpoint and the test value T_VAL based on the test operation results of the first storage device MD1 to the nth storage device MDn, the first operation enable signal 1OP_EN can be activated, and all the remaining second operation enable signals 2OP_EN to the mth operation enable signal MOP_EN can be deactivated. The command generator 2100 can output the operation command OP_CMD corresponding to the activation signal among the first operation enable signals 1OP_EN to the mth operation enable signal mOP_EN.

[0039] Address selector 2200 can output address ADD based on setpoint type information S_INFO. Setpoint type information S_INFO can be the type of target value to be changed selected based on test results. For example, the type of target value to be changed may include start programming voltage, step voltage, through voltage, read voltage, erase voltage, etc. Therefore, setpoint type information S_INFO can be information about any one of the start programming voltage, step voltage, through voltage, read voltage, and erase voltage. Furthermore, setpoint type information S_INFO can be information about any of the various values ​​required for various operations of the storage device.

[0040] Address selector 2200 can store addresses corresponding to various setting values ​​and can output address ADD corresponding to the input setting value type information S_INFO. Here, address ADD can be the address of a register in the storage device that stores the initial setting value.

[0041] When the test value T_VAL is input, the merging circuit 2300 can merge the operation command OP_CMD, the address ADD, and the test value T_VAL into a single operation command set OP_CMDs, and can output the operation command set OP_CMDs. Here, the test value T_VAL can be a value calculated based on the result of a test operation on the storage device, or it can be a value used to change the initial setting value stored in the storage device. When the operation command OP_CMD, the address ADD, and the test value T_VAL are input, the merging circuit 2300 can merge the input operation command OP_CMD, the address ADD, and the test value T_VAL into a single operation command set OP_CMDs, and can output the operation command set OP_CMDs. For example, the operation command OP_CMD, the address ADD, and the test value T_VAL included in the operation command set OP_CMDs can be sequentially output through the output lines of the merging circuit 2300.

[0042] Figure 3 This is a diagram illustrating a command generator according to one embodiment of the present disclosure.

[0043] Reference Figure 3 The command generator 2100 may include an operation selector 3100 and an operation command register 3200.

[0044] Operation selector 3100 can output a selected enable signal SL_EN based on a first operation enable signal 1OP_EN to an m-th operation enable signal mOP_EN. For example, operation selector 3100 can be configured as a multiplexer. When the first operation enable signal 1OP_EN to an m-th operation enable signal mOP_EN is input, operation selector 3100 can output the activation signal in the input signal as the selected enable signal SL_EN. Optionally, operation selector 3100 can be configured to output an enable signal SL_EN selected based on a combination of the input first operation enable signals 1OP_EN to m-th operation enable signals mOP_EN.

[0045] The operation command register 3200 may include a table containing various operation commands #_CMD corresponding to the selected enable signal SL_EN#. When the selected enable signal SL_EN is input, the operation command register 3200 can output the operation command #_CMD from the table corresponding to the selected enable signal SL_EN input in the selected enable signal#. For example, when the selected enable signal SL_EN corresponding to the AND operation is received, the operation command register 3200 can output the AND operation command AND_CMD corresponding to the AND operation from the table as the operation command OP_CMD. As another example, when the selected enable signal SL_EN corresponding to the XOR operation is received, the operation command register 3200 can output the XOR operation command XOR_CMD corresponding to the XOR operation from the table as the operation command OP_CMD.

[0046] Figure 4 This is a diagram illustrating an address selector according to one embodiment of the present disclosure.

[0047] Reference Figure 4 The address selector 2200 may include a table of address ADDs corresponding to various setpoint type information S_INFO. The setpoint type information S_INFO may be information about the initial setpoints stored in the storage device. For example, the setpoint type information S_INFO may include the start programming voltage start Vpgm, step voltage Vstep, pass voltage Vpass, read voltage Vread, and erase voltage Verase, etc. Different address ADDs can be assigned to the corresponding setpoint type information S_INFO. For example, the first address AD01 can be assigned to the start programming voltage start Vpgm, and the second address AD02 can be assigned to the step voltage Vstep. When a setpoint type information S_INFO is received, the address selector 2200 can output the address ADD assigned to the received setpoint type information S_INFO. For example, when a setpoint type information S_INFO corresponding to the start programming voltage start Vpgm is received, the address selector 2200 can output the first address AD01 assigned to the start programming voltage start Vpgm.

[0048] Figure 5 This is a diagram illustrating a storage device according to one embodiment of the present disclosure.

[0049] Reference Figure 5 ,because Figure 1 The first storage device MD1 to the nth storage device MDn shown can be configured identically to each other, so in Figure 5 The nth storage device MDn is shown as one implementation.

[0050] The nth storage device MDn may include a storage cell array 100, a voltage generator 200, a read / write circuit 300, an input / output circuit 400, and a control circuit 500.

[0051] The storage cell array 100 may include multiple storage blocks, and each of the multiple storage blocks may include multiple storage cells.

[0052] Voltage generator 200 can output various operating voltages Vop based on voltage code VOLCD. For example, voltage generator 200 can generate programming voltage, pass voltage, read voltage, or erase voltage based on voltage code VOLCD, and can output the generated voltage as operating voltage Vop.

[0053] The read / write circuit 300 can store data input from an external device via the data line DL, and can sense the data in the memory cell via the bit line BL based on the control signal CONSIG.

[0054] The input / output circuit 400 can be connected to an external device via input / output lines I / O, and can receive operation command sets OP_CMDs from the external device via input / output lines I / O. Here, the external device can be... Figure 1 The test apparatus 2000. The operation command set OP_CMDs may include the operation command OP_CMD, the address ADD, and the test value T_VAL. When the operation command set OP_CMDs is received, the input / output circuit 400 may send the operation command OP_CMD, the address ADD, and the test value T_VAL included in the operation command set OP_CMDs to the control circuit 500.

[0055] The control circuit 500 can output a voltage code VOLCD and a control signal CONSIG based on a command output from the input / output circuit 400. However, when receiving the operation command OP_CMD, the control circuit 500 may not output the voltage code VOLCD and the control signal CONSIG, and can store the set value by performing internal operations. For this purpose, the control circuit 500 may include control logic 510, an operation component 520, and a register group 530.

[0056] Control logic 510 can select logical operation logic based on the operation command OP_CMD. Operation component 520 can receive address ADD and test value T_VAL, and can execute operations based on the selected logical operation logic. Register group 530 can store initial settings and operation values ​​generated by operation component 520.

[0057] The control circuit 500 can perform programming, reading, or erasing operations using the operation values ​​stored in the register set 530. The control circuit 500 is described in more detail below.

[0058] Figure 6 This is a diagram specifically illustrating a control circuit according to one embodiment of the present disclosure.

[0059] Reference Figure 6 The control circuit 500 may include control logic 510, operation component 520 and register group 530.

[0060] Control logic 510 can output operation code OPCD based on operation command OP_CMD. Operation code OPCD can be a code with multiple bits, and the code corresponding to the input operation command OP_CMD can be output as operation code OPCD. For example, when operation command OP_CMD is a command corresponding to an AND operation, control logic 510 can output operation code OPCD for performing the AND operation.

[0061] Operation component 520 can select an operation algorithm based on operation code OPCD, and can execute the operation using address ADD and test value T_VAL based on the selected operation algorithm. For example, when operation code OPCD, address ADD, and test value T_VAL are input, operation component 520 can receive the initial setting value INT_VAL corresponding to address ADD from register group 530, operate on the initial setting value INT_VAL and test value T_VAL based on the selected algorithm, and generate operation value OP_VAL. Operation component 520 can output the operation value OP_VAL generated by the operation to register group 530.

[0062] Register set 530 may include multiple registers storing initial setting values ​​INT_VALs. Different addresses can be assigned to multiple registers separately. Therefore, register set 530 can output the initial setting value INT_VAL corresponding to the address ADD requested by operation component 520, and can store the operation value OP_VAL output from operation component 520 in the register corresponding to address ADD. That is, when the operation value OP_VAL is input, register set 530 can replace the initial setting value INT_VAL with the operation value OP_VAL, and can store the operation value OP_VAL. The operation value OP_VAL stored in register set 530 can be used as various setting values ​​during normal operation after a test operation of the storage device.

[0063] Figure 7 This is a diagram illustrating an operational method of control logic according to an embodiment of the present disclosure.

[0064] Reference Figure 7 When the operation command OP_CMD is entered, Figure 6The control logic 510 can determine the operation corresponding to the input operation command OP_CMD (step S51). When it is determined that the input operation command OP_CMD is a command for the first operation OP1, the control logic 510 can select the operation corresponding to the first operation OP1 (step S52). When it is determined that the input operation command OP_CMD is a command for the second operation OP2, the control logic 510 can select the operation corresponding to the second operation OP2 (step S53). When it is determined that the input operation command OP_CMD is a command for the third operation OP3, the control logic 510 can select the operation corresponding to the third operation OP3 (step S54).

[0065] Subsequently, control logic 510 can output the operation code OPCD (S55) corresponding to the selected operation. Figure 7 In the text, only the first operation OP1 to the third operation OP3 are disclosed, but due to... Figure 7 The flowchart shown is a diagram to help understand this embodiment and may include more operations. The operation code OPCD may include multiple bits and may include different codes based on the selected operation.

[0066] Figure 8 This is a diagram specifically illustrating a register set according to one embodiment of the present disclosure, and Figure 9 This is a diagram illustrating a method of operating on values ​​stored in a register according to one embodiment of the present disclosure.

[0067] Reference Figure 8Register group 530 may include a register REG# in which an initial setting value INT_VAL# is stored. For example, register REG# may include multiple registers REG01, REG02, ... Different addresses AD01, AD02, ... may be assigned to multiple registers REG01, REG02, ... For example, a first address AD01 may be assigned to a first register REG01 and may store the first initial setting value INT_VAL_01 for any of the multiple setting values ​​used for programming PGM operations. In such a method, the first initial setting values ​​INT_VAL_01 to the third initial setting value INT_VAL_03 associated with programming PGM operations may be stored in the first register REG01 to the third register REG03, respectively, and the fourth initial setting values ​​INT_VAL_04 to the sixth initial setting values ​​INT_VAL_06 associated with read operations may be stored in the fourth register REG04 to the sixth register REG06, respectively. The seventh register REG07 may store the seventh initial setting value INT_VAL_07 corresponding to mask data that can be used as a variable in the operation. Each of the first registers REG01 through the seventh register REG07 can have a capacity to store multiple bits. For example, when each of the first registers REG01 through the seventh register REG07 has a capacity of 10 bits, the 10-bit first initial setting value INT_VAL_01 can be stored in the first register REF01, or some of the 10 bits can be stored as the first initial setting value INT_VAL_01 for valid data VD. The seventh initial setting value INT_VAL_07, which can be used as mask data, can be set based on the valid data VD stored in other registers. For example, when the valid data VD stored in the first registers REG01 through the sixth register REG06 is 6 bits, the seventh initial setting value INT_VAL_07 can also include a valid value of 1 corresponding to the bit storing the valid data VD. In this case, the invalid value corresponding to the remaining bits can be 0.

[0068] Reference Figure 9 When inputting Figure 6 Operation component 520 Figure 6 When the address ADD is the address allocated to the first register REG01, the operation component 520 can... Figure 8Register group 530 receives the first initial setting value INT_VAL_01 stored in the first register REG01, and can perform operations based on the first initial setting value INT_VAL_01 and the test value T_VAL. For example, assuming the address corresponding to the test value T_VAL is the seventh address AD07, operation component 520 can generate the operation value OP_VAL by performing operations on the first initial setting value INT_VAL_01 and the seventh initial setting value IVT_VAL_07 stored in the first register REG01 and the seventh register REG07. The operation performed by operation component 520 can be a logical operation (AND, OR, XOR, ...) based on the operation code OPCD. For example, when the operation code OPCD is a code that performs an AND operation, operation component 520 can generate the operation value OP_VAL by performing an AND operation on the first initial setting value INT_VAL_01 and the seventh initial setting value IVT_VAL_07. As another example, when the operation code OPCD is the code that performs an OR operation, the operation component 520 can generate the operation value OP_VAL by performing an OR operation on the first initial setting value INT_VAL_01 and the seventh initial setting value IVT_VAL_07. Optionally, the operation component 520 can perform operations such as addition, subtraction, division, or multiplication using multiple arithmetic operations. When the operation value is generated, the operation component 520 can send the operation value OP_VAL to the register group 530. The register group 530 can store the operation value OP_VAL output from the operation component 520 in the first register REG01. That is, the first initial setting value INT_VAL_01 stored in the first register REG01 can be changed to the operation value OP_VAL. Therefore, the operation value OP_VAL stored in the first register REG01 can be used in normal operations performed after the test operation is completed.

[0069] Figure 10 This is a diagram specifically illustrating a register set according to another embodiment of the present disclosure, and Figure 11 This is a diagram illustrating a method of operating on values ​​stored in a register according to another embodiment of the present disclosure.

[0070] Reference Figure 10Register group 530 can store multiple initial setting values ​​corresponding to the same type. For example, suppose the first initial setting value INT_VAL_01 to the sixth initial setting value INT_VAL_06, which can be used as the starting programming voltage start Vpgm, are stored in the first register REG01 to the sixth register REG06 of register group 530, respectively. The first initial setting value INT_VAL_01 to the sixth initial setting value INT_VAL_06 can be selected based on the operating conditions of the storage device. The seventh initial setting value INT_VAL_07, corresponding to the mask data, can be stored in the seventh register REG07, and the eighth initial setting value INT_VAL_08 to the twelfth initial setting value INT_VAL_12, which are used as the voltage Vpass, can be stored in the eighth register REG08 to the twelfth register REG12, respectively. Besides... Figure 10 In addition to the voltages shown, voltages that can be used for operations such as programming, reading, or erasing can be stored in different registers for each level.

[0071] Reference Figure 11 Some initial settings stored in registers may become invalid data through operations. For example, when input to... Figure 6 Operation component 520 Figure 6 When the address ADD provides an address allocated to the first register REG01 and the second register REG02, the operation component 520 can receive the first initial setting value INT_VAL_01 and the second initial setting value INT_VAL_02 stored in the first register REG01 and the second register REG02, and can perform an operation based on the first initial setting value INT_VAL_01, the second initial setting value INT_VAL_02, and the test value T_VAL. For example, the seventh initial setting value INT_VAL_07 can be set to invalid data, and the operation value generated by performing the selected operation using the seventh initial setting value INT_VAL_07 can be set to invalid data.

[0072] In other words, when the test operation result based on the storage device invalidates a voltage that is not used in the initial programming voltage start Vpgm, the operation component 520 can invalidate the initial setting value stored in the selected register by performing an operation using address ADD and test value T_VAL. Optionally, the operation component 520 can increase or decrease all voltages of the selected type by performing an operation, and can increase or decrease some voltages of the selected type. The operation value or invalid data generated by the operation component 520 can be stored in each register of the register group 530.

[0073] Figure 12This is a diagram illustrating a storage system based on conventional methods.

[0074] Reference Figure 12 In the test system 1000_P based on the conventional method, the operation component 520, which can operate the initial setting value based on the test operation results of the first die DI1 to the nth die DIn (n is a positive integer), can be included only in the test apparatus 3000. That is, since the operation component 520, which can operate the initial setting value and store the operation value, is not included in the first die DI1 to the nth die DIn, each of a plurality of read operations and data transfer operations (①, ②, ③, ④, ...) can be performed in order to store the test value in the first die DI1 to the nth die DIn. Here, the die can be... Figure 1 The storage device is shown. For example, when an operation to change the initial setting value stored in each of the first die DI1 to the nth die DIn is initiated, the test device 3000 can read the initial setting value from the first die DI1 (①). The test device 3000 can operate the read initial setting value using the operation component 520 and send the operation value generated by the operation to the first die DI1 (②). When the operation value is stored in the first die DI1, the test device 3000 can read the initial setting value from the second die DI2 (③) and can send the operation value to the second die DI2 (④). In this method, when the test device 3000 performs the operation to change the initial setting value of each of the first die DI1 to the nth die DIn, the time required to complete both the reading operation and the operation value transmission operation for each die may increase. Furthermore, as the number of dies increases, the time required to reflect the operation value on the die may increase.

[0075] Conversely, when the above-described embodiments of this disclosure are applied, the operation time of the testing system can be shortened.

[0076] Figure 13 and Figure 14 This is a diagram illustrating the operation method of a test system according to one embodiment of the present disclosure.

[0077] Reference Figure 13In the test system 1000 according to this embodiment, since each of the first die DI1 to the nth die DIn includes an operation component 520, the read operation and operation value transmission operation can be omitted, thus shortening the operation time of the test system. For example, when the test device 2000 outputs an operation command set OP_CMDs, the operation command set OP_CMDs can be simultaneously sent to the first die DI1 to the nth die DIn (①). Subsequently, each of the first die DI1 to the nth die DIn can perform an operation based on the operation command set OP_CMDs using the operation component 520, and the operation value generated by the operation can be stored (②). Therefore, according to this embodiment, since the initial setting values ​​stored in each of the first die DI1 to the nth die DIn are operated simultaneously within the first die DI1 to the nth die DIn, and the operation values ​​are stored simultaneously, the operation time of the test system 1000 can be shortened.

[0078] Furthermore, even if the initial settings stored in the first die DI1 to the nth die DIn are of the same type, different values ​​can be set based on the die. In this case, even if the initial settings stored in different dies are constantly changing, each die can simultaneously change its initial settings based on the operation command set OP_CMDs.

[0079] Reference Figure 14 The starting programming voltage start Vpgm, corresponding to the first level LEV01 to the sixth level LEV06, can be stored as an initial setting value in the first register REG01 to the sixth register REG06 of the first die DI1. Conversely, the starting programming voltage start Vpgm, corresponding to the third level LEV03 to the eighth level LEV08, can be stored as an initial setting value in the first register REG01 to the sixth register REG06 of the second die DI2. As described above, when the initial setting values ​​stored in the first die DI1 and the second die DI2 are different from each other, the first die DI1 and the second die DI2 can simultaneously receive the operation command set OP_CMDs and can execute operations. By executing operations based on the address and test value included in the operation command set OP_CMDs, the initial setting value can be changed from the value stored in the first register REG01 to the value stored in the third register REG03. In other words, the third level LEV03 stored in the third register REG03 in the first die DI1 can be set as the start programming voltage start Vpgm, and the fifth level LEV05 stored in the third register REG03 in the second die DI2 can be set as the start programming voltage start Vpgm.

[0080] Figure 15This is a diagram illustrating the method of reflecting test result values ​​on dies manufactured in different wafers.

[0081] Reference Figure 15 When the initial settings of dies DI1 to DIn manufactured in different wafers 151, 152, and 153 change, the test apparatus 2000 can send different sets of operation commands to dies DI1 to DIn for each wafer. In other words, when the test results of the three different wafers 151, 152, and 153 are different, the test apparatus 2000 can output different sets of operation commands to simultaneously change the initial settings of the dies manufactured in each wafer for each wafer.

[0082] For example, when the test results of dies DI1 to DIn manufactured in each of the first wafers 151 to the third wafers 153 are different from each other, the test apparatus 2000 can send a first operation command set 1OP_CMDs to dies DI1 to DIn manufactured in the first wafer 151, send a second operation command set 2OP_CMDs to dies DI1 to DIn manufactured in the second wafer 152, and send a third operation command set 3OP_CMDs to dies DI1 to DIn manufactured in the third wafer 153.

[0083] Each of the first set of operation commands 1 OP_CMDs to the third set of operation commands 3 OP_CMDs may include an operation command OP_CMD, an address ADD, and a test value T_VAL. At least one or more of the operation command OP_CMD, address ADD, and test value T_VAL included in different operation command sets may have different values. For example, the test apparatus 2000 can output a first set of operation commands 1OP_CMDs having a first operation command 1OP_CMD, a first address 1ADD, and a first test value 1T_VAL to increase the initial setting value of the starting programming voltage of the dies DI1 to DIn included in the first wafer 151 by 2V; it can output a second set of operation commands 2OP_CMDs having a second operation command 2OP_CMD, a second address 2ADD, and a second test value 2T_VAL to decrease the initial setting value of the through voltage of the dies DI1 to DIn included in the second wafer 152 by 0.5V; and it can output a third set of operation commands 3OP_CMDs having a third operation command 3OP_CMD, a third address 3ADD, and a third test value 3T_VAL to decrease the initial setting value of the time for applying the programming voltage to the word line of the dies DI1 to DIn included in the third wafer 153 by 0.5ms.

[0084] Figure 15The first operation command set 1OP_CMDs to the third operation command set 3OP_CMDs shown help to understand the implementation of this disclosure. Therefore, the first operation command set 1OP_CMDs to the third operation command set 3OP_CMDs can be used in various ways in test operations that change various initial settings.

[0085] Figure 16 This is a diagram illustrating a method for reflecting the same test result value on different packaged chips.

[0086] Reference Figure 16 The test apparatus 2000 can send operation command sets OP_CMDs to multiple packages PC1 to PCk, each including multiple dies DI1 to DIn, to change the initial settings of the multiple dies DI1 to DIn included in each of the multiple packages PC1 to PCk. For example, when multiple dies DI1 to DIn are included in the first package PC1 and also in the kth package PCk, the test apparatus 2000 can selectively send operation command sets OP_CMDs only to the first package PC1 and the kth package PCk based on the result of the test operation, and can selectively change the initial settings stored in the multiple dies DI1 to DIn included in the first package PC1 and the kth package PCk. In this case, the initial settings of the multiple dies DI1 to DIn included in the unselected second package PC2 to (k-1)th package PCk-1 can be retained.

[0087] Figure 17 This is a diagram illustrating the methods for reflecting different test result values ​​on different packaged chips.

[0088] Reference Figure 17 The test apparatus 2000 can apply different test values ​​to different packages PC1 to PC4 based on the test results. In other words, when the test results for different packages PC1 to PC4 are different for each package, the test apparatus 2000 can send different sets of operation commands for each package.

[0089] For example, as a test result for packages PC1 to PC4, the type of voltage and the change in the initial setting value may vary depending on the package. In this case, the test apparatus 2000 may send different sets of operation commands 1OP_CMDs to 4OP_CMDs to each of packages PC1 to PC4.

[0090] As described above, according to this embodiment, multiple storage devices can operate on test values ​​and initial setting values ​​based on the set of operation commands output from the test device 2000, and independently store the operation values ​​generated by the operation. Therefore, the time required to change the initial setting values ​​stored in the multiple storage devices can be shortened.

[0091] Cross-reference to related applications

[0092] This application claims priority to Korean Patent Application 10-2020-0110537, filed with the Korean Intellectual Property Office on August 31, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A testing system, the testing system comprising: A storage device configured to store initial settings for performing normal operation; as well as A testing apparatus configured to generate a set of operation commands including test values ​​calculated based on the results of test operations performed on the storage device, and configured to send the set of operation commands to the storage device. The storage device generates an operation value by calculating the initial setting value and the test value based on the operation command set, replaces the initial setting value with the operation value, and stores the operation value.

2. The testing system according to claim 1, wherein, The testing apparatus includes: A command generator configured to output an operation command based on the result of the test operation; An address selector, configured to store within itself an address a setting value type information corresponding to the initial setting value; and A merging circuit configured to output the set of operation commands by merging the operation commands, the address, and the test value.

3. The testing system according to claim 2, wherein, The command generator includes: An operation selector, configured to receive a plurality of operation enable signals and configured to output an enable signal selected from the plurality of operation enable signals; and An operation command register is configured to store within itself operation commands corresponding to a plurality of selected enable signals in a table.

4. The testing system according to claim 3, wherein, The operation command register outputs the operation command to execute the logic operation corresponding to the selected enable signal.

5. The testing system according to claim 2, wherein, The setpoint type information includes the initial programming voltage, step voltage, pass voltage, read voltage, and erase voltage.

6. The testing system according to claim 1, wherein, The storage device is configured to perform logical operations including AND, OR, or XOR operations, or to perform arithmetic operations including addition, subtraction, multiplication, or division operations.

7. The testing system according to claim 1, wherein, The storage device includes: A storage cell array configured to store data; A voltage generator configured to output an operating voltage via word lines connected to a plurality of memory cells included in the memory cell array; A read / write circuit configured to sense data in the memory cell via a bit line connected to the memory cell; Input / output circuitry, configured to receive the set of operation commands; and A control circuit configured to perform the operation, configured to replace the initial set value with the operation value, and configured to store the operation value.

8. The testing system according to claim 7, wherein, The control circuit includes: A register group, configured to store a plurality of initial setting values ​​including the initial setting value; Control logic, configured to output operation codes based on operation commands included in the operation command set; and An operation component is configured to output an operation value based on the operation code by operating the initial setting value corresponding to the address included in the operation command set and the test value included in the operation command set.

9. The testing system according to claim 8, wherein, The register group includes multiple registers, each with an address and storing different initial settings.

10. The testing system according to claim 9, wherein, The register group sends the initial setting value stored in the register corresponding to the address to the operation component, and when the operation value is received from the operation component, it stores the operation value in the register corresponding to the address.

11. The testing system according to claim 1, wherein, The storage device is configured to perform normal operation based on the operation value.

12. A testing system, the testing system comprising: A command generator configured to output operation commands based on different operation enable signals; An address selector configured to output the address of a register in which an initial setpoint to be changed is stored; A merging circuit, configured to output a set of operation commands including the operation command, the address, and the test value when a test value is received; as well as A storage device configured to generate an operation value by calculating the initial setting value and the test value based on the operation command in the operation command set, and configured to replace the initial setting value stored in the register with the operation value.

13. The testing system according to claim 12, wherein, The command generator includes: An operation selector, configured to receive the operation enable signal and configured to output an enable signal selected from the operation enable signal; and A command register, configured to store a table containing operation commands corresponding to the selected enable signal, and configured to output the operation commands corresponding to the selected enable signal.

14. The testing system according to claim 12, wherein, The address selector includes a table that stores setting value type information about the type of the initial setting value and addresses respectively assigned to the setting value type information.

15. The testing system according to claim 14, wherein, The setpoint type information includes information about the starting programming voltage, step voltage, and pass voltage used for programming operations, information about the read voltage used for read operations, and information about the erase voltage used for erase operations.

16. The testing system according to claim 12, wherein, The storage device includes: A register group, configured to store a plurality of initial setting values ​​including the initial setting value; Control logic, configured to output operation code to execute a selected operation based on the operation commands included in the operation command set; and An operation component is configured to operate on the initial setting value corresponding to the address included in the operation command set and the test value included in the operation command set based on the operation code, and is configured to output the operation value as the result of the operation.

17. The testing system according to claim 16, wherein, The register group includes multiple registers, each with an address and storing different initial settings.

18. The testing system according to claim 17, wherein, The register group sends the initial setting value stored in the register corresponding to the address among the plurality of registers to the operation component, and when the operation value is received from the operation component, the operation value is stored in the register corresponding to the address.

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