Semiconductor memory device

Abstract

The semiconductor storage device of the present application includes: a plurality of first conductive layers; a plurality of second conductive layers; a first semiconductor layer disposed between the conductive layers; a charge storage layer including a first portion disposed between the plurality of first conductive layers and the first semiconductor layer, and a second portion disposed between the plurality of second conductive layers and the first semiconductor layer; and a first wiring electrically connected to the first semiconductor layer. The semiconductor storage device is configured to be capable of performing a readout operation and a first operation. In the readout operation, a readout voltage is supplied to an nth (n is an integer of 1 or more) first conductive layer counted from one side in a first direction, and a readout path voltage is supplied to at least a portion of the plurality of first conductive layers. In the first operation, a first voltage is supplied to the first wiring, and a second voltage smaller than the first voltage is supplied to an nth second conductive layer counted from one side in the first direction.

Description

[0001] Citation of relevant applications

[0002] This application asserts priority based on the priority of a prior Japanese patent application No. 2021-049289 filed on March 23, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described below relate to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device is known to include: a substrate; a plurality of first conductive layers arranged along a first direction intersecting the surface of the substrate; a plurality of second conductive layers disposed at intervals from the plurality of first conductive layers in a second direction intersecting the first direction and arranged along the first direction; a first semiconductor layer disposed between the plurality of first conductive layers and the plurality of second conductive layers, extending along the first direction and facing the plurality of first conductive layers and the plurality of second conductive layers; and a charge storage layer having a first portion disposed between the plurality of first conductive layers and the first semiconductor layer, and a second portion disposed between the plurality of second conductive layers and the first semiconductor layer. Summary of the Invention

[0005] The present invention provides a semiconductor memory device that can operate appropriately.

[0006] A semiconductor memory device according to one embodiment includes: a plurality of first conductive layers; a plurality of second conductive layers; a first semiconductor layer disposed between the plurality of first conductive layers and the plurality of second conductive layers; a charge storage layer having a first portion disposed between the plurality of first conductive layers and the first semiconductor layer, and a second portion disposed between the plurality of second conductive layers and the first semiconductor layer; and a first wiring electrically connected to the first semiconductor layer. The plurality of first conductive layers are arranged along a first direction. The plurality of second conductive layers are spaced apart from the plurality of first conductive layers in a second direction intersecting the first direction and are arranged along the first direction. The first semiconductor layer extends in the first direction and faces the plurality of first conductive layers and the plurality of second conductive layers. The semiconductor memory device is configured to perform a readout operation and a first operation performed before the readout operation. During the readout operation, a readout voltage is supplied to the nth (n is an integer greater than or equal to 1) first conductive layer counting from one side of the first direction among the plurality of first conductive layers, and a readout path voltage greater than the readout voltage is supplied to at least a portion of the plurality of first conductive layers. In the first operation, a first voltage is supplied to the first wiring, and a second voltage less than the first voltage is supplied to the nth second conductive layer, counting from one side in the first direction.

[0007] Based on the aforementioned configuration, a semiconductor memory device that operates appropriately can be provided. Attached Figure Description

[0008] Figure 1 This is a schematic block diagram showing the configuration of the storage system 10 in the first embodiment.

[0009] Figure 2 This is a schematic side view showing an example of the configuration of the storage system 10.

[0010] Figure 3 This is a schematic top view illustrating the aforementioned configuration example.

[0011] Figure 4 This is a schematic block diagram representing the structure of a memory die (MD).

[0012] Figure 5 This is a schematic equivalent circuit diagram representing a portion of the memory die MD.

[0013] Figure 6 This is a schematic top view representing a portion of the memory die MD.

[0014] Figure 7 It is Figure 6 The diagram shows a schematic top view of the enlarged portions A and A′ of the structure shown.

[0015] Figure 8 It is Figure 6 The diagram shows a schematic top view of the enlarged portions A and A′ of the structure shown.

[0016] Figure 9 This is a schematic 3D diagram representing a portion of the memory die MD.

[0017] Figure 10 It is Figure 7 and Figure 8 The diagram shows a schematic top view of part B, which is an enlarged representation.

[0018] Figure 11 This is a schematic bar chart used to illustrate the threshold voltage of the storage units MCI and MCO that record multiple bits of data.

[0019] Figure 12 This is a schematic cross-sectional view used to illustrate the data readout operation of the first embodiment.

[0020] Figure 13 This is a schematic cross-sectional view used to illustrate the hole filling operation of the first embodiment.

[0021] Figure 14 This is a schematic waveform diagram used to illustrate the hole charging operation and data readout operation of the first embodiment.

[0022] Figure 15 This is a schematic cross-sectional view used to illustrate the hole filling operation of the second embodiment.

[0023] Figure 16 This is a schematic waveform diagram used to illustrate the hole filling operation and data readout operation of the second embodiment.

[0024] Figure 17 This is a schematic cross-sectional view used to illustrate the hole filling operation of the third embodiment.

[0025] Figure 18 This is a schematic waveform diagram used to illustrate the hole charging operation and data readout operation of the third embodiment.

[0026] Figure 19 This is a schematic cross-sectional view used to illustrate the hole filling operation of the fourth embodiment.

[0027] Figure 20 This is a schematic waveform diagram used to illustrate the hole charging operation and data readout operation of the fourth embodiment.

[0028] Figure 21 This is a schematic cross-sectional view used to illustrate the hole filling operation of the fifth embodiment.

[0029] Figure 22 This is a schematic waveform diagram used to illustrate the hole filling operation and data readout operation of the fifth embodiment.

[0030] Figure 23 This is a schematic cross-sectional view used to illustrate the hole filling operation of the first embodiment.

[0031] Figure 24 This is a schematic cross-sectional view used to illustrate the hole filling operation of the sixth embodiment.

[0032] Figure 25 This is a schematic cross-sectional view used to illustrate the hole filling operation of the sixth embodiment.

[0033] Figure 26 This is a schematic waveform diagram used to illustrate the hole charging operation and data readout operation of the sixth embodiment.

[0034] Figure 27 This is a schematic cross-sectional view used to illustrate the hole filling operation of the seventh embodiment.

[0035] Figure 28 This is a schematic waveform diagram used to illustrate the hole charging operation and data readout operation of the seventh embodiment.

[0036] Figure 29 This is a schematic flowchart used to illustrate the writing operation of the eighth embodiment.

[0037] Figure 30 This is a schematic cross-sectional view used to illustrate the writing action.

[0038] Figure 31 This is a schematic cross-sectional view used to illustrate the writing action. Detailed Implementation

[0039] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Additionally, the following drawings are schematic diagrams, and sometimes certain components are omitted for ease of explanation. Furthermore, sometimes common parts in multiple embodiments are labeled with the same symbols, and descriptions are omitted.

[0040] Furthermore, when "semiconductor memory device" is mentioned in this specification, it sometimes refers to a memory chip, and sometimes to a memory system that includes a controller chip, such as a memory chip, memory card, or SSD (Solid State Drive). Moreover, it sometimes refers to a device including a host computer, such as a smartphone, tablet, or personal computer.

[0041] Furthermore, in this specification, when referring to the first component and the second component as "electrically connected," it can mean that the first component and the second component are directly connected, or that the first component and the second component are connected via wiring, semiconductor components, or transistors. For example, in the case of three transistors connected in series, even if the second transistor is in an off state, the first transistor can still be "electrically connected" to the third transistor.

[0042] Furthermore, in this specification, when referring to the first component as being "connected" "between" the second and third components, it sometimes means that the first, second, and third components are connected in series, and the second component is connected to the first and third components via the first component.

[0043] Furthermore, in this specification, when referring to a circuit or the like that makes two wirings "conduct", it sometimes means, for example, that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wirings and that the transistor or the like is in a switched-on state.

[0044] Furthermore, in this specification, the specific direction parallel to the upper surface of the substrate is referred to as the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and the direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0045] In addition, in this specification, the direction along a specific plane is sometimes referred to as the first direction, the direction intersecting the specific plane and the first direction is referred to as the second direction, and the direction intersecting the specific plane is referred to as the third direction. These first direction, second direction, and third direction may correspond to any one of the X direction, Y direction, and Z direction, or may not correspond to any one of the X direction, Y direction, and Z direction.

[0046] In addition, in this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is referred to as "upper", and the direction approaching the substrate along the Z direction is referred to as "lower". In addition, for a certain component, when referring to the lower surface and the lower end, it means the surface and the end on the substrate side of the component, and when referring to the upper surface and the upper end, it means the surface and the end on the side opposite to the substrate of the component. In addition, a surface intersecting the X direction or the Y direction is referred to as a side surface, etc.

[0047] [First Embodiment][Configuration] Figure 1 It is a schematic block diagram showing the configuration of the storage system 10 of the first embodiment.

[0048] The storage system 10 reads, writes, erases, etc. user data according to signals sent from the host computer 20. The storage system 10 is, for example, a memory chip, a memory card, an SSD, or other systems that can store user data. The storage system 10 includes a plurality of memory dies MD and a controller die CD. The memory dies MD store user data. The controller die CD is connected to the plurality of memory dies MD and the host computer 20. The controller die CD includes, for example, a processor, a RAM (Random Access Memory), etc. The controller die CD performs processes such as conversion between logical addresses and physical addresses, bit error detection / correction, garbage collection (compression), wear leveling, etc.

[0049] Figure 2 It is a schematic side view showing a configuration example of the storage system 10 of the present embodiment. Figure 3 It is a schematic top view showing the configuration example. For the sake of convenience of explanation, Figure 2 and Figure 3 a part of the configuration is omitted.

[0050] As Figure 2As shown, the storage system 10 of this embodiment includes a mounting substrate (MSB), multiple storage dies (MDs), and a controller die (CD). A pad electrode P is provided at the end region in the Y direction of the upper surface of the mounting substrate (MSB). The region in the Y direction of the upper surface of the mounting substrate (MSB), excluding the end regions, is bonded to the lower surface of the storage die (MD) via an adhesive or the like. Multiple storage dies (MDs) are stacked on the mounting substrate (MSB). The pad electrode P is provided at the end region in the Y direction of the upper surface of the storage die (MD). The region in the Y direction of the upper surface of the storage die (MD), excluding the end regions, is bonded to the lower surface of other storage dies (MDs) or controller die (CD) via an adhesive or the like. The controller die (CD) is stacked on the storage die (MD). The pad electrode P is provided at the end region in the Y direction of the upper surface of the controller die (CD).

[0051] like Figure 3 As shown, the mounting substrate MSB, multiple memory dies MD, and controller die CD each have multiple bonding pads P arranged along the X direction. The multiple bonding pads P disposed on the mounting substrate MSB, multiple memory dies MD, and controller die CD are interconnected via bonding lines B.

[0052] in addition, Figure 2 and Figure 3 The configuration shown is merely an example; the actual configuration can be adjusted accordingly. For example... Figure 2 and Figure 3 In the example shown, a controller die CD is stacked on multiple memory dies MD. Furthermore, the memory dies MD and the controller die CD are connected via bonding wires B. Additionally, the multiple memory dies MD and controller die CDs are contained within a single package. However, the controller die CD may also be contained within a different package than the memory dies MD. Furthermore, the multiple memory dies MD and controller die CDs may also be interconnected via through electrodes or the like, instead of being connected via bonding wires B.

[0053] Figure 4 This is a schematic block diagram representing the structure of a memory die (MD). Figure 5 This is a schematic equivalent circuit diagram representing a portion of the memory die MD.

[0054] like Figure 4 As shown, the memory die MD has a memory cell array (MCA) and peripheral circuitry (PC) for controlling the memory cell array (MCA).

[0055] The storage cell array (MCA) has multiple storage blocks (BLK). Each storage block (BLK) has multiple serial components (SU). Serial components (SU) are, for example... Figure 5The diagram shows multiple memory cells MU. Each of these memory cells MU has two memory strings MSI and MSO. One end of each memory string MSI and MSO is connected to drain-side selection transistors STD and STDT, respectively, and then connected to a common bit line BL via these drain-side selection transistors STD and STDT. The other end of each memory string MSI and MSO is connected to a common source-side selection transistor STS and STSb, and then connected to a common source line SL via these source-side selection transistors STS and STSb.

[0056] The memory string MSI has m+1 memory cells MCI connected in series (m is an integer greater than or equal to 1). The memory string MSO has m+1 memory cells MCO connected in series. The memory cells MCI and MCO are field-effect transistors, each having a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating layer has a charge storage layer for storing data. The threshold voltage of the memory cells MCI and MCO varies depending on the amount of charge in the charge storage layer. The gate electrodes of the m+1 memory cells MCI are connected to word lines WLI_0 to WLI_m. Furthermore, the gate electrodes of the m+1 memory cells MCO are connected to word lines WLO_0 to WLO_m. Word lines WLI_0 to WLI_m and WLO_0 to WLO_m are connected to all memory cells MU in the memory block BLK.

[0057] Furthermore, the memory strings MSI and MSO each have one or more dummy memory cells MCDD, which are connected between multiple memory cells MCI and MCO and drain-side select transistor STD. Additionally, the memory strings MSI and MSO each have one or more dummy memory cells MCDS, which are connected between multiple memory cells MCI and MCO and source-side select transistor STS. The dummy memory cells MCDD and MCDS are configured identically to the memory cells MCI and MCO. However, the dummy memory cells MCDD and MCDS are not used for storing data. The gate electrode of the dummy memory cell MCDD is connected to the dummy word line WLDD. The gate electrode of the dummy memory cell MCDS is connected to the dummy word line WLDS. The dummy word lines WLDD and WLDS are respectively connected to all memory cells MU in the memory block BLK.

[0058] The selection transistors (STD, STDT, STS, STSb) are field-effect transistors, each possessing a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrode of the drain-side selection transistor STDT is connected to the drain-side selection gate line SGDT. The drain-side selection gate line SGDT is connected to all memory cells MU in the memory block BLK. The gate electrode of the drain-side selection transistor STD is connected to the drain-side selection gate line SGD. The drain-side selection gate line SGD is connected to all memory cells MU in the string assembly SU. The gate electrodes of the source-side selection transistors STS and STSb are connected to the source-side selection gate lines SGS and SGSb, respectively. The source-side selection gate lines SGS and SGSb are connected to all memory cells MU in the memory block BLK.

[0059] For example Figure 4 As shown, the peripheral circuit PC includes: a line decoder RD connected to the memory cell array MCA; a sense amplifier module SAM connected to the memory cell array MCA; and a voltage generation circuit VG connected to the line decoder RD and the sense amplifier module SAM. In addition, the peripheral circuit PC includes a sequencer, address register, status register, etc. (not shown).

[0060] The line decoder RD transmits the operating voltage generated in the voltage generation circuit VG to the word lines WLI, WLO and the select gate lines (SGDT, SGD, SGS, SGSb) specified by the address data.

[0061] The sense amplifier module (SAM) includes multiple sense amplifier units (not shown) corresponding to multiple bit lines (BL). Each sense amplifier unit includes: a sense transistor having a gate electrode electrically connected to the bit line (BL); multiple data latch circuits connected to the drain electrode of the sense transistor; and a voltage adjustment circuit that adjusts the voltage of the bit line (BL) based on data from one of the multiple data latch circuits.

[0062] The voltage generation circuit VG has multiple voltage generation units. These multiple voltage generation units can be boost circuits such as charge pump circuits or buck circuits such as voltage regulators. During data read-out operations, write operations, etc., the voltage generation circuit VG generates various voltages of different magnitudes and supplies these voltages to the line decoder RD and the sense amplifier module SAM.

[0063] Next, refer to Figures 6-10 An example of the configuration of the semiconductor memory device according to this embodiment will be described. Figure 6 This is a schematic top view representing a portion of the memory die MD. Figure 7 and Figure 8 It is Figure 6The diagram shows a schematic top view with enlarged representations of portions A and A′ in the structure shown. Figure 8 omitted in Figure 7 Part of the structure shown. Figure 9 This is a schematic 3D diagram representing a portion of the memory die MD. Figure 10 It is Figure 7 and Figure 8 The diagram shows a schematic top view of part B, which is an enlarged representation.

[0064] like Figure 6 As shown, the memory die MD includes a semiconductor substrate 100. In the example shown, two memory cell array regions R arranged along the X direction are disposed on the semiconductor substrate 100. MCA In the memory cell array region R MCA A wiring area R is provided side-by-side in the X direction. HU .

[0065] The semiconductor substrate 100 is, for example, a single-crystal silicon (Si) semiconductor substrate containing p-type impurities. An n-type well containing n-type impurities and a p-type well containing p-type impurities are provided on the upper surface of the semiconductor substrate. Furthermore, peripheral circuitry PCs are provided on the surface of the semiconductor substrate 100, for example. Figure 4 At least a portion of transistors, wiring, etc.

[0066] Storage cell array region R MCA It has multiple storage blocks (BLKs) arranged along the Y direction. For example, a storage block (BLK)... Figure 7 As shown, it has multiple string components SU arranged along the Y direction.

[0067] For example Figure 9 As shown, the string assembly SU includes: multiple stacked bulk structures LSI and LSO, arranged alternately along the Y direction; and a trench structure AT disposed between these multiple stacked bulk structures LSI and LSO. The stacked bulk structure LSI, for example, includes m+9 conductive layers 110I stacked in the Z direction. The stacked bulk structure LSO, for example, includes m+9 conductive layers 110O stacked in the Z direction. The trench structure AT includes multiple memory string structures MSS arranged in the X direction. Each memory string structure MSS includes: a generally bottom-cylindrical semiconductor layer 120 extending in the Z direction; a gate insulating layer 130 disposed between the stacked bulk structures LSI and LSO and the semiconductor layer 120; and an insulating layer 140 such as silicon oxide (SiO2) disposed in the central portion of the semiconductor layer 120. Furthermore, an insulating layer 150 such as silicon oxide (SiO2) is disposed between the multiple memory string structures MSS arranged along the X direction.

[0068] The conductive layers 110I and 110O are generally plate-shaped conductive layers extending in the X direction, such as a multilayer film of titanium nitride (TiN) and tungsten (W), or a conductive layer of polycrystalline silicon (Si) implanted with impurities. An insulating layer 101, such as silicon oxide (SiO2), is disposed between the multiple conductive layers 110I and 110O arranged in the Z direction.

[0069] The first conductive layer 110I and 110O from the bottom among the multiple conductive layers 110I and 110O functions as the gate electrode of the source-side select transistor STSb and the source-side select gate line SGSb.

[0070] The second conductive layer 110I and 110O from the bottom among the multiple conductive layers 110I and 110O functions as the gate electrode and source-side select gate line SGS of the source-side select transistor STS.

[0071] The third conductive layer 110I and 110O from the bottom among the multiple conductive layers 110I and 110O functions as the gate electrode of the dummy memory cell MCDS and the dummy word line WLDS.

[0072] The conductive layers 110I located from the bottom to the 4th to the (m+4th)th from the bottom of the multiple conductive layers 110I function as the gate electrode of the memory cell MCI and the word lines WLI_0 to WLI_m.

[0073] The conductive layers 110O located from the bottom 4th to the (m+4th)th of the multiple conductive layers 110O function as the gate electrode of the memory cell MCO and the word lines WLO_0 to WLO_m.

[0074] The conductive layer 110I and 110O located at the (m+5)th position from the bottom among the multiple conductive layers 110I and 110O serve as the gate electrode of the dummy memory cell MCDD and the dummy word line WLDD.

[0075] The conductive layers 110I and 110O located from the bottom (m+6th to m+8th) among the multiple conductive layers 110I and 110O function as the gate electrode of the drain-side select transistor STD and the drain-side select gate line SGD.

[0076] The conductive layer 110I and 110O located at the (m+9)th position from the bottom among the multiple conductive layers 110I and 110O function as the gate electrode of the drain-side select transistor STDT and the drain-side select gate line SGDT.

[0077] Figure 8 This is an XY cross-section representing the (n+3)th conductive layer 110I and 110O (n is an integer greater than or equal to 1 and less than or equal to m+1) counting from the bottom. Figure 8 In the cross-section shown, one end of the conductive layer 110I arranged along the Y direction is included in the conductive layer 110I in the X direction within a storage block BLK. Figure 8 The left end of the conductive layer 110O is commonly connected. Furthermore, one end of the conductive layer 110O in the X direction (located within a storage block BLK) is included in a plurality of conductive layers 110O arranged along the Y direction. Figure 8 The right ends are connected in a common manner.

[0078] Figure 7 This is a schematic top view showing the structure of the (m+5)th to (m+9)th conductive layers 110I and 110O counting from the bottom. Figure 7 In the plane shown, a plurality of conductive layers 110I arranged along the Y direction are included at one end of the conductive layer 110I in the X direction within a string assembly SU. Figure 7 The left end) is commonly connected. Furthermore, one end of the conductive layer 110O in the X direction (in a string assembly SU) is included among the multiple conductive layers 110O arranged along the Y direction. Figure 7 (The right end) is connected in common.

[0079] Semiconductor layer 120 ( Figure 9 For example, it is a semiconductor layer such as undoped polycrystalline silicon (Si). The semiconductor layer 120, as described above, has a generally bottomed cylindrical shape. The semiconductor layer 120 serves as a connection point with memory modules such as MSI and MSO (Mean Interconnect). Figure 4 The corresponding multiple memory cells MCI, MCO, dummy memory cells MCDD, MCDS, and the channel regions of selection transistors (STSb, STS, STD, STDT) function.

[0080] Semiconductor layer 121 ( Figure 9 The semiconductor layer 121 is connected to the lower end of the semiconductor layer 120. The semiconductor layer 121 is, for example, a polycrystalline silicon (Si) semiconductor layer containing n-type impurities such as phosphorus (P). The semiconductor layer 121 serves as the source line SL. Figure 4 To fulfill its function.

[0081] Furthermore, an impurity layer, including n-type impurities such as phosphorus (P) and polycrystalline silicon (Si), is formed on the upper end of the semiconductor layer 120 (not shown in the diagram). The semiconductor layer 120 is connected to the bit line BL via this impurity layer. Figure 4 Electrical connection.

[0082] The gate insulating layer 130 has a generally cylindrical shape and extends in the Z direction along the outer peripheral surface of the semiconductor layer 120. The gate insulating layer 130 includes a tunnel insulating layer 131 such as silicon oxide (SiO2), a charge storage film 132 such as silicon nitride (SiN), and a blocking insulating layer 133 such as silicon oxide (SiO2) disposed from the semiconductor layer 120 side toward the conductive layers 110I and 110O side.

[0083] For example Figure 7 As shown, wiring area R HU It has multiple contacts CC and a support structure HR disposed near these multiple contacts CC. The multiple contacts CC are respectively connected to conductive layers 110I and 110O. The support structure HR penetrates the multiple conductive layers 110I and 110O stacked along the Z direction. The support structure HR may also be an insulating layer such as silicon oxide (SiO2).

[0084] [Threshold voltages of memory cell MCI and MCO] Next, refer to Figure 11 The threshold voltages of the memory cells MCI and MCO are explained.

[0085] As described above, the memory cell array MCA has multiple memory cells MCI and MCO. When a write operation is performed on these multiple memory cells MCI and MCO, the threshold voltage of these memory cells MCI and MCO is controlled to various states.

[0086] Figure 11 This is a schematic bar chart illustrating the threshold voltages of the memory cells MCI and MCO that store multiple bits of data. The horizontal axis represents the voltages of the word lines WLI and WLO, and the vertical axis represents the number of memory cells MCI and MCO.

[0087] Figure 11 The diagram illustrates three distributions of the threshold voltages for memory cells MCI and MCO. For example, the threshold voltages of the MCI and MCO of a memory cell controlled in the Er state are greater than the read-out voltage V. BB And less than the readout voltage V CGAR Furthermore, the magnitude of the minimum threshold voltage contained in the threshold distribution of the Er state is the verification voltage V. VFYEP The magnitude of the magnitude. Furthermore, the threshold voltage of the memory cells MCI and MCO controlled in state A is greater than the read voltage V. CGAR And less than the readout voltage V CGBR Furthermore, the minimum threshold voltage contained in the threshold distribution of state A is the verification voltage V. VFYA The magnitude of the magnitude. Furthermore, the threshold voltage of the memory cells MCI and MCO controlled in state B is greater than the read voltage V. CGBR Furthermore, the minimum threshold voltage contained in the threshold distribution of state B is the verification voltage V. VFYB The magnitude of the difference. Furthermore, the threshold voltages of all memory cell MCI and MCO are less than the read path voltage V. READ .

[0088] Assign one or more bits of data to each of these threshold distributions.

[0089] For example, when allocating 3 bits of data to memory cells MCI and MCO, the threshold voltages of memory cells MCI and MCO are controlled to belong to 2. 3 = Any one of the 8 threshold distributions. In addition, assign any one of the following 8 threshold distributions: "0,0,0", "0,0,1", "0,1,0", "0,1,1", "1,0,0", "1,0,1", "1,1,0", "1,1,1".

[0090] Furthermore, for example, when allocating 1 bit of data to memory cells MCI and MCO, the threshold voltage of memory cells MCI and MCO is controlled to belong to 2. 1 = Either of the two threshold distributions. Furthermore, assign any data between "0" and "1" to these two threshold distributions.

[0091] [Data Readout Action] Next, refer to Figure 12 The data readout operation of the semiconductor memory device in this embodiment will be briefly explained. Figure 12 This is a schematic cross-sectional view used to illustrate the data readout action.

[0092] Furthermore, the data read operation in this embodiment is performed uniformly on all memory cells MCI and MCO contained in the specified string component SU within the specified memory block BLK and connected to the specified word line WLI or word line WLO. Hereinafter, such a configuration containing multiple memory cells MCI and MCO is sometimes referred to as a page.

[0093] Furthermore, the following description illustrates an example of performing a data read operation on the page corresponding to the memory string MSI and word line WLI_n. Additionally, in the following description, the drain-side select gate line SGD corresponding to the selected memory string MSI is sometimes referred to as drain-side select gate line SGD_SEL, and the drain-side select gate line SGD corresponding to the unselected memory string MSO is sometimes referred to as drain-side select gate line SGD_USEL.

[0094] During data readout operations, for example Figure 12 As shown, the voltage V supplied to the bit line BL is... SRC +V BL In addition, a voltage V is supplied to the source line SL. SRC Voltage V SRC Greater than the ground voltage V SS Voltage V SRC +V BL Greater than voltage V SRC .

[0095] In addition, the gate lines SGDT and SGD_SEL on the drain side are supplied with voltage V. SGVoltage V SG Greater than voltage V SRC +V BL In addition, voltage V SG With voltage V SRC +V BL The difference is greater than the threshold voltage at which the drain-side selection transistors STDT and STD operate as NMOS (N-channel metal oxide semiconductor) transistors. Therefore, an electron channel is formed in the channel region of the drain-side selection transistors STDT and STD corresponding to the selected memory string MSI.

[0096] In addition, the gate line SGD_USEL is supplied with a voltage V on the drain side. DD Voltage V DD Greater than voltage V SRC In addition, voltage V DD With voltage V SRC +V BL The difference is less than the threshold voltage at which the drain-side selection transistor STD operates as an NMOS transistor. Therefore, no channel is formed in the channel region of the drain-side selection transistor STD corresponding to the unselected memory string MSO.

[0097] In addition, a read path voltage V is supplied to the word lines WLI_0 to WLI_n-2, WLI_n+2 to WLI_m, and the corresponding dummy word line WLDD. READ In addition, the read path voltage V is supplied to word lines WLI_n-1 and WLI_n+1. READk Read the path voltage V READk Greater than the readout path voltage V READ Therefore, electronic channels are formed in the channel regions of multiple non-selective memory cells (MCIs).

[0098] In addition, a read voltage V is supplied to the select word line WLI_n. CGRV Read the voltage V CGRV For example, as a reference Figure 11 The reading voltage V is explained. CGAR V CGBR Any one of ... Therefore, based on the data recorded in the Selected Storage Unit (MCI), an electronic channel may or may not be formed in the channel region of the Selected Storage Unit (MCI).

[0099] In addition, a read path voltage V is supplied to the word lines WLO_0 to WLO_n-3, WLO_n+3 to WLO_m, and the corresponding dummy word line WLDD. READ Therefore, electronic channels are formed in the channel regions of multiple non-selective memory cells (MCOs).

[0100] In addition, a readout disconnect voltage V is supplied to word lines WLO_n-1 to WLO_n+1. BB In addition, a grounding voltage V is supplied to the word lines WLO_n-2 and WLO_n+2. SS Therefore, no channels are formed in the channel region of the memory cell MCO connected to these word lines.

[0101] In addition, voltages are supplied to the source-side gate lines SGS and SGSb. .Voltage Greater than voltage

[0102] V SRC +V BL In addition, voltage With voltage V SRC +V BL The difference is greater than that of the source-side select transistor STS.

[0103] STSb serves as the threshold voltage for the NMOS transistor to operate. Therefore, an electron channel is formed in the channel region of the source-side selection transistors STS and STSb.

[0104] Here, when an electronic channel is formed in the channel region of the selected memory cell MCI, current flows through the bit line BL. Conversely, when no electronic channel is formed in the channel region of the selected memory cell MCI, current does not flow through the bit line BL. During data readout, current is generated by utilizing the sense amplifier module SAM (…). Figure 4 The current in the bit line BL is detected, and the data of the selected memory cell MCI can be read. Additionally, in the following description, the sense amplifier module SAM ( Figure 4 The action of detecting the current in the bit line BL is called a sensing action.

[0105] in addition, Figure 12 In the middle, the readout disconnect voltage V is supplied to the word lines WLO_n-1 to WLO_n+1. BB The read path voltage V is supplied to the word lines WLO_0 to WLO_n-3 and WLO_n+3 to WLO_m. READ However, the configuration described is merely illustrative, and the specific method can be adjusted accordingly. For example, a readout disconnect voltage V can also be supplied to all word lines WLO_0 to WLO_m. BB .

[0106] [Threshold voltage variation] For example, when data is written to the memory cell MCI connected to the word line WLI_n, the charge storage film 132 of the memory cell MCI ( Figure 9Electrons are stored in the cell to adjust the threshold voltage of the memory cell MCO. Next, when data is written to the memory cell MCO connected to the word line WLO_n, electrons are stored in the charge storage film 132 of the memory cell MCO. Figure 9 The threshold voltage of the storage cell MCO is adjusted by storing electrons in the charge storage film 132 of the storage cell MCO. At this time, the threshold voltage of the storage cell MCO may sometimes change due to the electric field from the electrons stored in the charge storage film 132 of the storage cell MCO.

[0107] Here, this phenomenon can be suppressed by storing holes in the channel region of the storage cell MCO. That is, when holes are stored in the channel region of the storage cell MCO, the electric field lines generated by electrons from the charge storage film 132 of the storage cell MCO can be canceled by these holes.

[0108] Therefore, in the semiconductor memory device of this embodiment, before performing a data readout operation on the memory cell MCI, a hole is filled into the channel region of the memory cell MCI. Hereinafter, this operation will be referred to as the hole filling operation.

[0109] [Electric hole charging action] Next, refer to Figure 13 The hole-filling operation of the semiconductor memory device of this embodiment will be briefly explained. Figure 13 This is a schematic cross-sectional view used to illustrate the hole filling operation.

[0110] During the charging action of the hole, for example Figure 13 The voltage V supplied to the alignment line BL is shown. DDSA In addition, a ground voltage V is supplied to the source line SL. SS Voltage V DDSA Greater than voltage V SRC .

[0111] In addition, a readout voltage V is supplied to the drain-side selected gate line SGDT. BB This generates GIDL (Gate Induced Drain Leakage) in the drain-side select transistor STDT, thus creating holes in the channel region of the STDT.

[0112] In addition, a ground voltage V is supplied to the gate line SGD_SEL on the drain side. SS Here, the grounding voltage V SS With voltage V DDSAThe difference is less than the threshold voltage at which the drain-side selection transistor STD operates as a PMOS (P-channel metal oxide semiconductor) transistor. Therefore, no channel is formed in the channel region of the drain-side selection transistor STD corresponding to the selected memory string MSI.

[0113] In addition, a readout voltage V is supplied to the drain-side gate line SGD_USEL. BB Here, the disconnect voltage V is read. BB With voltage V DDSA The difference is greater than the threshold voltage at which the drain-side selection transistor STD operates as a PMOS transistor. Therefore, a hole channel is formed in the channel region of the drain-side selection transistor STD corresponding to the unselected memory string MSO.

[0114] In addition, a ground voltage V is supplied to the word lines WLI_0 to WLI_m, and the dummy word lines WLDD and WLDS corresponding to these word lines WLI_0 to WLI_m. SS Here, the grounding voltage V SS With voltage V DDSA The difference is less than the threshold voltage required for the memory cell MCI and the dummy memory cells MCDD and MCDS to operate as PMOS transistors. Therefore, no channel is formed in the channel region of the memory cell MCI and the dummy memory cells MCDD and MCDS corresponding to the selected memory string MSI.

[0115] In addition, a ground voltage V is supplied to the word lines WLO_0 to WLO_n-3 and the dummy word lines WLDS corresponding to these word lines WLO_0 to WLO_n-3. SS Here, the grounding voltage V SS With voltage V DDSA The difference is less than the threshold voltage required for the memory cell MCO and the dummy memory cell MCDS to operate as PMOS transistors. Therefore, no channel is formed in the channel region of the memory cell MCO and the dummy memory cell MCDS connected to these word lines WLO_0 to WLO_n-3 and the dummy word line WLDS.

[0116] In addition, a readout disconnect voltage V is supplied to the word lines WLO_n-2 to WLO_m and the dummy word lines WLDD corresponding to these word lines WLO_n-2 to WLO_m. BB Here, the disconnect voltage V is read. BB With voltage V DDSAThe difference is greater than the threshold voltage at which the memory cell MCO and the dummy memory cell MCDD operate as PMOS transistors. Therefore, a hole channel is formed in the channel region of the memory cell MCO and the dummy memory cell MCDD connected to these word lines WLO_n-2 to WLO_m and the dummy word line WLDD.

[0117] In addition, a ground voltage V is supplied to the source-side gate lines SGS and SGSb. SS Therefore, no channel is formed in the channel region of the source-side selected transistors STS and STSb.

[0118] According to the method, a hole is generated in the drain-side selection transistor STDT, which can charge the channel region of the memory cell MCO corresponding to the word line WLO_n. This suppresses fluctuations in the threshold voltage of the memory cell MCI.

[0119] [Including the actions of charging the hole and reading out the data] Next, refer to Figure 14 The hole charging operation and data reading operation of the semiconductor memory device in this embodiment will be explained in more detail. Figure 14 This is a schematic waveform diagram used to illustrate the hole charging and data readout operations. Additionally, Figure 14 The data also includes the voltages of the drain-side select gate lines USGD and USGDT corresponding to the unselected memory block BLK.

[0120] Figure 14 In the example, at timing t101, a ground voltage V is supplied to the drain-side select gate lines SGDT, SGD_SEL, SGD_USEL, USGD, USGDT, dummy word lines WLDD, WLDS, word lines WLI_0 to WLI_m, WLO_0 to WLO_m, source-side select gate lines SGS, SGSb, bit line BL, and source line SL. SS .

[0121] The hole charging operation begins at time t101. At time t101, a reference is supplied to each wiring. Figure 13 The voltage specified is as follows. Additionally, the voltage V supplied to the gate lines USGD and USGDT on the drain side is selected. SRC .

[0122] The hole charging operation ends at timing t102. At timing t102, the voltage on word lines WLO_n-1 to WLO_n+1 is maintained at the readout disconnect voltage V. BB Furthermore, the voltages of the drain-side gate selection lines USGD and USGDT are maintained at voltage V. SRC Supply grounding voltage V to all other wiring. SS .

[0123] The data readout operation begins at timing t103. At timing t103, the voltage V is supplied to the gate lines SGDT and SGD_SEL on the drain side. SG In addition, the gate line SGD_USEL on the drain side is supplied with a voltage V. DD However, in this sequence, a voltage V can also be supplied to the gate line SGD_USEL on the drain side. SG In addition, for the word line WLI_0~ WLO_m supplies the readout path voltage V READ However, in this sequence, the voltage of the select word line WLI_n can also be maintained at the ground voltage V. SS Furthermore, at this time sequence, voltage V is supplied to word lines WLI_n-1 and WLI_n+1. READk Furthermore, at this time sequence, voltages are supplied to the source-side gate lines SGS and SGSb. .

[0124] At time t104, voltage V is supplied to bit line BL. SRC .

[0125] At timing t105, a ground voltage V is supplied to the select word line WLI_n. SS In addition, the gate line SGD_USEL on the drain side is supplied with a voltage V. SG In this case, the voltage V supplied to the gate line SGD_USEL on the drain side is selected. DD .

[0126] At timing t106, a voltage greater than the read voltage V is supplied to the select word line WLI_n. CGRV The specific voltage. However, in this sequence, a read voltage V can also be supplied to the select word line WLI_n. CGRV Furthermore, at this time sequence, a voltage V is supplied to the bit line BL. SRC +V BL .

[0127] At timing t107, a read voltage V is supplied to the select word line WLI_n. CGRV .

[0128] During the time series t107 to t108, the sensing amplifier module SAM ( Figure 4 Perform sensing actions.

[0129] At timing t108, a voltage greater than the readout voltage V is supplied to the select word line WLI_n. CGRV The specific voltage. However, in this sequence, a read voltage V can also be supplied to the select word line WLI_n. CGRV Furthermore, at this time sequence, a voltage V is supplied to the bit line BL.SRC +V BL .

[0130] At timing t109, a read voltage V is supplied to the select word line WLI_n. CGRV .

[0131] Additionally, the read voltage V supplied to the select word line WLI_n at timing t108 or timing t109 CGRV Unlike the read voltage V supplied to the select word line WLI_n in timing t106 or timing t107. CGRV .

[0132] During the time period t109~t110, the sensing amplifier module SAM ( Figure 4 Perform sensing actions.

[0133] At time t110, a grounding voltage V is supplied to each wiring. SS .

[0134] Furthermore, in the example shown, at time t103, an electron channel is formed on the outer peripheral surface of the semiconductor layer 120, through which the bit line BL and the source line SL are connected. This action suppresses the generation of hot electrons, thereby also suppressing erroneous writes that occur during data readout.

[0135] In this embodiment, a hole-filling operation is performed at times t101 to t102, causing holes to be stored on a portion of the outer peripheral surface of the semiconductor layer 120. However, when an electron channel is formed on the entire outer peripheral surface of the semiconductor layer 120 at time t103, the stored holes will disappear.

[0136] Therefore, in this embodiment, during timing t101 to t110, the voltage of word lines WLO_n-1 to WLO_n+1 is maintained at the readout disconnect voltage V. BB This method suppresses the generation of hot electrons and maintains holes in a portion of the outer peripheral surface of the semiconductor layer 120. Furthermore, it is preferable that the voltages of the word lines WLO_n-1 to WLO_n+1 are maintained at the readout voltage V at least until the timing of the completion of all sensing operations included in the data readout operation. BB .

[0137] also, Figure 14 The following example illustrates the reading of the first readout voltage V during timing t106 to t108. CGRV The corresponding data is read out during timing t108 to t110, along with the second readout voltage V. CGRV The corresponding data. However, the readout voltage V used in the data readout process. CGRVThe quantity can be adjusted appropriately. For example, in the data readout operation, only one readout voltage V can be read. CGRV In the case of corresponding data, the processing performed in timings t108 to t110 is omitted. Furthermore, for example, in the data readout operation, only three or more readout voltages V are read. CGRV In the case of the corresponding data, in addition to the processing performed in time series t106~t108 and the processing performed in time series t108~t110, the same processing as the aforementioned processing is also performed.

[0138] [Second Embodiment] Next, refer to Figure 15 and Figure 16 The semiconductor memory device of the second embodiment will be described. Figure 15 This is a schematic cross-sectional view used to illustrate the hole filling operation of the semiconductor memory device according to the second embodiment. Figure 16 It is a schematic waveform diagram used to illustrate the hole charging action and data readout action.

[0139] For reference Figure 13 As explained above, in the hole-filling operation of the first embodiment, a hole is generated by the STDT selective transistor on the drain side. Furthermore, a readout voltage V is supplied to the word lines WLO_n-2 to WLO_m. BB A hole channel is formed in the channel region of the memory cell MCO connected to these word lines WLO_n-2 to WLO_m, and the hole is filled into the channel region of this range.

[0140] However, the method described is merely illustrative, and the specific actions can be adjusted accordingly. For example, a readout voltage V can also be supplied to at least one of the word lines WLO_0 to WLO_n-3. BB And to fill the hole with electricity over a wider area.

[0141] The hole-filling operation in the second embodiment is performed in essentially the same way as the hole-filling operation in the first embodiment. However, as Figure 15 and Figure 16 As shown, during the hole charging operation in the second embodiment, a readout disconnect voltage V is supplied to the word lines WLO_0 to WLO_n-3. BB Without supplying ground voltage V SS .

[0142] [Third Embodiment] Next, refer to Figure 17 and Figure 18 The semiconductor memory device of the third embodiment will be described. Figure 17 This is a schematic cross-sectional view used to illustrate the hole-filling operation of the semiconductor memory device according to the third embodiment. Figure 18 It is a schematic waveform diagram used to illustrate the hole charging action and data readout action.

[0143] For reference Figure 13 As explained above, in the hole-filling operation of the first embodiment, a hole is generated by the STDT selective transistor on the drain side. Furthermore, a readout voltage V is supplied to the word lines WLO_n-2 to WLO_m. BB A hole channel is formed in the channel region of the memory cell MCO connected to these word lines WLO_n-2 to WLO_m, and the hole is filled into the channel region of this range.

[0144] However, the method described is merely illustrative, and the specific actions can be adjusted accordingly. For example, a transistor STSb can be selected on the source side to generate a hole, instead of a transistor STDT on the drain side.

[0145] like Figure 17 As shown, during the hole filling operation in the third embodiment, a ground voltage V is supplied to the alignment line BL. SS In addition, a voltage V is supplied to the source line SL. SRC .

[0146] In addition, a ground voltage V is supplied to the gate lines SGDT, SGD_SEL, and SGD_USEL on the drain side. SS Therefore, a channel is not formed in the channel region of the STDT transistor on the drain side.

[0147] In addition, a ground voltage V is supplied to the word lines WLI_0~m and the corresponding dummy word lines WLDD and WLDS. SS Here, the grounding voltage V SS With voltage V SRC The difference is less than the threshold voltage required for the memory cell MCI and the dummy memory cells MCDD and MCDS to operate as PMOS transistors. Therefore, no channel is formed in the channel region of the memory cell MCI and the dummy memory cells MCDD and MCDS corresponding to the selected memory string MSI.

[0148] In addition, a readout disconnect voltage V is supplied to the word lines WLO_0 to n+2 and the dummy word lines WLDS corresponding to these word lines WLO_0 to n+2. BB Therefore, electrical holes are formed in the channel regions of the memory cells MCO and dummy memory cells MCDD that are connected to these word lines WLO_0 to n+2 and the dummy word lines WLDS.

[0149] In addition, a ground voltage V is supplied to the word lines WLO_n+3 to WLO_m and the dummy word lines WLDD corresponding to these word lines WLO_n+3 to WLO_m. SSTherefore, no channel is formed in the channel region of the memory cell MCO and the dummy memory cell MCDD connected to these word lines WLO_n+3 to WLO_m and the dummy word line WLDD.

[0150] In addition, a readout voltage V is supplied to the source-side selected gate line SGS. BB Therefore, a hole channel is formed in the channel region of the selective transistor (STS) on the source side.

[0151] In addition, a readout voltage V is supplied to the source-side selected gate line SGSb. BB Therefore, GIDL is generated on the source-side selective transistor STSb, thereby creating a hole in the channel region of the source-side selective transistor STSb.

[0152] like Figure 18 As shown, in the timing t101 of the hole filling operation in the third embodiment, a reference is supplied to each wiring. Figure 17 The voltage specified is as follows. Additionally, the voltage V supplied to the gate lines USGD and USGDT on the drain side is selected. SRC .

[0153] The hole charging operation ends at timing t102. At timing t102, the voltage on word lines WLO_n-1 to WLO_n+1 is maintained at the readout disconnect voltage V. BB Furthermore, the voltage of the source line SL and the voltages of the drain-side select gate lines USGD and USGDT are maintained at voltage V. SRC Supply grounding voltage V to all other wiring. SS .

[0154] The operations below timing t103 are performed in the same manner as in the first embodiment.

[0155] [Fourth Embodiment] Next, refer to Figure 19 and Figure 20 The semiconductor memory device of the fourth embodiment will be described. Figure 19 This is a schematic cross-sectional view used to illustrate the hole filling operation of the semiconductor memory device according to the fourth embodiment. Figure 20 It is a schematic waveform diagram used to illustrate the hole charging action and data readout action.

[0156] For reference Figure 16 As explained above, in the hole-filling operation of the third embodiment, a hole is generated at the source side by selecting the transistor STSb. Furthermore, a readout voltage V is supplied to the word lines WLO_0 to WLO_n+2. BB A hole channel is formed in the channel region of the memory cell MCO connected to these word lines WLO_0 to WLO_n+2, and the hole is filled into the channel region of this range.

[0157] However, the method described is merely illustrative, and the specific actions can be adjusted accordingly. For example, a readout disconnect voltage V can be supplied to at least one of the word lines WLO_n+3 to WLO_m. BB And to fill the hole with electricity over a wider area.

[0158] The hole-filling operation in the fourth embodiment is performed in essentially the same way as the hole-filling operation in the third embodiment. However, as Figure 19 and Figure 20 As shown, during the hole charging operation in the fourth embodiment, a readout disconnect voltage V is supplied to the word lines WLO_n+3 to WLO_m. BB Without supplying ground voltage V SS .

[0159] [Fifth Embodiment] Next, refer to Figure 21 and Figure 22 The semiconductor memory device of the fifth embodiment will be described. Figure 21 This is a schematic cross-sectional view used to illustrate the hole filling operation of the semiconductor memory device according to the fifth embodiment. Figure 22 It is a schematic waveform diagram used to illustrate the hole charging action and data readout action.

[0160] For reference Figure 13 As explained above, in the hole-filling operation of the first embodiment, a hole is generated on the drain side by a selective transistor STDT. Furthermore, as described in reference... Figure 17 As explained above, in the hole filling operation of the third embodiment, a hole is generated by the source-side selective transistor STSb.

[0161] However, the method described is merely illustrative, and the specific operation can be adjusted accordingly. For example, instead of selecting either the drain-side transistor STDT or the source-side transistor STSb, a hole can be generated on both sides.

[0162] like Figure 21 As shown, during the hole filling operation in the fifth embodiment, a voltage V is supplied to the alignment line BL. DDSA In addition, a voltage V is supplied to the source line SL. SRC .

[0163] In addition, a readout voltage V is supplied to the drain-side selected gate line SGDT. BB Therefore, the selective transistor STDT on the drain side generates GIDL, thereby creating a hole in the channel region of the selective transistor STDT on the drain side.

[0164] In addition, a ground voltage V is supplied to the gate line SGD_SEL on the drain side. SSTherefore, no channel was formed in the channel region of the STD selected on the drain side corresponding to the selected memory string MSI.

[0165] In addition, a readout voltage V is supplied to the drain-side gate line SGD_USEL. BB Therefore, a hole channel is formed in the channel region of the select transistor STD on the drain side corresponding to the unselected memory string MSO.

[0166] In addition, a ground voltage V is supplied to the word lines WLI_0 to WLI_m, and the dummy word lines WLDD and WLDS corresponding to these word lines WLI_0 to WLI_m. SS Therefore, no channel is formed in the channel regions of the memory cell MCI corresponding to the selected memory string MSI and the dummy memory cells MCDD and MCDS.

[0167] In addition, a readout disconnect voltage V is supplied to the word lines WLO_0 to WLO_m, and the dummy word lines WLDD and WLDS corresponding to these word lines WLO_0 to WLO_m. BB Therefore, electrical holes are formed in the channel regions of the memory cells MCO and dummy memory cells MCDS and MCDD that are connected to these word lines WLO_0 to WLO_m and the dummy word lines WLDD and WLDS.

[0168] In addition, a readout voltage V is supplied to the source-side selected gate line SGS. BB Therefore, a hole channel is formed in the channel region of the selective transistor (STS) on the source side.

[0169] In addition, a readout voltage V is supplied to the source-side selected gate line SGSb. BB Therefore, GIDL is generated on the source-side selective transistor STSb, thereby creating a hole in the channel region of the source-side selective transistor STSb.

[0170] like Figure 22 As shown, in the timing t101 of the hole filling operation in the fifth embodiment, a reference is supplied to each wiring. Figure 21 The voltage specified is as follows. Additionally, the voltage V supplied to the gate lines USGD and USGDT on the drain side is selected. SRC .

[0171] The hole charging operation ends at timing t102. At timing t102, the voltage on word lines WLO_n-1 to WLO_n+1 is maintained at the readout disconnect voltage V. BB Furthermore, the voltage of the source line SL and the voltages of the drain-side select gate lines USGD and USGDT are maintained at voltage V. SRC Supply grounding voltage V to all other wiring. SS .

[0172] The operations below timing t103 are performed in the same manner as in the first embodiment.

[0173] [Sixth Embodiment] As referred to Figure 5 As explained, each memory block BLK is provided with a drain-side select gate line SGDT, which is connected to all drain-side select transistors STDT contained in one memory block BLK.

[0174] also, Figure 7 In the illustrated configuration, a single memory block BLK contains five drain-side select gate lines (SGDs) formed by conductive layer 110I and five drain-side select gate lines (SGDs) formed by conductive layer 110O. The voltage supplied to one of these ten drain-side select gate lines (SGDs) selected based on address data can be independently controlled, along with the voltage supplied to the other nine. However, sometimes the same voltage may be supplied to all nine drain-side select gate lines (SGDs).

[0175] Here, for example, refer to Figure 13 As explained, during the hole filling operation in the first embodiment, a readout voltage V is supplied to the drain-side selected gate line SGDT. BB This results in a hole being generated in the channel region of the drain-side select transistor STDT. Furthermore, a readout voltage V is supplied to the drain-side select gate line SGD_USEL. BB Thus, a hole channel is formed in the channel region of the selected transistor STD on the drain side.

[0176] The configuration, when performing the hole filling operation, for example... Figure 23 The diagram also shows that holes are generated in the drain-side selective transistor STDT contained in the string assembly SU other than the selected string assembly SU. In addition, hole channels are generated in the channel region of the drain-side selective transistor STDT contained in the string assembly SU other than the selected string assembly SU, and the holes are filled into the outer peripheral surface of the corresponding semiconductor layer 120.

[0177] In the sixth embodiment, a method is illustrated in which holes are filled only into the outer peripheral surface of the semiconductor layer 120 contained in the selected string assembly SU, and holes are not filled into the outer peripheral surface of the semiconductor layer 120 contained in other string assemblies SU.

[0178] Figure 24 and Figure 25 This is a schematic cross-sectional view used to illustrate the hole filling operation of the semiconductor memory device according to the sixth embodiment. Figure 26It is a schematic waveform diagram used to illustrate the hole charging action and data readout action.

[0179] The hole-filling operation in the sixth embodiment is performed in essentially the same way as the hole-filling operation in the first or second embodiment. However, as Figures 24-26 As shown, during the hole charging operation in the sixth embodiment, a readout voltage V is supplied to the drain-side selected gate line SGD_SEL and the corresponding dummy word line WLDD. BB Without supplying ground voltage V SS In addition, a ground voltage V is supplied to the gate line SGD_USEL on the drain side. SS Without supplying the readout disconnect voltage V BB .

[0180] In the method, for example Figure 24 As shown, electrical holes are formed in the channel region of two adjacent dummy memory cells (MCDDs) in the Y direction. Here, for example, refer to... Figure 9 As explained above, the semiconductor layer 120 in this embodiment is formed in a generally cylindrical shape. Therefore, when, for example... Figure 24 When hole channels are formed in the channel regions of two adjacent dummy memory cells (MCDDs) in the Y direction, these two channel regions are interconnected via the side surface of the semiconductor layer 120 in the X direction. Therefore, similar to the first or second embodiment, holes can be stored on the outer peripheral surface of the semiconductor layer 120.

[0181] Furthermore, in the method, a ground voltage V is formed by selecting the gate line SGD_USEL on the drain side. SS This causes the drain-side select transistor STD, which is connected to the drain-side select gate line SGD_USEL, to be in the off state. Therefore, for example... Figure 25 As shown, in an unselected string assembly SU, the channel region of the drain-side selection transistor STDT can be electrically disconnected from the channel regions of the memory cells MCI and MCO.

[0182] Therefore, according to the hole filling operation of the sixth embodiment, holes are only filled into the outer peripheral surface of the semiconductor layer 120 contained in the selected string assembly SU, and holes are not filled into the outer peripheral surface of the semiconductor layer 120 contained in other string assemblies SU.

[0183] [Seventh Embodiment] In embodiments 1 to 6, at time t101 (refer to...) Figure 14The hole charging operation begins. At this time, hole channels are formed on the outer peripheral surface of semiconductor layer 120 near word lines WLO_n-2 to WLO_m. Furthermore, the hole charging operation ends at timing t102. At this time, the hole channels near word lines WLO_n-1 to WLO_n+1 are electrically floating. Here, at timing t103, a read path voltage V is supplied to word lines WLO_n-1 to WLO_n+1. READ V READk At this point, the potential of the hole channel may change due to capacitive coupling with word lines WLI_n-1 to WLI_n+1.

[0184] In the seventh embodiment, a method for suppressing potential fluctuations in the hole channel is illustrated.

[0185] Figure 27 This is a schematic cross-sectional view used to illustrate the hole filling operation of the semiconductor memory device according to the seventh embodiment. Figure 28 It is a schematic waveform diagram used to illustrate the hole charging action and data readout action.

[0186] The hole-filling operation in the seventh embodiment is performed in essentially the same way as the hole-filling operation in any of the first to sixth embodiments. However, as Figure 27 and Figure 28 As shown, during the hole charging operation in the seventh embodiment, a read path voltage V is supplied to the select word line WLI_n. READ In addition, the read path voltage V is supplied to word lines WLI_n-1 and WLI_n+1. READk Furthermore, the voltage supplied to the select word line WLI_n is maintained at the read path voltage V during the timing period t101 to t105. READ Furthermore, the voltage supplied to word lines WLI_n-1 and WLI_n+1 is maintained at the read path voltage V during the timing period t101 to t110. READk .

[0187] According to the method, during the period below time t102 when the hole channel becomes floating, the voltages of word lines WLI_n-1 and WLI_n+1 are maintained at a fixed value. Therefore, fluctuations in the hole channel potential can be suppressed.

[0188] Additionally, the voltages of preferred word lines WLI_n-1 and WLI_n+1 are maintained at the readout path voltage V until the timing of the completion of all sensing actions included in the data readout operation. READk .

[0189] [Eighth Embodiment] In the first to seventh embodiments, a data readout operation was illustrated as one form of readout operation. Furthermore, an example of performing a hole-filling operation before performing the data readout operation was described. However, semiconductor memory devices sometimes perform readout operations in addition to performing data readout operations. The hole-filling operation in the first to seventh embodiments may, for example, be performed before performing readout operations other than data readout operations.

[0190] For example, in the write operation of a semiconductor memory device, the programming and verification operations are sometimes performed repeatedly. The programming operation is as follows: a programming voltage V is supplied to the select word lines WLI and WLO. PGM Electrons are stored in the charge storage film 132, thereby increasing the threshold voltage of the memory cells MCI and MCO. Additionally, the programming voltage V... PGM Greater than the readout path voltage V READ The verification action is a form of the read action. The verification action detects whether the threshold voltages of the memory cells MCI and MCO have risen to the required level. In this case, for example, a hole-filling action can also be performed between the execution of the programming action and the execution of the verification action.

[0191] Furthermore, for example, in the write operation of a semiconductor memory device, the erase voltage supply operation and the erase verification operation are sometimes performed repeatedly. The erase voltage supply operation is as follows: supplying a ground voltage V to the word lines WLI and WLO. SS Furthermore, an erase voltage is supplied to at least one of the bit line BL and the source line SL to store holes in the charge storage film 132, thereby reducing the threshold voltages of the memory cells MCI and MCO. Additionally, the erase voltage is greater than the readout path voltage V. READ The erase verification action is a form of read action. The erase verification action detects whether the threshold voltages of the memory cells MCI and MCO have decreased to the required level. In this case, for example, a hole charging action may be performed during the period between the execution of the erase voltage supply action and the execution of the erase verification action.

[0192] The following is for reference Figures 29-31 This demonstrates the method for writing actions. Figure 29 This is a schematic flowchart illustrating the write operation of the semiconductor memory device according to the eighth embodiment. Figure 30 and Figure 31 This is a schematic cross-sectional view used to illustrate the write operation. Furthermore, the write operation of this embodiment is uniformly performed on the memory cells MCI and MCO within a specified page. Figure 30 and Figure 31 The example below illustrates a write operation performed on a page corresponding to the memory string MSI.

[0193] Step S101 ( Figure 29 In ), the number of loops n W Set to 1. Number of loops n W Recorded in registers, etc.

[0194] In step S102, the programming action is performed.

[0195] During programming operations, such as adjusting the threshold voltage of the select memory cells MCI and MCO that are connected to multiple select memory cells MCI and MCO, the bit line BL( Figure 4 Supply voltage V SRC A voltage V is supplied to the bit line BL connected to the select memory cells MCI and MCO that do not undergo threshold voltage adjustment among multiple select memory cells MCI and MCO. DD .

[0196] In addition, such as Figure 30 As shown, a programming voltage V is supplied to the conductive layer 110I, which functions as the select word line WLI. PGM A write pass voltage V is supplied to the conductive layers 110I and 110O, which function as the non-select word lines WLI and WLO. PASS .

[0197] Programming voltage V PGM The voltage at which electrons are stored in the charge storage film 132 of the selected storage cells MCI and MCO is greater than the readout path voltage V. READ Write through voltage V PASS The voltage that keeps the storage cells MCI and MCO in the ON state regardless of the data recorded in them, and the read path voltage V. READ Same as or greater than this, but less than the programming voltage V PGM .

[0198] Thus, an electron channel is formed in the semiconductor layer 120 to connect the bit line BL with the channel regions of the selected memory cells MCI and MCO. Furthermore, electrons in the channel regions of the selected memory cells MCI and MCO are stored in the charge storage film 132 through the tunnel insulating layer 131.

[0199] Step S103 ( Figure 29 Then, the hole filling operation is performed. The hole filling operation performed in step S103 can also be any of the hole filling operations in the first embodiment to the seventh embodiment.

[0200] Step S104 ( Figure 29 In the process, the verification action is performed.

[0201] The verification process is performed in essentially the same way as the data reading process. However, for example... Figure 31As illustrated, during the verification process, a verification voltage V is supplied to the conductive layer 110I, which functions as the select word line WLI. VFYX Without supplying readout voltage V CGRV Verify voltage V VFYX For example, as a reference Figure 11 The verification voltage V described VFYA V VFYB Any one of …

[0202] Step S105 ( Figure 29 In step S106, the result of the verification action is determined. For example, if the ratio of MCI to MCO of the memory cells in the ON state is detected to be above a fixed number during the verification action, the verification is determined to have failed, and the process proceeds to step S108. On the other hand, if the ratio of MCI to MCO of the memory cells in the ON state is detected to be below a fixed number during the verification action, the verification is determined to have passed, and the process proceeds to step S108.

[0203] In step S106, the loop count n is determined. W Has a specific number N been reached? W Before reaching a specific number N. W In the case of reaching a specific number N, proceed to step S107. W If the situation is as described, proceed to step S109.

[0204] In step S107, the number of iterations n W Adding 1 proceeds to step S102. Furthermore, in step S107, for example, the programming voltage V is... PGM Apply a specific voltage ΔV.

[0205] In step S108, the write operation ends by storing status data indicating that the write operation has been completed normally in a status register (not shown).

[0206] In step S109, the write operation ends by storing the status data indicating that the write operation did not end properly in a status register (not shown).

[0207] [Other Embodiments] The semiconductor memory device and its control method according to the first to eighth embodiments have been illustrated above. However, the above embodiments are merely illustrative, and the specific embodiments may be adjusted appropriately.

[0208] For example, refer to Figures 1-10 The structure described is merely an example; the actual structure can be adjusted accordingly.

[0209] For example, Figure 5In the illustrated configuration, a dummy memory cell MCDD is provided between the drain-side selection transistor STD and the memory cells MCI and MCO. Furthermore, a dummy memory cell MCDS is provided between the source-side selection transistor STS and the memory cells MCI and MCO. However, the dummy memory cells MCDD and MCDS can be omitted, or multiple dummy memory cells MCDD and MCDS can be provided. In this case, the conductive layers 110I and 110O (deposited in the Z direction) can be appropriately adjusted. Figure 9 The quantity of ).

[0210] In addition, for example Figure 5 In the illustrated configuration, the drain-side selection transistor STDT and the drain-side selection transistor STD are provided separately. Furthermore, the source-side selection transistor STS and the source-side selection transistor STSb are provided separately. However, the drain-side selection transistor STDT can be omitted, and the drain-side selection transistor STD performs a portion of the functions of the drain-side selection transistor STDT. Similarly, the source-side selection transistor STSb can be omitted, and the source-side selection transistor STS performs a portion of the functions of the source-side selection transistor STSb. In this case, the conductive layers 110I and 110O (deposited in the Z direction) can be appropriately adjusted. Figure 9 The quantity of ).

[0211] In addition, for example Figure 7 In the illustrated configuration, five drain-side select gate lines (SGDs) formed by conductive layer 110I and five drain-side select gate lines (SGDs) formed by conductive layer 110O are provided in one memory block BLK. However, the number of drain-side select gate lines (SGDs) provided in one memory block BLK may be more than 10 or less than 10.

[0212] In addition, for example Figure 9 In the illustrated configuration, the semiconductor layer 120 is configured as a generally cylindrical shape. However, the semiconductor layer 120 may also have, for example, a generally flat portion facing the side of the conductive layer 110I and a generally flat portion facing the side of the conductive layer 110O.

[0213] In addition, for example Figure 9In the illustrated configuration, semiconductor layer 121 contains n-type impurities such as phosphorus (P), and the lower end of semiconductor layer 120 is connected to semiconductor layer 121. However, semiconductor layer 121 may also contain p-type impurities such as boron (B), and the lower end of semiconductor layer 120 may also be connected to semiconductor layer 121. With this configuration, when performing any of the hole-charging operations in embodiments 3 to 5, GIDL is not generated by the source-side selective transistor STSb, and charging of semiconductor layer 120 can be performed through holes in semiconductor layer 121. Furthermore, the operations of embodiments 7 and 8 can also be performed in combination with the aforementioned operations.

[0214] In addition, for example, refer to Figures 12 to 31 The actions described are merely examples; the specific methods can be adjusted accordingly.

[0215] For example, the first embodiment ( Figure 13 ), second implementation method ( Figure 15 ) or the 5th embodiment ( Figure 21 During the hole charging process, a ground voltage V is supplied to the gate line SGD_SEL on the drain side. SS The drain-side gate line SGD_USEL is supplied with a readout voltage V. BB However, for example, a readout voltage V can also be supplied to both the drain-side gate lines SGD_SEL and SGD_USEL. BB Furthermore, the actions of the 7th and 8th embodiments can also be performed in combination with the aforementioned actions.

[0216] Furthermore, in the data readout operation of embodiments 1 to 7, for example, the readout path voltage V is supplied to word lines WLI_n-1 and WLI_n+1. READk However, the read path voltage V can also be supplied to word lines WLI_n-1 and WLI_n+1. READ .

[0217] [Instruction Set] In embodiments 1 to 7, when an instruction set indicating the intention to perform a data read operation is input from the controller die CD to the storage die MD, both a hole-filling operation and a data read operation can be performed corresponding to the input of that instruction set. In this case, for example, a parameter indicating whether a hole-filling operation is performed during a data read operation can be set as an operation parameter of the semiconductor memory device. Furthermore, in embodiments 1 to 7, the instruction set indicating the intention to perform a hole-filling operation and the instruction set indicating the intention to perform a data read operation can be different instruction sets.

[0218] In the eighth embodiment, when an instruction set is input from the controller die CD to the storage die MD to perform a write operation or the like, both hole filling and write operations can be performed corresponding to the input of that instruction set. In this case, for example, a parameter indicating whether a hole filling operation is performed during a write operation or the like can be set as an operation parameter of the semiconductor memory device.

[0219] [Other] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention and are included in the invention as described in the claims and within the same scope.

Claims

1. A semiconductor memory device comprising: Multiple first conductive layers are arranged along a first direction; A plurality of second conductive layers are arranged at intervals from the plurality of first conductive layers in a second direction intersecting the first direction, and are arranged along the first direction; A first semiconductor layer is disposed between the plurality of first conductive layers and the plurality of second conductive layers, extends in the first direction, and faces the plurality of first conductive layers and the plurality of second conductive layers; A charge storage layer comprising a first portion and a second portion, the first portion being disposed between the plurality of first conductive layers and the first semiconductor layer, and the second portion being disposed between the plurality of second conductive layers and the first semiconductor layer; and The first wiring is electrically connected to the first semiconductor layer; and The semiconductor memory device is configured to perform a read operation and a first operation performed prior to the read operation; In the readout action: A readout voltage is supplied to the nth first conductive layer, counting from one side of the first direction, among the plurality of first conductive layers, where n is an integer greater than or equal to 1; At least a portion of the plurality of first conductive layers are supplied with a readout path voltage greater than the readout voltage; and A second voltage is supplied to the nth second conductive layer, counting from one side in the first direction; In the first action: A first voltage greater than the second voltage is supplied to the first wiring; The second voltage is supplied to the nth second conductive layer; and At least a portion of the plurality of first conductive layers is supplied with a voltage less than the readout path voltage; and The voltage of the nth second conductive layer is maintained at the second voltage from the first timing of the first action to the second timing of the end of the sensing action in the readout action.

2. The semiconductor memory device according to claim 1, wherein In the first operation, the second voltage is supplied to the (n-1)th to (n+1)th second conductive layers counting from one side in the first direction.

3. The semiconductor memory device according to claim 2, wherein... During the readout operation, the second voltage is supplied to the (n-1)th to (n+1)th second conductive layers.

4. The semiconductor memory device according to claim 3, wherein The voltage of the (n-1)th to (n+1)th second conductive layer is maintained at the second voltage during the period from the first timing sequence to the second timing sequence.

5. The semiconductor memory device according to claim 1, wherein... In the first operation, the second voltage is supplied to at least a portion of the plurality of second conductive layers that are closer to the first wiring than the nth second conductive layer.

6. The semiconductor memory device according to claim 1, comprising: The second wiring is electrically connected to the first semiconductor layer; and In the first operation, a third voltage greater than the second voltage is supplied to the second wiring.

7. The semiconductor memory device according to claim 6, wherein In the first action, the second voltage is supplied to at least a portion of the plurality of second conductive layers that are closer to the second wiring than the nth second conductive layer.

8. The semiconductor memory device according to claim 1, comprising: A third conductive layer is arranged side-by-side with the plurality of first conductive layers in the first direction; and The fourth conductive layer is disposed spaced apart from the third conductive layer in the second direction and is arranged side-by-side with the plurality of second conductive layers in the first direction; and The first semiconductor layer is disposed between the third conductive layer and the fourth conductive layer, and is opposite to the third conductive layer and the fourth conductive layer; In the readout action: A fourth voltage is supplied to the third conductive layer; and A fifth voltage, less than the fourth voltage, is supplied to the fourth conductive layer; and In the first action: The second voltage is supplied to at least one of the third or fourth conductive layers.

9. The semiconductor memory device according to claim 1, comprising: A third conductive layer is arranged side-by-side with the plurality of first conductive layers in the first direction; and The fourth conductive layer is disposed spaced apart from the third conductive layer in the second direction and is arranged side-by-side with the plurality of second conductive layers in the first direction; and The first semiconductor layer is disposed between the third conductive layer and the fourth conductive layer, and is opposite to the third conductive layer and the fourth conductive layer; In the readout action: A fourth voltage is supplied to the third conductive layer; A fifth voltage, less than the fourth voltage, is supplied to the fourth conductive layer; and In the first action: The second voltage is supplied to the third conductive layer; and The fifth voltage is supplied to the fourth conductive layer.

10. The semiconductor memory device according to claim 1, wherein The voltages of the (n-1)th and (n+1)th first conductive layers, counting from one side of the first direction, are maintained at or greater than the readout path voltage during the period from the first timing sequence to the second timing sequence.

11. The semiconductor memory device of claim 10, wherein... The voltage of the nth first conductive layer is maintained at the readout path voltage during the period from the first timing sequence to the third timing sequence between the first timing sequence and the second timing sequence.

12. The semiconductor memory device according to claim 1, wherein The readout action is a data readout action; and The first action and the read action are executed upon input of an instruction set corresponding to the intention to perform the data read action.

13. The semiconductor memory device according to claim 1, wherein The readout action is a data readout action; The first action is executed upon input of an instruction set corresponding to the intent to perform the first action; and The readout action is performed by inputting a set of instructions corresponding to the intention of performing the readout action.

14. The semiconductor memory device according to claim 1, wherein The read action is a verification action included in the write action; and The first action and the verification action are performed in accordance with the input of the instruction set corresponding to the intention of performing the write action.

15. The semiconductor memory device according to claim 1, wherein The readout action is an erase verification action included in the erase action; and The first action and the erasure verification action are executed upon input of the instruction set corresponding to the intention to perform the erasure action.

16. The semiconductor memory device according to claim 1, wherein In the fourth timing sequence between the first timing sequence and the second timing sequence, the readout path voltage is supplied to the nth first conductive layer.

17. The semiconductor memory device according to claim 1, wherein In the fourth timing sequence between the first timing sequence and the second timing sequence, the readout path voltage is supplied to at least a portion of the plurality of first conductive layers.

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