Apparatus, system, and method for probabilistic data structures for error tracking

Abstract

Devices, systems, and methods for probabilistic data structures for error tracking. A memory device can include error correction code (ECC) circuitry that determines whether data read from a memory array includes an error. If so, a row address associated with the read data is provided to error tracking circuitry. The error tracking circuitry can use a probabilistic data structure, such as a plurality of count values, each indexed by a different hash value of a row address. The count values can be used to determine whether a given row address is associated with an error repeat. The memory can store these identified problematic addresses in a data storage structure for purposes of, e.g., diagnosis and / or repair.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to semiconductor devices, such as semiconductor memory devices, and more particularly to apparatuses, systems, and methods for probabilistic data structures for error tracking. BACKGROUND

[0002] The semiconductor memory device can include a plurality of memory cells for storing information. The stored information can be encoded into binary data, and each memory cell can store a single bit of information. Due to various different errors, the information in the memory cells can decay or change, which can result in reading erroneous information (e.g., bits having different states than the bits initially written) from the memory device.

[0003] There can be many applications that can be used to ensure high fidelity of information read from memory. The memory device can include error correction circuitry that can be used to determine whether the information read from the memory cells contains any errors compared to the data written to the memory cells, and can correct the errors found. SUMMARY

[0004] According to an aspect of the present application, an apparatus is provided. The apparatus includes a first hash circuit configured to provide a first count value based on an n-bit hash of a received row address; a second hash circuit configured to provide a second count value based on an m-bit hash of the received row address, where n and m are different numbers; a problem address storage structure configured to store the received row address as a stored problem address if the first count value, the second count value, or a combination thereof exceeds a threshold value.

[0005] According to another aspect of the present application, an apparatus is provided. The apparatus includes a memory array including a plurality of word lines; error correction code (ECC) circuitry configured to identify a row address based on one or more errors in data read from one of the plurality of word lines associated with the row address; a first stack including a plurality of first registers, each of the plurality of first registers configured to store a count value associated with a first number of the plurality of word lines, wherein the first stack is configured to provide a first count value associated with the identified row address; a second stack including a plurality of second registers, each of the plurality of second registers configured to store a count value associated with a second number of the plurality of word lines, wherein the second number is different than the first number, and wherein the first stack is configured to provide a second count value associated with the identified row address; and a problem address storage device configured to store the identified row address based on the first count value, the second count value, or a combination thereof.

[0006] According to yet another aspect of the present application, a method is provided. The method includes hashing a row address to a first hash including a first number of bits, changing a first count value associated with a value of the first hash, hashing the row address to a second hash including a second number of bits different from the first number of bits, changing a second count value associated with a value of the second hash, and storing the row address in a data stack based on the first count value, the second count value, or a combination thereof. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block diagram of a semiconductor device according to one embodiment of the present disclosure.

[0008] Figure 2 is a block diagram of an error tracking circuit according to some embodiments of the present disclosure.

[0009] Figure 3 is a set of block diagrams showing example operations of a set of data structures according to some embodiments of the present disclosure.

[0010] Figure 4 is a set of block diagrams showing example operations of a set of data structures according to some embodiments of the present disclosure.

[0011] Figure 5 is a schematic diagram of an error correction code (ECC) control circuit according to some embodiments of the present disclosure.

[0012] Figure 6 is a block diagram of a method of tracking row addresses associated with errors according to some embodiments of the present disclosure.

[0013] Figure 7 is a block diagram of a hash circuit according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The following description of certain examples is merely exemplary in nature and is not intended to limit the scope of the disclosure, its application, or uses. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the described system and method can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed system and method, and it is to be understood that other embodiments can be utilized and that structural and logical changes can be made without departing from the spirit and scope of the present disclosure. Furthermore, the following description of various examples is not intended to limit the scope of the present disclosure to the precise examples described. Accordingly, the following detailed description is exemplary and explanatory only and is not intended to be limiting or to unduly limit the scope of the present disclosure.

[0015] Memory devices can include a memory array having a plurality of memory cells, each memory cell located at an intersection of a word line (row) and a bit line (column). During a read or write operation, a row can be activated, and data can be read from or written to the memory cells along the activated row. Each row can include memory cells storing multiple bits of data and multiple bits of check information, such as data bits and check bits, which can be used to correct up to a certain number of errors in the data bits. For example, a row can include i data bits and k check bits, which can be used to correct up to j data bits. During a write operation, the check bits can be generated by error correction circuitry based on the data written to the memory cells of the row. During a read operation, the error correction circuitry can use the check bits to determine whether the read data bits are correct, and can correct any errors found.

[0016] In addition to correcting this information, memory can also be used to track which memory cells have defects. For example, memory can keep track of the most recent row address associated with a read operation that contained one or more error bits. However, it can be desirable to track several problematic addresses within the memory, and / or to more complexly analyze which address(es) are “problematic addresses” and the specific number of times data read from the word line associated with those addresses includes errors.

[0017] The present disclosure is directed to devices, systems, and methods for probabilistic data structures for error tracking. A memory can include error correction code (ECC) circuitry and error tracking circuitry. When an error in read data is detected, the ECC circuitry can provide a row address associated with the read operation to the error tracking circuitry. The error tracking circuitry can include a first hash circuitry and a second hash circuitry, where the first hash circuitry can hash the row address to an n-bit hash, and the second hash circuitry can hash the row address to an m-bit hash. The error tracking circuitry can change a first count value associated with a value of the n-bit hash and a second count value associated with a value of the m-bit hash. Based on these count values, the error tracking circuitry can determine whether the address is a problematic address associated with frequent errors. The error tracking circuitry can store such problematic addresses to a problem storage circuitry. Problematic addresses in the problem storage circuitry can be retrieved by a controller of the memory, and / or can be used as part of one or more repair operations (e.g., post-package repair).

[0018] The use of multiple hash circuits (and multiple hash lengths) can be useful because it can reduce the total number of count values that are required to be stored for tracking, while still maintaining a relatively high degree of statistical significance for the tracking. The use of hash circuits can result in collisions, where multiple addresses can be associated with the same hash value (e.g., the same count value). However, the use of multiple different hash circuits means that when a first address and a second address can collide in the first hash circuit, they can not collide in the second hash circuit. There can be more collisions between addresses in the shorter hash (e.g., the count value associated with the shorter hash value can be associated with more word lines), while the longer hash can still have fewer collisions, which can offset the shorter hash. Because a count value must be maintained for each hash value (based on the length of the hash), the use of different length hashes can reduce the total number of count values that need to be stored. This can result in probabilistic error tracking, in that the hash and count value scheme does not necessarily guarantee that a given problematic row will be accurately identified, but does have a reasonably high likelihood of identifying such a row, with only a relatively small number of tracked count values.

[0019] Figure 1 is a block diagram of a semiconductor device according to one embodiment of the disclosure. The semiconductor device 100 can be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0020] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of memory banks. In Figure 1 In embodiments, the memory array 118 is shown as including eight memory banks BANK0-BANK7. The memory array 118 in other embodiments can include more or fewer memory banks. Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC disposed at the intersections of the plurality of word lines WL and the plurality of bit lines BL. The word lines WL are selected by a row decoder 108, and the bit lines BL are selected by a column decoder 110. In Figure 1 In embodiments, the row decoder 108 includes a row decoder for each memory bank, and the column decoder 110 includes a column decoder for each memory bank. The bit lines BL are coupled to respective sense amplifiers (SAMP). Read data from the bit lines BL are amplified through the sense amplifiers SAMP and transferred to a read / write amplifier through a local I / O line (LIOT / B), a transfer gate (TG), and a main I / O line (MIOT / B) coupled to an error correction code (ECC) control circuit 120. Conversely, write data output from the ECC control circuit 120 is transferred to the sense amplifiers SAMP through the main I / O line MIOT / B, the transfer gate TG, and the local I / O line LIOT / B, and written to the memory cells MC coupled to the bit lines BL.

[0021] The semiconductor device 100 can employ a plurality of external terminals including command and address (C / A) terminals coupled to a command and address bus to receive commands and addresses and a CS signal, clock terminals for receiving a clock CK and / CK, data terminals DQ for providing data, and power terminals for receiving supply potentials VDD, VSS, VDDQ, and VSSQ.

[0022] The clock terminals are provided with external clocks CK and / CK supplied to the input circuit 112. The external clocks can be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is supplied to the command decoder 106 and an internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clocks can be used for timing operations of various internal circuits. The internal data clock LCLK is supplied to the input / output circuit 122 to time operations of circuits included in the input / output circuit 122, e.g., to a data receiver to time reception of write data.

[0023] The C / A terminals can be provided with memory addresses. The memory addresses supplied to the C / A terminals are transferred to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the addresses and supplies a decoded row address XADD to the row decoder 108 and a decoded column address YADD to the column decoder 110. The address decoder 104 can also supply a decoded bank address BADD which can indicate the memory array bank 118 containing the decoded row address XADD and column address YADD. The C / A terminals can have commands. Examples of commands include timing commands for controlling timing of various operations, access commands for accessing memory such as read commands for performing read operations and write commands for performing write operations, and other commands and operations. The access commands can be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate memory cells to be accessed.

[0024] The commands can be provided as internal command signals to the command decoder 106 via the command / address input circuit 102. The command decoder 106 includes circuitry to decode the internal command signals to generate various internal signals and commands for performing operations. For example, the command decoder 106 can provide row command signals to select word lines, column command signals to select bit lines.

[0025] The device 100 can receive an access command as a read command. When the read command is received and timely supplied with the bank address, row address, and column address, read data is read from the memory cells in the memory array 118 corresponding to the row and column addresses. The command decoder 106 receives the read command and provides an internal command to cause the read data from the memory array 118 to be provided to the ECC control circuit 120. The read command can also cause one or more check bits associated with the read data to be provided to the ECC control circuit 120 along the MIOT / B. The ECC control circuit 120 can use the check bits to determine whether the read data includes any errors and, if any errors are detected, can correct the errors to generate corrected read data. The corrected read data is output from the data terminals DQ to the outside of the device 100 via the input / output circuit 122. When it is determined that the read data includes errors, the ECC control circuit 120 can provide an error detection signal ErrDet at the active level.

[0026] The device 100 can receive an access command as a write command. When the write command is received and timely supplied with the bank address, row address, and column address, write data is supplied to the ECC control circuit 120 through the DQ terminals. The write data supplied to the data terminals DQ is written to the memory cells in the memory array 118 corresponding to the row and column addresses. The command decoder 106 receives the write command and provides an internal command to cause the data receiver in the input / output circuit 122 to receive the write data. A write clock can also be provided to the external clock terminal to time the reception of the write data by the data receiver in the input / output circuit 122. Via the input / output circuit 122, the write data is supplied to the ECC control circuit 120. The ECC control circuit 120 can generate a plurality of check bits based on the write data and can provide the write data and check bits to the memory array 118 to be written to the memory cells MC.

[0027] The ECC control circuit 120 can be used to ensure fidelity of data read from a particular group of memory cells to data written into the group of memory cells. The device 100 can include a plurality of different ECC control circuits 120, with each circuit responsible for the memory cells MC of a different portion of the memory array 118. For example, one or more ECC control circuits 120 can be used for each group of the memory array 118.

[0028] Each ECC control circuit 120 can receive a number of data bits (from the IO circuit 122 or the memory array 118) and can correct potential errors in the data bits using a number of parity bits based on the number of data bits. For example, as part of a write operation, the ECC control circuit 120 can receive 128 bits of data from the IO circuit and can generate 8 parity bits based on the 128 data bits. The 128 data bits and 8 parity bits (e.g., 136 total bits) can be written to the memory array 118. As part of an example read operation, the ECC control circuit 120 can receive 128 data bits and 8 parity bits from the memory cell array 118. The ECC control circuit 120 can use the 8 parity bits to determine whether there are any errors in the 128 read data bits and can correct any errors found. For example, the ECC control circuit 120 can be able to locate and correct one error in the 128 data bits based on the 8 parity bits. When discussing various embodiments with reference to an ECC circuit that uses 8 parity bits to find one error in 128 data bits, it should be understood that these are for illustrative purposes only, and other example embodiments can use other numbers of data bits, error bits, and parity bits. Figure 5 Example ECC circuits are discussed in more detail in the Background.

[0029] The memory can include an error tracking circuit 130 that can track which memory cells, if any, are associated with relatively frequent problems. For example, the error tracking circuit 130 can track rows of the memory array 118 that have been identified during read operations to include error bits. The ECC control circuit 120 can provide a signal ErrDet at the activity level to indicate that an error bit has been detected. In response to the signal ErrDet at the activity level, the error tracking circuit 130 can receive a row address XADD. The error tracking circuit 130 can include one or more count values associated with the received address. Based on the values of the one or more count values, the error tracking circuit can determine whether the row is a ‘problem row’ Err XADD associated with a relatively high number of errors, and if so, can store the identified problem row Err XADD in a problem storage structure (e.g., a register stack). In some embodiments, the identified problem row Err XADD can be read out of the error tracking circuit 130 (e.g., to a data terminal DQ). In some embodiments, the identified problem row Err XADD can be used as part of a repair operation (e.g., a post-package repair operation). The repair operation can include redirecting the problem address Err XADD to a redundant row of memory.

[0030] Error tracking circuit 130 can use the count values to track how many times each address has been associated with an error bit. However, it can not be practical to store a count value for each of the different row addresses. Error tracking circuit 130 can use count values that are associated with multiple row addresses. Error tracking circuit 130 can use a hash circuit to compress a row address to a hash value, and can use the hash value as an index into the count values. Since each count value matches several addresses, based on what count value, error tracking circuit 130 can not be able to tell which address associated with the count value is problematic based on a single count value. Thus, error tracking circuit 130 can include multiple hash circuits, each generating a hash that is used to index into a different set of count values. The hash circuits can be independent of each other, so the hash value generated for a given address can not be the same between different hash circuits. This can mean that each count value is associated with a different set of address values. Similarly, when a given address is received (e.g., due to ErrDet being active), multiple count values can be indexed and updated. Error tracking circuit 130 can use one of these count values (and / or some value based on one or more of these count values) as a comparison value, and can compare it to a threshold value. If the comparison result is greater than the threshold value, then address XADD can be stored in the problem address storage.

[0031] Device 100 can also receive a command that causes it to perform one or more refresh operations as part of a self-refresh mode. In some embodiments, the self-refresh mode command can be issued to the memory device 100 from an external source. In some embodiments, the self-refresh mode command can be generated periodically by a component of the device. In some embodiments, the refresh signal AREF can also be activated when an external signal indicates a self-refresh entry command. The refresh signal AREF can be a pulsed signal that is activated when the command decoder 106 receives a signal indicating entry into the self-refresh mode. The refresh signal AREF can be activated immediately after the command input, and can then be activated cyclically with a desired internal timing. The refresh signal AREF can be used to control the timing of refresh operations during the self-refresh mode. Thus, refresh operations can continue automatically. A self-refresh exit command can stop the automatic activation of the refresh signal AREF and return to the IDLE state. The refresh signal AREF is supplied to the refresh control circuit 116. The refresh control circuit 116 supplies a refresh row address RXADD to the row decoder 108, which can refresh one or more word lines WL indicated by the refresh row address RXADD.

[0032] The power terminals have supply potentials VDD and VSS. The supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc. based on the supply potentials VDD and VSS supplied to the power terminals. The internal potential VPP is used primarily in the row decoder 108, the internal potentials VOD and VARY are used primarily in the sense amplifiers SAMP included in the memory array 118, and the internal potential VPERI is used in many of the peripheral circuit blocks.

[0033] The power terminals also have supply potentials VDDQ and VSSQ. The supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. The supply potentials VDDQ and VSSQ supplied to the power terminals can be the same as the supply potentials VDD and VSS supplied to the power terminals in one embodiment of the present disclosure. The supply potentials VDDQ and VSSQ supplied to the power terminals can be different from the supply potentials VDD and VSS supplied to the power terminals in another embodiment of the present disclosure. The supply potentials VDDQ and VSSQ supplied to the power terminals are used by the input / output circuit 122 so that supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0034] Figure 2 is a block diagram of an error tracking circuit according to some embodiments of the present disclosure. In some embodiments, the error tracking circuit 200 can be included in Figure 1 the error tracking circuit 130 of

[0035] The error tracking circuit 200 includes a plurality of hash circuits 212, 222, and 232 that hash a row address XADD along a row address bus when a signal ErrDet (e.g., Figure 1 Each hash circuit changes a count value stored in one of the registers of the associated data stack 210, 220, and 230, respectively, based on a hash value generated by the respective hash circuit when the signal ErrDet (e.g., provided by the ECC circuit 120) is active. The changed count value (e.g., the count value associated with the row address XADD) can be provided to the count logic circuit 202, which can use the provided count value to determine whether the row address XADD is associated with a problem row. If the count logic 202 determines that the row address XADD is a problem row, the problem logic 240 can store the row address XADD in the problem storage structure 242. The addresses stored in the problem storage structure 242 can be read out of the memory for diagnostic purposes, and / or the addresses stored in the problem storage can be used to repair the row (e.g., by redirecting the row address XADD to a redundant row of the memory).

[0036] Figure 2 The count logic circuit 202 of FIG. 2 shows a plurality of subcomponents of each of the count locator 204, the threshold comparator 206, and the count adjuster 208. These subcomponents are shown in dashed boxes and are optional components of the count logic 202. In some embodiments, the dashed subcomponents can represent system-level components of a memory coupled to the count logic circuit 202. For example, the timer subcomponent can be coupled to a clock signal of the memory (e.g., ICLK of FIG. 2). In some embodiments, the subcomponents can represent optional features of the error tracking circuit 200 and can be enabled / disabled by user settings (e.g., via mode register settings, via fuses, etc.). Figure 1

[0037] The error tracking circuit 200 includes a plurality of hash circuits, such as 212, 222, and 232, each associated with a data stack (e.g., 210, 220, and 230, respectively). Since the hash circuits and data stacks can generally be similar to each other, only the first hash circuit 212 and the data stack 210 will be described in detail for brevity.

[0038] The first hash circuit 212 can be an m-bit hash circuit. In response to the active level signal ErrDet, the first hash circuit 212 can receive a row address XADD on a row address bus and can convert it to an m-bit hash value. For example, the row address XADD can be a certain number of bits (e.g., 17 bits). The first hash circuit 212 can hash the row address XADD to the number of m-bits. The number of bits m can generally be less than the number of bits in the unhashed row address XADD. Thus, multiple values of the row address XADD can be associated with a given m-bit hash value.

[0039] The data stack 210 can be any structure capable of storing a plurality of different count values. For example, the data stack 210 can include a plurality of registers, each of which can store a count value (e.g., as a binary number). The data stack 210 can hold a number of count values equal to the number of possible values of the m-bit hash value (e.g., 2 m For example, if the first hash circuit 212 is an 8-bit hash circuit, the data stack 210 can include 256 different count values. Thus, each count value can be associated with one of the values of the m-bit hash value.

[0040] ​When receiving a row address XADD, the hash circuit 212 can provide an m-bit hash value associated with the value of the row address XADD. Responsive to the m-bit hash value, a count value associated with the value of the m-bit hash value in the data stack 210 can be changed (e.g., incremented). In some embodiments, the count value CV0 associated with the m-bit hash value (e.g., associated with the row address XADD) can be provided to the count logic circuit 202, which can change the count value CV0 and then rewrite it to the data stack 210.

[0041] The different hash circuits 212, 222, and 232 can be independent of one another. Accordingly, a given row address can be hashed to a first value by the first hash circuit 212 and to a second hash value by the second hash circuit 222. The first hash value and the second hash value are not necessarily the same value (although they can be). Since the hash values are used as indices to count values, this means that each count value can be associated with a different set of row addresses.

[0042] The different hash circuits 212, 222, and 232 can all generate different lengths of hashes. For example, the first hash circuit 212 can be an m-bit hash circuit, the second hash circuit 222 can be an n-bit hash circuit, and the third hash circuit 232 can be an o-bit hash circuit, where m, n, and o are different numbers. Accordingly, the associated data stacks 210, 220, and 230 can hold different numbers of count values. For example, m can be an 8-bit hash, and the first data stack 210 can hold 256 count values; n can be 7, and the second data stack 220 can hold 128 different count values; o can be 6, and the third data stack 230 can hold 64 different count values. Different lengths of hashes can be used in other example embodiments. The use of different hashes means that each count value can be associated with a different number of row addresses.

[0043] Each of the hash circuits 212, 222, and 232 can receive a set of hash keys (not shown) that can partially determine the hash value generated responsive to a received row address. The hash keys can be stored in a memory (e.g., a set of latches, a pattern register, etc.) and can be received by the hash circuits 212, 222, and 232. Each hash circuit can receive a set of hash keys that has a length based on the length of the hash value and can have multiple hash keys based on the number of bits in the received row address. For example, if a row address is R bits long, the first hash circuit 212 can receive a first set of hash keys that includes R individual keys, each of which is an m-bit binary number. The second hash circuit 222 can receive a second set of hash keys that includes R individual keys, each of which is an n-bit binary number. The third hash circuit 232 can receive a third set of hash keys that includes R individual keys, each of which is an o-bit binary number.

[0044] In some embodiments, each set of hash keys can be independent of each other. In some embodiments, several sets of keys can share one or more individual keys, but can be shortened to occupy different lengths of hash output. In some embodiments, the memory device can generate the hash keys. For example, a random number generator can generate the hash keys based on a seed value.

[0045] In response to the row address XADD, each of the data stacks 210, 220, and 230 can provide a respective count value CV0, CV1, and CV2 to the count logic circuit 202. Because each count value can be associated with a different set (and different number) of values of the row address XADD, the count values can be different from each other. The count adjuster circuit 208 of the count logic 202 can update the received values, for example, by increasing the values. In some embodiments, how the count adjuster 208 changes the count values CV0-CV2 can be based in part on the values of the count values CV0-CV2. For example, if the value CV0 is above a threshold (e.g., has reached a maximum value), then only the count value CV1 can be changed (e.g., increased).

[0046] In some embodiments, the count adjuster circuit 208 can periodically change the count values in different directions (e.g., decrease the values). For example, after a set amount of time (e.g., a certain number of clock cycles), the count adjuster 208 can change (e.g., decrease) all of the count values stored in the data stacks 210, 220, and 230. In some embodiments, the count adjuster 208 can decrease the count values to a minimum value by resetting (e.g., to 0).

[0047] The count locator circuit 204 can select one of the received count values, or can synthesize a new value based on the set of count values CV0-CV2. The count locator circuit 204 can use one or more statistics based on the set of count values CV0-CV2. For example, the count locator circuit 204 can compare the count values CV0-CV2 and take the minimum value. The count locator circuit 204 can also generate a statistic based on the set of count values, and for example, can provide an average or median value of CV0-CV2. In some embodiments, only one of the minimum, median, and average values can be provided. In some embodiments, a user can be able to select which statistic to use. In some embodiments, the count locator can calculate and output all three of the minimum, median, and average values, and can use the values separately. Other example embodiments can use other statistics.

[0048] In some embodiments, the count locator 204 does not use the statistic, but can select one of the count values CV0-CV2. For example, in an embodiment, the count locator 204 can provide a particular count value (e.g., CV2) as long as the previous count value is above a threshold value (e.g., change CV1 if CV0 is greater than the threshold value). In some embodiments, which count value is used can be changed periodically. For example, the count value can be randomly selected.

[0049] The count locator circuit 204 can provide the statistic (e.g., the minimum value) to the threshold comparator circuit 206. The threshold comparator circuit 206 can compare the received statistic to a threshold value Thresh. If the threshold comparator circuit 206 determines that the received statistic is greater than the value Thresh, the count logic circuit 202 can provide the capture signal Capture at an active level (e.g., a high logic level, a pulse, a rising edge, etc.). In some embodiments, the threshold value can be changed periodically. For example, the threshold value Thresh can be randomly changed based on the output of a random number generator RNG.

[0050] The problem logic circuit 240 can receive the signal Capture. When the signal Capture is active, the problem logic circuit 240 can store the current value of the row address XADD in the problem address memory 242. The problem address memory 242 can be a data structure with a plurality of registers, each of which can be used to store a problem row address XADD. In some embodiments, the addresses stored in the problem address memory 242 can be provided out of memory. For example, a controller can perform a read operation and specify the problem address memory, and a list of problem addresses can be retrieved. In some embodiments, these addresses can be deleted from memory when read out. In some embodiments, the count adjuster 208 can decrease the count value associated with those addresses when the addresses are read out. In some embodiments, the addresses in the problem address memory 242 can be repaired.

[0051] In some embodiments, a user can select various features of the error tracking circuit 200. For example, the user can be able to set one or more modes of operation of the error tracking circuit, and / or can be able to enable or disable particular features. In some embodiments, the user can be able to select whether the minimum value, the average value, or the median value is used to generate the comparison value. Similarly, the user can select the threshold value used by the threshold comparator 206. In some embodiments, the user can be able to select a mode of operation, for example, by selecting whether to update (e.g., increase) each count value associated with a row address, or to update the count in a "cascade" fashion with a count value from a first stack (e.g., 210) before updating the count value in a next stack (e.g., 220) that needs to reach a threshold value.

[0052] Figure 3 These are a set of block diagrams illustrating instance operations of a set of data structures according to some embodiments of this disclosure. Figure 3 The block diagram illustrates the operation of different components of an error tracking station. The block diagram represents the data flow within each component and does not necessarily show the structure of that component. In some embodiments, Figure 3 Instance block diagrams can represent the operation of error tracking circuits, such as Figure 1 Error tracking circuit 130 and / or Figure 2 Error tracking circuit 200.

[0053] Figure 3 A block diagram 310 of counting storage is shown, which represents the storage in various data storage structures (e.g., Figure 2 The indexes of the count values ​​within (210, 220, and 230) are shown, with each data storage structure storing multiple count values ​​associated with the associated hash circuit. Count storage block diagram 310 shows the indexes of the storage structures (e.g., stacks) along the vertical axis and the indexes of the stored count values ​​along the horizontal axis. For clarity, letters (e.g., A through D in this example) are used to index different stacks, while numbers are used to index the count values. Note that the numbers shown in block diagram 310 represent the indexes of the individual count values, not the values ​​of those count values.

[0054] exist Figure 3 In Example Figure 310, each of the data storage structures AD is associated with a hash circuit that generates hash values ​​of different lengths. For example, the first data storage structure A is associated with a 9-bit hash circuit that generates 9-bit numbers (e.g., 512 total values). Accordingly, data storage structure A can store 512 distinct count values, indexed from 0 to 511. Similarly, data structure B is associated with an 8-bit hash (e.g., 256 total values), data structure C with a 7-bit hash (e.g., 128 total values), and data structure D with a 6-bit hash (e.g., 64 total values). Accordingly, the memory with these four data structures in total would need to store 960 total values ​​(e.g., 512 + 256 + 128 + 64). Conversely, if the memory included four data structures and each data structure used an 8-bit hash, it would need to track 1,024 distinct values ​​(e.g., 4 * 256).

[0055] When a row address is received (e.g., when the signal ErrDet is received), each hash circuit can generate a hash based on the value of the row address. The circles on block diagram 310 indicate instance group count values ​​that can be activated by a given row address. The first hash circuit can hash the address to the value 247, the second hash circuit can hash the address to the value 19, the third hash circuit can hash the address to the value 101, and the fourth hash circuit can hash the address to the value 1. These are represented in the count value table 320.

[0056] Count value table 320 shows the actual count value associated with a count index, where the count index is associated with a row address. For example, when the first hash circuit receives row address XADD, the count associated with hash value 247 in stack A has a value of 1024. Accordingly, the value 1024 can be used as the count value (e.g., Figure 2 CV0) is provided to the counting logic circuit (e.g., Figure 2 (202).

[0057] Except for Table 330, which indicates that the counter regulator (e.g., Figure 2 Apart from the updated count values ​​(208), Table 330 is similar to Table 320. For example, each count value has been increased (e.g., the count value 247 in stack A has increased from 1024 to 1025). These count values ​​can be written back to the stack. The updated count values ​​shown in Table 330 can also be used to generate statistics for comparison with thresholds.

[0058] In some embodiments, different data stacks can store count values ​​as binary numbers of the same length. In other embodiments, different data stacks can store count values ​​as binary numbers of different lengths. For example, since there are more collisions in data storage structure D, it is generally expected that each count value will be updated (e.g., incremented) more frequently than the count values ​​in data storage structure A (which has fewer collisions because it is associated with a longer hash value). Accordingly, in some embodiments, more bits are available to store each count value in a lower data structure rather than a higher data structure.

[0059] Each count value can represent the number of times an address value hashed to a hash value (which indexes the count) has been received (e.g., identified as containing an error bit). Because each count value can be associated with a different set of address values, the count values ​​can be different from each other. Figure 3 In the instances, the instance row address is associated with count values ​​1025, 3227, 764, and 2676. The counter locator circuit (e.g., Figure 2 (204) can select a minimum count value, which in this case is 764. The count value selected by the counter locator (and / or the value synthesized by the counter locator) can be provided to comparator 340. Comparator 340 (e.g.,Figure 2 The threshold comparator 206) can determine whether the value is above the threshold. If the value is above the threshold, the comparator 340 can provide a signal Capture at the activity level, which can cause the current value of the row address (e.g., the value associated with the circled count value) to be stored in the problem storage structure (e.g., 242) in the memory. Figure 2

[0060] Figure 4 are a set of block diagrams showing example operations of a set of data structures in accordance with some embodiments of the present disclosure. Figure 4 An example is shown in which not all count values associated with a given address are necessarily changed. Figure 4 The elements of Figure 3 The elements of Figure 4 For brevity, Figure 3 Elements in

[0061] As shown in block diagram 410, addresses associated with count values in each of four registers are received. Table 420 shows the indices of the count values and the values of those count values. In particular, the addresses are associated with count value 4095 in stack A, count 2786 in stack B, value 357 in stack C, and value 72 in stack D. Table 420 shows the count values after being updated in response to receiving the row addresses associated with those values. However, unlike Figure 3 In Figure 4 the count values are updated in a cascading manner. In the cascading update manner, the comparator 425 checks whether the count value from a first stack (e.g., stack A) is above a threshold. If the count is below the threshold, the count value from the first stack is updated (e.g., incremented). If the count value is at or above the threshold, the comparator 425 can check the count value from a next stack (e.g., stack B).

[0062] In the example of Figure 4 the count values can be stored as 12-bit numbers (e.g., values from 0 to 4,095). The threshold Thi used by the first comparator can be the maximum value in the count values (e.g., 4,095). Accordingly, when a row address is received, the first comparator 425 can check the first value (in this case, the threshold, e.g., the maximum value 4,095). Since the first count value (e.g., the count of stack A) is the threshold, the comparator 425 can check the second count value (e.g., the count value of stack B). Since that count value (e.g., 2,786) is below the threshold Thi of the first comparator 425, the count value associated with the second stack can be changed (e.g., incremented), as shown in table 430. Since the count value in the second stack is not at or above the threshold of the first comparator 425, the counts in the remaining data structures (e.g., the counts retrieved from stacks C and D) are not checked or updated.​

[0063] In some embodiments, the number of bits used to store the count values can be of different lengths. For example, when updating the count values in a 'cascade' fashion, it can generally be expected that the counts in lower data structures (e.g., stack D) can be lower values than the counts in higher data structures (e.g., stack A). Accordingly, fewer bits can be used to store the count values in the lower data structures. For example, 12 bits can be used to store each count value in the top data structure (e.g., stack A), while 8 bits can be used to store each count value in the bottom data structure (e.g., stack D). Other examples can use other example numbers of bits. This can further reduce the number of bits tracked (in total) in the collected data structures.

[0064] In Figure 4 instances, the count values can be selected based on the data structure in which they reside, rather than computing statistics based on the set of count values. For example, the count values of the last data stack (e.g., stack D) can be used. In Figure 4 instances, the value is 72. In some embodiments, other data stacks can be used to select a value for comparison by the second comparator 440. In some embodiments, which data structure's count values are used can vary (e.g., can be randomly selected). In some embodiments, each data stack can be associated with a different threshold in the comparator 440.

[0065] Figure 5 is a schematic diagram of an error correction code (ECC) control circuit according to some embodiments of the present disclosure. In some embodiments, Figure 5 ECC control circuit 500 of Figure 1 ECC control circuit 120. The ECC control circuit 500 can receive write data bits WD and can generate written parity bits WP. These can be provided as data bits D and parity bits P to a memory array. The ECC control circuit 500 can receive data D from the memory array as read data RD, receive parity bits P as read parity bits PR, and can generate corrected data bits CRD based on the bits RD and PR.

[0066] During an example read operation, read amplifiers 501 are activated to amplify read parity bits PR and read data RD. The amplified bits PR and RD are provided to syndrome generator circuit 520. The syndrome generator circuit 520 provides syndrome bits S based on the read bits RD and PR. In some embodiments, the number of syndrome bits S can match the number of parity bits PR. The syndrome bits S are provided to error locator circuit 525.

[0067] The error locator circuit 525 includes two parts: a first error locator circuit 530 and a second error locator circuit 540. The first error locator circuit 530 provides a first set of error determination signals EBST and a second set of error determination signals EDQ based in part on the syndrome bits S. The data provided to / received at the DQ terminals can be grouped into data strings on different DQ terminals (e.g., 8-bit data strings on each of 16 different DQ terminals for 128 total bits). The first set of error determination signals EBST can indicate the location of error bits in the data string. In some embodiments, there can be one bit for each bit in the data string, and the signal EBST can be provided with the DQ terminals. The second set of error determination signals EDQ can indicate which DQ terminal the error bit is being provided to. In some embodiments, there can be one bit for each DQ terminal, and the signal EDQ can be provided with the data string bits.

[0068] The error determination signals EBST and EDQ can be provided to the second error locator circuit 540. The second error locator circuit 540 can decode the signals EBST and EDQ to identify the location of error bits in the read data RD. The location of the error bits can be specified by an error location signal EL. In some embodiments, there can be multiple bits of the error location signal EL, each associated with a bit of the read data RD, based on the number of bits of the read data RD.

[0069] When an error in the read data RD is detected, the error locator circuit 525 can provide a signal ErrDet at the active level. For example, the error locator circuit 525 provides the signal ErrDet based on the syndrome signal S. The signals from the first or second error locator circuits 530 and 540 can be used as the error check signal ErrDet. For example, error detection logic can receive one or more of the signals EDQ, EBST, and ELT, and provide the signal ErrDet at the active level in response to at least one of those signals being at the active level.

[0070] The error location signal EL is provided to the error corrector circuit 550. The error corrector circuit 550 also receives the read data RD and corrects one or more error bits in RD based on the error location signal EL. For example, if the nth bit of the error location signal EL is at a high logic level, the error corrector circuit 550 can change the state of the nth read bit RD. The error corrector circuit 550 can provide corrected read data CRD. The corrected read data CRD can be provided to the DQ disk and read from the device.

[0071] In an example write operation of a memory device, the ECC control circuit 500 can receive write data WD and data mask signals DM. The first multiplexer 503 can synthesize the write data WD and corrected read data CRD based on the data mask signals DM. The first multiplexer 503 can provide data D to be written to the memory array. In some embodiments, the data mask signals DM can be associated with different data string bits received at the data terminals. When one (or more) of the data mask bits DM is active, the write data WD associated with that data mask bit can be replaced with the corrected read data CRD in the data D.

[0072] The second multiplexer 504 can synthesize the write data WD and read data RD based on the data mask signals. The second multiplexer 504 can provide parity write data PWD. The parity write data PWD can be provided to the encoder circuit 510, which can encode the parity data PWD into write parity WP’. The write parity WP’ is provided to the translator circuit 505, which generates the write parity WP to be written as parity bits P to the memory array.

[0073] The translator circuit 505 includes an XOR logic gate 505a and a third multiplexer 505b. The XOR logic gate 505a has input terminals coupled to the syndrome bits S and the write parity bits WP’. The XOR logic gate 505a provides an output at a high logic level when the syndrome bits S and the associated write parity bits WP’ are different. The third multiplexer 505b provides the output of the XOR logic gate 505a or the write parity WP’ as the write parity WP. The multiplexer 505b selects the source of the write parity WP bits based on the translation signal EDM. When the translation signal EDM is active, the write parity WP is the output of the XOR gate 505a. When the translation signal EDM is inactive, the signal WP’ is provided as the signal WP.

[0074] The mask error detector circuit 560 provides the signal EDM based on the syndrome bits S and the data mask DM. The mask error detector circuit 560 can determine whether the error bit belongs to the same data string data as the data string data masked by the data mask signal DM. If so, the signal EDM can be activated. If not, the signal EDM can remain inactive.

[0075] Figure 6 is a block diagram of a method of tracking row addresses associated with errors according to some embodiments of the present disclosure. In some embodiments, the method 600 can be implemented by one or more components discussed in Figure 1 to Figure 5 While a certain order of operations is discussed with respect to the method 600, it should be understood that certain operations can be performed in a different order, repeated, and / or omitted in other embodiments. In some embodiments, certain steps can occur simultaneously.

[0076] Method 600 can generally begin at block 610, which describes hashing a row address to a first hash that contains a first number of bits. The first hash circuit (e.g., 212 of FIG. 2) can be an m-bit hash. The first number of bits can generally be shorter than the length of the row address. Accordingly, the first hash can be associated with a first set of row addresses. Figure 2

[0077] Block 620 can generally follow block 610, which describes changing a first count value associated with a value of the first hash. The first hash can be used as an index to a first set of count values (e.g., stored in data storage structure 210 of FIG. 2). The count value associated with the value of the first hash can be changed, e.g., incremented (e.g., by count adjuster 208). Figure 2

[0078] Blocks 610 and 620 can generally occur concurrently with blocks 630 and 640. Block 630 describes hashing a row address to a second hash that contains a second number of bits. The second number of bits can be different than the first number of bits. The second hash can be generated by a second hash circuit (e.g., 222 of FIG. 2), and can be an n-bit hash. The n-bit hash can also be shorter than the number of bits of the row address. Figure 2

[0079] Block 640 can generally follow block 630, which describes changing a second count value associated with a value of the second hash. The second hash can be used as an index to a second set of count values (e.g., stored in data storage structure 220 of FIG. 2). The count value associated with the value of the second hash can be changed, e.g., by incrementing. Figure 2

[0080] Block 650 can generally follow blocks 620 and 640, which describes storing the row address in a data stack based on the first count value, the second count value, or a combination thereof. For example, the count locator circuit (e.g., 204 of FIG. 2) can select the minimum of the first count value and the second count value as a comparison value and compare it to a threshold value. If the comparison value is greater than the threshold value, the received row address can be stored in a problem address storage data structure (e.g., 242 of FIG. 2). Example embodiments can use other values as the comparison value, including other statistical quantities such as the mean or median, or select a particular count value based on the data structure storing the count values. In some embodiments, a user can select how the comparison value is selected. In some embodiments, multiple comparison values can be generated, each of which can be compared to a threshold value, and the memory can have multiple problem address storage structures that store addresses based on different comparison values. Figure 2 Figure 2

[0081] Figure 7 ​​​​​​This is a block diagram of a hash circuit according to some embodiments of the present disclosure. In some embodiments, the hash circuit 700 can be used as... Figure 2 Hash circuits 212, 222, and / or 232. To explain the general operation of hash circuits, Figure 7 The hash circuit 700 represents a simplified diagram of the operation of the hash circuit. The hash circuit of this disclosure can use more complex logic and / or other processes to convert the input signal into a hash.

[0082] Figure 7 The hash circuit 700 is shown to include a random number generator (RNG) 702, which can be used to generate the set of hash keys Key based on a seed value Seed. Figure 7 In some embodiments, RNG 702 may be included in hash circuit 700, which may directly receive a seed value Seed to generate a set of keys. In some embodiments, RNG 702 may be a system-level component and may not be included in each individual hash circuit. In some embodiments, RNG 702 may be omitted, and other methods may be used to generate the key.

[0083] The hash circuit 700 can receive an input value, which can be an N+1-bit number (e.g., Input<0:N>). In some embodiments, the value Input can be a row address. The hash circuit 700 can generate an output value, Hash, which can be an M+1-bit number (e.g., Hash<0:M). The value M can generally be a number less than the value N.

[0084] RNG 702 generates a set of keys based on values ​​N and M. Specifically, RNG 702 generates N+1 keys, each of length M+1. Box 704 can combine each key in this set of keys with a bit of the input value. For example, each bit of the input value (e.g., Input...) ) can be combined with the corresponding key in the key Ki<0:M> to generate a Word. So, the first bit can be combined with the first key, and so on. In Figure 7 In the example of FIG. 7, AND logic can be used to combine each bit of Input with the associated key. Each word can be M+1 bits long, and there can be a set of N+1 words after each bit of Input is combined with the associated key.

[0085] Block 706 can combine the words together to generate the output Hash. In the example of FIG. 7, XOR logic can be used to combine all of the words together. Once the words are combined, the output can be the output value Hash (length M+1 bits). Figure 7

[0086] It will of course be understood that, in accordance with the present systems, apparatus, and methods, any one of the examples, embodiments, or processes described herein can be combined with one or more other examples, embodiments, and / or processes, and / or performed between separate apparatuses or portions of apparatuses, in accordance with the present systems, apparatus, and methods.

[0087] Finally, the above discussion is meant to be illustrative only of the present systems, and should not be construed to limit the appended claims to any particular embodiment or group of embodiments. Accordingly, while the present systems have been described herein in detail and with reference to exemplary embodiments, it is to be understood that the systems are not limited to the disclosed embodiments or examples, and that many modifications and variations are possible without departing from the spirit or scope of the systems as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.​

Claims

1. A semiconductor device comprising: a first hash circuit configured to receive a row address and to hash the received row address to a first hash comprising a first number of bits; a plurality of first registers configured to store a first set of count values; a second hash circuit configured to receive the row address and to hash the received row address to a second hash comprising a second number of bits different from the first number of bits; a plurality of second registers configured to store a second set of count values; a count logic circuit configured to index a first count value of the stored first set of count values selected based on the first hash, to index a second count value of the stored second set of count values selected based on the second hash, and to compare the first count value, the second count value, or a combination thereof to a threshold value; a problem address storage structure configured to store the row address as a stored problem address if the first count value, the second count value, or a combination thereof exceeds the threshold value.

2. The semiconductor device of claim 1, further comprising: a memory array configured to provide read data based in part on a row address; and an error correction code (ECC) circuit configured to detect an error in the read data and to provide an error detection signal at an active level when an error is detected, wherein the first hash circuit and the second hash circuit are configured to receive the row address as the received row address when the error detection signal is at the active level.

3. The semiconductor device of claim 1, wherein the count logic circuit is configured to increment the first count value and the second count value.

4. The semiconductor device of claim 1, wherein the count logic circuit is configured to provide a command signal at an active level based on comparing a minimum value, a median value, an average value, or a combination thereof of the first count value and the second count value to the threshold value, wherein the problem address storage structure is configured to store the received row address in response to the command signal at the active level.

5. The semiconductor device of claim 1, further comprising a count regulator circuit configured to reset the first count value and the second count value based on a timer.

6. The semiconductor device of claim 1, further comprising a random number generator configured to provide a random number, wherein the threshold value is adjusted based on the random number.

7. The semiconductor device of claim 1, wherein the first count value is associated with a first number of row address values, and wherein the second count value is associated with a second number of row address values different from the first number.

8. A semiconductor device comprising: a memory array comprising a plurality of word lines; an error correction code (ECC) circuit configured to identify a row address based on one or more errors in data read from one of the plurality of word lines associated with the row address; a first hash circuit configured to receive the row address and to hash the received row address to a first hash; a first stack comprising a plurality of first registers configured to store a first set of count values, each of the first set of count values being associated with a first number of the plurality of word lines, wherein the first stack is configured to provide a first count value selected based on the first hash; a second hash circuit configured to receive the row address and hash the received row address to a second hash; a second stack comprising a plurality of second registers configured to store a second set of count values, each of the second set of count values being associated with a second number of the plurality of word lines, wherein the second number is different than the first number, and wherein the second stack is configured to provide a second count value selected based on the second hash; and a problem address storage configured to store the identified row address based on the first count value, the second count value, or a combination thereof.

9. The semiconductor device of claim 8, further comprising a count logic circuit configured to compare the first count value to a threshold value and to increase the second count value in response to the first count value exceeding the threshold value, and wherein the count logic circuit is further configured to index the first count value of the first set of stored count values selected based on the first hash and to index the second count value of the second set of stored count values selected based on the second hash.

10. The semiconductor device of claim 9, wherein the problem address storage is configured to store the identified row address based on the second count value.

11. The semiconductor device of claim 8, further comprising a count logic circuit configured to provide a command signal at an active level when a comparison value exceeds a threshold value, wherein the comparison value is a minimum value, an average value, a median value, or a combination thereof of the first count value and the second count value, and wherein the problem address storage is configured to store the identified row address based on the command signal at the active level.

12. The semiconductor device of claim 11, wherein the threshold value is based in part on a random number.

13. The semiconductor device of claim 8, wherein the first hash is used as an index for the plurality of first registers of the first stack, and wherein the second hash is used as an index for the plurality of second registers of the second stack, wherein the first hash is different in length than the second hash.

14. The semiconductor device of claim 13, wherein the first hash comprises a first number of bits, and wherein the second hash comprises a second number of bits different than the first number of bits.

15. The semiconductor device of claim 14, wherein the row address comprises a third number of bits, and wherein each of the first number of bits and the second number of bits is less than the third number of bits.

16. A method for a semiconductor device, the method comprising: receiving a row address; hashing the row address to a first hash comprising a first number of bits; selecting a first count value from a plurality of first count values based on a value of the first hash; changing the first count value; hashing the row address to a second hash comprising a second number of bits different from the first number of bits; selecting a second count value from a plurality of second count values based on a value of the second hash; changing the second count value; comparing the first count value, the second count value, or a combination thereof to a threshold value; and based on the comparison, storing the row address in a data stack.

17. The method of claim 16, further comprising: reading data from a memory array based on the row address; determining whether the data includes any errors using error correction code (ECC) circuitry; and if the data includes at least one error, hashing the row address to the first hash and the second hash.

18. The method of claim 16, further comprising storing the row address in the data stack based on an average, a median, a minimum, or a combination thereof of the first count value and the second count value exceeding a threshold value.

19. The method of claim 16, further comprising changing the second count value if the first count value is above a threshold value.

20. The method of claim 19, further comprising storing the row address in the data stack based on a comparison of the second count value to a second threshold value. ​

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