Methods for forming vertical transistor arrays and memory cell arrays

Abstract

This application relates to methods for forming vertical transistor arrays and memory cell arrays. One method for forming a vertical transistor array includes forming pillars, each pillar individually including an upper source / drain region, a channel region vertically below the upper source / drain region, and a sacrificial material above the upper source / drain region. An interposer material surrounds the sacrificial material of each of the pillars. The interposer material and the sacrificial material comprise different compositions from each other. Horizontally elongated and spaced conductive gate lines are operatively formed individually next to the channel region of each individual pillar. The sacrificial material is removed to expose the upper source / drain region of each individual pillar, thereby forming an opening in the interposer material directly above the upper source / drain region of the individual pillar.

Description

Technical Field

[0001] The embodiments disclosed herein relate to methods for forming vertical transistor arrays and methods for forming individual memory cell arrays including vertical transistors and memory devices above the vertical transistors. Background Technology

[0002] Memory is a type of integrated circuit system used in computer systems to store data. Memory can be manufactured as one or more arrays of individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines, gate lines, or gate lines). Digital lines electrically interconnect memory cells along the columns of the array, and access lines electrically interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of digital lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods without power. Non-volatile memory is typically defined as memory with a retention time of at least approximately 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In binary systems, these states are considered either "0" or "1". In other systems, at least some individual memory cells can be configured to store more than two information levels or states.

[0004] A capacitor is a type of electronic component that can be used in a memory cell. A capacitor has two electrical conductors separated by an electrically insulating material. Energy as an electric field can be stored electrostatically within this material. Depending on the composition of the insulating material, the stored field will be volatile or non-volatile. For example, a capacitor insulating material containing only SiO2 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor, which has at least a portion of a ferroelectric material as the insulating material. Ferroelectric materials are characterized by having two stable polarization states, and thus can be programmable materials that can comprise capacitors and / or memory cells. The polarization states of the ferroelectric material can be changed by applying a suitable programming voltage and remain thereafter (at least for a period of time) after the programming voltage is removed. Each polarization state has a charge storage capacitance different from the other, and ideally can be used to write (i.e., store) and read the memory state without reversing the polarization state until it is desired to reverse it. Less ideally, in some memories with ferroelectric capacitors, the act of reading the memory state may reverse the polarization. Therefore, when the polarization state is determined, the memory cell is rewritten to place the memory cell in a read-ahead state immediately after its determination. Regardless, due to the bistable nature of the ferroelectric material that forms part of the capacitor, the memory cell incorporating a ferroelectric capacitor is ideally non-volatile. Other programmable materials can be used as capacitor insulators to make the capacitor non-volatile.

[0005] Field-effect transistors (FETs) are another type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel region between them. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is largely prevented. FETs may also include additional structures, such as a reversible programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate. In any case, the gate insulator can be programmable, for example, ferroelectric.

[0006] Of course, capacitors and transistors can be used in integrated circuit systems other than memory circuit systems. Summary of the Invention

[0007] This disclosure relates to a method for forming a vertical transistor array, comprising: forming pillars, each pillar individually including an upper source / drain region, a channel region vertically below the upper source / drain region, and a sacrificial material above the upper source / drain region; an interposer surrounding the sacrificial material of each of the pillars, the interposer and the sacrificial material comprising different compositions from each other; operably forming horizontally elongated and spaced conductive gate lines unilaterally adjacent to the channel region of each pillar; removing the sacrificial material to expose the upper source / drain region of the individual pillars, and thereby removing the interposer surrounding the sacrificial material. An opening is formed directly above the upper source / drain region of the individual pillar in the material; a metal material is formed in the individual pillar within the opening, directly abutting the upper source / drain region of the individual pillar, and on top of the intermediate material on the lateral outer side of the opening, the metal material on top of the intermediate material interconnecting the metal materials in the individual opening; and the metal material is removed back to have an uppermost surface not higher than the uppermost surface of the intermediate material, and disconnected to prevent the metal materials in the individual opening from interconnecting, thereby forming a laterally isolated individual metal plug in the individual opening.

[0008] In another aspect of this disclosure, a method for forming a vertical transistor array includes: forming pillars, each pillar individually including an upper source / drain region, a channel region vertically below the upper source / drain region, and a sacrificial material above the upper source / drain region; an interposer surrounding the sacrificial material of the individual pillars, the interposer and the sacrificial material comprising compositions distinct from each other; operably forming horizontally elongated and spaced conductive gate lines adjacent to the channel region of the individual pillars; removing the sacrificial material to expose the upper source / drain region of the individual pillars, thereby forming an opening in the interposer directly above the upper source / drain region of the individual pillars; after the initial formation of the opening, laterally widening the individual pillars in a vertical cross-section above the upper source / drain region; forming a metallic material in the individually widened opening, directly abutting the individual pillars. The upper source / drain region of the pillar, and on top of the intermediate material on the lateral outer side of the widened opening, the metal material on top of the intermediate material interconnects the metal materials in the individual widened openings; the metal material is removed back to have an uppermost surface not higher than the uppermost surface of the intermediate material, and disconnected to prevent the metal materials in the individual openings from interconnecting, and thus forming laterally isolated individual metal material plugs in the individual openings, the metal material and the upper source / drain region having different compositions from each other, the back removal of the metal material removes all the metal material from the top of the intermediate material, after the back removal of the metal material, the uppermost surface of the metal material and the uppermost surface of the intermediate material are coplanar; after forming the laterally isolated individual metal material plugs, the intermediate material is selectively etched perpendicularly relative to the metal material plugs.

[0009] In another aspect of this disclosure, a method for forming an array of memory cells, each including a vertical transistor and a memory device above the vertical transistor, comprises: forming horizontally elongated and spaced digital lines, the digital lines individually interconnecting a corresponding plurality of the vertical transistors in a column direction; forming pillars, the pillars being on top of and directly electrically coupled to the individual digital lines; each pillar individually including an upper source / drain region, a channel region vertically below the upper source / drain region, and a sacrificial material above the upper source / drain region; an interposer surrounding the sacrificial material of the individual pillars, the interposer and the sacrificial material comprising compositions distinct from each other; operably forming horizontally elongated and spaced conductive gate lines adjacent to the channel region of the individual pillars, and individually interconnecting a corresponding plurality of the vertical transistors in a row direction; removing the... Sacrificial material is used to expose the upper source / drain regions of the individual pillars, thereby forming an opening in the intermediate material directly above the upper source / drain regions of the individual pillars; a metallic material is formed in one of the openings, directly abutting the upper source / drain regions of the individual pillars, and on top of the intermediate material laterally outside the opening, the metallic material on top of the intermediate material interconnecting the metallic materials in the individual openings; the metallic material is removed back to have an uppermost surface not higher than the uppermost surface of the intermediate material, and disconnected to prevent the metallic materials in the individual openings from interconnecting, thereby forming laterally isolated individual metallic plugs in the individual openings; and after removing the metallic material, a storage device is formed, the storage device being individually above and electrically coupled to one of the individual metallic plugs. Attached Figure Description

[0010] Figure 1 This is a schematic cross-sectional view of a portion of the substrate during the process according to an embodiment of the present invention, and is shown by... Figure 2 and 3 Obtain line 1-1 from the middle.

[0011] Figure 2 Through Figure 1 The diagrammatic cross-sectional view obtained from line 2-2 in the figure.

[0012] Figure 3 Through Figure 1 The diagrammatic cross-sectional view obtained from line 3-3 in the figure.

[0013] Figures 4 to 27 It is in the process according to some embodiments of the present invention Figures 1 to 3 The illustrated sequential cross-sections, unfolded, enlarged and / or partial views of the structure or its parts or alternative embodiments thereof. Detailed Implementation

[0014] Embodiments of the present invention include methods for forming vertical transistor arrays, such as methods for forming individual memory cell arrays comprising vertical transistors and memory devices above the vertical transistors. (See reference...) Figures 1 to 27 An example method embodiment for forming a memory cell array is described.

[0015] refer to Figures 1 to 3 This illustrates a portion of a substrate structure 10, which includes a base substrate 11 comprising any one or more of conductive / conductive / conductive, semiconductive / semiconductor / semiconductive, and insulating / insulator / insulator (i.e., electrically) materials herein. Various materials may be vertically formed over and within the base substrate 11. Materials may be... Figures 1 to 3 The material depicted may be adjacent to, vertically inside, or vertically outside the substrate. For example, other parts of the integrated circuit system or fully fabricated components may be disposed above, around, or within the substrate 11. Regarding the memory circuitry system, control and / or other peripheral circuitry systems for operating components within the memory cell array may also be fabricated, and may or may not be fully or partially within the array or subarrays. Furthermore, multiple subarrays may be fabricated and operated independently, collaboratively, or otherwise relative to each other. As used in this document, "subarray" may also be considered an array.

[0016] Example substrate 11 is shown comprising horizontally elongated and spaced conductive digital lines 26, which individually interconnect corresponding plurality of vertical transistors (not yet shown) in direction 28 (e.g., column direction). An insulating material 17 (e.g., silicon nitride and / or silicon dioxide) is positioned between the digital lines 26. Line 73 is formed on top of the digital lines 26 and the insulating material 17. Line 73 comprises materials suitable for forming the source / drain regions and channel regions of the vertical transistors, as will become apparent from the continuing discussion. Polycrystalline silicon is one such material, by way of example only, and in any case, if ultimately doped, then during the process, the final concentration of impurities may or may not be appropriately doped to modify conductivity. A sacrificial material 27 (e.g., silicon nitride) co-extends with line 73 on top (e.g., with a thickness of 200 to 300 angstroms). Insulating materials 34 and 35 are shown between line 73 and sacrificial material 27. Example materials are silicon carbide (34) and silicon dioxide (35; for example, produced by spin-coating dielectric and associated processing).

[0017] refer to Figures 4 to 6 , Figures 1 to 3 The materials of line 33, material 27, and materials 34 and 35 have been patterned in direction 24 (e.g., row direction) to form pillar 29, which sits atop individual digital lines 26 and is directly electrically coupled to them. Figures 4 to 6Prior to the treatment (not shown), more sacrificial material 27 may have already been deposited. Figures 1 to 3 On top of the structure, the lines of sacrificial material 27 (not shown) extend along direction 24 on top of the pillar 29. In any case, the pillar 29 includes an upper source / drain region 32 and a channel region 15 vertically below it. In one embodiment, and as shown, the pillar 29 also includes a lower source / drain region 30 vertically below the channel region 15. Alternatively, and only as an example, the pillar 29 may not include a lower source / drain region, which is an inherent portion of the uppermost portion of the individual digit lines 26 immediately below it (not shown). The pillar 29 also includes sacrificial material 27 above the upper source / drain region 32. In one embodiment, the upper source / drain region 32 comprises a conductive-doped semiconducting material, wherein the sacrificial material 27 directly abuts the semiconductor material.

[0018] refer to Figures 7 to 9 Horizontally elongated and spaced conductive gate lines 33 have been operably and individually formed adjacent to the channel region 15 of the individual pillars 29. Prior to the formation of the gate lines 33, gate insulators 31 (e.g., silicon dioxide and / or silicon nitride) have been formed adjacent to the pillars 29 (e.g., some or all of the insulating material 34 has been previously removed). The gate lines 33 may be formed largely in a self-aligned manner, for example, by depositing, for example, a conformal layer adjacent to the depicted pillars 29, followed by maskless anisotropic etching to remove this substantially above the horizontal surface. This may or may not overlap laterally with some of the upper and lower source / drain regions. In any case, the tip of the gate line 33 can be determined by timing the etching of the material of such gate lines. For example, the tip can be determined by depositing insulating and / or sacrificial material (not shown) to have a tip at the desired tip of the conductive gate line 33. In any case, the subsequent processing is shown to include the deposition of insulating material 36 (e.g., a combination of deposited silicon carbide and silicon dioxide processed by spin dielectric treatment, as with respect to materials 34 and 35 respectively). Figures 7 to 9 An example processing has been demonstrated to form individual vertical transistors 75, wherein gate lines 33 individually interconnect the respective plurality of vertical transistors 75 in direction 24 (e.g., row direction 24).

[0019] The above process is merely one example of forming pillar 29, which is on top of and directly electrically coupled to individual digital lines 26, and has an intermediary material (e.g., 31, 34 / 35, 36) surrounding the sacrificial material 27 of the individual pillar 29. The intermediary materials 31, 34 / 35, 36 and the sacrificial material 27 comprise compositions different from each other. Any other technique may be used. In one embodiment, and as shown, the intermediary materials 31, 34 / 35, 36 comprise a first intermediary material 31, 34 / 35 and a second intermediary material 36, each comprising a composition different from the composition of the sacrificial material 27. The second intermediary material 36 is formed after the gate line 33 is formed. In one of these embodiments, the first intermediary materials 31, 34 / 35 are formed before the gate line 33 is formed, and the second intermediary material 36 is formed after the first intermediary material 34 / 35 is formed.

[0020] refer to Figures 10 to 12 The sacrificial material 27 (not shown) has been removed (e.g., by selective isotropic or anisotropic etching) to expose the upper source / drain regions 32 of the individual pillars 29, thereby forming an opening 37 directly above the upper source / drain regions 32 of the individual pillars 29 in the intermediate materials 31, 34 / 35, 36.

[0021] refer to Figures 13 to 15 Individual openings 37 have already been formed after their initial formation, above the upper source / drain region 32 in a vertical cross-section (e.g., Figure 15 Laterally widened in a cross-section (e.g., by isotropic etching) in the direction 28. In one embodiment and as shown, individual openings 37 have already been formed after their initial formation, in a cross-section (e.g., in a perpendicular cross-section). Figure 14 The lateral widening occurs above the upper source / drain region 32 in another vertical cross-section orthogonal to the cross-section along direction 24. In a later embodiment, this lateral widening occurs simultaneously in both the one and the other vertical cross-sections (e.g., by isotropic etching).

[0022] refer to Figures 16 to 18 Metal material 40 is formed in individual openings 37, directly abutting the upper source / drain regions 32 of individual pillars 29, and laterally outside the openings 37 on top of the intermediate materials 31, 34 / 35, 36 (e.g., on top of their uppermost surface 46). The metal material 40 on top of the intermediate materials 31, 34 / 35, 36 interconnects the metal materials 40 in the individual openings 37. In one embodiment, the metal material 40 comprises titanium nitride 42 and elemental tungsten 43, and in one embodiment includes metal silicide 41 (e.g., WSi below it). xIn this embodiment, the metal silicide 41 directly contacts the titanium nitride 42. However, in one embodiment, as shown, the metal material 40 is formed on top of the second interposer 36, wherein the uppermost surface 46 of the interposer includes the uppermost surface of the second interposer 36. Alternatively, in one embodiment, the first interposer is formed before the gate line is formed, and the second interposer is formed after the first interposer is formed, with the metal material formed on top of the first interposer, and the uppermost surface of the interposer including the uppermost surface of the first interposer.

[0023] refer to Figures 19 to 21 The metal material 40 has been removed back (e.g., by chemical mechanical polishing, resist etching, or other etching) to have a surface 45 no higher than the uppermost surface 46 of the intermediate material 31, 34 / 35, 36, and disconnected to prevent the metal materials 40 in the individual openings 37 from interconnecting, thereby forming laterally isolated individual metal material plugs 50 in the individual openings 37. Thus, in one embodiment, this is shown in a horizontal cross-section (e.g., Figure 19 An example method of forming the metal plug 50 in a fully circumferentially self-aligned manner (without additional subtractive patterning of the metal material 40 using a mask above the intermediate materials 31, 34 / 35, 36 in the array region 12). The uppermost surface 46 of the intermediate materials 31, 34 / 35, 36 may be moved downward during this removal of the metal material 40 (not shown). In any case and in one embodiment, after the metal material 40 is removed back, each of the uppermost surface 45 of the metal material 40 and the uppermost surface 46 of the intermediate materials 31, 34 / 35, 36 is planar and, in one embodiment, coplanar. Alternatively and only by way of example, the top surface of the metal material 40 may be lower than the top surface of the intermediate materials 31, 34 / 35, 36, regardless of whether any of them is planar (not shown). In any case, and in one embodiment as shown, removing the metal material 40 back removes all of this metal material on top of the intermediate materials 31, 34 / 35, 36. In one embodiment, the metal material 40 and the upper source / drain region 32 have different compositions from each other.

[0024] refer to Figures 22 to 24 After the individual metal plugs 50 are formed to be laterally isolated, the intermediate materials 31, 34 / 35, 36 have been selectively etched perpendicularly relative to the metal plugs 50, and in one embodiment, the uppermost surface 46 of the intermediate materials 31, 34 / 35, 36 is formed below the bottom 52 of the metal plugs 50.

[0025] refer to Figures 25 to 27In one embodiment, silicon nitride 53 has been formed to replace the removed vertically etched intermediate materials 31, 34 / 35, 36. In any case, and in one embodiment, after removing the metal material 40 to form the metal material plug 50, a storage device 85 is formed, which is individually above and electrically coupled (e.g., directly electrically coupled to) one of the individual metal material plugs 50. Any suitable storage device can be used, wherein the storage device 85 is schematically shown as a capacitor having a lower capacitor electrode 86, an upper capacitor electrode 88, and a capacitor insulator 87 therebetween. By way of example only, the upper capacitor electrode 88 may be a capacitor plate or wire shared by all capacitors within the array 12.

[0026] The aforementioned processing or construction can be viewed relative to an array of components formed as a single stack or single layer of such components above or as part of the underlying substrate, or within such a single stack or single layer (although a single stack / layer may have multiple levels). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed anywhere as part of the completed construction, and in some embodiments may be below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / layers may be provided or fabricated above and / or below the stacks / layers shown in the figures or described above. Furthermore, the arrays of components may be the same or different from each other in different stacks / layers, and the different stacks / layers may have the same or different thicknesses from each other. Intermediate structures may be disposed between vertically adjacent stacks / layers (e.g., additional circuitry and / or dielectric layers). Similarly, different stacks / layers may be electrically coupled relative to each other. Multiple stacks / layers may be fabricated individually and sequentially (e.g., one on top of another), or two or more stacks / layers may be fabricated substantially simultaneously.

[0027] The assemblies and structures discussed above can be used in integrated circuit / circuit systems and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power supply modules, communication modems, processor modules, and special-purpose modules, and can contain multi-layered, multi-chip modules. Electronic systems can be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting equipment, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0028] In this document, unless otherwise indicated, “vertical,” “higher,” “up,” “lower,” “top,” “top,” “bottom,” “above,” “below,” “below,” “under,” “upward,” and “downward” generally refer to the vertical direction. “Horizontal” means along a generally perpendicular direction (i.e., within 10 degrees) relative to the direction in which the substrate is processed during manufacturing, and vertical is a direction generally orthogonal to horizontal. The reference to “precise horizontal” is along a generally perpendicular direction (i.e., not at an angle) relative to the direction in which the substrate is processed during manufacturing. Furthermore, as used herein, “vertical” and “horizontal” are generally perpendicular to each other and are independent of the orientation of the substrate in three-dimensional space. Additionally, “vertically extending” and “extending vertically” refer to a direction deviating at least 45° from the precise horizontal. Furthermore, regarding field-effect transistors, “extending vertically,” “vertically extending,” “horizontally extending,” “horizontally extending,” and the like refer to the orientation of the transistor’s channel length along which current flows between the source and drain regions during operation. For bipolar junction transistors, "extending vertically," "extending vertically," "extending horizontally," and the like are orientations that refer to the length of the substrate along which current flows between the emitter and collector during operation. In some embodiments, any component, feature, and / or region extending vertically extends vertically or within 10° of the vertical.

[0029] Furthermore, "directly above," "directly below," and "directly under" require that the two stated areas / materials / components have at least some lateral overlap (i.e., horizontally) relative to each other. Moreover, using "directly above" without the preceding "directly" only requires that a portion of the area / material / component above another area / material / component is vertically outside of that other area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components). Similarly, using "below" and "under" without the preceding "directly" only requires that a portion of the area / material / component below / beneath another area / material / component is vertically inside that other area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components).

[0030] Any of the materials, regions, and structures described herein may be homogeneous or heterogeneous, and in any event may be continuous or discontinuous over any overlying material. Where one or more example compositions are provided for any material, the material may comprise, consist substantially of, or be composed of such one or more compositions. Furthermore, unless otherwise stated, each material may be formed using any suitable existing or yet-to-be-developed technique, examples of which include atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation.

[0031] Furthermore, “thickness” itself (without a directional adjective) is defined as the average straight-line distance perpendicular to the nearest surface of adjacent materials or regions of different compositions through a given material or region. Additionally, the various materials or regions described herein may have substantially constant or variable thicknesses. If a variable thickness is present, then the thickness refers to the average thickness, unless otherwise indicated, and this material or region will have a minimum and a maximum thickness due to the variable thickness. As used herein, “different compositions” only requires that portions of two said materials or regions that can directly contact each other are chemically and / or physically different (e.g., if such materials or regions are not homogeneous). If two said materials or regions are not directly contacting each other, then “different compositions” only requires that the closest portions of two said materials or regions are chemically and / or physically different (if such materials or regions are not homogeneous). In this document, a material, region, or structure is “directly contacting” another when there is at least one physical contact between the materials, regions, or structures. In contrast, the words “above,” “on,” “adjacent to,” “alongside,” and “against” without the preceding “direct” encompass “direct contact” and constructions in which (some) intermediate materials, (some) areas, or (some) structures cause the materials, areas, or structures to be in contact with each other without physical contact.

[0032] In this document, if, during normal operation, current can flow continuously from one zone-material-component to another, and this is done primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated, then the zone-material-components are “electrically coupled” to each other. Another electronic component may be electrically coupled between and to the zone-material-components. In contrast, when zone-material-components are referred to as “directly electrically coupled,” there are no intermediate electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between directly electrically coupled zone-material-components.

[0033] In this document, any use of the terms "row" and "column" is for the convenience of distinguishing one series or orientation of features from another series or orientation of features along which components have been or may be formed. "Row" and "column" are used synonymously with any series of areas, components, and / or features and are not related to function. In any case, rows may be straight and / or curved and / or parallel and / or non-parallel to each other, and columns may be as well. Furthermore, rows and columns may intersect each other at 90° or one or more other angles (i.e., other than right angles).

[0034] Combinations of any of the conductive / conductor / conductive materials mentioned herein may be metallic materials and / or conductive-doped semiconducting / semiconductor / semiconductive materials. "Metallic material" is any elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metallic compounds, or combinations thereof.

[0035] In this document, any use of "selective" in relation to etching, removal, deposition, and / or forming is an action in which one material is acted relative to another(s) of said materials at a rate of at least 2:1 by volume. Furthermore, any use of selective deposition, selective growth, or selective forming is the deposition, growth, or formation of a material relative to another(s) of said materials at a rate of at least 2:1 by volume for at least the first 75 angstroms.

[0036] In this document, "self-alignment" means a technique by which at least the transverse surfaces of a structure are defined by depositing material against the sidewalls of a previously patterned structure. In the context of this document, "circumferential self-alignment" refers to a self-alignment technique by which all transverse surfaces of a structure are defined by depositing material against the surrounding sidewalls of a previously patterned structure.

[0037] Unless otherwise indicated, the use of “or” in this document covers either or both.

[0038] in conclusion

[0039] In some embodiments, a method for forming a vertical transistor array includes forming pillars, each pillar individually including an upper source / drain region, a channel region vertically below the upper source / drain region, and a sacrificial material above the upper source / drain region. An intermediate material surrounds the sacrificial material of the individual pillars. The intermediate material and the sacrificial material comprise compositions distinct from each other. Horizontally elongated and spaced conductive gate lines are operatively formed individually next to the channel region of the individual pillars. The sacrificial material is removed to expose the upper source / drain region of the individual pillars, thereby forming an opening in the intermediate material directly above the upper source / drain region of the individual pillars. A metal material is formed in the individual pillar within the opening, directly abutting the upper source / drain region of the individual pillar, and laterally outside the opening on top of the intermediate material. The metal material on top of the intermediate material interconnects the metal materials in the individual openings. The metal material is removed back to have an uppermost surface not higher than the uppermost surface of the intermediate material and disconnected to prevent interconnection of the metal materials in the individual openings, thereby forming laterally isolated individual metal plugs in the individual openings.

[0040] In some embodiments, a method for forming a vertical transistor array includes forming pillars, each pillar individually including an upper source / drain region, a channel region vertically below the upper source / drain region, and a sacrificial material above the upper source / drain region. An intermediate material surrounds the sacrificial material of the individual pillars. The intermediate material and the sacrificial material comprise compositions distinct from each other. Horizontally elongated and spaced conductive gate lines are operatively formed individually next to the channel region of the individual pillars. The sacrificial material is removed to expose the upper source / drain region of the individual pillar, thereby forming an opening in the intermediate material directly above the upper source / drain region of the individual pillar. The individual pillar in the opening widens laterally above the upper source / drain region in a vertical cross-section after its initial formation. A metallic material is formed in the individual widened opening, directly abutting the upper source / drain region of the individual pillar, and on top of the intermediate material on the lateral outer side of the widened opening. The metallic material on top of the intermediate material interconnects the metallic materials in the individual widened openings. The metal material is removed backwards to its uppermost surface, which is no higher than the uppermost surface of the intermediate material, and disconnected to prevent interconnection of the metal material in the individual openings, thereby forming laterally isolated individual metal plugs in the individual openings. The metal material and the upper source / drain regions have different compositions from each other. The metal material is removed backwards, and all metal material is removed from the top of the intermediate material. After the metal material is removed backwards, the uppermost surface of the metal material and the uppermost surface of the intermediate material are coplanar. After forming the laterally isolated individual metal plugs, the intermediate material is selectively etched perpendicularly relative to the metal plugs.

[0041] In some embodiments, a method for forming an array of memory cells, each including a vertical transistor and a memory device above the vertical transistor, includes forming horizontally elongated and spaced digital lines, each digital line individually interconnecting a corresponding plurality of vertical transistors in a column direction. A pillar is formed on top of and directly electrically coupled to the individual in the digital lines. Each pillar individually includes an upper source / drain region, a channel region vertically below the upper source / drain region, and a sacrificial material above the upper source / drain region. An intermediate material surrounds the sacrificial material of the individual in the pillar. The intermediate material and the sacrificial material comprise compositions distinct from each other. Horizontally elongated and spaced conductive gate lines are operatively formed individually next to the channel region of the individual pillars and individually interconnect a corresponding plurality of vertical transistors in a row direction. The sacrificial material is removed to expose the upper source / drain region of the individual pillar, thereby forming an opening in the intermediate material directly above the upper source / drain region of the individual pillar. A metallic material is formed in the individual within the opening, directly abutting the upper source / drain region of the individual pillar, and on top of the intermediate material on the lateral outer side of the opening. The metal material on top of the intermediate material interconnects the metal materials in the individual openings. The metal material is removed back to a surface no higher than the uppermost surface of the intermediate material, and disconnected to prevent interconnection of the metal materials in the individual openings, thereby forming laterally isolated individual metal plugs in the individual openings. After removing the metal material, a storage device is formed, which is individually located above and electrically coupled to one of the individual metal plugs.

[0042] In accordance with regulations, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the means disclosed herein include exemplary embodiments. Therefore, the claims should be given their full scope literally and should be properly interpreted in accordance with the doctrine of equivalents.

Claims

1. A method for forming an array of vertical transistors, comprising: forming pillars individually comprising an upper source / drain region, a channel region vertically below the upper source / drain region, and a sacrificial material above the upper source / drain region; a mediating material around the sacrificial material of individual ones of the pillars, the mediating material and the sacrificial material comprising different compositions from one another; individually forming horizontally elongated and spaced conductive gate lines operatively alongside the channel regions of individual ones of the pillars; removing the sacrificial material to expose the upper source / drain regions of individual ones of the pillars, and thereby forming openings in the mediating material directly above the upper source / drain regions of individual ones of the pillars; forming a metallic material in individual ones of the openings directly against the upper source / drain regions of individual ones of the pillars, and atop the mediating material laterally outside of the openings, the metallic material atop the mediating material interconnecting the metallic material in the individual openings; and back-removing the metallic material to have an uppermost surface no higher than an uppermost surface of the mediating material, and breaking it to discontinue interconnecting the metallic material in the individual openings, and thereby forming individually metallic material plugs laterally isolated in the individual openings.

2. The method of claim 1, wherein the upper source / drain regions comprise conductively-doped semiconductive material, the sacrificial material directly against the conductively-doped semiconductive material.

3. The method of claim 1, comprising, after forming the openings and before forming the metallic material therein, laterally widening the individual openings above the upper source / drain regions in one vertical cross-section after initial formation of the individual openings.

4. The method of claim 3, comprising, after forming the openings and before forming the metallic material therein, laterally widening the individual openings above the upper source / drain regions in another vertical cross-section orthogonal to the one vertical cross-section after initial formation of the individual openings.

5. The method of claim 4, wherein the lateral widening in the one and the another vertical cross-section occur simultaneously.

6. The method of claim 1, wherein the metallic material comprises titanium nitride and elemental tungsten.

7. The method of claim 6, wherein the metallic material comprises a metal silicide under the titanium nitride and the elemental tungsten.

8. The method of claim 7, wherein the metal silicide is directly against the titanium nitride.

9. The method of claim 1, wherein, after the back-removing of the metallic material, each of the uppermost surface of the metallic material and the uppermost surface of the mediating material is coplanar.

10. The method of claim 9, wherein, after the back-removing of the metallic material, the uppermost surface of the metallic material and the uppermost surface of the mediating material are coplanar.

11. The method of claim 1 including, after forming the laterally-isolated individual plugs of metallic material, selectively vertically etching the intervening material relative to the plugs of metallic material.

12. The method of claim 11 wherein the vertical etching of the intervening material forms its uppermost surface to be below a bottom of the plugs of metallic material.

13. The method of claim 1 wherein, the intervening material comprises first and second intervening materials, each of which comprises a composition different from the composition of the sacrificial material; the second intervening material is formed after forming the gate lines, the metallic material being formed atop the second intervening material, the uppermost surface of the intervening material comprising an uppermost surface of the second intervening material.

14. The method of claim 13 wherein the first intervening material is formed before forming the gate lines, the second intervening material being formed after forming the first intervening material, the metallic material being formed atop the first intervening material, and the uppermost surface of the intervening material comprising an uppermost surface of the first intervening material.

15. The method of claim 1 wherein the metallic material and the upper source / drain regions have compositions different from one another.

16. The method of claim 1 wherein the removing back the metallic material removes all of the metallic material atop the intervening material.

17. The method of claim 1 wherein, the gate lines individually interconnect a respective plurality of the vertical transistors in a row direction; and before forming the gate lines, horizontally elongated and spaced conductive lines are formed, the conductive lines individually interconnecting a respective plurality of the vertical transistors in a column direction.

18. The method of claim 1 wherein the plugs of metallic material are formed to be circumferentially self-aligned in horizontal cross-section.

19. A method for forming an array of vertical transistors comprising: forming pillars individually comprising an upper source / drain region, a channel region vertically below the upper source / drain region, and a sacrificial material above the upper source / drain region; an intervening material surrounding the sacrificial material of individual ones of the pillars, the intervening material and the sacrificial material comprising compositions different from one another; horizontally elongated and spaced conductive gate lines are individually formed operatively alongside the channel regions of individual ones of the pillars; the sacrificial material is removed to expose the upper source / drain regions of individual ones of the pillars and thereby form openings in the intervening material directly above the upper source / drain regions of individual ones of the pillars; after the openings are initially formed, individual ones of the openings are laterally widened above the upper source / drain regions in one vertical cross-section; metallic material is formed in the individual widened openings directly against the upper source / drain regions of individual ones of the pillars and atop the intervening material laterally outside of the widened openings, the metallic material atop the intervening material interconnecting the metallic material in the individual widened openings; removing said metal material back to have an uppermost surface no higher than an uppermost surface of said intervening material, and breaking it to avoid interconnecting said metal material in said individual openings, and thereby forming laterally isolated individual metal material plugs in said individual openings, said metal material and said upper source / drain regions having compositions different from one another, said removing said metal material back removing all of said metal material atop said intervening material, said uppermost surface of said metal material and an uppermost surface of said intervening material being coplanar after said removing said metal material back; after forming said laterally isolated individual metal material plugs, selectively vertically etching said intervening material relative to said metal material plugs.

20. A method for forming an array of memory cells individually comprising a vertical transistor and a storage device over said vertical transistor, comprising: forming horizontally elongated and spaced digit lines individually interconnecting a respective plurality of said vertical transistors in a column direction; forming a pillar atop and directly electrically coupled to an individual of said digit lines; said pillar individually comprising an upper source / drain region, a channel region vertically below said upper source / drain region, and a sacrificial material above said upper source / drain region; an intervening material surrounding said sacrificial material of an individual of said pillars, said intervening material and said sacrificial material comprising compositions different from one another; individually forming horizontally elongated and spaced conductive gate lines operable alongside said channel regions of individual said pillars, and individually interconnecting a respective plurality of said vertical transistors in a row direction; removing said sacrificial material to expose said upper source / drain regions of individual said pillars, and thereby forming openings in said intervening material directly above said upper source / drain regions of individual said pillars; forming a metal material in individual of said openings directly against said upper source / drain regions of individual said pillars, and atop said intervening material laterally outside of said openings, said metal material atop said intervening material interconnecting said metal material in said individual openings; removing said metal material back to have an uppermost surface no higher than an uppermost surface of said intervening material, and breaking it to avoid interconnecting said metal material in said individual openings, and thereby forming laterally isolated individual metal material plugs in said individual openings; and after removing said metal material, forming a storage device individually over and electrically coupled to one of said individual metal material plugs.

21. The method of claim 20 wherein said storage device is a capacitor.

22. The method of claim 20 comprising: after forming said laterally isolated individual metal material plugs, selectively vertically etching said intervening material relative to said metal material plugs; forming silicon nitride in place of said vertically etched intervening material; and forming said storage device over said silicon nitride.

23. The method of claim 22 wherein said vertical etching of said intervening material forms its uppermost surface to be below a bottom of said metal material plug.

24. The method of claim 20 including, after forming said openings and before forming said metal material therein, laterally widening said individual openings above said upper source / drain regions in one vertical cross section after initial formation of said individual openings.

25. The method of claim 20 wherein, after said removing said metal material back, each of said uppermost surface of said metal material and said uppermost surface of said intervening material are coplanar.

26. The method of claim 25 wherein, after said removing said metal material back, said uppermost surface of said metal material and said uppermost surface of said intervening material are coplanar.

27. The method of claim 20 wherein, said intervening material comprises a first intervening material and a second intervening material comprising a composition different from a composition of said sacrificial material; said second intervening material is formed after forming said gate lines, said metal material is formed atop said second intervening material, said uppermost surface of said intervening material comprises an uppermost surface of said second intervening material.

28. The method of claim 27 wherein said first intervening material is formed before forming said gate lines, said second intervening material is formed after forming said first intervening material, said metal material is formed atop said first intervening material, and said uppermost surface of said intervening material comprises an uppermost surface of said first intervening material.

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