Metal-insulator-semiconductor (MIS) contacts in three-dimensional (3D) vertical memory

Abstract

This application relates to metal-insulator-semiconductor (MIS) contacts in three-dimensional vertical memory. Systems, methods, and apparatus are provided for vertically stacked memory cell arrays having horizontally oriented access devices having a first source / drain region and a second source / drain region separated by a channel region, and a gate opposite the channel region; vertically oriented access lines coupled to the gate and separated from the channel region by a gate dielectric. The memory cell has a horizontally oriented memory node coupled to the second source / drain region and a horizontally oriented digital line coupled to the first source / drain region. In one example, an insulating material is formed on the surface of the first source / drain region, and a conductive material is formed on the insulating material to form a metal-insulator-semiconductor (MIS) interface between the horizontally oriented digital line and the first source / drain region of the horizontally oriented access device.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically to metal-insulator-semiconductor (MIS) contacts in three-dimensional (3d) vertical memory. Background Technology

[0002] Memory is commonly implemented in electronic systems such as computers, mobile phones, and handheld devices. Many different types of memory exist, including volatile and resettable memory. Volatile memory requires power to maintain its data and can include Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Synchronous Dynamic Random Access Memory (SDRAM). Non-volatile memory provides persistent data by retaining the stored data when no power is applied and can include NAND flash memory, NOR flash memory, Nnitride read-only memory (NROM), phase-change memory (e.g., phase-change random access memory), resistive memory (e.g., resistive random access memory), crosspoint memory, ferroelectric random access memory (FeRAM), etc.

[0003] As design rules shrink, the semiconductor space available for manufacturing memory (including DRAM arrays) will decrease. A corresponding memory cell for DRAM may include access means, such as transistors, having first and second source / drain regions separated by a channel region. A gate may be opposite to the channel region and may be separated from the channel region by a gate dielectric. Access lines, such as word lines, are electrically connected to the gate of the DRAM cell. A DRAM cell may include memory nodes, such as capacitor cells, coupled to digital lines via access means. Access means can be activated (e.g., to select a cell) via access lines coupled to access transistors. Capacitors may store charge (e.g., logic "1" or "0") corresponding to the data value of the corresponding cell. Summary of the Invention

[0004] One aspect of this disclosure provides a method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines, wherein the method includes: vertically depositing multiple layers of a first dielectric material, a semiconductor material, and a second dielectric material in a repetitive, iterative manner to form a vertical stack, wherein the semiconductor material comprises a lightly doped semiconductor material, and a first source / drain region and a second source / drain region are formed therein, horizontally separated by a channel region; forming a vertical opening using a first etching process to expose vertical sidewalls in the vertical stack; selectively etching the second dielectric material to form a first horizontal opening; depositing an insulating material on a surface above the first source / drain region in the first horizontal opening; depositing a first conductor material on the surface of the insulating material in the first horizontal opening to form horizontally oriented digital line contacts with the first source / drain region, wherein the first conductor, the insulating material, and the first source / drain region constitute a metal-insulator-semiconductor (MIS) interface; and depositing a second conductor material on the first conductor material to form digital lines in the first horizontal opening.

[0005] Another aspect of this disclosure provides a method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines, wherein the method includes: forming a plurality of first vertical openings having a first horizontal direction and a second horizontal direction through a vertical stack of a first dielectric material, a semiconductor material having a channel region, and a second dielectric material, the vertical openings extending primarily along the second horizontal direction to form elongated vertical pillars with sidewalls in the vertical stack; conformally depositing a first conductor material on the gate dielectric material of alternating first few of the plurality of first vertical openings; removing portions of the first conductor material in the alternating first few openings of the plurality of first vertical openings to form a plurality of individual vertical access lines along the sidewalls of the elongated vertical pillars; and then... A conductive material is conformally deposited on an insulating material in alternating subsequent openings of a plurality of first vertical openings; portions of the first conductive material and insulating material in the alternating subsequent openings of the plurality of first vertical openings are removed to form a plurality of separate, vertical metal-insulator-semiconductor (MIS) interfaces with a channel region; a second vertical opening is formed, the second vertical opening extending primarily along a first horizontal direction through a vertical stack to expose vertical sidewalls in the vertical stack; a second dielectric material is selectively etched to form a first horizontal opening; a dopant is vapor-doped into the top surface of a lightly doped semiconductor material to form a first source / drain region; and a second conductive material is deposited on the first source / drain region to form digital lines in the first horizontal opening.

[0006] Another aspect of this disclosure provides a memory device having a horizontally oriented access device and a vertically oriented access line, wherein the memory device includes: a vertically stacked memory cell array, comprising: a horizontally oriented access device having a first source / drain region and a second source / drain region separated by a horizontal channel region, and a gate opposite to and separated from the horizontal channel region by a gate dielectric; a vertically oriented access line coupled to the gate and separated from the horizontal channel region by a gate dielectric; a horizontally oriented memory node electrically coupled to the second source / drain region of the horizontally oriented access device; a horizontally oriented digital line electrically coupled to the first source / drain region of the horizontally oriented access device; a horizontally formed metal-insulator-semiconductor (MIS) interface between the first source / drain region and the digital line; and a vertical body contact formed to directly electrically contact one or more body regions in the horizontally oriented access device and separated from the first source / drain region and the horizontally oriented digital line by a dielectric. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0008] Figure 2 The following is a perspective view illustrating a portion of a digital line according to several embodiments of the present disclosure, the digital line having a metal-insulator-semiconductor (MIS) interface between the digital line and a first source / drain region of a semiconductor device.

[0009] Figure 3 The following is a perspective view illustrating a portion of a digital line according to several embodiments of the present disclosure, the digital line having a metal-insulator-semiconductor (MIS) interface between the digital line and a first source / drain region of a semiconductor device.

[0010] Figure 4A to 4K This is a cross-sectional view of a method for forming a vertically stacked memory cell array at multiple stages of a semiconductor manufacturing process, according to various embodiments of the present disclosure, to form a metal-insulator-semiconductor (MIS) contact in a three-dimensional (3d) vertical memory.

[0011] Figures 5A to 5B-1 Examples of methods for forming a vertically stacked memory cell array having metal-insulator-semiconductor (MIS) contacts in a three-dimensional (3d) vertical memory are described according to several embodiments of the present disclosure at another stage of the semiconductor manufacturing process.

[0012] Figures 6A to 6E Examples of methods for forming a vertically stacked memory cell array having metal-insulator-semiconductor (MIS) contacts in a three-dimensional (3d) vertical memory are described according to several embodiments of the present disclosure at another stage of the semiconductor manufacturing process.

[0013] Figures 7A to 7E Examples of methods for forming a vertically stacked memory cell array having metal-insulator-semiconductor (MIS) contacts in a three-dimensional (3d) vertical memory are described according to several embodiments of the present disclosure at another stage of the semiconductor manufacturing process.

[0014] Figures 8A to 8E According to several embodiments of this disclosure, example methods are described for forming a vertically stacked memory cell array having metal-insulator-semiconductor (MIS) contacts in a three-dimensional (3d) vertical memory at another stage of the semiconductor manufacturing process, said array.

[0015] Figures 9A to 9B Cross-sectional views of an example horizontally oriented access device are illustrated according to several embodiments of the present disclosure, the horizontally oriented access device being coupled to a horizontally oriented memory node and to a vertically oriented access line and a horizontally oriented digital line.

[0016] Figure 10 This is a block diagram of a device in the form of a computing system including a memory device, according to several embodiments of the present disclosure. Detailed Implementation

[0017] Embodiments of this disclosure describe a digital line having a metal-insulator-semiconductor (MIS) interface between the digital line and a first source / drain region of a semiconductor device. The digital line with the MIS interface between the digital line and the first source / drain region is formed together with a horizontal access device in a vertically stacked memory cell array. The horizontal access device is integrated with the vertically oriented access line and with the horizontally oriented digital line. Body contacts may be formed to provide better body bias control to a body region of the horizontally oriented access device (e.g., a transistor). In one embodiment, the MIS interface is configured to make electrical contact with a channel region to provide a channel contact for the horizontally oriented access device. The channel contact may be shared between adjacent horizontally oriented access devices and / or vertically stacked horizontally oriented access devices, and provides a shared bias to the channel region. This further provides better access device channel control for silicon oxide channel access devices and improved device refresh. Vertically oriented channel contact lines, such as those made of highly doped p-type (p+) semiconductor material, can be integrated to form channel contacts with the channel regions of horizontally oriented access devices.

[0018] According to one embodiment, an insulating material is formed on the surface of the first source / drain region, and a conductive material is formed on the insulating material to form a metal-insulator-semiconductor (MIS) interface between the horizontally oriented digital line and the first source / drain region of the horizontally oriented access device, thereby creating a better-designed electrical contact with the first source / drain region of the horizontally oriented access device. The MIS technology described herein further reduces the potential dopant diffusion at the source / drain-to-digital line contact, resulting in potentially more uniform and lower digital line contact resistance as well as lower source / drain doping requirements.

[0019] The figures in this document follow a numbering convention where the first or first few digits correspond to the figure number in the diagram, and the remaining digits identify the elements or components within the diagram. Similar elements or components between different figures can be identified by using similar digits. For example, reference number 104 may refer to... Figure 1 The component "04" in the text, and similar components can be found in the text. Figure 2 In this context, it is referred to as 204. Multiple similar elements within a drawing can be referred to using a reference number followed by a character and another number or letter. For example, 302-1 could refer to... Figure 3 Component 302-1 and 302-2 may refer to component 302-2, which may be similar to component 302-1. Such similar components are usually referred to without hyphens and additional numbers or letters. For example, components 302-1 and 302-2 or other similar components may generally be referred to as 302.

[0020] Figure 1 This is a block diagram of a device according to several embodiments of the present disclosure. Figure 1 A circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device is shown according to embodiments of the present disclosure. Figure 1 The cell array can have multiple sub-cell arrays 101-1, 101-2, ..., 101-N. Sub-cell arrays 101-1, 101-2, ..., 101-N can be arranged along a second direction (D2) 105. Each of the sub-cell arrays (e.g., sub-cell array 101-2) can contain multiple access lines 103-1, 103-2, ..., 103-Q (which may also be referred to as word lines). Furthermore, each of the sub-cell arrays (e.g., sub-cell array 101-2) can contain multiple digital lines 107-1, 107-2, ..., 107-P (which may also be referred to as bit lines, data lines, or sensing lines). Figure 1In the diagram, digital lines 107-1, 107-2, ..., 107-P are described as extending along a first direction (D1) 109, and access lines 103-1, 103-2, ..., 103-Q are described as extending along a third direction (D3) 111. According to an embodiment, the first direction (D1) 109 and the second direction (D2) 105 can be considered to be in a horizontal (“XY”) plane. The third direction (D3) 111 can be considered to be in a vertical (“Z”) plane. Therefore, according to the embodiment described herein, access lines 103-1, 103-2, ..., 103-Q extend along a vertical direction (e.g., the third direction (D3) 111).

[0021] A memory cell (e.g., 110) may include access means such as access transistors, and a memory node located at the intersection of each access line 103-1, 103-2, ..., 103-Q and each digital line 107-1, 107-2, ..., 107-P. The memory cell can be written to or read from using the access lines 103-1, 103-2, ..., 103-Q and the digital lines 107-1, 107-2, ..., 107-P. The digital lines 107-1, 107-2, ..., 107-P may electrically interconnect the memory cells along the horizontal columns of each sub-cell array 101-1, 101-2, ..., 101-N, and the access lines 103-1, 103-2, ..., 103-Q may electrically interconnect the memory cells along the vertical rows of each sub-cell array 101-1, 101-2, ..., 101-N. A memory cell (e.g., 110) may be located between an access line (e.g., 103-2) and a digital line (e.g., 107-2). Each memory cell can be uniquely addressed by a combination of access lines 103-1, 103-2, ..., 103-Q and digital lines 107-1, 107-2, ..., 107-P.

[0022] Digital lines 107-1, 107-2, ..., 107-P may be or comprise conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. Digital lines 107-1, 107-2, ..., 107-P may extend along a first direction (D1) 109. Digital lines 107-1, 107-2, ..., 107-P in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a vertical direction (e.g., in a third direction (D3) 111).

[0023] Access lines 103-1, 103-2, ..., 103-Q may be or include conductive patterns (e.g., metal lines) extending in a vertical direction (e.g., on a third direction (D3) 111) relative to the substrate. Access lines in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a first direction (D1) 109.

[0024] The gate of a memory cell (e.g., memory cell 110) may be connected to an access line (e.g., 103-2), and a first conductive node (e.g., a first source / drain region) of an access means (e.g., a transistor) of memory cell 110 may be connected to a digital line, e.g., 107-2. Each of the memory cells, e.g., memory cell 110, may be connected to a storage node, e.g., a capacitor. A second conductive node (e.g., a second source / drain region) of an access means (e.g., a transistor) of memory cell 110 may be connected to a storage node (e.g., a capacitor). Although the references to first and second source / drain regions are used herein to denote two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as “first” and / or “second” source / drain regions have any unique meaning. It is only intended that one of the source / drain regions is connected to a digital line, e.g., 107-2, while the other may be connected to a storage node.

[0025] Figure 2 Some embodiments of this disclosure illustrate a three-dimensional (3D) semiconductor memory device (e.g., in...). Figure 1 The image shows a perspective view of a portion of a sub-cell array 101-2, which is a vertically oriented stack of memory cells in an array. Figure 3 Explanation and display Figure 2 The unit cell of the 3D semiconductor memory device shown in the figure (e.g., in Figure 1 A perspective view of the memory cell 110 shown in the image.

[0026] As in Figure 2 As shown, a bonding can be formed on the substrate 200. Figure 1 One of the described arrays of multiple sub-cells, for example, 101-2. For example, substrate 200 may be or comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0027] As in Figure 2 As shown in the example embodiments, the substrate 200 may be fabricated thereon with memory cells extending in a vertical direction (e.g., third direction (D3)111). Figure 1 The memory cells 110 in the memory cell stack are vertically oriented. According to some embodiments, the vertically oriented memory cell stack can be manufactured such that each memory cell (e.g., memory cells 110) is vertically oriented. Figure 1 The memory cells 110 are formed on multiple vertical levels (e.g., a first level (L1), a second level (L2), and a third level (L3)). Repeating vertical levels L1, L2, and L3 can be along the vertical direction (e.g., ...). Figure 1The third-party (D3) 111 arrangement shown is, for example, “stacked” and can be separated from the substrate 200 by an insulating material 220. Each of the repeating vertical levels L1, L2, and L3 may include, for example, multiple discrete components (e.g., regions) to the lateral access device 230 (e.g., transistors) and storage nodes (e.g., capacitors), including access lines 103-1, 103-2, ..., 103-Q connections and digital lines 107-1, 107-2, ..., 107-P connections. The multiple discrete components to the lateral access device 230 (e.g., transistors) may be formed in multiple iterations of the vertical repeating layers within each level, as described below. Figures 4A to 4K A more detailed description, and along the second direction (D2)205 (similar to) Figure 1 The second direction (D2)105 shown in the figure extends horizontally.

[0028] A plurality of discrete components (e.g., transistors) to the lateral access device 230 may include a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225, the discrete components extending laterally along a second direction (D2) 205 and formed in the body of the access device. In some embodiments, the channel region 225 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 221 and the second source / drain region 223 may include n-type dopant regions formed in the p-type doped body of the access device to form an n-type conductive transistor. In some embodiments, the first source / drain region 221 and the second source / drain region 223 may include p-type dopant formed in the n-type doped body of the access device to form a p-type conductive transistor. By way of example, and not limitation, an n-type dopant may contain phosphorus (P) atoms, and a p-type dopant may contain boron (B) atoms formed in the oppositely doped bulk region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0029] Storage node 227, for example, a capacitor, can be connected to a corresponding terminal of the access device. (As in...) Figure 2 As shown, storage node 227, such as a capacitor, can be connected to the second source / drain region 223 of the access device. The storage node may be or contain a memory element capable of storing data. Each of the storage nodes may be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistive body containing a phase change material. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g., Figure 1 The memory node associated with each access device of the memory cell 110 in the memory cell can be similarly arranged along the second direction (D2) 205 (similar to Figure 1The second direction (D2)105) shown in the figure extends.

[0030] As in Figure 2 As shown, multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P are arranged along the first direction (D1) 209 (similar to...). Figure 1 The first direction (D1) 109) extends. Multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P can be similar to... Figure 1 The digital lines 107-1, 107-2, ..., 107-P shown are illustrated. Multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P may be arranged along a third direction (D3) 211, for example, "stacked". The multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P may contain a conductive material. For example, the conductive material may contain one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, the embodiments are not limited to these examples.

[0031] In each of the vertical hierarchies (L1)213-1, (L2)213-2, and (L3)213-P, the horizontally oriented memory cell (e.g., Figure 1 The memory cells 110 in the memory may be horizontally spaced apart from each other along the first direction (D1) 209. However, as described below... Figure 4A to 4KIn more detail, multiple discrete components of the lateral access device 230 (e.g., a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225 and extending laterally along a second direction (D2) 205, and multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending laterally along a first direction (D1) 209) can be formed in different vertical layers within each level. For example, the multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending along the first direction (D1) 209 can be disposed on and electrically contacted on the top surface of the first source / drain region 221, and orthogonal to the lateral access device 230 (e.g., a transistor) extending laterally along the second direction (D2) 205. In some embodiments, a plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending along a first direction (D1) 209 are formed in a higher vertical layer, farther from the substrate 200, and within a layer, such as within layer (L1), compared to the layer in which discrete components forming laterally oriented access devices (e.g., a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225). In some embodiments, the plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P extending along the first direction (D1) 209 may be directly and / or connected to the top surface of the first source / drain region 221 via additional contacts comprising metal silicide.

[0032] like Figure 2 As shown in the example embodiments, access lines 203-1, 203-2, ..., 203-Q extend relative to substrate 200 in a vertical direction, for example, along a third direction (D3) 211. Furthermore, as in... Figure 2 As shown, a sub-cell array (e.g., Figure 1 Access lines 203-1, 203-2, ..., 203-Q in the sub-cell array 101-2 can be spaced apart from each other along a first direction (D1) 209. Access lines 203-1, 203-2, ..., 203-Q can extend vertically between a pair of laterally oriented memory devices 230 (e.g., transistors) provided with a third direction (D3) 211 relative to the substrate 200, the pair of laterally oriented memory devices extending laterally along a second direction (D2) 205 but adjacent to each other in a layer (e.g., a first layer (L1)) along the first direction (D1) 209. Each of the access lines 203-1, 203-2, ..., 203-Q can extend vertically along a third direction (D3) on the sidewall of a corresponding one of the vertically stacked plurality of laterally oriented memory devices 230 (e.g., transistors).

[0033] For example, and as in Figure 3As shown in more detail, the first of the vertically extended access lines (e.g., 203-1) may be adjacent to the sidewall of the channel region 225 of the first lateral access device 230 (e.g., transistor) in the first level (L1) 213-1, the sidewall of the channel region 225 of the first lateral access device 230 (e.g., transistor) in the second level (L2) 213-2, and the sidewall of the channel region 225 of the first lateral access device 230 (e.g., transistor) in the third level (L3) 213-P, etc. Similarly, the second vertically extending access line (e.g., 203-2) may be adjacent to the sidewall of the channel region 225 of the second laterally oriented access device 230 (e.g., transistor) in the first layer (L1) 213-1, spaced apart from the first laterally oriented access device 230 (e.g., transistor) in the first layer (L1) 213-1 along the first direction (D1) 209. The second vertically extending access line (e.g., 203-2) may also be adjacent to the sidewall of the channel region 225 of the second laterally oriented access device 230 (e.g., transistor) in the second layer (L2) 213-2, and the sidewall of the channel region 225 of the second laterally oriented access device 230 (e.g., transistor) in the third layer (L3) 213-P. The embodiments are not limited to a specific number of layers.

[0034] The vertically extending access lines 203-1, 203-2, ..., 203-Q may contain a conductive material, such as a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound. Access lines 203-1, 203-2, ..., 203-Q may correspond to... Figure 1 The word line (WL) described.

[0035] As in Figure 2 As shown in the example embodiment, conductive body contacts 295 can be formed in each layer (L1) 213-1, (L2) 213-2, and (L3) 213-P on the substrate 200, extending along a first direction (D1) 209 from the end face of the lateral orientation access device 230 (e.g., a transistor). The body contacts 295 can be connected to each memory cell (e.g., Figure 1 The body of the lateral access device 230 (e.g., a transistor) in the memory cell 110 (as in the memory cell 110) (such as the body of the lateral access device 230) (e.g., a transistor) Figure 3 (As shown in 336), for example, the body region. Body contact 295 may contain a conductive material, such as one of a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound.

[0036] Although not in Figure 2As shown, however, insulating material may fill other spaces in the vertically stacked memory cell array. For example, the insulating material may comprise one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments are not limited to these examples.

[0037] Figure 3 A more detailed description of some embodiments according to this disclosure, for example, in Figure 1 The unit cells of the vertically stacked array of memory cells within the sub-cell array 101-2, for example Figure 1 Memory unit 110 in. For example, in Figure 3 As shown, the first source / drain region 321 and the second source / drain region 323 can be doped regions of a lateral access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be similar to... Figure 2 The first source / drain region 221 and the second source / drain region 223 are shown in the diagram. The first source / drain region and the second source / drain region can be separated by a channel 325 formed in the body (e.g., body region 326) of the semiconductor material of the lateral access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be formed by n-type or p-type dopant doped in the body region 326. The embodiments are not limited thereto.

[0038] For example, in an n-type conductive transistor configuration, the body region 326 of the lateral access device 330 (e.g., a transistor) may be formed of a lightly doped (p-)p-type semiconductor material. In one embodiment, the body region 326 and the channel 325 separating the first source / drain region 321 and the second source / drain region 323 may comprise a lightly doped p-type (e.g., low dopant concentration (p-)) polysilicon material composed of boron (B) atoms as an impurity dopant for the polysilicon. The first source / drain region 321 and the second source / drain region 323 may also comprise metals, and / or metal composite materials formed using atomic layer deposition processes, etc., containing ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), a highly doped degenerate semiconductor material, and / or indium oxide (In₂O₃) or indium tin oxide (In₂O₃). 2-x Sn x At least one of O3). However, the embodiments are not limited to these examples. As used herein, degenerate semiconductor material is intended to mean a semiconductor material with a high doping level, such as polycrystalline silicon, in which there are significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.). In contrast, non-degenerate semiconductors contain a moderate doping level in which the dopant atoms are sufficiently separated from each other in the semiconductor host lattice and the interactions are negligible.

[0039] In this example, the first source / drain region 321 and the second source / drain region 321 may contain highly doped n-type conductivity impurities (e.g., highly doped (n+)) doped in the first source / drain region 321 and the second source / drain region 323. In some embodiments, the highly doped n-type conductivity first drain region 321 and the second drain region 323 may contain a high concentration of phosphorus (P) atoms deposited therein. However, the embodiments are not limited to this example. In other embodiments, the lateral access device 330 (e.g., a transistor) may be constructed with p-type conductivity, in which case the type of impurity (e.g., dopant) conductivity will be the opposite.

[0040] As in Figure 3 As shown in the example embodiment, the first source / drain region 321 may occupy the upper portion of the body 326 of the lateral orientation access device 330 (e.g., a transistor). For example, the first source / drain region 321 may have a bottom surface 324 within the body 326 of the lateral orientation access device 330, which is positioned vertically in a third direction (D3) 311 higher than the bottom surface of the body 326 of the lateral orientation access device 330. Thus, the lateral orientation transistor 330 may have a body portion 326 below the first source / drain region 321 and adjacent to a body contact (e.g., a transistor). Figure 2 The electrical contact shown in Figure 295. Furthermore, as in... Figure 3 As shown in the example embodiments, similar to Figure 2 The number lines 207-1, 207-2, ..., 207-P and Figure 1 The digital lines 107-1, 107-2, ..., 107-P shown in the figure (e.g., 307-1) can be placed on the top surface 322 of the first source / drain region 321 and electrically coupled thereto.

[0041] As in Figure 3 As shown in the example embodiments, similar to Figure 2 Access lines 203-1, 203-2, ..., 203-Q and Figure 1Access lines 103-1, 103-2, ..., 103-Q (e.g., 303-1) may extend vertically to the lateral access device 330 adjacent to the sidewall of the channel region 325 portion of the body 326 on a third direction (D3) 311, for example, a transistor horizontally conducting between the first source / drain region 321 and the second source / drain region 323 along a second direction (D2) 305. A gate dielectric material 304 may be interposed between the access line 303-1 (a portion of which is formed to the gate of the lateral access device 330 (e.g., a transistor)) and the channel region 325. The gate dielectric material 304 may comprise, for example, a high-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, etc., or combinations thereof. Embodiments are not limited thereto. For example, in the case of high-k dielectric materials, the gate dielectric material 304 may include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0042] Figure 4A For a cross-sectional view used to form a digital line at a stage of a semiconductor manufacturing process, the digital line has a metal-insulator-semiconductor (MIS) interface between the digital line and a first source / drain region of a semiconductor device having horizontally oriented access devices and vertically oriented access lines, for example in Figures 1 to 3 As described herein, and according to several embodiments of this disclosure.

[0043] exist Figure 4AIn the example embodiments shown in the examples, the method includes depositing alternating layers of first dielectric material 430-1, 430-2, ..., 430-N (collectively referred to as first dielectric material 430), semiconductor material 432-1, 432-2, ..., 432-N (collectively referred to as semiconductor material 432), and second dielectric material 433-1, 433-2, ..., 433-N (collectively referred to as second dielectric material 433) in a repetitive iterative manner to form a vertical stack 401 on the working surface of a semiconductor substrate 400. The alternating materials in the repetitive vertical stack 401 may be separated from the substrate 400 by an insulating material 420. In one embodiment, the first dielectric material 430 may be deposited to have a thickness in the range of twenty (20) nanometers (nm) to sixty (60) nm, for example, a vertical height in a third third direction (D3). In one embodiment, the semiconductor material 432 may be deposited to have a thickness in the range of twenty (20) nm to one hundred (100) nm, for example, a vertical height. In one embodiment, a second dielectric material 433 may be deposited to have a thickness in the range of ten (10) nm to thirty (30) nm, for example, a vertical height. However, the embodiments are not limited to these examples. As shown in Figure 4, the vertical direction 411 is illustrated as a third direction (D3), for example, the z-direction in the xyz coordinate system, similar to... Figures 1 to 3 The first, second, and third-party directions (D3) shown in the figure.

[0044] In some embodiments, the first dielectric material 430-1, 430-2, ..., 430-N may be an interlayer dielectric (ILD). By way of example, and not limitation, the first dielectric material 430-1, 430-2, ..., 430-N may include an oxide material, such as SiO2. In another example, the first dielectric material 430-1, 430-2, ..., 430-N may include silicon nitride (Si3N4) material (also referred to herein as “SiN”). In yet another example, the first dielectric material 430-1, 430-2, ..., 430-N may include silicon oxycarbide (SiO2). x C y In another example, the first dielectric material 430-1, 430-2, ..., 430-N may comprise silicon oxynitride (SiO2). x N y Materials (also referred to herein as "SiON"), and / or combinations thereof. Examples are not limited to these instances.

[0045] In some embodiments, semiconductor materials 432-1, 432-2, ..., 432-N may comprise polycrystalline and / or amorphous silicon (Si) materials. Semiconductor materials 432-1, 432-2, ..., 432-N may be lightly doped p-type (p-) silicon materials. Semiconductor materials 432-1, 432-2, ..., 432-N may be formed from lightly doped p-type (p-) silicon materials by using boron atoms (B) as impurity dopants in a low concentration of vapor phase. The lightly doped p-type (p-) silicon material may be polycrystalline silicon. However, the embodiments are not limited to these examples.

[0046] In some embodiments, the second dielectric material 433-1, 433-2, ..., 433-N may be an interlayer dielectric (ILD). By way of example, and not limitation, the second dielectric material 433-1, 433-2, ..., 433-N may include a nitride material. The nitride material may be silicon nitride (Si3N4) material (also referred to herein as "SiN"). In another example, the second dielectric material 433-1, 433-2, ..., 433-N may include silicon oxycarbide (SiOC) material. In yet another example, the second dielectric material 433-1, 433-2, ..., 433-N may comprise silicon oxynitride (SiON) and / or combinations thereof. The embodiments are not limited to these examples. However, according to an embodiment, the second dielectric materials 433-1, 433-2, ..., 433-N are intentionally selected to differ in material or composition from the first dielectric materials 430-1, 430-2, ..., 430-N, such that a selective etching process can be performed on one of the first and second dielectric layers, the selective etching process being selective for the other of the first and second dielectric layers. For example, the second SiN dielectric materials 433-1, 433-2, ..., 433-N can be selectively etched relative to the semiconductor materials 432-1, 432-2, ..., 432N and the first oxide dielectric materials 430-1, 430-2, ..., 430-N.

[0047] Alternating layers of first dielectric material 430-1, 430-2, ..., 430-N, layers of semiconductor material 432-1, 432-2, ..., 432-N, and layers of second dielectric material 433-1, 433-2, ..., 433-N can be iteratively deposited in a semiconductor manufacturing apparatus using a semiconductor manufacturing process such as chemical vapor deposition (CVD). However, the embodiment is not limited to this example, and other suitable semiconductor manufacturing techniques can be used to iteratively deposit alternating layers of first dielectric material, semiconductor material, and second dielectric material to form a vertical stack 401.

[0048] These layers can occur vertically in repeated iterations. Figure 4AIn the example, three layers numbered 1, 2, and 3 are shown in repeated iterations. For example, the stack may include: a first dielectric material 430-1, a semiconductor material 432-1, a second dielectric material 433-1, a third dielectric material 430-2, a second semiconductor material 432-2, a fourth dielectric material 433-2, a fifth dielectric material 430-3, a third semiconductor material 432-3, and a sixth dielectric material 433-3. Thus, the stack may include: a first oxide material 430-1, a first semiconductor material 432-1, a first nitride material 433-1, a second oxide material 430-2, a second semiconductor material 432-2, a second nitride material 433-2, a third oxide material 430-3, a third semiconductor material 432-3, and a third nitride material 433-3 in further repeated iterations. However, the embodiments are not limited to this example and may include more or fewer repeated iterations.

[0049] Figure 4B This is a cross-sectional view used in another stage of the semiconductor manufacturing process to form digital lines and body contacts for a semiconductor device having horizontally oriented access devices and vertically oriented access lines, for example in... Figures 1 to 3 As described herein, and according to several embodiments of this disclosure.

[0050] According to an embodiment, Figure 4B to 4K The semiconductor manufacturing process described herein can be performed as follows: Figures 5A to 6E This occurs after the formation of the slender column and access line extending along the second direction, as shown in the diagram.

[0051] As in Figure 4B As shown, vertical openings 471 can be formed through the layers within a vertically stacked memory cell to expose the vertical sidewalls in the vertical stack. The vertical openings 471 can be formed by repeated iterations of oxide material 430, semiconductor material 432, and nitride material 433. Thus, the vertical openings 471 can be formed through the first oxide material 430-1, the first semiconductor material 432-1, the first nitride material 433-1, the second oxide material 430-2, the second semiconductor material 432-2, the second nitride material 433-2, the third oxide material 430-3, the third semiconductor material 432-3, and the third nitride material 433-3. However, the embodiments are not limited to these examples. Figure 4B The single vertical opening shown in the figure. Multiple vertical openings can be formed through the material layers. Vertical opening 471 can be formed to expose the vertical sidewalls in the vertical stack.

[0052] Figure 4CFor forming a cross-sectional view of a digital line at another stage of the semiconductor manufacturing process, the digital line has a metal-insulator-semiconductor (MIS) interface between the digital line and a first source / drain region of a semiconductor device having horizontally oriented access devices and vertically oriented access lines, for example in Figures 1 to 3 As described herein, and according to several embodiments of this disclosure.

[0053] Etching agent can flow into vertical opening 471 to selectively etch the second dielectric material 433. For example, etching agent can flow into vertical opening 471 to selectively etch nitride material 433. The etching agent can target all iterations of the second dielectric material 433 within the stack. Thus, the etching agent can target the first nitride material 433-1, the second nitride material 433-2, and the third nitride material 433-3 within the stack.

[0054] Selective etching processes can utilize one or more etch chemicals selected from aqueous etch chemicals, semi-aqueous etch chemicals, vapor-phase etch chemicals, or plasma etch chemicals, as well as other possible selective etch chemicals. For example, dry etch chemicals using oxygen (O2) or O2 and sulfur dioxide (SO2) (O2 / SO2) can be used. Dry etch chemicals using O2 or O2 and nitrogen (N2) (O2 / N2) can be used to selectively etch the second dielectric material 433. Alternatively or additionally, selective etching to remove the second dielectric material 433 may include selective etch chemicals using phosphoric acid (H3PO4) or hydrogen fluoride (HF) and / or the use of selective solvents (e.g., NH4OH or HF) and other possible etch chemicals or solvents to dissolve the second dielectric material 433. The etching process may cause oxidation of only the nitride material 433. Figure 4C As illustrated in the examples, the etching process can form a protective oxide coating, such as a second oxide material 434, on the semiconductor material 432. Therefore, during a selective etching process, the first dielectric material 430 and the semiconductor material 432 can remain intact. For example, a selective etching process can etch a portion of the nitride material 433 without removing the oxide material 430 and the polysilicon material 432.

[0055] As described, during the selective etching process, the semiconductor material 432 may be protected by a second oxide material 434 formed on the semiconductor material 432. The second oxide material 434 may be present in all iterations of the semiconductor material 432. For example, the second oxide material 434 may be present on the sidewalls of the first semiconductor material 432-1, the second semiconductor material 432-2, and the third semiconductor material 432-3, etc., in the vertical opening 471 within the stack.

[0056] Figure 4DFor a cross-sectional view used to form a digital line at another stage of the semiconductor manufacturing process, the digital line has a metal-insulator-semiconductor (MIS) contact between the digital line and a first source / drain region of a semiconductor device having horizontally oriented access devices and vertically oriented access lines, for example in Figures 1 to 3 As described herein, and according to several embodiments of this disclosure.

[0057] A selective etching process can etch nitride material 433 to form a first horizontal opening 473. The selective etching process can be performed such that the first horizontal opening 473 has a length or depth (D1) 476 from the vertical opening 471, a first distance 476. The distance (D1) 476 can be controlled by controlling time, the composition of the etchant gas, and the etching rate of the reactive gas flowing into the vertical opening 471, such as rate, concentration, temperature, pressure, and time parameters. Thus, the nitride material 433 can be etched from the vertical opening 471 at a first distance 476. The selective etching can be isotropic, but selective for the second dielectric material 433, essentially stopping at the first dielectric material 430 and the semiconductor material. Therefore, in one example embodiment, a selective etching process can remove substantially all of the nitride material 433 in the upper layer from the top surface of the semiconductor material 432 to the bottom surface of the first dielectric material (e.g., oxide material), while horizontally etching a distance (D1) 476 from the vertical opening 471 between the semiconductor material 432 and the oxide material 430. In this example, the horizontal opening 473 will have a height (H1) 435, which is substantially equal to and controlled by the thickness of the second dielectric layer 433 (e.g., nitride material) deposited. However, the embodiments are not limited to this example. As described herein, a selective etching process can etch the nitride material 433 to the first distance (D1) 476 and the height (H1) 435. In some embodiments, the height (H1) 435 may range from twenty (20) nanometers (nm) to two hundred (200) nm.

[0058] Figure 4E For forming a cross-sectional view of a digital line at another stage of the semiconductor manufacturing process, the digital line has a metal-insulator-semiconductor (MIS) interface between the digital line and a first source / drain region of a semiconductor device having horizontally oriented access devices and vertically oriented access lines, for example in Figures 1 to 3 As described herein, and according to several embodiments of this disclosure.

[0059] The first source / drain region 475 can be formed by vapor-phase doping of a dopant into a portion of the top surface of the semiconductor material 432 via a horizontal opening 473. Vapor-phase doping can be used to achieve highly isotropic, e.g., non-directional doping. In another example, the bonding can be broken by thermal annealing of a dopant gas, such as phosphorus, under high-energy plasma assistance. The embodiments are not limited thereto. Other suitable semiconductor manufacturing techniques can also be utilized. The width of the first source / drain region 475 doped into the top surface portion of the semiconductor material 432 can be formed substantially entirely along a first distance (D1) 476 from the first horizontal opening 473 to the vertical opening 471. The source / drain region 475 can be formed, for example, by vapor-phase doping of phosphorus (P) atoms as an impurity dopant using the high plasma energy of PECVD, to form a highly concentrated, n-type doped (n+) region in the top surface of the semiconductor material 432.

[0060] Figure 4F For forming a cross-sectional view of a digital line at another stage of the semiconductor manufacturing process, the digital line has a metal-insulator-semiconductor (MIS) interface between the digital line and a first source / drain region of a semiconductor device having horizontally oriented access devices and vertically oriented access lines, for example in Figures 1 to 3 As described herein, and according to several embodiments of this disclosure.

[0061] As in Figure 4F As demonstrated in the examples, insulator material 487 can be deposited onto Figure 4E On the first source / drain region 475 in the first horizontal opening (e.g., 473). In some embodiments, atomic layer deposition (ALD) can be used to deposit the insulating material. In other embodiments, other deposition processes, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or other deposition techniques, can be used. Embodiments are not limited to the examples given above. In examples using ALD, the insulating material 487 can be deposited to cover... Figure 4E The surface of the first horizontal opening 473 is located above the surface of the first source / drain region 475. Insulating material 487 may be deposited to a first thickness (t1) on the surface of the first source / drain region 475. In some embodiments, the first thickness may include two (2) angstroms on the surface of the first source / drain region 475. To ten (10) The height range between these examples. However, the embodiments are not limited to this example. Depositing insulating material 487 may include depositing multiple insulating materials in a combined manner. In one example embodiment, insulating material 487 may include lanthanum oxide (La2O3) material. In another example embodiment, insulating material 487 may include zirconium oxide (ZrO2) material. In yet another example embodiment, insulating material 487 may include titanium oxide (TiO2) material. However, the embodiments are not limited to these example insulating materials 487.

[0062] A first conductor material 489 may be deposited on an insulator material 487 in a first horizontal opening. The first conductor material 489 may be deposited in a similar manner to the insulator material 487. The first conductor material connected to the insulator material 487 may form a metal, insulator, and semiconductor (MIS) interface with the first source / drain region 475. Thus, the first conductor material 489 connected to the insulator material 487 may form a horizontally oriented digital line contact with the first source / drain region 475. In some embodiments, the first conductor material 489 may include a molybdenum (Mo) component. In some embodiments, the first conductor material 489 may include a lanthanum (La) component. In some embodiments, the first conductor material 489 may include a ruthenium (Ru) component. However, the embodiments are not limited to these examples. In some embodiments, the first conductor 489 connected to the insulator material 487 may be designed to contact the semiconductor material 432, such that a separately formed source / drain region, such as 475, formed by doping into the semiconductor material 432 is not used.

[0063] The second conductor material 477 may be conformally deposited into a portion of the vertical opening 471, for example, using a chemical vapor deposition (CVD) process, such that the second conductor material 477 may also be deposited into the first horizontal opening 473 on the first conductor material 489. In some embodiments, the second conductor material 477 may comprise titanium nitride (TiN) material. In some embodiments, the second conductor material 477 may be tungsten (W). In this example, some embodiments may include forming the tungsten (W) material according to the methods described in commonly assigned, co-pending U.S. Patent Application No. ________________, entitled "Digital Line Formation for Horizontally Oriented Access Devices," filed July 30, 2020 (Attorney General's No. 1013.0510001). The second conductor material 477 may be deposited on the first conductor material 489 to form a horizontally oriented digital line.

[0064] Figure 4GFor forming a cross-sectional view of a digital line at another stage of the semiconductor manufacturing process, the digital line has a metal-insulator-semiconductor (MIS) interface between the digital line and a first source / drain region of a semiconductor device having horizontally oriented access devices and vertically oriented access lines, for example in Figures 1 to 3 As described herein, and according to several embodiments of this disclosure.

[0065] The second conductor material 477, the first conductor material 489, and the insulator material 487 may be recessed back into the horizontal opening 473, for example, etched away from the vertical opening 471 using atomic layer etching (ALE) or other suitable techniques. In some instances, the combination of conductor material 477, first conductor material 489, and insulator material 487 may be etched back into the horizontal opening 473 at a second distance (D2) 483 from the vertical opening 471. The second conductor material 477 may be selectively etched, leaving oxide material 430, a portion of the combination of second conductor material 477, first conductor material 489, and insulator material 487, semiconductor material 432 (e.g., MIS), and source / drain regions 475 intact. A third etching process may be used to etch the conductor material 477. In some embodiments, an isotropic etching process may be used to etch the combination of second conductor material 477, first conductor material 489, and insulator material 487. The second conductor material 477 may be recessed rearward by a second distance (D2) 483 in the horizontal opening 473 to remain above the first source / drain region 475. In some embodiments, the second conductor material 477, connected to the insulator material 487 and the first conductor material 489, may form an integral, horizontally oriented conductive digital line (e.g., respectively). Figures 1 to 3 Part of the number lines 107, 207 and 307 in the text.

[0066] Figure 4H For forming a cross-sectional view of a digital line at another stage of the semiconductor manufacturing process, the digital line has a metal-insulator-semiconductor (MIS) interface between the digital line and a first source / drain region of a semiconductor device having horizontally oriented access devices and vertically oriented access lines, for example in Figures 1 to 3 As described herein, and according to several embodiments of this disclosure.

[0067] As in Figure 4H As shown, semiconductor material in the vertical opening 471 can be protected (in Figure 4C to 4GThe oxide material of the sidewall (described as 434), a portion of the first source / drain region 475, a portion of the insulator material 487, a portion of the first conductor material 489, and a first portion 478 of the semiconductor material 432 below the first source / drain region 475 are selectively etched away to allow the formation of body contacts to the body region of the horizontal access device. In this example, the portion of the source / drain region 475, the portion of the insulator material 487, the portion of the first conductor material 489, and the top of the semiconductor material 432 below the first source / drain region 475 (e.g., the first portion 478) may also be etched back from the vertical opening 471 to a second distance (D2) 483. The etching may be performed using a fourth etching process (e.g., using atomic layer etching (ALE) or other suitable techniques). In some embodiments, the insulator material 487, the first conductor material 489, and the first source / drain region 475 may be etched to the same horizontal distance (D2) 483 from the vertical opening 471 as the second conductor material 477.

[0068] Therefore, a second horizontal opening 472 can be formed by etching a portion of the source / drain region 475, a portion of the insulating material 487, a portion of the first conductor material 489, and the top surface (e.g., 478) of the semiconductor material 432 below the first source / drain region 475 at a second horizontal distance (D2) 483 from the vertical opening 471. The second horizontal opening 472 may have a second vertical height (H2) 485. The second vertical height (H2) 485 may be larger than, for example, vertically higher than, the combination of the height (H1) 435 of the first horizontal opening 473 formed in the second dielectric material (e.g., nitride material) and the height of the source / drain region 475 (the depth of vapor phase doping into the top surface of the semiconductor material 432). For example, the second height (H2) 485 may also include the height of the etched-away top portion (e.g., 478) of the semiconductor material 432. Therefore, the second distance (D2) 483 can be shorter than the first distance (D1) 476, but the second height 485 can be shorter than the first height (in Figures 4D to 4E The description is as follows: H1) High.

[0069] Figure 4I For forming a cross-sectional view of a digital line at another stage of the semiconductor manufacturing process, the digital line has a metal-insulator-semiconductor (MIS) interface between the digital line and a first source / drain region of a semiconductor device having horizontally oriented access devices and vertically oriented access lines, for example in Figures 1 to 3 As described herein, and according to several embodiments of this disclosure.

[0070] As in Figure 4IAs shown, the third dielectric material 474 is conformally deposited into the vertical opening 471, for example, using a CVD process, and can conformally fill the second horizontal opening (in) of the vertical opening 471. Figure 4D to 4H The description is 472). The third dielectric material 474 may be horizontally adjacent to the insulating material 487, the first conductor material 489, and the second conductor material 477, for example... Figure 1 The first portion of the source / drain region 475 and the first portion of the lightly doped (e.g., p-type, p-type) semiconductor material 432 extend along a first direction (D1) 109. For example, in some embodiments, a third dielectric material 474 may be in direct contact with the first dielectric material 430 and with the insulator material 487, the first conductor material 489 and the second conductor material 477, the source / drain region 475 and the first portion of the lightly doped semiconductor material 432. However, the embodiments are not limited to this example.

[0071] The third dielectric material 474 may be the same as or a different material from the second dielectric material 433. For example, the second dielectric material may be Si2N3, and the third dielectric material may be Si3N4. In another example, the third dielectric material 474 may include silicon dioxide (SiO2). In yet another example, the third dielectric material 474 may include silicon oxycarbide (SiO2). x C y In another example, the third dielectric material 474 may comprise silicon oxynitride (SiO2). x N y (and / or combinations thereof.) Examples are not limited to these instances.

[0072] Figure 4J For forming a cross-sectional view of a digital line at another stage of the semiconductor manufacturing process, the digital line has a metal-insulator-semiconductor (MIS) interface between the digital line and a first source / drain region of a semiconductor device having horizontally oriented access devices and vertically oriented access lines, for example in Figures 1 to 3 As described herein, and according to several embodiments of this disclosure.

[0073] The third dielectric material 474 can be rearwardly recessed to remove from the first vertical opening 471 and maintain the first vertical opening 471 to allow deposition of conductive material (in Figure 4K(As shown in the figure) to form a direct electrical contact between such conductive material deposited in the vertical opening 471 and the second portion 479 of the lightly doped (e.g., p-type, lightly doped (p-)) semiconductor material 432 (e.g., body region contact) of the horizontally oriented access device (e.g., 901 in FIG. 9) within the vertical stack. In some embodiments, a third dielectric material 474 may be etched away from the vertical opening 471 to expose the sidewalls of the first dielectric material 430, the third dielectric material 474, and the second portion 479 of the semiconductor material 432.

[0074] Figure 4K For forming a cross-sectional view of a digital line at another stage of the semiconductor manufacturing process, the digital line has a metal-insulator-semiconductor (MIS) interface between the digital line and a first source / drain region of a semiconductor device having horizontally oriented access devices and vertically oriented access lines, for example in Figures 1 to 3 As described herein, and according to several embodiments of this disclosure.

[0075] As in Figure 4K As shown, conductive material 495 is deposited into a vertical opening 471 to form a direct electrical contact with a second portion 479 of a lightly doped (e.g., p-type, lightly doped (p-)) semiconductor material 432. In some embodiments, the conductive material may be a metal such as tungsten (W). However, the embodiments are not limited thereto. In some embodiments, conductive material 495 is a heavily doped (e.g., p-type, heavily doped (p+)) semiconductor material that can be deposited into the vertical opening 471. In this example, the highly conductive material 495 may be a heavily doped p-type (p+) silicon material. The conductive material 495 may be a polycrystalline silicon material. In one example, forming a conductive bulk contact includes depositing a degenerate semiconductor material. As used herein, degenerate semiconductor material is intended to mean a semiconductor material with a high doping level, such as polycrystalline silicon, that has significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.). In contrast, non-degenerate semiconductors contain a moderate doping level, where the dopant atoms are sufficiently separated from each other in the semiconductor host lattice and the interactions are negligible.

[0076] In some instances, the conductive material 495 may be a highly doped p-type (p+) silicon-germanium (SiGe) material. The SiGe material can be deposited into the vertical opening 471 at a relatively low temperature. However, the embodiments are not limited to these examples. The conductive material 495 may form a conductive bulk contact with the second portion 479 of the semiconductor material 432.

[0077] The conductive material 495 can reduce holes generated by gate-induced drain leakage (GIDL) during operation of the lateral access device. The conductive material 495 can control the channel potential within the semiconductor material 432 by controlling hole formation within the semiconductor material 432. For example, if the first source / drain region 475 is not electrically isolated from the conductive material 495 by the third dielectric material 474, hole formation can occur between the first source / drain region 475, the conductive material 495, and the body region of the lateral access device.

[0078] Figure 5A This is an example method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines at another stage of the semiconductor manufacturing process, for example in... Figures 1 to 3 As described herein, and according to several embodiments of this disclosure. Figure 5A A top view of a semiconductor structure at a specific point in time, illustrating a semiconductor manufacturing process, is provided according to one or more embodiments. Figure 5A In an example embodiment shown in the examples, the method includes using an etching process to form a plurality of first vertical openings 500 through which the substrate is vertically stacked, the plurality of first vertical openings having a first horizontal direction (D1) 509 and a second horizontal direction (D2) 505. In one example, as in Figure 5A As shown, a plurality of first vertical openings 500 extend primarily along a second horizontal direction (D2) 505 and can form elongated vertical pillars 513 with sidewalls 514 in the vertical stack. The plurality of first vertical openings 500 can be formed using photolithography to pattern a photomask 535 on the vertical stack, for example, to form a hard mask (HM), prior to etching the plurality of first vertical openings 500. However, the embodiments are not limited to this example.

[0079] As in Figure 5A As shown, one embodiment may include "first" "alternating first vertical openings 513-1, 513-2..." and "second" alternating first vertical openings 517-1, 517-2. The first vertical opening 513 may be formed through the vertical stack in a first horizontal direction and a second horizontal direction, and extends mainly in the opposite direction of the second horizontal direction to form an elongated vertical pillar in the vertical stack.

[0080] Figure 5B For along Figure 5A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at a specific point in the semiconductor manufacturing process. Figure 5BThe cross-sectional view shown illustrates alternating layers of first dielectric material 530-1, 530-2, ..., 530-N, semiconductor material 532-1, 532-2, ..., 532-N, and second dielectric material 533-1, 533-2, ..., 533-N on semiconductor substrate 500 to form a vertical stack, for example, as shown in Figure 4, 401. Figure 5B The conductive materials 540-1, 540-2, ..., 540-4 can be formed on the gate dielectric material 538 in the plurality of first vertical openings 500. By way of example, and not limitation, the gate dielectric material 538 can be conformally deposited in the plurality of first vertical openings 500 using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings. The gate dielectric 538 can be deposited to a specific thickness (t1) suitable for a particular design rule, for example, a gate dielectric thickness of approximately 10 nanometers (nm). However, the embodiments are not limited to this example. By way of example, and not limitation, the gate dielectric 538 may include silicon dioxide (SiO2) material, aluminum oxide (Al2O3) material, high dielectric constant (k), such as high-k dielectric materials and / or combinations thereof, as well as... Figure 3 As described in the text.

[0081] In addition, such as in Figure 5B As shown, conductive materials 540-1, 540-2, ... 540-4 can be conformally deposited in a plurality of first vertical openings 500 on the surface of the gate dielectric material 538. By way of example, and not limitation, conductive materials 540-1, 540-2, ... 540-4 can be conformally deposited in a plurality of first vertical openings 500 on the surface of the gate dielectric material 538 using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings above the gate dielectric 538. Conductive materials 540-1, 540-2, ... 540-4 can be conformally deposited to a specific thickness (t2) to form vertically oriented access lines, for example shown as... Figure 1The access lines 103-1, 103-2, ..., 103-Q (which may also be referred to as word lines) shown herein are as applicable to specific design rules. For example, conductive materials 540-1, 540-2, ..., 540-4 may be conformally deposited to a thickness of approximately 20 nanometers (nm). However, the embodiments are not limited to this example. By way of example and not limitation, conductive materials 540-1, 540-2, ..., 540-4 may include one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.), and / or as such. Figure 3 One of its other combinations as described in the text.

[0082] As in Figure 5B As shown, conductive materials 540-1, 540-2, ..., 540-4 can be recessed backwards only along the slender vertical pillars (in Figure 5B The vertical sidewalls (now shown as 542-1, 542-2, and 542-3) in the cross-sectional views are preserved. Multiple individual vertical access lines formed by conductive materials 540-1, 540-2, ..., 540-4 can be recessed backwards by using a suitable selective anisotropic etching process to cut the conductive materials 540-1, 540-2, ..., 540-4 from the first vertical opening (e.g., ...). Figure 5A The bottom surface of 500 is removed to expose the gate dielectric 538 on the bottom surface to form individual vertical access lines 540-1, 540-2, ..., 540-4. (See also...) Figure 5B As shown, a dielectric material 539, such as an oxide or other suitable spin-on dielectric (SOD), can then be deposited in the first vertical opening 500 using a process such as CVD to fill the first vertical opening 500. The dielectric can be planarized to the top surface of a hard mask 535 of a vertical semiconductor stack using chemical mechanical planarization (CMP) or other suitable semiconductor manufacturing techniques. Subsequent photolithography material 536 (e.g., a hard mask) can be deposited using CVD and planarized using CMP to cover and close the first vertical opening 500 above the individual vertical access lines 540-1, 540-2, ..., 540-4. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0083] Figure 5B-1 For along Figure 5A The cross-sectional view taken by the cutting line A-A' shows alternating first or multiple first vertical openings (as in...). Figure 5AThe 513 described in the text) and the alternating second plurality of first vertical openings (such as Figure 5A Alternative embodiments of 517 described herein. Figure 5B-1 The embodiments shown herein are for forming a metal-insulator-semiconductor (MIS) interface as a channel contact for a channel region of a horizontal access device for a vertical three-dimensional (3D) memory as described herein. Figure 5B Same, Figure 5B-1 This describes a cross-sectional view of a semiconductor structure at a specific time during the semiconductor manufacturing process. Figure 5B-1 The cross-sectional view shown illustrates the repeated iteration of alternating layers of first dielectric material 530-1, 530-2, ..., 530-N, semiconductor material 532-1, 532-2, ..., 532-N, and second dielectric material 533-1, 533-2, ..., 533-N on semiconductor substrate 500 to form a vertical stack, for example, as shown in Figure 4, 401.

[0084] As in Figure 5B As shown in the example embodiments, alternating first plurality of first vertical openings 513-1 and alternating second plurality of first vertical openings 517-1 may each have a gate dielectric material 538 and vertical access lines 540-1, 540-2, ..., 540-4 formed therein. However, alternatively, Figure 5B-1 It is explained that conductive materials 540-1, 540-2, ..., 540-4 can be formed in alternating first plurality of first vertical openings (such as in...). Figure 5A On the gate dielectric material 538 described in 513), and the metal material, insulating material and semiconductor material (MIS) interface 587 / 589 (as described in FIG. 4) can be formed on alternating second plurality of first vertical openings (e.g. Figure 5A As described in 517). For example, in Figure 5B-1 As shown, conductive material 5516, for example, highly doped p-type (p+) polycrystalline silicon material, can be further deposited in alternating second plurality of first vertical openings 517-1 to form conductive contacts with MIS interfaces 587 / 589 and to serve as channel contacts in alternating second plurality of first vertical openings 517-1.

[0085] Alternatively, the metal, insulating, and semiconductor (MIS) interfaces 587 / 589 may be formed in alternating first plurality of first vertical openings 513. A conductive material 516, such as polysilicon, may be deposited in the alternating first plurality of first vertical openings 513 using a process such as CVD to fill the alternating first plurality of first vertical openings 513. The conductive material 516 may serve as a channel region contact and provide a conductive path for the MIS interface.

[0086] The gate material 540 and gate dielectric 538 can be formed in alternating first plurality of first vertical openings 513-1 by conformally depositing a second conductor material 540 on the gate dielectric material 538. MIS interfaces 589 / 587 can be formed in alternating second plurality of first vertical openings 517-1 by conformally depositing a first conductor material 589 on the insulating material 587. The first conductor material 589 can form the metallic portion of the MIS interfaces 587 / 589. In some embodiments, the first conductor material 589 and the second conductor material 540 can be the same material. In some embodiments, the first conductor material 589 is a different conductor material from the second conductor material 540.

[0087] By way of example and not limitation, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD) or other suitable deposition processes can be used to conformally deposit the interfaces of metallic materials, insulating materials and semiconductor materials (MIS) in alternating second plurality of first vertical openings 517-1 to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings.

[0088] The first conductor material 589 can be recessed rearward to remain only along the vertical sidewalls of the slender vertical pillar, now as in Figure 5B-1 As shown in the cross-sectional view. The first conductor material 589 can be patterned and separated to form multiple individual MIS channel contacts to the channel region of the elongated vertical pillars. The MIS interface can be used to facilitate the removal of holes from the channel region 516. The MIS interface can also be used to provide a potential barrier for electrons from the body contacts. In the alternating first plurality of first vertical openings 513-1, the second conductor material 540 can be recessed to form multiple individual vertical access lines.

[0089] Figure 6A This is an example method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines at another stage of the semiconductor manufacturing process, for example in... Figures 1 to 3 As described herein, and according to several embodiments of this disclosure. Figure 6A A top view of a semiconductor structure at a specific point in time, illustrating a semiconductor manufacturing process, is provided according to one or more embodiments. Figure 6A In an example embodiment, the method includes using a photolithography process to pattern... Figure 5B The photolithography masks in the middle are 636 and 536. Figure 6AThe method further illustrates the use of selective isotropic etching to remove portions of exposed conductive material 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z, to separately and individually form multiple individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z, for example, Figure 1 Access lines 103-1, 103-2, ..., 103-Q, etc. are shown. Therefore, multiple individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z are shown along the sidewall of a slender vertical support, for example along... Figure 5B The sidewalls of the slender vertical struts 542-1, 542-2 and 542-3 in the cross-sectional view.

[0090] As in Figure 6A As shown in the examples, the exposed conductive materials 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z can be rearwardly removed into the first vertical opening using a suitable selective isotropic etching process (e.g., Figure 5A The gate dielectric material 638 in (500) is as follows. Figure 6A As shown, a subsequent dielectric material 641, such as an oxide or other suitable spin-on dielectric (SOD), can be deposited to fill the remaining openings. Exposed conductive materials 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z can be removed from the remaining openings using processes such as CVD or other suitable techniques. The dielectric material 641 can be planarized onto the top surface of a previously hard mask 635 of a vertical semiconductor stack (e.g., 401 as shown in FIG. 4) using processes such as CMP or other suitable techniques. In some embodiments, CVD deposition and CMP planarization followed by photolithography material 537 (e.g., a hard mask) can be used to cover and enclose a plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and 640-Z above the working surface of the vertical semiconductor stack 401 in FIG. 4, thereby protecting the plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and 640-Z along the sidewalls of the elongated vertical pillars. However, the embodiments are not limited to these processing examples.

[0091] Figure 6A-1This is an example method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines at an alternative stage of semiconductor manufacturing processes, for example in... Figures 1 to 3 As described herein, and according to several embodiments of this disclosure. Figure 6A-1 A top view illustrating a semiconductor structure at a specific point in time during a semiconductor manufacturing process, according to one or more embodiments, having alternating first vertical openings 613 and second vertical openings 617.

[0092] Thus, the interface 687 / 689 of metallic, insulating, and semiconductor (MIS) materials can be displayed along the sidewall of an elongated vertical pillar, for example, along... Figure 5B-1 The sidewalls of the slender vertical struts 542-1, 542-2, and 542-3 in the cross-sectional view. The vertical MIS interfaces 687 / 689 can be separated by a conductive material 616. (As shown in...) Figure 6A-1 As shown, a conductive material 616, such as polycrystalline silicon, can then be deposited to fill openings 613 and 617. The conductive material 616 can be shown as being between the sidewalls of elongated vertical pillars. The conductive material 616 can be used as a contact in the channel area.

[0093] Figure 6B Explanation along Figure 6A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 6B The cross-sectional view shown is away from multiple individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and shows alternating layers of first dielectric material 630-1, 630-2, ..., 630-N, semiconductor material 632-1, 632-2, ..., 632-N, and second dielectric material 633-1, 633-2, ..., 633-N on semiconductor substrate 600, repeating iteratively to form a vertical stack, for example, as shown in Figure 4, 401. Figure 6B As shown, the vertical direction 611 is described as the third direction (D3), for example, the z-direction in the xyz coordinate system, similar to... Figures 1 to 3 The first, second, and third directions shown are in the third direction (D3) 111. The plane of the drawing extending left and right is on the first direction (D1) 609. Figure 6B In an example embodiment, dielectric material 641 is shown filling a vertical opening in the deposition of residual gate dielectric 638. The hard mask 637 described above covers the illustrated structure.

[0094] Figure 6C Explanation along Figure 6AThe cross-sectional view taken by the cutting line B-B' in the diagram shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 6C The cross-sectional view shown is illustrated as extending along an axis of alternating layers of first dielectric materials 630-1, 630-2, ..., 630-N, semiconductor materials 632-1, 632-2, ..., 632-N, and second dielectric materials 633-1, 633-2, ..., 633-N in a second direction (D2) 605, along which horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) may be formed within the semiconductor material layers 632-1, 632-2, ..., 632-N. Figure 6C In the drawing, adjacent opposite vertical access lines 640-3 are indicated by dashed lines, which indicate the position of the plane and orientation of the drawing.

[0095] Figure 6D Explanation along Figure 6A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 6D The cross-sectional view shown is illustrated as extending along a repeating axis in the second direction (D2) 605 along alternating layers of first dielectric material 630-1, 630-2, ..., 630-N, semiconductor material 632-1, 632-2, ..., 632-N, and second dielectric material 633-1, 633-2, ..., 633-N, outlining the region where the horizontally oriented access device and horizontally oriented memory node (e.g., capacitor cell) can be formed within the semiconductor material layers 632-1, 632-2, ..., 632-N. Figure 6C In the diagram, dielectric material 641 is shown filling the space between a horizontally oriented access device and a horizontally oriented memory node, which are spaced apart along a first direction (D1), extending into and out of the plane of the drawing to obtain a three-dimensional array of vertically oriented memory cells. At the left end of the drawing, alternating layers of first dielectric materials 630-1, 630-2, ..., 630-N, semiconductor materials 632-1, 632-2, ..., 632-N, and second dielectric materials 633-1, 633-2, ..., 633-N are shown in repeated iterations, with horizontally oriented digital lines (e.g., ...) at said locations. Figure 1 The digital lines shown in the figure (107-1, 107-2, ..., 107-P, etc.) can be integrated to form an electrical contact with the second source / drain region or the digital line conductive contact material (described in more detail below).

[0096] Figure 6E Explanation along Figure 6AThe cross-sectional view taken by the cutting line D-D' in the diagram shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 6E The cross-sectional view shown is illustrated from right to left on the plane of the drawing, extending along the axis of alternating layers of first dielectric material 630-1, 630-2, ..., 630-N, semiconductor material 632-1, 632-2, ..., 632-N, and second dielectric material 633-1, 633-2, ..., 633-N in the first direction (D1) 609, spanning multiple individual vertical access lines 640-1. The regions 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) intersect with the regions of semiconductor materials 632-1, 632-2, ..., 632-N, where a channel region can be formed, which is separated from the plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1) by the gate dielectric 638. Figure 6E In the illustration, a first dielectric filling material 639 is shown to separate the space between adjacent horizontally oriented access devices and horizontally oriented storage nodes, which may be formed to extend into and out of the plane of the drawing, as described in more detail below, and may be spaced apart along a first direction (D1) 609 and vertically stacked in an array extending along a third direction (D3) 611 in a three-dimensional (3D) memory.

[0097] Figure 7A This is an example method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines at another stage of the semiconductor manufacturing process, for example in... Figures 1 to 3 As described herein, and according to several embodiments of this disclosure. Figure 7A A top view of a semiconductor structure at a specific point in time, illustrating a semiconductor manufacturing process, is provided according to one or more embodiments. Figure 7A In an example embodiment, the method includes using a photolithography process to pattern photomasks 735, 736, and / or 737, for example... Figures 6A to 6E 635, 636 and / or 637. Figure 7A The method further illustrates the use of one or more etching processes to etch the memory node region 750 (and... Figure 7A and 7C A vertical opening 751 is formed in 744) through the vertical stack and extending primarily along the first horizontal direction (D1) 709. One or more etching processes are performed in a second region adjacent to the semiconductor material. Figures 7B to 7EThe vertical stack shown in the figure forms a vertical opening 751 to expose the third sidewall in the repeated iterations of alternating layers of first dielectric material 730-1, 730-2, ..., 730-N, semiconductor material 732-1, 732-2, ..., 732-N, and second dielectric material 733-1, 733-2, ..., 733-N. Other numbered components may be similar to those components shown and discussed in conjunction with Figure 6.

[0098] In some embodiments, this process is combined Figure 4A to 4K The described semiconductor manufacturing process was performed prior to this. However, Figures 7B to 7E The embodiments shown illustrate the formation (in conjunction with) of the executed digital line 777, insulating material 787, first conductor material 789, and first source / drain region. Figure 4A to 4K (As described) "followed by" the sequence of the memory node manufacturing process, such as first forming the digital lines. Here, the digital lines 777 can be described as running along multiple individual vertical access lines 740.

[0099] According to the example implementation, in Figures 7B to 7E As shown in the figure, the method includes vertical stacking ( Figure 4A A second vertical opening 751 is formed in the vertical stack (401), and the second regions 744 of the semiconductor materials 732-1, 732-2, ..., 732-N are selectively etched to form a second horizontal opening 779, from the vertical stack ( Figure 4A The vertical opening 751 of 401 is extended backward by a second horizontal distance (D2 opening). According to an embodiment, selectively etching the second region 744 of the semiconductor material 732-1, 732-2, ..., 732-N may include using an atomic layer etching (ALE) process. (The last sentence appears to be incomplete and possibly refers to a different context.) Figure 7C To further explain, the second source / drain region 778 can be formed in the semiconductor materials 732-1, 732-2, ..., 732-N at the far end of the second horizontal opening 779 from the vertical opening.

[0100] Figure 7B Explanation along Figure 7A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 7BThe cross-sectional view shown is away from multiple individual vertical access lines 740-1, 740-2, ..., 740-N, 740-(N+1), ..., 740-(Z-1), and shows alternating layers of dielectric materials 730-1, 730-2, ..., 730-(N+1), semiconductor materials 732-1, 732-2, ..., 732-N, and second dielectric materials 733-1, 733-2, ..., 733-N separated by openings 751 on a semiconductor substrate 700, forming a vertical stack. Figure 7B As shown, the vertical direction 711 is described as a third direction (D3), for example, the z-direction in the xyz coordinate system, similar to... Figures 1 to 3 The first, second, and third directions shown are in the third direction (D3) 111. The plane of the drawing extending left and right is on the first direction (D1) 709. Figure 7B In an example embodiment, the materials within the vertical stack—dielectric materials 730-1, 730-2, ..., 730-(N+1), semiconductor materials 732-1, 732-2, ..., 732-N; and second dielectric materials 733-1, 733-2, ..., 733-N—extend along the second direction (D2) and along the orientation axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory into the plane of the drawing and out of the plane of the drawing.

[0101] Figure 7C Explanation along Figure 7A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an exemplary semiconductor manufacturing process of an embodiment of this disclosure. Figure 7C The cross-sectional view shown is illustrated as extending along the plane of the drawing in the second direction (D2) 705, along the axis of repeated iterations of alternating layers of first dielectric material 730-1, 730-2, ..., 730-N, semiconductor material 732-1, 732-2, ..., 732-N, and second dielectric material 733-1, 733-2, ..., 733-N, and wherein the horizontally oriented access device and the horizontally oriented storage node (e.g., capacitor cell) may be formed within the semiconductor material layers 732-1, 732-2, ..., 732-N.

[0102] exist Figure 7C In the example embodiment, the vertical opening 751 and the horizontal opening 779 are shown to be combined Figure 7A The masking, patterning, and etching processes described are used to create the image. For example, in... Figure 7CAs shown, semiconductor materials 732-1, 732-2, ..., 732-N in the second region 744 have been selectively removed to form a horizontal opening 779. In one example, an atomic layer etching (ALE) process is used to selectively etch semiconductor materials 732-1, 732-2, ..., 732-N, and then a second distance (D2 opening) is removed backward from the vertical opening 751. Figures 8A to 8E As shown in the image, later or first, relative to Figure 4A to 4K The manufacturing process shown herein can form horizontally oriented storage nodes, such as capacitor cells, in the second horizontal opening 779.

[0103] exist Figure 7C The diagram also shows that a first source / drain region 775 can be formed by vapor-doping a dopant into a portion of the top surface of semiconductor material 732. In some embodiments, the first source / drain region 775 may be adjacent to the vertical access line 740. According to one example embodiment, as in... Figure 7C As shown, a second source / drain region 778 can be formed at the distal end of the second horizontal opening 779 from the vertical opening 751 by the following operation: a high-energy vapor-phase dopant of phosphorus (P) used in n-type transistors flows into the second horizontal opening 779 to dope the dopant in semiconductor materials 732-1, 732-2, ..., 732-N. In one example, vapor-phase doping can be used to achieve highly isotropic non-directional doping to form the horizontally oriented access device in the second source / drain region 778 to region 742. In another example, the bonding can be broken by thermal annealing of a dopant gas, such as phosphorus, under high-energy plasma assistance. However, the embodiments are not limited to these, and other suitable semiconductor manufacturing techniques can be utilized.

[0104] The second conductor material 777 may be deposited adjacent to the second dielectric material 733. The second conductor material 777 may be deposited on the insulator material 787 and the first conductor material 789. Thus, the second conductor material 777, connected to the first conductor material 789 and the insulator material 787, may form a horizontally oriented digital line contact with the first source / drain region 775. In some embodiments, the third dielectric material 774 may simultaneously maintain direct contact with the insulator material 787, the first conductor material 789 and the second conductor material 777, the source / drain region 775 and a first portion of the lightly doped semiconductor material 732 under the first dielectric material 730. The third dielectric material 774 may form a direct electrical contact with the conductive material 795 (e.g., the body region contact of the horizontally oriented access device).

[0105] As in Figure 7C Further, it is shown that the first electrode (e.g., 761) for the horizontally oriented memory node will be coupled to the second source / drain region 778 of the horizontal access device. As will be shown later... Figure 7C As shown, such horizontally oriented storage nodes are formed in a second horizontal opening 779, which is in a second direction (D2), horizontally in the plane of the drawing, and at a distance from the vertical stack (e.g., Figure 4A The vertical opening 751 in 401) is the second distance (D2 opening), and extends along the orientation axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory. Figure 7C In the drawing, adjacent relative vertical access lines 740-3 are indicated by dashed lines, which indicate the positions set inward from the plane and direction of the drawing.

[0106] Figure 7D Explanation along Figure 7A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 7D The cross-sectional view shown is illustrated as follows: Along the second direction (D2) 705, on the left and right sides of the plane of the drawing, an axis extending from alternating layers of first dielectric materials 730-1, 730-2, ..., 730-N, semiconductor materials 732-1, 732-2, ..., 732-N, and second dielectric materials 733-1, 733-2, ..., 733-N, a region is shown where horizontally oriented access devices and horizontally oriented memory nodes (e.g., capacitor cells) will be formed within the semiconductor material layers 732-1, 732-2, ..., 732-N. The left end of the drawing shows the alternating layers of first dielectric materials 730-1, 730-2, ..., 730-N, semiconductor materials 732-1, 732-2, ..., 732-N, and second dielectric materials 733-1, 733-2, ..., 733-N, where horizontally oriented digital lines (e.g., ...) are located. Figure 1 The digital lines 107-1, 107-2, ..., 107-P shown in the figure can be integrated with the first source / drain region or the conductive contact material of the digital line (as described above). Figure 4A to 4K (As described) to form an electrical contact.

[0107] Furthermore, while the terms "first" and "second" source / drain region are used in this document to refer to two separate and distinct source / drain regions, this does not imply that the source / drain regions referred to as "first" and / or "second" have any unique meaning. It simply means that one of the source / drain regions is connected to a digital line, e.g., 107-2, while the other can be connected to a memory node.

[0108] In some embodiments, the second conductor material 777 may be described as being adjacent to the second dielectric material 733. The second conductor material 777 may be adjacent to the dielectric material 741. The body contact region 795 may be described as being along alternating layers of first dielectric materials 730-1, 730-2, ..., 730-N, semiconductor materials 732-1, 732-2, ..., 732-N, and second dielectric materials 733-1, 733-2, ..., 733-N in repeated iterations.

[0109] Figure 7E Explanation along Figure 7A The cross-sectional view taken by the cutting line D-D' in the diagram shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 7E The cross-sectional view shown is illustrated in the drawing plane from right to left, extending along the axis of alternating layers of first dielectric materials 730-1, 730-2, ..., 730-N, semiconductor materials 732-1, 732-2, ..., 732-N, and second dielectric materials 733-1, 733-2, ..., 733-N in a first direction (D1) 709, crossing multiple individual vertical access lines 740-1, 740-2, ..., 740-4, and intersecting with regions of semiconductor materials 732-1, 732-2, ..., 732-N, where channel regions can be formed, separated from the multiple individual vertical access lines 740-1, 740-2, ..., 740-4 by a gate dielectric 738. Figure 7E In the diagram, a first dielectric filling material 739 is shown separating the space between adjacent horizontally oriented access devices, which can be formed to extend into and out of the plane of the drawing, as in combination with... Figure 4A to 4K The array described herein is spaced apart along a first direction (D1) 709 and stacked vertically in a three-dimensional (3D) memory extending along a third direction (D3) 711.

[0110] Figure 8A This is an example method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines at another stage of the semiconductor manufacturing process, for example in... Figures 1 to 3 As described herein, and according to several embodiments of this disclosure. Figure 8A A top view of a semiconductor structure at a specific point in time, illustrating a semiconductor manufacturing process, is provided according to one or more embodiments. Figure 8A In an example embodiment, the method includes using a photolithography process to pattern photomasks 835, 836, and / or 837, for example... Figures 6A to 6E 635, 636 and / or 637, or Figures 7A to 7E 735, 736 and / or 737. Figure 8AThe method further illustrates the use of one or more etching processes to etch the memory node region 850 (and... Figure 8A and 8C A vertical opening 851 is formed in 844) through the vertical stack and extending primarily along the first horizontal direction (D1) 809. One or more etching processes are performed in a second region adjacent to the semiconductor material. Figures 8B to 8E The vertical stack shown in the figure forms a vertical opening 851 to expose the third sidewall in the repeated iterations of alternating layers of first dielectric material 830-1, 830-2, ..., 830-N, semiconductor material 832-1, 832-2, ..., 832-N, and second dielectric material 833-1, 833-2, ..., 833-N. Other numbered components may be similar to those shown and discussed in conjunction with Figures 6 and 7.

[0111] In some embodiments, as illustrated in FIG7, this process is performed after selectively removing the access device region of the semiconductor material, in which a first source / drain region, a channel region, and a second source / drain region of the horizontally oriented access device are formed. According to an example embodiment, in Figures 8B to 8E As shown, the method includes selectively etching second regions of semiconductor materials 832-1, 832-2, ..., 832-N, depositing second source / drain regions and capacitor cells through a second horizontal opening, the second horizontal opening being rearward at a second horizontal distance from the vertically stacked vertical opening 851. In some embodiments, such as in Figures 8B to 8E As shown, the method includes forming capacitor cells as storage nodes within a second horizontal opening. By way of example, and not limitation, forming the capacitors includes using an atomic layer deposition (ALD) process to sequentially deposit a first electrode 861 and a second electrode 856 separated by a cell dielectric 863 within the second horizontal opening. Other suitable semiconductor fabrication techniques and / or storage node structures may be used. Digital lines 877 are visible along a plurality of individual vertical access lines 840.

[0112] Figure 8B Explanation along Figure 8A The cross-sectional view taken by the cutting line AA′ in the figure shows another view of the semiconductor structure at this particular point in an exemplary semiconductor manufacturing process of an embodiment of this disclosure. Figure 8BThe cross-sectional view shown is away from multiple individual vertical access lines 840-1, 840-2, ..., 840-N, 840-(N+1), ..., 840-(Z-1) and shows a repeating iteration of alternating multilayer dielectric materials 830-1, 830-2, ..., 830-(N+1), separated by horizontally oriented capacitor cells having a first electrode 861 (e.g., bottom cell contact electrode), a cell dielectric 863, and a second electrode 856 (e.g., top, common node electrode) on a semiconductor substrate 800 to form a vertical stack. Figure 8B As shown, the vertical direction 811 is described as a third direction (D3), for example, the z-direction in the xyz coordinate system, similar to... Figures 1 to 3 The first, second, and third directions shown are in the third direction (D3) 111. The plane of the drawing extending left and right is on the first direction (D1) 809. Figure 8B In an example embodiment, the first electrode 861 (e.g., the bottom electrode to be coupled to the source / drain region of the horizontal access device) and the second electrode 856 are described as being separated by a cell dielectric material 863 that extends along a second direction (D2) and along the orientation axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory into and out of the plane of the drawing.

[0113] Figure 8C Explanation along Figure 8A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an exemplary semiconductor manufacturing process of an embodiment of this disclosure. Figure 8C The cross-sectional view shown is illustrated as extending along the plane of the drawing in the second direction (D2) 805, along the axis of alternating layers of first dielectric materials 830-1, 830-2, ..., 830-N, semiconductor materials 832-1, 832-2, ..., 832-N, and second dielectric materials 833-1, 833-2, ..., 833-N in a repeating iteration, and along which horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) may be formed within the semiconductor material layers 832-1, 832-2, ..., 832-N. Figure 8CIn the example embodiment, the horizontally oriented memory node (e.g., a capacitor cell) is described as having been formed using this semiconductor manufacturing process, and shows a first electrode 861 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and a second electrode 856 (e.g., a top electrode to be coupled to a common electrode plane, such as a ground plane) separated by a cell dielectric 863. However, the embodiments are not limited to this example. In other embodiments, the first electrode 861 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and the second electrode 856 (e.g., a top electrode to be coupled to a common electrode plane, such as a ground plane) separated by a cell dielectric 863 may be formed after the first source / drain region, the channel region, and the second source / drain region are formed in regions of semiconductor materials 832-1, 832-2, ..., 832-N, at a location designated for the horizontally oriented access device described below, for example, placement formation.

[0114] exist Figure 8C In an example embodiment, a horizontally oriented memory node having a first electrode 861 (e.g., a bottom electrode to be coupled to the source / drain region of a horizontal access device) and a second electrode 856 (e.g., a top electrode to be coupled to a common electrode plane, such as a ground plane) is shown formed in a second horizontal opening (e.g., Figure 7C As shown in 779), in the second direction (D2), on the left and right sides of the plane of the drawing, the distance is formed in the vertical stack (e.g., Figure 4A The vertical opening in 401) (e.g., Figure 7C The second distance (D2 opening) of 751) extends along the directional axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory. Figure 8C In the drawing, adjacent relative vertical access lines 840-3 are indicated by dashed lines, which indicate the positions set inward from the plane and direction of the drawing.

[0115] The second conductor material 877 may be described as being adjacent to the second dielectric material 833. The second conductor material 877 may be formed on the first conductor material 889 and the insulating material 887. Thus, the second conductor material 877, connected to the first conductor material 889 and the insulating material 887, may form a horizontally oriented digital line contact with the first source / drain region 875. In some embodiments, the third dielectric material 874 may be below the first dielectric material 830 and simultaneously maintain direct contact with the second conductor material 877, the first conductor material 889, the insulating material 887, the first source / drain region 875, and a first portion of the lightly doped semiconductor material 832. The third dielectric material 874 may form a direct electrical contact with the conductive material 895 (e.g., the body region contact of the horizontally oriented access device).

[0116] Figure 8D Explanation along Figure 8A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 8D The cross-sectional view shown is illustrated as extending along the second direction (D2) 805 in the plane of the drawing, left and right, along the alternating axes of multiple layers of first dielectric material 830-1, 830-2, ..., 830-N, semiconductor material 832-1, 832-2, ..., 832-N, and second dielectric material 833-1, 833-2, ..., 833-N, in the region where the horizontally oriented access device and horizontally oriented storage node (e.g., capacitor cell) can be formed within the semiconductor material 832-1, 832-2, ..., 832-N layers. Figure 8C In the illustration, dielectric material 841 is shown filling the space between horizontally oriented access devices, which are spaced apart along a first direction (D1), extending into and out of the plane of the drawing, to obtain a three-dimensional array of vertically oriented memory cells. However, in Figure 8D In the cross-sectional view, a second electrode 856 is also shown, for example, the top common electrode of the capacitor cell structure, existing in the space between horizontally adjacent devices. At the left end of the drawing, alternating layers of first dielectric materials 830-1, 830-2, ..., 830-N, semiconductor materials 832-1, 832-2, ..., 832-N, and second dielectric materials 833-1, 833-2, ..., 833-N are shown in repeated iterations, with horizontally oriented digital lines (e.g., ...) at said locations. Figure 1 The digital lines 107-1, 107-2, ..., 107-P shown in the figure can be integrated to form an electrical contact with the second source / drain region or the digital line conductive contact material (described in more detail below).

[0117] In some embodiments, the second conductor material 877 may be described as being adjacent to the second dielectric material 833. The insulator material 887 and the first conductor material 889 may not be described. The second conductor material 877 may be adjacent to the dielectric material 841. The body contact region 895 may also be described as being along alternating layers of first dielectric materials 830-1, 830-2, ..., 830-N, semiconductor materials 832-1, 832-2, ..., 832-N, and second dielectric materials 833-1, 833-2, ..., 833-N in a repeating iteration.

[0118] Figure 8E Explanation along Figure 8A The cross-sectional view taken by the cutting line D-D' in the diagram shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 8E The cross-sectional view shown is illustrated in the drawing plane from right to left, extending along the axis of alternating layers of first dielectric materials 830-1, 830-2, ..., 830-N, semiconductor materials 832-1, 832-2, ..., 832-N, and second dielectric materials 833-1, 833-2, ..., 833-N in a first direction (D1) 809, crossing multiple individual vertical access lines 840-1, 840-2, ..., 840-4, and intersecting with regions of semiconductor materials 832-1, 832-2, ..., 832-N, where channel regions can be formed, separated from the multiple individual vertical access lines 840-1, 840-2, ..., 840-4 by a gate dielectric 838. Figure 8E In the diagram, a first dielectric filling material 839 is shown to separate the space between adjacent horizontally oriented access devices and horizontally oriented storage nodes, which may be formed to extend into and out of the plane of the drawing, as described in more detail below, and may be spaced apart along a first direction (D1) 809 and vertically stacked in an array extending along a third direction (D3) 811 in a three-dimensional (3D) memory.

[0119] Figure 9A According to several embodiments of the present disclosure, a cross-sectional view is provided of a portion of an example horizontally oriented access device coupled to a horizontally oriented memory node and coupled to vertically oriented access lines and horizontally oriented digital lines, and which may form part of a vertically stacked memory cell array. The horizontally oriented access device 901 may have a first source / drain region and a second source / drain region separated by a channel region, and a gate opposite to the channel region and separated from it by a gate dielectric.

[0120] As in Figure 9A As shown in the example, the first source / drain region 975-1 is illustrated as being in direct electrical contact with the horizontally oriented digital line 977-1. In some embodiments, the conductive digital lines 977-1 and 977-2 are formed of a metallic composition including tungsten (W). However, the embodiments are not limited to this example. Although the terms “first” and “second” source / drain regions may be used herein to designate different and separate source / drain regions, the terms “first” and / or “second” are not limited to the corresponding source / drain regions, and their respective placement and their respective “first” or “second” labels may be interchanged within the horizontally oriented access device described herein for convenience. For example, the first source / drain region 975-1 may be equivalently referred to as the “second” source / drain region 975-1. Regardless of whether the source / drain region is labeled “first” or “second”, it may be separated from another source / drain region by a channel region in the body of the horizontal access device.

[0121] An insulator material 987 and a conductor material 989 may be formed between the conductive digital line 977-1 and the first source / drain region 975-1. The insulator material 987 may be deposited on the first source / drain region 975-1. In some embodiments, the insulator material 987-1 may be deposited below the conductive digital line 977-2. In some embodiments, the insulator material 987 may include lanthanum oxide (La2O3). In some embodiments, the insulator material may include zirconium oxide (ZrO2). In some embodiments, the insulator material may include titanium oxide (TiO2). The conductor material 989 may be deposited on the insulator material 987 to form a metal, insulator, and semiconductor (MIS) interface with the first source / drain region 975. In some embodiments, the conductor material 989 may include molybdenum (Mo). In some embodiments, the conductor material 989 may include ruthenium (Ru). In some embodiments, the conductor material 989 may include lanthanum (La). However, the embodiments are not limited to these examples.

[0122] exist Figure 9A In this example, a first source / drain region 975-1 is illustrated to be formed in the body of the horizontally oriented access device 901, within a lightly doped, p-type (p-) channel and body region. The first source / drain region 975-1 is separated from the vertical body contact 995 by a dielectric material 974. As shown, interlayer dielectric (ILD) materials 930-1 and 930-2 can separate the horizontally oriented access devices of the vertically stacked memory cells. The interlayer dielectric materials 930-1 and 930-2 can be of a first dielectric material type, such as an oxide-based dielectric material. However, the embodiments are not limited to this example.

[0123] exist Figure 9A In one example, horizontally oriented digital lines, such as 977-1 and 977-2, are formed with a second dielectric material type (e.g., a nitride-based dielectric material). However, the embodiments are not limited to this example. According to an embodiment, the first dielectric material and the second dielectric material are of different compositions and are different, such that a second dielectric nitride material can be selectively etched, for example, relative to the first dielectric material (e.g., an oxide material). The first dielectric materials 930-1 and 930-2, the horizontally oriented access device 901 including a first source / drain region 975-1 and a p-type channel in the body region 932-1, and the digital lines 977-1 and 977-2 form three layers of a vertically stacked memory cell.

[0124] As in Figure 9AAs shown in the example embodiments, the vertical body contact 995 is formed to make direct electrical contact with one or more body regions 932-1 in the horizontally oriented access device 901. In some embodiments, the vertical body contact 995 may be a metal such as tungsten (W). In some embodiments, the vertical body contact 995 may be a conductive doped polycrystalline silicon material, such as a highly doped p-type (p+) polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples. As used herein, the term "highly doped" is intended to mean a high concentration of dopant impurities such that there are significant interactions between the dopant atoms. The p-type dopant may contain boron atoms (B), and the n-type dopant may contain phosphorus atoms (P). According to the embodiments, the vertical body contact 995 is separated from the first source / drain region 975-1 and the horizontally oriented digital lines 977-1 and 977-2 by a dielectric 974 (e.g., SiN in this example).

[0125] In some embodiments, dielectric 974 further defines a first portion of the body region 932-1 of the horizontally oriented access device 901 (e.g., Figure 4H 478) is separated from the vertical body contact 995 to reduce void formation in the body region 932-1 between the vertical body contact 995 and the body region 932-1. In some embodiments, the dielectric 974 further separates a first portion (e.g., ) of the body region 932-1 of the horizontally oriented access device 901. Figure 4H 478) is separated from the vertical body contact 995 to reduce gate-induced drain leakage (GIDL) in the horizontally oriented access device 901. In some embodiments, the horizontally oriented memory node (e.g., as shown in Figure 478) is separated from the vertical body contact 995 to reduce gate-induced drain leakage (GIDL) in the horizontally oriented access device 901. Figure 7C The capacitor cell shown in the figure is coupled to a second source / drain region (not shown in Figure 9). In this example, the capacitor cell has a first horizontally oriented electrode electrically coupled to the second source / drain region and a second horizontally oriented electrode separated from the first horizontally oriented electrode by the cell dielectric.

[0126] Therefore, as shown in the example embodiment of FIG9, vertical conductive body contact lines 995, for example, made of highly doped semiconductor material, can be deposited into vertical openings 995 to form conductive body contacts directly and only with portions of the horizontally oriented access device via channels and body regions 932-1 made of low-doped semiconductor material.

[0127] According to an embodiment, a second dielectric material 974 is deposited to form a small direct electrical contact area between the conductive body contact 995 and the channel in the body region 932-1 of the horizontally oriented access device, while also providing direct electrical isolation from the directly electrically connected first source / drain regions 975-1 and digital lines 977-1 and 977-2. The small direct electrical contact area between the conductive body contact 995 and the channel in the body region 932-1, and the electrical isolation from the first source / drain regions 975-1 and digital lines 977-1 and 977-2, reduces capacitive coupling between the body contact 995 and the first source / drain regions 975-1 and digital lines 977-1 and 977-2. The small direct electrical contact area also blocks hole diffusion between the highly doped semiconductor material 995 and the body region 932-1.

[0128] Figure 9B According to several embodiments of this disclosure, a cross-sectional view of a portion of an example horizontally oriented access device is illustrated. This horizontally oriented access device is coupled to a horizontally oriented memory node and to vertically oriented access lines and horizontally oriented digital lines, and may form part of a vertically stacked memory cell array. In this embodiment, the body contacts may include an insulating material and a conductive material in contact with a semiconductor conductor. The horizontally oriented access device 901 may have a first source / drain region and a second source / drain region separated by a channel region, and a gate opposite the channel region and separated from it by a gate dielectric.

[0129] Insulator material 987 and conductor material 989 can form electrical contacts with the body region of the horizontally oriented access device 901. Insulator material 987 and conductor material 989 can form a metal, insulating, and semiconductor (MIS) interface with a p-type channel in body region 932-1. In one embodiment, titanium material can be formed on silicon material in the p-type channel to form titanium silicide; and tungsten material can be formed on titanium silicide to form a conductive body contact. The MIS interface can be formed to contact body region 932-2, as repeated in a vertical stack.

[0130] Figure 10 This is a block diagram of a device in the form of a computing system 1000 including a memory device 1003, according to various embodiments of the present disclosure. As used herein, for example, the memory device 1003, memory array 1010, and / or host 1002 may also be individually considered a "device". According to an embodiment, according to the embodiment described herein, the memory device 1002 may include at least one memory array 1010 having memory cells formed with digital lines having a metal-insulator-semiconductor (MIS) interface between the digital lines and a first source / drain region.

[0131] In this example, system 1000 includes a host 1002 coupled to memory device 1003 via interface 1004. Among various other types of systems, computing system 1000 may be a personal laptop computer, desktop computer, digital camera, mobile phone, memory card reader, or Internet of Things (IoT) enabled device. Host 1002 may include multiple processing resources (e.g., one or more processors, microprocessors, or other types of control circuitry) capable of accessing memory 1003. System 1000 may include a separate integrated circuit, or both host 1002 and memory device 1003 may be on the same integrated circuit. For example, host 1002 may be a system controller for a memory system comprising multiple memory devices 1003, wherein system controller 1005 provides access to the respective memory devices 1003 via another processing resource, such as a central processing unit (CPU).

[0132] exist Figure 10 In the example shown, host 1002 is responsible for executing the operating system (OS) and / or various applications (e.g., processes) that can be loaded onto it (e.g., from memory device 1003 via controller 1005). The OS and / or various applications can be loaded from memory device 1003 by providing access commands from host 1002 to memory device 1003 to access data including the OS and / or various applications. Host 1002 can also access data used by the OS and / or various applications by providing access commands to memory device 1003 to retrieve said data used in the execution of the OS and / or various applications.

[0133] For clarity, system 1000 has been simplified to focus on features particularly relevant to this disclosure. Memory array 1010 may be a DRAM array comprising at least one memory cell having a digital line having a metal-insulator-semiconductor (MIS) interface between the digital line and a first source / drain region formed according to the techniques described herein. For example, memory array 1010 may be an unshielded DL 4F2 array, such as a 3D-DRAM memory array. Array 1010 may include memory cells arranged in rows coupled by word lines (which may be referred to herein as access lines or select lines) and columns coupled by digital lines (which may be referred to herein as sense lines or data lines). Although Figure 10 The illustration shows a single array 1010, but the embodiments are not limited thereto. For example, the memory device 1003 may include multiple arrays 1010 (e.g., multiple DRAM cell memory blocks).

[0134] Memory device 1003 includes address circuitry 1006 for latching address signals provided via interface 1004. The interface may include, for example, a physical interface employing a suitable protocol (e.g., a data bus, address bus, and command bus, or a combined data / address / command bus). This protocol may be custom or proprietary, or interface 1004 may employ a standardized protocol, such as PCIe, Gen-Z, CCIX, etc. Address signals are received and decoded by row decoder 1008 and column decoder 1012 to access memory array 1010. Data can be read from memory array 1010 by sensing changes in voltage and / or current on a sensing line sensed by sensing circuitry 1011. Sensing circuitry 1011 may include, for example, a sensing amplifier that can read and latch pages (e.g., rows) of data from memory array 1010. I / O circuitry 1007 can be used for bidirectional data communication with host 1002 via interface 1004. The read / write circuitry 1013 is used to write data to or read data from the memory array 1010. As an example, the circuitry 1013 may include various drivers, latching circuitry, etc.

[0135] Control circuitry system 1005 decodes signals provided by host 1002. These signals may be commands provided by host 1002. These signals may include chip enable signals, write enable signals, and address latch signals, which control operations performed on memory array 1010, including data read operations, data write operations, and data erase operations. In various embodiments, control circuitry system 1005 is responsible for executing instructions from host 1002. Control circuitry system 1005 may include a state machine, a sequencer, and / or some other type of control circuitry system, which may be implemented in hardware, firmware, or software, or any combination of these. In some instances, host 1002 may be a controller external to memory device 103. For example, host 1002 may be a memory controller coupled to the processing resources of a computing device.

[0136] The term semiconductor can refer to, for example, a material, a wafer, or a substrate, and includes any basic semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a substrate semiconductor structure, and other semiconductor structures. Furthermore, when referring to the semiconductor described above, regions / junctions may have been formed in the substrate semiconductor structure using prior processing steps, and the term semiconductor may include an underlying material containing such regions / junctions.

[0137] The figures in this document follow a convention where the first or first few digits correspond to the figure number of the diagram, and the remaining digits identify the elements or components in the diagram. Similar (e.g., identical) elements or components between different figures can be identified by using similar digits. It will be understood that elements shown in the various embodiments herein may be added, swapped, and / or removed to provide multiple additional embodiments of this disclosure. Furthermore, it will be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate embodiments of this disclosure and should not be considered limiting.

[0138] As used herein, “multiple” or “a certain number” of something can refer to one or more of such things. For example, multiple or a certain number of memory cells can refer to one or more memory cells. “Multiple” something means two or more. As used herein, multiple actions performed simultaneously refer to actions that at least partially overlap within a specific time period. As used herein, the term “coupled” can include not electrically coupled to an intermediate element, directly coupled and / or directly connected (e.g., through direct physical contact), or indirectly coupled and / or connected to an intermediate element, or wirelessly coupled. The term “coupled” can further include two or more elements that cooperate or interact with each other (e.g., as in a causal relationship). An element coupled between two elements can be between the two elements and coupled to each of the two elements.

[0139] It should be recognized that the term "vertical" takes into account variations in perpendicularity due to routine manufacturing, measurement, and / or assembly, and the meaning of the term "vertical" will be known to those skilled in the art. For example, vertical may correspond to the z-direction. As used herein, when a particular element is "adjacent" to another element, the particular element may cover the other element, may be above the other element, or may be on the side of the other element and / or may be in direct physical contact with the other element. For example, "side" may refer to a horizontal direction that may be perpendicular to the z-direction (e.g., the y-direction or x-direction).

[0140] While specific embodiments have been described and illustrated herein, those skilled in the art will understand that arrangements intended to achieve the same results may be substituted for the specific embodiments shown. This invention is intended to cover variations or modifications of various embodiments of this disclosure. It should be understood that the above description has been made in an illustrative rather than limiting manner. Upon review of the above description, those skilled in the art will readily recognize combinations of the above embodiments and other embodiments not specifically described herein. The scope of the various embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined by reference to the entire scope of the appended claims together with their equivalents.

Claims

1. A method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines, the method comprising: A vertical stack (401) is formed by vertically depositing multiple layers of first dielectric material (430, 530, 630, 730, 830, 930), semiconductor material (432, 532, 632, 732, 832, 932) and second dielectric material (433, 533, 633, 733, 833, 933) in a repetitive iterative manner. The semiconductor material (432, 532, 632, 732, 832, 932) comprises a lightly doped semiconductor material, in which a first source / drain region (321, 475, 775, 875, 975) and a second source / drain region (323, 478, 778) are formed horizontally separated by channel regions (225, 325). Vertical openings (471, 513 / 517, 613 / 617) are formed using a first etching process to expose the vertical sidewalls in the vertical stack (401); The second dielectric material (433, 533, 633, 733, 833, 933) is selectively etched to form a first horizontal opening (473); An insulating material (487, 587, 687, 787, 887, 987) is deposited on the surface above the first source / drain regions (321, 475, 775, 875, 975) in the first horizontal opening (473); A first conductor material (489, 589, 789, 889) is deposited on the surface of the insulating material (487, 587, 687, 787, 887, 987) in the first horizontal opening (473) to form a horizontally oriented digital line contact with the first source / drain region (321, 475, 775, 875, 975), wherein the first conductor material (489, 589, 789, 889), the insulating material (487, 587, 687, 787, 887, 987) and the first source / drain region (321, 475, 775, 875, 975) constitute a metal-insulator-semiconductor (MIS) interface; A second conductor material (477, 777, 877) is deposited on the first conductor material (489, 589, 789, 889) to form a digital line in the first horizontal opening (473).

2. The method of claim 1, wherein depositing the insulating material comprises depositing a plurality of different insulating materials in combination.

3. The method of claim 1, further comprising, prior to depositing the insulating material, vapor-doping a low-n-type dopant (n-) into the top surface of a low-doped p-type (p-) semiconductor material to form the first source / drain region, such that the first source / drain region has a lower dopant concentration than the second source / drain region.

4. The method according to any one of claims 1 to 3, wherein depositing the insulating material includes forming a lanthanum oxide (La2O3) layer on the first source / drain region to a thickness (t1) in the range of two (2) angstroms (Å) to ten (10) angstroms (Å).

5. The method according to any one of claims 1 to 3, wherein depositing the insulating material comprises forming a zirconium oxide (ZrO2) layer on the first source / drain region to a thickness (t1) in the range of two (2) angstroms (Å) to ten (10) angstroms (Å).

6. The method according to any one of claims 1 to 3, wherein depositing the insulating material includes forming a titanium oxide (TiO2) layer on the first source / drain region to a thickness (t1) in the range of two (2) angstroms (Å) to ten (10) angstroms (Å).

7. The method according to any one of claims 1 to 3, wherein depositing the first conductor material comprises depositing ruthenium (Ru) on the surface of the insulating material.

8. The method according to any one of claims 1 to 3, wherein depositing the first conductor material comprises depositing lanthanum (La) on the surface of the insulating material.

9. The method according to any one of claims 1 to 3, wherein depositing the first conductor material comprises depositing molybdenum (Mo) on the surface of the insulating material.

10. The method according to any one of claims 1 to 3, wherein depositing the insulating material comprises using an atomic layer deposition (ALD) process to deposit the insulating material on the first source / drain region.

11. The method according to any one of claims 1 to 3, wherein depositing the second conductor material comprises depositing tungsten (W) on the first conductor material to form the digital line.

12. The method according to any one of claims 1 to 3, wherein the method further comprises: Selectively etch the first conductor material and the second conductor material, the insulating material, the first source / drain region and a first portion of the lightly doped semiconductor material below the first source / drain region to form a second horizontal opening, the second horizontal opening extending horizontally backward a second distance from the vertical opening; A third dielectric material (474, 774, 874) is deposited laterally adjacent to the first and second conductor materials and the first source / drain region in the second horizontal opening (472, 779); and Conductive material is deposited into the vertical opening to form a conductive body contact with the second portion (479) of the lightly doped semiconductor material.

13. A method for forming a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines, the method comprising: A vertical stack (401) of semiconductor materials (432, 532, 632, 732, 832, 932) having channel regions (225, 325) and a second dielectric material (433, 533, 633, 733, 833, 933) is formed to form a first horizontal direction (509, 609, 709, 809). 9) and a plurality of first vertical openings (471, 513 / 517, 613 / 617) in the second horizontal direction (505, 605, 705, 805), the plurality of first vertical openings (471, 513 / 517, 613 / 617) extending mainly along the second horizontal direction (505, 605, 705, 805) to form an elongated vertical pillar with sidewalls in the vertical stack (401); The first conductive material (495, 540, 640, 795, 895) is conformally deposited on the gate dielectric material (304, 538, 638, 738, 838) in alternating first plurality of first vertical openings (471, 513, 613); A portion of the first conductive material (495, 540, 640, 795, 895) in the alternating first plurality of first vertical openings (471, 513, 613) is removed to form a plurality of individual vertical access lines along the sidewall of the elongated vertical pillar. The first conductor material (489, 589, 789, 889) is conformally deposited on the insulating material (487, 587, 687, 787, 887, 987) in alternating second plurality of first vertical openings (471, 517, 617); Parts of the first conductor material (489, 589, 789, 889) and the insulating material (487, 587, 687, 787, 887, 987) in the alternating second plurality of first vertical openings (471, 517, 617) are removed to form a plurality of separate vertical metal-insulator-semiconductor (MIS) interfaces with the channel region. A second vertical opening (751, 851) is formed, which extends primarily along the first horizontal direction (509, 609, 709, 809) through the vertical stack (401) to expose the vertical sidewalls in the vertical stack (401). The second dielectric material is selectively etched to form a first horizontal opening (473); Vapor doping of the dopant is performed on the top surface of a lightly doped semiconductor material contained in the semiconductor materials (432, 532, 632, 732, 832, 932) to form first source / drain regions (321, 475, 775, 875, 975); and A second conductor material (477, 777, 877) is deposited on the first source / drain region (321, 475, 775, 875, 975) to form a digital line in the first horizontal opening (473).

14. The method of claim 13, further comprising: The insulating material is deposited on the surface above the first source / drain region in the first horizontal opening; and The first conductor material is deposited on the surface of the insulating material in the first horizontal opening to form a metal-insulator-semiconductor (MIS) layer between the digital line and the first source / drain region.

15. The method of claim 13, wherein depositing the first conductor material comprises depositing titanium nitride (TiN) on the surface of the insulating material.

16. The method of any one of claims 13 to 15, further comprising depositing the conductive material in the alternating second plurality of first vertical openings on the MIS interface to form a channel region contact, wherein the MIS facilitates the removal of holes from the channel region and provides a barrier for electrons.

17. A memory device having a horizontally oriented access device and a vertically oriented access line, comprising: A vertically stacked memory cell array, comprising: A horizontally oriented access device (230, 330, 901) has a first source / drain region (321, 475, 775, 875, 975) and a second source / drain region (323, 478, 778) separated by a horizontal channel region (225, 325), and a gate opposite to the horizontal channel region (225, 325) and separated from it by a gate dielectric (304, 538, 638, 738, 838); Vertical access lines (103-1, 103-2, ..., 103-Q, 203-1, 203-2, ..., 203-Q, 303-1) are coupled to the gate and separated from the horizontal channel regions (225, 325) by the gate dielectric (304, 538, 638, 738, 838); A horizontally oriented storage node (227) electrically coupled to the second source / drain region (323, 478, 778) of the horizontally oriented access device (230, 330, 901); Horizontally oriented digital lines (107-1, 107-2, ..., 107-P, 207-1, 207-2, ..., 207-P, 307-1, 977) are electrically coupled to the first source / drain regions (321, 475, 775, 875, 975) of the horizontally oriented access devices (230, 330, 901); A horizontally formed metal-insulator-semiconductor (MIS) interface is located between the first source / drain regions (321, 475, 775, 875, 975) and the digital lines; and Vertical body contacts (295, 995) are formed to make direct electrical contact with one or more body regions (326, 932-1) in the horizontally oriented access device, and are separated from the first source / drain regions (321, 475, 775, 875, 975) and the horizontally oriented digital lines by a dielectric.

18. The memory device of claim 17, further comprising dual gates formed on opposite sides of the horizontal channel region.

19. The memory device of claim 17, further comprising: A single gate, which is opposite to a first side of the horizontal channel region; and The contact point in the channel area is opposite to the second side of the horizontal channel area.

20. The memory device of claim 19, wherein the channel region contact includes a MIS interface formed between the horizontal channel regions and a conductive path shared between horizontally oriented access devices.

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