Package structure, semiconductor device and manufacturing method thereof

Abstract

The package structure includes a solder component, a first redistribution layer structure on the solder component, and a die mounted on and electrically coupled to the first redistribution layer structure. The first redistribution layer structure includes one or more dielectric layers filled with a thermally conductive dielectric material. Embodiments of the present application also relate to semiconductor devices and methods of manufacturing the same.

Description

Technical Field

[0001] Embodiments of this application relate to packaging structures, semiconductor devices, and methods of manufacturing the same. Background Technology

[0002] 3D integrated circuits (3DICs) comprise semiconductor devices having two or more layers of active electronic components that are vertically stacked and interconnected to form an integrated circuit. Heat dissipation is a challenge in 3DICs because 3D IC systems with increased chip density can exhibit high heat density and poor heat dissipation performance.

[0003] Heat generated within the internal die of a 3DIC device can be trapped in the internal region of the bottom stack of dies, leading to localized temperature spikes, sometimes referred to as hot spots. These hot spots, caused by heat generated by the devices, can negatively impact the electrical performance of other devices on top of the stack and often result in electromigration and reliability issues in the 3DIC package. These shortcomings and problems need to be addressed. Summary of the Invention

[0004] Some embodiments of this application provide a packaging structure including: a solder component; a first redistribution layer structure located on the solder component, the first redistribution layer structure including one or more dielectric layers filled with thermally conductive dielectric material; and a die mounted on the first redistribution layer structure and electrically coupled to the first redistribution layer structure.

[0005] Other embodiments of this application provide a semiconductor device including: one or more electrical connectors; a stack of one or more dies; and one or more redistribution layer structures electrically coupling the one or more dies to the one or more electrical connectors, at least one of the one or more redistribution layer structures including a thermally conductive horizontal layer adjacent to the one or more electrical connectors.

[0006] Further embodiments of this application provide a method of manufacturing a semiconductor device, comprising: attaching a first die in a package; applying a first molding material to surround the first die; forming one or more first conductive layers electrically connected to the first die under the first molding material; and forming one or more first dielectric layers comprising aluminum nitride, boron nitride, or a combination thereof, any one of the one or more first dielectric layers being disposed on a corresponding first conductive layer. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1 This is a cross-sectional view of a stacked package (PoP) device according to an exemplary embodiment of the present invention.

[0009] Figures 2 to 16 This is a cross-sectional view of an integrated fan-out (InFO) package at different stages of the back-end process (BEOL) manufacturing process according to an exemplary embodiment of the present invention.

[0010] Figure 17 This is a cross-sectional view of an integrated fan-out (InFO) package according to an exemplary embodiment of the present invention. Detailed Implementation

[0011] The following disclosure provides numerous exemplary embodiments or instances for implementing different features of the provided subject matter. Simplified examples of specific components and arrangements are described below to explain the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which each term is used. The use of examples in this specification, including instances of any term discussed herein, is merely illustrative and in no way intended to limit the scope and meaning of the invention or any exemplary terminology. Similarly, the invention is not limited to the various embodiments given in this specification.

[0013] While the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the scope of the embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0014] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0015] In this document, the term “coupled” may also be referred to as “electrically coupled”, and the term “connected” may be referred to as “electrically connected”. “Coupled” and “connected” may also be used to describe two or more elements cooperating or interacting with each other.

[0016] Various embodiments of the invention will be described with respect to specific contexts, namely three-dimensional (3D) integrated fan-out (InFO) stacked package (PoP) devices. However, the concepts in this invention can also be applied to other semiconductor structures or circuits.

[0017] Figure 1 This is a cross-sectional view of a multi-layer packaged (PoP) device 100 according to some embodiments of the present invention. Figure 1 As shown, the PoP device 100 includes a top package 110 electrically coupled to a bottom package 120 using one or more redistribution layers formed in the Integrated Fan-Out Stacked Package (InFOPoP) device, which will be described in more detail below. In some embodiments, the top package 110 and the bottom package 120 may include various other components, layers, circuitry, and structures, which are omitted here for brevity.

[0018] like Figure 1 As shown, the top package 110 is mounted on top of the bottom package 120. The top package 110 may include one or more device dies 112, 114. In some embodiments, the device dies 112, 114 are vertically discrete memory components. For example, the device dies 112, 114 may be memory components, such as, for example, dynamic random access memory (DRAM) or other suitable types of memory devices. Although Figure 1 The image depicts two device dies 112 and 114, but the invention is not limited thereto. In various embodiments, the top package 110 may include any number of device dies 112 and 114.

[0019] In some embodiments, device dies 112, 114 in the top package 110 are electrically coupled to the bottom package 120 via wiring connections, vias, and contact pads in the top package substrate 118. The top package 110 may include molding material 116 or another suitable sealant to cover the device dies 112, 114 and protect the wiring connection.

[0020] At the front side of the bottom package 120, the bottom package 120 includes a bottom package substrate. In some embodiments, the bottom package substrate is polybenzoxazole (PBO) or other suitable substrate material. Figure 1 As shown, one or more solder components 130 are mounted to the bottom package substrate to serve as electrical connections. In some embodiments, the solder components 130 are formed from solder balls from a ball grid array (BGA). As shown, the solder components 130 allow the bottom package 120 to be mounted and electrically coupled to, for example, the underlying printed circuit board (PCB) 140 or other components. In some embodiments, one or more integrated passive devices (IPDs) 190 may be mounted below the bottom package 120 and located between the bottom package 120 and the underlying printed circuit board 140.

[0021] like Figure 1 As shown, the bottom package 120 includes a front-side redistribution layer (RDL) structure 122 in the bottom package substrate. The front-side RDL structure 122 electrically couples the device dies 150 in the bottom package 120 to, for example, solder components 130 and printed circuit boards 140. In some embodiments, the device dies 150 and 160 in the bottom package 120 are logic devices or logic components, such as logic integrated circuits, analog circuits, etc. Device dies 150 and 160 may be sealed with molding material 126 or any other suitable sealant to cover device dies 150 and 160. Although the two device dies 150 and 160 are stacked vertically and via, as shown in the figure, they are connected to the bottom package substrate. Figure 1 The conductive components shown are connected to each other, but in some other embodiments, the bottom package 120 may include any number of device dies integrated and sealed by molding material 126.

[0022] In some embodiments, device dies 150 and 160 may be mounted under or to the passivation layer using a die-attachment film (DAF). In some embodiments, the passivation layer comprises polybenzoxazole (PBO), anolyn polymer film (ABF), or other suitable materials. A buffer layer comprising PBO, ABF, or other suitable materials may be disposed above the passivation layer. Optionally, a laminated tape may be disposed above the buffer layer. The laminated tape may comprise solder release (SR) film, ABF, back-side laminated tape (LC tape) comprising thermosetting polymers or other suitable materials. In some embodiments, an underfill material may be used to seal portions of the top package 110 and the bottom package 120. The underfill material may extend from the top surface of the printed circuit board 140, along the side of the bottom package 120, and along the side of the top package 110. In some embodiments, the underfill material may be disposed between the top package substrate 118 and the laminated tape or buffer layer.

[0023] Still referencing Figure 1 The bottom package 120 also includes a through-hole (TPV) 124 that penetrates the molding material 126 and extends between the front and back sides of the bottom package 120. The through-hole 124 (which may also be referred to herein as an InFO through-hole (TIV) or metal via) is embedded in and passes through the molding material 126. In some embodiments, the through-hole 124 comprises copper, nickel (Ni), a copper alloy (copper / titanium), solder, solder alloys including tin-silver (SnAg), tin-bismuth (SnBi), tin-copper (SnCu), tin-silver-copper (SnAgCu), tin-silver-copper-nickel (SnAgCuNi), or combinations thereof, or one or more of another suitable metal. Although Figure 1 The diagram shows four through-holes 124, but in some other embodiments, the bottom package 120 may include more or fewer through-holes 124.

[0024] In some embodiments, the bottom package 120 also includes a back-side RDL structure 128. In some embodiments, a portion of the back-side RDL structure 128 may extend over the top surface of the device die 160. Therefore, the device die 160 is electrically coupled to, for example, device dies 112 and 114 in the top package 110 and the package via 124. Furthermore, another portion of the back-side RDL structure 128 may extend over the package via 124. Specifically, redistribution layer bonding pads 1282 from the back-side RDL structure 128 are disposed on the upper portion of the package via 124 and cover or otherwise cover it. Figure 1The top of the via 124 is located in the package. Therefore, the back-side RDL structure 128 can be electrically coupled to the device die 160 and the front-side RDL structure 122 via the via 124. In some embodiments, the redistribution layer bonding pad 1282 and the via 124 are formed of the same material (e.g., copper). Therefore, the redistribution layer bonding pad 1282 and the via 124 can appear as a single, integral structure.

[0025] Solder component 170 is formed or mounted on redistribution layer bonding pad 1282 and package via 124 and is electrically coupled to redistribution layer bonding pad 1282 and package via 124. Solder component 170 electrically couples top package 110 to bottom package 120. In some embodiments, solder component 170 is formed of solder paste, organic solderability preservative (OSP) or other suitable conductive material or any combination thereof. In some embodiments, intermetallic compound (IMC) is disposed between solder component 170 and the underlying redistribution layer bonding pad 1282 covering package via 124. Intermetallic compound is the product of a reflow process for electrically coupling solder component 170 and package via 124.

[0026] In some other embodiments, the three-dimensional integrated chip can be implemented in different ways because Figure 1 Device 100 is merely an example and is not intended to limit the invention. For example, some semiconductor devices can implement a 3D system-on-a-chip (“3D SoIC”) structure, which is a non-monolithic vertical structure comprising two to eight two-dimensional (2D) flip chips with different functions stacked on top of each other, such as logic chips, memory chips, radio frequency (RF) chips, etc. As a non-limiting example, the logic chip may include a central processing unit (CPU), and the memory chip may include an array of static random access memory (SRAM), an array of dynamic random access memory (DRAM), an array of magnetic random access memory (MRAM), or other memory arrays. In a 3D SoIC structure, the 2D chips can be interconnected via microbumps, bonding pads, through-silicon vias (TSVs), or other interconnect structures.

[0027] Poor thermal performance in IC packages can lead to electromigration and reliability issues, resulting in suboptimal IC performance. Different types of IC chips may have different thermal tolerances. For example, memory chips such as SRAM arrays may have lower thermal tolerances compared to logic chips. In some advanced nodes, it may be necessary to reduce chip speed (e.g., by about 5% to 10%) to meet temperature requirements.

[0028] Due to die stacking, 3D IC structures can achieve higher power densities than individual dies in advanced nodes. These 3D IC structures feature increased chip density per unit area and higher power / thermal density, presenting greater challenges for heat dissipation. For example, electromigration increases the resistance of interconnects and TSVs, degrading chip performance and reducing the lifetime of the 3D IC structure. The materials included in 3D IC structures can also cause reliability issues, particularly those with different coefficients of thermal expansion (CTE). Materials with different CTEs can lead to thermomechanical stresses between integrated circuit (IC) chips.

[0029] like Figure 1 As shown, heat generated in the internal die may be trapped in the internal region 180 of the bottom stacked device dies 150, 160 and cause hot spots. In some embodiments, localized hot spots can occur on any chip layer and are not limited to chip layers with logic chips. To provide a heat dissipation path for transferring and dissipating the heat generated by the device dies 150, 160, in some embodiments of the invention, the front RDL structure 122 may include one or more dielectric layers filled with a thermally conductive dielectric material, such as a material having a thermal conductivity substantially equal to or greater than about 2 W / (m·K).

[0030] By forming a dielectric layer in the front RDL structure 122 using a thermally conductive but electrically insulating material, heat in the front RDL structure 122 can be effectively transferred and removed. As a non-limiting example, the thermally conductive dielectric material used for the dielectric layer may include one or more of aluminum nitride (AlN), boron nitride (BN) (such as hexagonal boron nitride (h-BN)), or any combination thereof. Under certain temperature conditions (e.g., at 300 K), aluminum nitride provides a high thermal conductivity of up to about 285-321 W / (m·K) and is an electrical insulator with a static dielectric constant of about 8.5. Hexagonal boron nitride provides a high thermal conductivity of up to about 400 W / (m·K) in the plane and about 6 W / (m·K) out of the plane, and is an electrical insulator with a static dielectric constant of about 6.9 in the plane and about 3.5 out of the plane.

[0031] In some embodiments of the invention, the front RDL structure 122 may include one or more conductive layers, and at least one of the conductive layers has a thickness substantially greater than 4 micrometers. In some embodiments, the thickness of a conductive layer may be in the range of about 4-10 micrometers. A thick conductive layer (such as a metal layer) in the front RDL structure 122 can also improve the thermal conductivity of the front RDL structure 122 and heat dissipation between different layers in the bottom package 120. Therefore, one or more thermally conductive horizontal layers adjacent to the electrical connections can be formed in the bottom package 120 to transfer heat away from localized hot spots.

[0032] For illustrative purposes, see reference Figures 2 to 16 Describes the manufacturing method of the bottom package 120. Figures 2 to 16 This is a cross-sectional view of an integrated fan-out (InFO) package 200 at different stages of the back-end process (BEOL) manufacturing process according to some embodiments of the present invention.

[0033] Although the manufacturing process is shown and described herein as a series of steps or events, it should be understood that the order in which such steps or events are shown should not be construed as limiting. For example, some steps may occur in a different order and / or simultaneously with other steps or events in addition to those shown and / or described herein. Furthermore, it may not be necessary to implement all the steps shown to achieve one or more aspects or embodiments described herein. Additionally, one or more steps described herein may be performed in one or more separate steps and / or stages.

[0034] exist Figure 2 The invention provides a carrier 201, an adhesive layer 202, and a polymer base layer 203. In some embodiments, the carrier 201 comprises glass, ceramic, or other suitable materials to provide structural support during the formation of various components in the device package. In some embodiments, the adhesive layer 202, comprising, for example, an adhesive layer, a photothermal conversion (LTHC) coating, an ultraviolet (UV) film, etc., is disposed above the carrier 201. The polymer base layer 203 is coated on the carrier 201 via the adhesive layer 202. In some embodiments, the polymer base layer 203 is formed of polybenzoxazole (PBO), ajinomoto polymer film (ABF), polyimide, benzocyclobutene (BCB), solder resist (SR) film, die attachment film (DAF), etc., but the invention is not limited thereto.

[0035] Now for reference Figure 3 Subsequently, a back-side redistribution layer (RDL) 204 is formed. In some embodiments, the back-side RDL 204 includes one or more redistribution lines, which are conductive components, including, for example, conductors and / or vias formed between one or more dielectric layers. In some embodiments, the dielectric layer is formed of aluminum nitride, boron nitride, or a combination thereof. In some embodiments, the dielectric layer is formed of other suitable materials, including PI, PBO, BCB, epoxy resin, silicone resin, acrylate, nanofilled phenolic resin, siloxane, fluorinated polymer, polynorbornene, etc., using any suitable method, including, for example, spin coating, sputtering, etc.

[0036] In some embodiments, conductive components / layers are formed between dielectric layers. The formation of such conductive components includes patterning the dielectric layers using a combination of processes such as photolithography and etching, and forming the conductive components within the patterned dielectric layers by, for example, depositing a seed layer and using a mask layer to define the shape of the conductive components. The conductive components are designed to form functional circuitry and input / output components for subsequent attachment to a device die.

[0037] Now for reference Figure 4 A patterned photoresist 205 is formed over the back-side RDL 204 and the polymer substrate layer 203. In some embodiments, for example, the photoresist 205 is deposited as a blanket layer over the back-side RDL 204. Next, portions of the photoresist 205 are exposed using a photomask (not shown). The exposed or unexposed portions of the photoresist 205 are then removed, depending on whether a negative or positive resist is used. The resulting patterned photoresist 205 includes openings 206 disposed at the peripheral region of the carrier 201. In some embodiments, the openings 206 further expose conductive components in the back-side RDL 204.

[0038] Now for reference Figure 5 A seed layer 207 is deposited on the patterned photoresist 205. Next, refer to... Figure 6 The opening 206 is filled with a conductive material 208, including materials such as copper, silver, and gold, to form a conductive via. In some embodiments, the opening 206 is plated with the conductive material 208 during a plating process, including, for example, electrochemical plating or electroless plating. In some embodiments, the conductive material 208 fills the opening 206.

[0039] Now for reference Figure 7 A grinding and chemical mechanical polishing (CMP) process is performed to remove the excess portion of the conductive material 208 located above the photoresist 205.

[0040] Now for reference Figure 8 The photoresist 205 is removed. In some embodiments, plasma ashing or wet stripping processes are used to remove the photoresist 205. In some embodiments, the plasma ashing process is followed by wet immersion in a sulfuric acid (H2SO4) solution to clean the package 200 and remove any remaining photoresist material.

[0041] Therefore, a conductive via 209 is formed above the backside RDL 204. Optionally, in some embodiments, the conductive via 209 is replaced with a conductive post or wire, including, for example, copper wire, gold wire, or silver wire. In some embodiments, the conductive vias 209 are spaced apart from each other by openings 210, and at least one opening 210 between adjacent conductive vias 209 is large enough to house one or more semiconductor device dies therein.

[0042] Now for reference Figure 9 Device die 211 is mounted and attached to package 200. In some embodiments, an adhesive layer is used to secure device die 211 to the back side RDL 204. Although Figure 9 The image shows one device die 211, but in some other embodiments, two or more device dies 211 (such as driver dies and receiver dies) may be mounted and attached to the package 200. In some embodiments, a stack of one or more device dies (e.g., Figure 1 The device dies 150 and 160 can be mounted and attached to the package 200.

[0043] Now for reference Figure 10 After the device die 211 is mounted to the polymer base layer 203 in the back-side RDL 204 and / or opening 210, a molding compound 212 is formed in the package 200. The molding compound 212 is dispensed to fill the gaps between the device die 211 and the conductive vias 209, the gaps between adjacent conductive vias 209, and / or the gaps between any two devices 211. In some embodiments, the molding compound 212 comprises any suitable material, including, for example, epoxy resin, molding underfill, etc. In some embodiments, compression molding, transfer molding, and liquid sealant molding are suitable methods for forming the molding compound 212, but the invention is not limited thereto. For example, the molding compound 212 may be dispensed in liquid form between the device die 211 and the conductive vias 209. Subsequently, a curing process may be performed to solidify the molding compound 212. In some embodiments, the molding compound 212 may overflow the device die 211 and the conductive via 209, such that the molding compound 212 covers the top surface of the device die 211 and the conductive via 209.

[0044] Now for reference Figure 11 A grinding and chemical mechanical polishing (CMP) process is performed to remove excess portions of the molding compound 212, and the molding compound 212 is ground back to reduce its overall thickness and thus expose the conductive via 209. Because the resulting structure includes the conductive via 209 extending through the molding compound 212, the conductive via 209 is also referred to as a molded via, intermediate via (TIV), etc. The conductive via 209 provides an electrical connection to the back-side RDL 204 in the package 200. In some embodiments, the conductive via 209 may be used with a 3D silicon interposer.

[0045] Now for reference Figure 12A patterned dielectric layer 213 with openings is formed on the molding compound 212. In some embodiments, the dielectric layer 213 comprises aluminum nitride, boron nitride, or a combination thereof. In some embodiments, the dielectric layer 213 comprises PI, PBO, BCB, epoxy resin, silicone resin, acrylate, nanofilled phenolic resin, siloxane, fluorinated polymer, polynorbornene, etc. In some embodiments, the dielectric layer 213 is selectively exposed to an etchant configured to etch the dielectric layer 213 to form openings, including, for example, CF4, CHF3, C4F8, HF, etc. As illustrated, the openings expose conductive pillars and conductive vias 209. In some embodiments, the openings include one or more vias and a metal wiring trench thereon. The vias extend vertically from the bottom surface of the dielectric layer 213 to the bottom surface of the metal trench, which extends to the top surface of the dielectric layer 213.

[0046] Now for reference Figure 13 In some embodiments, the openings are filled with a conductive material to form a conductive layer Mx having one or more conductive components (e.g., redistribution lines). For illustration, a seed layer (not shown) is formed in the openings and the conductive material is plated in the openings using, for example, an electrochemical plating process, a chemical plating process, etc. The resulting vias Vx in the dielectric layer 213 are electrically connected to conductive pillars or conductive vias 209, as illustrated. In some embodiments, a conductive material comprising, for example, copper or aluminum is deposited by a deposition process, a subsequent electroplating process, and a CMP process, as described above, and therefore, for brevity, a detailed description thereof is omitted here.

[0047] Now for reference Figure 14 In some embodiments, a dielectric layer 214 having conductive components is formed over dielectric layer 213. Specifically, a conductive layer My having one or more conductive components (e.g., redistribution lines) and vias Vy is formed between dielectric layers 214 and 215. In some embodiments, the redistribution lines include conductive components disposed between the respective dielectric layers. In some embodiments, dielectric layer 215 is patterned to form openings, and a metallic material is formed within the openings to form redistribution lines.

[0048] Now for reference Figure 15 In some embodiments, an additional dielectric layer 216 having conductive components is formed above dielectric layer 215. Specifically, a conductive layer Mz having one or more conductive components (e.g., redistribution lines) and vias Vz is formed between dielectric layers 215 and 216. In some embodiments, the width of the conductive components within one or more of conductive layers Mx, My, or Mz may be equal to or substantially greater than 0.8 micrometers. In some embodiments, the spacing between adjacent conductive components within one or more of conductive layers Mx, My, or Mz may be equal to or substantially greater than 0.8 micrometers. In some embodiments, the height of vias Vx, Vy, or Vz may be about 1.5 micrometers.

[0049] As illustrated, in some embodiments, device die 211 is electrically connected to the conductive components of the redistribution lines. In some embodiments, the redistribution lines formed between dielectric layers are substantially similar in composition and formation process to those of the back-side RDL 204, and therefore their detailed description is omitted here for brevity.

[0050] Now for reference Figure 16 Then, an under-bump metal (UBM) 217 ​​is formed to electrically connect to the conductive layer Mz on the dielectric layer 216. External connectors 218A, 218B, and 218C, configured as input / output (I / O) pads (including, for example, solder balls on the under-bump metal 217), are then formed. In some embodiments, connectors 218A, 218B, and 218C are ball grid array (BGA) balls, controlled-collapse chip connector bumps, etc., disposed on the under-bump metal 217, which is formed above the redistribution line. In some embodiments, connectors 218A, 218B, and 218C are used to electrically connect the package 200 to other package components, including, for example, another die, an interposer, a package substrate, a printed circuit board, a motherboard, etc.

[0051] In some embodiments, testing is performed at this stage to ensure that the package 200 has been properly formed. Thereafter, the package 200 is peeled off from the carrier portion and flipped over. For example, the carrier 201 and optionally the adhesive layer 202 can be removed from the package 200. Figure 17 This is a cross-sectional view of an integrated fan-out (InFO) package 200 according to some embodiments of the present invention. Figure 17 As shown, in some embodiments, the polymer substrate layer 203 remains in the resulting package 200 as an insulating and protective layer, but the invention is not limited thereto. In some embodiments, a tape layer is deposited after the adhesive layer 202 is removed. In some embodiments, a laser drilling process is performed to create grooves and expose the redistribution layer bonding pads from the back side RDL 204.

[0052] In various embodiments, other packaging technologies may be applied to manufacture the top package 110 and / or the bottom package 120. Possible packaging technologies include, for example, chip-on-substrate (CoWoS), die-face-down InFO, die-face-up InFO, backside-down InFO, etc. Figures 2 to 16 The manufacturing processes shown and described herein are simplified examples and are not intended to limit the invention.

[0053] like Figure 17As shown, the RDL structure in package 200 includes one or more dielectric layers filled with a thermally conductive dielectric material such as aluminum nitride, boron nitride, or combinations thereof, and one or more conductive layers. Specifically, the conductive layers in the RDL structure may include metal layers (e.g., layers Mx, My, and Mz). In some embodiments, the metal layers may include aluminum, copper, or combinations thereof, but the invention is not limited thereto. In some embodiments, at least one of the metal layers (e.g., layers Mx, My, and Mz) has a thickness substantially greater than 4 micrometers (e.g., in the range of about 4-10 micrometers).

[0054] The top metal layer (e.g., layer Mz) is adjacent to solder components (e.g., connectors 218A, 218B, and 218C), and the inner metal layer (e.g., layer Mx) is adjacent to the device die 211. The intermediate metal layer (e.g., layer My) is electrically coupled to the top and inner metal layers through corresponding vias.

[0055] In some embodiments, the thickness of the top metal layer is substantially greater than the thickness of the intermediate metal layer, and the thickness of the intermediate metal layer is substantially greater than the thickness of the inner metal layer. For example, in some embodiments, the thickness of the inner metal layer and the thickness of the redistribution lines in the inner metal layer may be about 2 micrometers, the thickness of the intermediate metal layer and the thickness of the redistribution lines in the intermediate metal layer may be about 3 micrometers, and the thickness of the top metal layer and the thickness of the redistribution lines in the top metal layer may be substantially greater than 4 micrometers (e.g., about 6 micrometers), but the invention is not limited thereto.

[0056] By providing a relatively thick and wide top metal layer for power distribution, the RDL structure can provide the desired electrical performance and heat dissipation. Furthermore, the thick top metal layer, arranged adjacent to connectors 218A, 218B, and 218C, can also reduce the voltage drop effect that often leads to increased delay.

[0057] Refer again Figure 1 After manufacturing the top package 110 and the bottom package 120, the top package 110 can be mounted onto the bottom package 120. In some embodiments, a die bonding process is performed to reflow solder component 170. The top package 110 and the bottom package 120 are electrically coupled together via the reflow solder component 170. Figure 1 As shown, underfill (or sealing material, sealant, etc.) may optionally be inserted or formed between the top package 110 and the bottom package 120. The PoP structure can then be mounted to the printed circuit board 140.

[0058] In some embodiments, one or more thick metal layers (e.g., substantially greater than or equal to 6 micrometers) having a dielectric layer filled with a thermally conductive dielectric material (such as AlN or h-BN) can also be used to form the backside RDL structure 128 of the bottom package 120 to further improve heat dissipation, but the invention is not limited thereto. For example, the structure of the backside RDL structure 128 may include one or more conductive layers located above the molding material and electrically connected to the device die, and one or more dielectric layers respectively disposed on the corresponding one or more conductive layers. Thus, the device dies 112 and 114 molded in the molding material 116 are electrically coupled to the redistribution layer bonding pads 1282 and the conductive layers in the backside RDL structure 128, as well as the via wiring bonding connections, RDL structure, vias, contact pads in the top package substrate 118, and solder components 170.

[0059] By employing a thermally conductive horizontal layer (which may be one or more thermally conductive dielectric layers, one or more thick metal layers, or both) adjacent to the electrical connections as a heat dissipation structure, 3DICs consistent with the embodiments described herein can improve the thermal characteristics of the IC package by effectively transferring heat generated by the stacked device dies and trapped in the internal regions of the package, and removing heat through the electrical connections. Therefore, 3DICs consistent with the embodiments described herein can maintain the operating temperature of the memory die or chip within a desired range (e.g., approximately 80°C–100°C). This optimized thermal performance not only improves chip speed and performance but also avoids potential electromigration and reliability issues associated with 3DIC packages.

[0060] In some embodiments, a package structure is disclosed, comprising: a solder component; a first redistribution layer structure located on the solder component, the first redistribution layer structure including one or more dielectric layers filled with thermally conductive dielectric material; and a die mounted on and electrically coupled to the first redistribution layer structure.

[0061] In some embodiments, the first redistribution layer structure includes one or more conductive layers, at least one of which has a thickness substantially greater than 4 micrometers. In some embodiments, the first redistribution layer structure includes one or more dielectric layers filled with aluminum nitride, boron nitride, or a combination thereof. In some embodiments, the first redistribution layer structure includes a top metal layer adjacent to the solder component and an intermediate metal layer electrically coupled to the top metal layer, the thickness of the top metal layer being substantially greater than the thickness of the intermediate metal layer. In some embodiments, the first redistribution layer structure further includes an inner metal layer electrically coupled to the intermediate metal layer and adjacent to the die, the thickness of the intermediate metal layer being substantially greater than the thickness of the inner metal layer. In some embodiments, the top metal layer includes aluminum, copper, or a combination thereof. In some embodiments, the thickness of the top metal layer is substantially greater than or equal to 6 micrometers. In some embodiments, the package structure further includes a second redistribution layer structure electrically coupled to the die and the first redistribution layer structure. In some embodiments, the second redistribution layer structure includes one or more dielectric layers filled with the thermally conductive dielectric material. In some embodiments, the thermally conductive dielectric material has a thickness substantially greater than or equal to 2 Wm. -1 K -1 Thermal conductivity. In some embodiments, a semiconductor device is also disclosed, comprising: one or more electrical connections; a stack of one or more dies; and one or more redistribution layer structures electrically coupling the one or more dies to the one or more electrical connections, at least one of the one or more redistribution layer structures including a thermally conductive horizontal layer adjacent to the one or more electrical connections.

[0062] In some embodiments, the thermally conductive horizontal layer includes a first redistribution line having a thickness substantially greater than 4 micrometers. In some embodiments, the thermally conductive horizontal layer further includes a dielectric layer filled with a thermally conductive dielectric material. In some embodiments, the thermally conductive dielectric material includes aluminum nitride, boron nitride, or a combination thereof. In some embodiments, the one or more redistribution layer structures include a back-side redistribution layer structure or a front-side redistribution layer structure.

[0063] In some embodiments, a method is also disclosed, comprising: attaching a first die in a package; applying a first molding material to surround the first die; forming one or more first conductive layers electrically connected to the first die under the first molding material; and forming one or more first dielectric layers comprising aluminum nitride, boron nitride, or a combination thereof, any one of the one or more first dielectric layers being disposed on a corresponding first conductive layer.

[0064] In some embodiments, the method further includes: forming one or more second conductive layers electrically connected to the first die over the first molding material; and forming one or more second dielectric layers, any one of the one or more second dielectric layers disposed on a corresponding second conductive layer. In some embodiments, forming the one or more first conductive layers includes: forming at least one of the one or more first conductive layers having a thickness substantially greater than 4 micrometers. In some embodiments, forming the one or more first dielectric layers includes: forming at least one of the one or more first dielectric layers filled with a thermally conductive dielectric material having a thickness substantially greater than or equal to 2 W / m². -1 K -1 The thermal conductivity. In some embodiments, the method further includes: forming one or more electrical connections electrically connected to the one or more first conductive layers.

[0065] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A packaging structure, comprising: Solder components, configured for mounting to a printed circuit board; A first package, comprising: a first redistribution layer structure located on the solder component, the first redistribution layer structure including a dielectric layer comprising hexagonal boron nitride; a first die mounted on and electrically coupled to the first redistribution layer structure; a second die stacked perpendicularly to the first die and connected to the first die via a conductive component; and a back-side redistribution layer structure extending above and adjacent to the top surface of the second die; and A second package, stacked on top of the first package, includes one or more third dies electrically coupled to the back-side redistribution layer structure. The one or more third dies in the second package are electrically coupled to the first package via wire bonding. The first redistribution layer structure includes a plurality of first metal layers, wherein the top metal layer of the plurality of first metal layers adjacent to the solder component is thicker than the other metal layers of the plurality of first metal layers, and the inner metal layer of the plurality of first metal layers adjacent to the first die is thinner than the other metal layers of the plurality of first metal layers, and an intermediate metal layer is disposed between the top metal layer and the inner metal layer; The back-side redistribution layer structure includes one or more second metal layers, which are thicker than the inner metal layer and electrically connected to the top surface of the second die. The second die adjacent to the back-side redistribution layer structure is not directly connected to the first redistribution layer structure.

2. The packaging structure according to claim 1, wherein, The plurality of first metal layers have a thickness greater than 4 micrometers.

3. The packaging structure according to claim 1, wherein, The plurality of third dies includes a plurality of third dies stacked perpendicularly to each other.

4. The packaging structure according to claim 1, wherein, The intermediate metal layer is electrically coupled to the top metal layer, and the thickness of the top metal layer is greater than the thickness of the intermediate metal layer.

5. The packaging structure according to claim 4, wherein, The inner metal layer is electrically coupled to the intermediate metal layer, and the thickness of the intermediate metal layer is greater than the thickness of the inner metal layer.

6. The packaging structure according to claim 4, wherein, The top metal layer includes aluminum, copper, or a combination thereof.

7. The packaging structure according to claim 3, wherein, The plurality of third dies are electrically coupled to the redistribution layer bonding pads of the back redistribution layer structure of the first package via wire bonding connectors.

8. The packaging structure according to claim 1, further comprising: The back-side redistribution layer structure is electrically coupled to the first die and the first redistribution layer structure.

9. The packaging structure according to claim 3, wherein, The plurality of third cores are embedded in the molding material.

10. The packaging structure according to claim 3, wherein, The plurality of third dies are vertically discrete memory components.

11. A semiconductor device, comprising: One or more electrical connections configured to be mounted to a printed circuit board; A stack of multiple dies is located within a first package, the multiple dies being vertically stacked and connected to each other via conductive components, the multiple dies including a first die and a second die; as well as One or more redistribution layer structures electrically couple the plurality of dies to the one or more electrical connectors, the one or more redistribution layer structures including a first redistribution layer structure and a back redistribution layer structure electrically coupling one or more of the plurality of dies, the first redistribution layer structure including a thermally conductive horizontal layer adjacent to the one or more electrical connectors, the thermally conductive horizontal layer including a dielectric layer comprising hexagonal boron nitride; as well as A second package, stacked on top of the first package, includes one or more third dies electrically coupled to the back-side redistribution layer structure and electrically coupled to the first package via wire bonding. The first redistribution layer structure includes a plurality of first metal layers, wherein the top metal layer of the plurality of first metal layers adjacent to the one or more electrical connectors is thicker than the other metal layers of the plurality of first metal layers, and the inner metal layer of the plurality of first metal layers adjacent to the first die is thinner than the other metal layers of the plurality of first metal layers, and an intermediate metal layer is disposed between the top metal layer and the inner metal layer; The back-side redistribution layer structure includes one or more second metal layers, which are thicker than the inner metal layer and electrically connected to the top surface of the second die. The first die is adjacent to the first redistribution layer structure and is larger than the second die adjacent to the back redistribution layer structure, and the second die is not directly connected to the first redistribution layer structure.

12. The semiconductor device according to claim 11, wherein, The thermally conductive horizontal layer includes redistribution lines.

13. The semiconductor device according to claim 11, wherein, The plurality of third dies includes a plurality of third dies stacked perpendicularly to each other.

14. The semiconductor device according to claim 13, wherein, The plurality of third cores are embedded in the molding material.

15. The semiconductor device according to claim 13, wherein, The plurality of third dies are vertically discrete memory components.

16. A method for manufacturing a semiconductor device, comprising: A first die and a second die are attached to a first package, the first die and the second die being stacked vertically and connected to each other via a conductive component; Apply a first molding material to surround the first die and the second die; A plurality of first conductive layers electrically connected to the first die are formed under the first molding material; A first dielectric layer comprising hexagonal boron nitride is formed, thereby forming a first redistribution layer structure comprising the plurality of first conductive layers and the first dielectric layer; A back-side redistribution layer structure comprising one or more second conductive layers is formed over the first molding material; as well as One or more third dies in the second package are electrically coupled to the second conductive layer and the first package via wire bonding. Wherein, the first redistribution layer structure is disposed on the solder component, the top conductive layer of the plurality of first conductive layers adjacent to the solder component is thicker than the other conductive layers of the plurality of first conductive layers, and the inner conductive layer of the plurality of first conductive layers adjacent to the first die is thinner than the other conductive layers of the plurality of first conductive layers, and an intermediate conductive layer is disposed between the top conductive layer and the inner conductive layer; Wherein, the one or more second conductive layers are thicker than the inner conductive layer and are electrically connected to the top surface of the second die, and The second die is adjacent to the back redistribution layer structure and is not directly connected to the first redistribution layer structure.

17. The method according to claim 16, wherein, The plurality of third dies includes a plurality of third dies stacked perpendicularly to each other.

18. The method according to claim 17, wherein, The plurality of third cores are embedded within the second molding material.

19. The method of claim 17, wherein, The plurality of third dies are vertically discrete memory components.

20. The method of claim 16, wherein, The first die and the second die are mounted under or to the passivation layer using a die attachment film.

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