ESD protection structure with adjustable trigger voltage and manufacturing method thereof

Abstract

The present invention provides an ESD protection device with adjustable trigger voltage and a method for manufacturing the same. The ESD protection structure comprises: a deep well of a first conductivity type and a functional device layer, the functional device layer being located within the deep well and comprising: a body region of a second conductivity type; a source and a drain of a first conductivity type; a gate structure disposed on the surface of the body region; an opening defined between the gate structure and the drain, with a lightly doped drain region disposed below the opening. When an influx of electrostatic positive current causes the voltage between the source and the body region below the channel region to reach a turn-on threshold voltage, the parasitic NPN bipolar transistor is turned on. The present invention also provides a method for manufacturing an ESD protection device with adjustable trigger voltage. The functional device layer manufactured by the method is located within the deep well and is compatible with actual CMOS triple-well processes.

Description

Technical Field

[0001] The present invention relates to the field of electrostatic protection, and in particular to a bidirectional ESD protection structure and a manufacturing method thereof. Background Art

[0002] As microelectronic devices scale down in size, particularly as metal-oxide-semiconductor field-effect transistors (MOSFETs) reach deep submicron and nanometer dimensions, devices are becoming more susceptible to failure due to electrostatic discharge (ESD), leading to a decline in circuit reliability. Furthermore, the continuous improvement in computing speed and functional integration within integrated circuits (ICs) has led to the integration of more and more modules on silicon substrates, exposing chips to greater ESD challenges and risks.

[0003] Generally, ESD protection devices are categorized as non-hysteretic and hysteretic. Hysteretic devices, such as grounded-gate NMOS, gate-controlled MOS, and silicon-controlled rectifiers, have an internal feedback loop. When the trigger voltage is reached, parasitic elements within the device are activated, increasing the device current. Subsequently, the voltage drop across the device decreases, forming a low-resistance path and dissipating the current. Compared to non-hysteretic devices, hysteretic devices offer greater protection and flexibility, as well as lower power consumption due to the lower voltage, but they require specific process design.

[0004] Currently, due to the thinner gate dielectrics and isolation of small-sized devices, the device's ability to withstand static electricity is weakened, and the window for ESD device design is narrowed. Therefore, providing an ESD protection structure for small-sized devices has become one of the urgent problems to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide an ESD protection structure with adjustable trigger voltage and a manufacturing method thereof, so as to solve the problems of high voltage ESD protection devices in the prior art, such as high voltage resistance, generally high trigger voltage, and difficulty in adjustment.

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention provides an ESD protection structure with adjustable trigger voltage, the ESD protection structure comprising: a substrate, a deep well having a first conductivity type, and a functional device layer, the deep well being arranged on the substrate, the functional device layer being located within the deep well, and the functional device layer comprising: a body region having a second conductivity type opposite to the first conductivity type; a source and a drain having the first conductivity type, spaced apart and formed within the body region, the drain being configured as an electrostatic introduction terminal; a gate structure, arranged on the surface of the body region, the gate structure comprising a gate electrode and a gate electrode arranged between the interface between the gate electrode and the body region a gate dielectric layer; an opening portion is arranged in the body region, the opening portion is limited between the gate structure and the drain, and a lightly doped drain region is further provided between the body region and the drain and located below the opening portion; wherein the first conductivity type is N-type, the body region below the source and the channel region and the drain constitute the emitter region, base region and collector region of the parasitic NPN bipolar transistor; when the influx of electrostatic positive current causes the turn-on threshold voltage between the source and the body region below the channel region to be reached, the parasitic NPN bipolar transistor is triggered to be turned on; by adjusting the length of the channel region, the width of the base region is changed, thereby realizing modulation of the trigger voltage.

[0007] Optionally, the lightly doped drain region is N-type and has a 5×10 18 cm -2 to 1×10 19 cm -2 doping concentration.

[0008] Optionally, the source is connected to a common ground terminal, and when a negative signal is introduced into the gate electrode, the band-to-band tunneling between the body region and the lightly doped drain region is increased by increasing the voltage of the gate electrode.

[0009] Optionally, the body region is connected to a common ground terminal through a body contact to form a leakage channel.

[0010] Optionally, the functional device layer further includes a functional lead-out structure, which passes through the N-type deep well and is electrically connected to the bottom of the body region, and a back bias voltage is introduced through the functional lead-out structure to adjust the potential of the body region.

[0011] In addition, the present invention also provides a method for manufacturing an ESD protection structure with adjustable trigger voltage, the method comprising: providing a P-type substrate, and forming an N-type deep well on the P-type substrate; forming the P-type body region in the N-type deep well; patterning the P-type body region to form an opening in the P-type body region; forming a patterned gate structure on the surface of the P-type body region and adjacent to the opening; forming a lightly doped drain region in a section of the P-type body region adjacent to the gate structure; forming a first N-type injection region and a second N-type injection region in the P-type body region; and forming a first N-type injection region and a second N-type injection region in the P-type body region. Two N-injection regions, the second N-injection region is adjacent to the lightly doped drain region and defines an opening portion together with the gate structure, the second N-injection region constitutes the drain of the ESD protection structure, the first N-injection region is formed on the side of the gate structure away from the opening portion to constitute the source of the ESD protection structure, and the drain is configured as an electrostatic introduction terminal; wherein the source, the P-type body region below the channel region and the drain constitute the emitter region, base region and collector region of the parasitic NPN bipolar transistor, and the trigger voltage is modulated by modulating the length of the channel region and changing the width of the base region.

[0012] Optionally, the manufacturing method further comprises: forming the lightly doped drain region by an ion implantation process, wherein the lightly doped drain region is N-type and has a 5×10 18 cm -2 to 1×10 19 cm -2 doping concentration.

[0013] Optionally, the P-type body region is connected to a common ground terminal through a body contact to form a leakage channel.

[0014] Optionally, the manufacturing method further comprises forming a functional lead-out structure through the N-type deep well, wherein the functional lead-out structure is electrically connected to the bottom of the P-type body region.

[0015] As described above, the ESD protection structure with adjustable trigger voltage and its manufacturing method of the present invention include an opening portion defined between the gate structure and the drain electrode. By increasing the spacing between the drain contact and the gate electrode, the thermal damage of the drain contact to the gate structure can be reduced, thereby improving the voltage resistance of the ESD protection structure; and the lightly doped drain (LDD) region provided below the opening portion can cause band-to-band tunneling at the interface between the P-type body region below the gate structure and the lightly doped drain region by adjusting the gate voltage, thereby raising the potential of the P-type body region and causing the parasitic bipolar transistor to turn on; by adjusting the length of the channel region, the trigger voltage can be adjusted, thereby achieving adjustable trigger voltage at the layout level. On the other hand, the ESD protection structure has a functional device layer based on MOSFET, which is located in a deep well and can be integrated with semiconductor devices manufactured using a conventional CMOS triple-well process to meet the reliability requirements of integrated circuits, especially under high-voltage conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic cross-sectional view of the ESD protection structure of the present invention is shown

[0017] Component number description

[0018] 110 first N-type implantation region

[0019] 120 Second N-type implantation region

[0020] 130 gate structure

[0021] 132 gate electrode

[0022] 134 gate dielectric layer

[0023] 140 opening

[0024] 150 P-type body region

[0025] 152 Channel Area

[0026] 154 Lightly doped drain region

[0027] 160 N-type deep well

[0028] 170 substrate

[0029] 210 functional device layer

[0030] 220 Parasitic NPN Bipolar Transistor DETAILED DESCRIPTION

[0031] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0033] For ease of description, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation other than the orientation depicted in the drawings. Furthermore, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or one or more intervening layers may be present. Furthermore, as used herein, "between" includes both endpoints.

[0034] In this application, the term "substrate" may be a conventional silicon substrate or other bulk substrate including a layer of semiconducting material.

[0035] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0036] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0037] In an ESD protection device based on a gate-grounded NMOS (GG-NMOS), the drain is connected to an I / O pin, and the gate, source, and bulk substrate are shorted to ground. In the absence of a positive electrostatic pulse, the NMOS device is in the off state. However, when a positive electrostatic pulse appears at the I / O pin, the drain-to-substrate junction is reverse biased, and the voltage reaches the avalanche breakdown voltage of the PN junction formed by the drain region and the bulk substrate, generating a large number of electron-hole pairs. The hole current is injected into the bulk substrate, flows through the substrate into the ground contact hole, and generates a voltage drop across the substrate resistor. This voltage drop is actually applied to the source-to-substrate junction, causing the PN junction formed by a part of the bulk substrate and the source region to reach the turn-on threshold voltage, thereby causing the parasitic NPN bipolar transistor to turn on. However, existing GGNMOS-based ESD protection devices are hysteresis-type ESD protection devices with a high trigger voltage.

[0038] Example 1

[0039] like Figure 1 As shown, the ESD protection structure with adjustable trigger voltage of the present invention includes a first N-type implant region 110 , a second N-type implant region 120 , a gate structure 130 , an opening 140 , a P-type body region 150 and a substrate 170 .

[0040] An N-type deep well (DNW) 160 is formed on the substrate 170 to isolate external noise and / or crosstalk. A functional device layer 210 is disposed within the N-type deep well. The functional device layer 210 includes a P-type body region 150, a first N-type implant region 110, and a second N-type implant region 120, wherein the first N-type implant region and the second N-type implant region are spaced apart in the P-type body region 150. The functional device layer 210 also includes a gate structure 130, which is disposed on the surface of the P-type body region and located between the first N-type implant region 110 and the second N-type implant region 120. The gate structure 130 may include a gate electrode 132 and a gate dielectric layer 134 disposed at the interface between the gate electrode and the P-type body region. The first N-type implant region 110 may be connected to a common ground terminal (Vss), and the second N-type implant region 120 may be configured as an electrostatic introduction terminal. The P-type body region 150 can be connected to Vss via a body contact, thereby forming a static discharge path, which helps to suppress thermal damage caused by charge accumulation in the P-type body region. In this embodiment, the depth of the P-type body region is greater than the depth of the active area defined by the first N-type implant region 110 and the second N-type implant region 120.

[0041] The functional device layer 210 further includes an opening 140, which is defined between the gate structure 130 and the second N-type implant region 120. A lightly doped drain (LDD) region 154 is further provided below the opening 140. The lightly doped drain region extends from the second N-type implant region to a position adjacent to the gate dielectric layer; that is, the lightly doped drain region 154 is located in the connecting region between the second N-type implant region 120 and the channel region 152. The lightly doped drain region 154 has the same doping type as the second N-type implant region 120. The first N-type implant region 110 and the second N-type implant region 120 are heavily N-type doped, for example, with a doping concentration of 1×10 20 cm -2 The doping concentration of the lightly doped drain region is relatively high, and the doping concentration of the P-type body region 150 is relatively low. For example, the lightly doped drain region 154 has a doping concentration of 5×10 18 cm -2 to 1×10 19 cm -2 doping concentration.

[0042] The ESD protection structure of the present invention can be integrated into a semiconductor device, wherein the isolation structure can be isolated from adjacent semiconductor devices by an isolation structure. For example, the isolation structure can be a shallow trench isolation (STI) arranged outside a single ESD protection structure, thereby achieving isolation between electrodes. The functional device layer 210 is formed in an N-type deep well, and the N-type deep well can be compatible with a conventional CMOS triple-well process. As an example, a back bias voltage can be introduced at the bottom of the substrate, and the potential of the body region is increased by expanding the depletion layer between the N-type deep well and the body region, thereby achieving modulation of the trigger voltage.

[0043] In another example, the functional device layer 210 further includes a functional lead-out structure (not shown), which passes through the N-type deep well and is electrically connected to the bottom of the P-type body region. A back bias voltage is introduced through the functional lead-out structure to adjust the potential of the P-type body region, thereby achieving modulation of the trigger voltage.

[0044] The length of the channel region is equivalent to the base width of the parasitic bipolar transistor. By adjusting the length of the channel region, the base width of the parasitic NPN bipolar transistor is changed, thereby achieving modulation of the trigger voltage. The length of the channel region is related to the thickness of the body region and satisfies the following range: L C >W DP +50(nm), where the width of the P region depletion layer is:

[0045]

[0046] where ∈ s is the dielectric constant, is the built-in potential difference, q is the charge, and N A 、N D For example, the P-type body region may have a doping concentration of 5x10 17 cm -2 The width at the opening is 25 nm, the channel length is 50 nm, the thickness of the P-type body region excluding the depletion layer width is 50 nm, and the ESD protection structure has a trigger voltage greater than or equal to 1.7 V.

[0047] The working principle of the ESD protection structure with adjustable trigger voltage of the present invention is as follows: the first N-type injection region 110 is connected to Vss. When a positive electrostatic pulse is introduced into the second N-type injection region 120, a lateral electrostatic field is formed between the P-type body region and the second N-type injection region, thereby generating a strong electric field region near the lightly doped drain region near the gate structure. At the same time, a negative signal is applied to the gate electrode, which can cause the energy band at the interface between the P-type body region and the lightly doped drain region below the gate structure to bend, inducing band-to-band tunneling. Specifically, carriers generated in the channel valence band tunnel to the conduction band of the lightly doped drain region, causing the local potential of the P-type body region below the channel region to rise, thereby causing the P-type body region below the channel region and the first N-type injection region to form a positive bias. As the voltage between the gate electrode and the source increases, the energy band bends more, and more carriers in the channel region complete tunneling. Once the junction voltage between the P-type body region below the channel region and the first N-type implant region reaches the turn-on threshold voltage, electrons passing through the P-type body region from the first N-type implant region are collected in the second N-type implant region, causing the parasitic NPN bipolar transistor 220 to turn on and form a low-resistance path, thereby maintaining a discharge path from the body region to the ground terminal. As previously described, the first N-type implant region 110, the P-type body region 150 below the channel region, and the second N-type implant region 120 sequentially constitute the emitter, base, and collector of the parasitic NPN bipolar transistor 220.

[0048] On the other hand, the functional device layer 210 includes an NMOS transistor with an opening portion. By modulating the voltage and / or back bias voltage of the gate electrode, band-to-band tunneling can be induced between the P-type body region and the lightly doped drain region near the gate structure, thereby realizing modulation of the trigger voltage of the ESD protection structure.

[0049] Example 2

[0050] The second embodiment of the present invention provides a method for manufacturing an ESD protection structure with adjustable trigger voltage, wherein the ESD protection structure with adjustable trigger voltage described in the first embodiment of the present invention is preferably prepared by the manufacturing method of this embodiment, and other methods may also be used. It should be noted that the above sequence does not strictly represent the process sequence of the method for manufacturing the ESD protection structure protected by the present invention, and those skilled in the art may make changes based on the actual process steps. Specifically, Figure 1 The manufacturing method of the ESD protection structure with adjustable trigger voltage includes at least the following steps:

[0051] A semiconductor substrate is provided. In an embodiment of the present invention, a P-type substrate is provided.

[0052] An N-type deep well 160 is formed on the semiconductor substrate. Depending on the application, the N-type deep well can be formed using conventional processes in the art, such as ion implantation or diffusion. Subsequently, a functional device layer 210 is formed within the N-type deep well 160. In this example, the functional device layer includes a P-type body region 150, a first N-type implant region 110, and a second N-type implant region 120.

[0053] Specifically, a P-type body region 150 is formed in the N-type deep well 160 by methods including but not limited to ion implantation or diffusion. Different types of doping ions and doping concentrations are selected based on actual needs to obtain the P-type body region 150. The specific steps are not repeated here.

[0054] A gate structure 130 is formed on the surface of the P-type body region 150 and patterned. The gate structure 130 may include a gate electrode 132 and a gate dielectric layer 134 disposed between the gate electrode and the P-type body region 150 .

[0055] An N-type lightly doped drain (NLDD) region 154 can be formed in a section of the P-type body region 150 adjacent to the gate structure 130 through a process such as ion implantation. Next, a first N-implant region 110 and a second N-implant region 120 are formed in the P-type body region 150. The second N-implant region is adjacent to the NLDD region 154 and defines an opening 140 along a sidewall of the gate structure 130. The first N-implant region is formed on a side of the gate structure away from the opening. The first N-implant region 110 and the second N-implant region 120 respectively constitute the source and drain of the ESD protection structure.

[0056] In the functional device layer, the first N-injection region, the P-type body region below the channel region, and the second N-injection region constitute the emitter, base, and collector of a parasitic NPN bipolar transistor. Isolation regions are formed outside the active region defined by the first N-injection region and the second N-injection region, respectively. The isolation regions may be STI structures or other structures used for electrical isolation in the art. In some examples, the fabrication method further includes the following steps: forming a functional lead-out structure (not shown) through the N-type deep well, the functional lead-out structure being electrically connected to the bottom of the P-type body region 150.

[0057] It should be noted that the structure of the bidirectional ESD protection device with adjustable trigger voltage in this embodiment may be the structure of the first embodiment, or other structures that can realize the device may be adopted, and is not limited to this embodiment.

[0058] In summary, the present invention provides an ESD protection structure with adjustable trigger voltage and a method for manufacturing the same. The ESD protection structure includes an opening defined between the gate structure and the drain, and a lightly doped drain (LDD) region provided below the opening. The opening is utilized to prevent thermal damage to the ESD protection structure. By adjusting the gate voltage, band-to-band tunneling can occur at the interface between the body region and the lightly doped drain region below the gate structure, especially at the interface between the channel region and the lightly doped drain region, thereby raising the potential of the body region and causing the parasitic bipolar transistor to turn on. By adjusting the length of the channel region, the trigger voltage of the ESD protection can be adjusted. On the other hand, the functional device layer provided by the present invention is formed in an N-type deep well, and the N-type deep well is compatible with a conventional CMOS triple-well process. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0059] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. An ESD protection structure with adjustable trigger voltage, characterized in that: The ESD protection structure includes: a substrate, an N-type deep well, and a functional device layer, wherein the deep well is provided on the substrate, the functional device layer is located in the deep well, and the functional device layer includes: a body region having a P type opposite to the N type; An N-type source and drain are formed in the body region at intervals, and the drain is configured as an electrostatic introduction terminal; a gate structure disposed on the surface of the body region, the gate structure comprising a gate electrode and a gate dielectric layer disposed between the gate electrode and the body region interface; an opening portion, the opening portion being defined between the gate structure and the drain electrode, a lightly doped drain region being further provided below the opening portion, the lightly doped drain region extending from the drain electrode to a position adjacent to the gate dielectric layer; the lightly doped drain region being N-type and having a higher doping concentration than the P-type body region; Among them, the source, the body region below the channel region and the drain constitute the emitter region, base region and collector region of the parasitic NPN bipolar transistor; when the influx of electrostatic positive current causes the turn-on threshold voltage between the source and the body region below the channel region to be reached, the parasitic NPN bipolar transistor is triggered to turn on; by adjusting the length of the channel region, the width of the base region is changed, thereby realizing modulation of the trigger voltage; the source is connected to the common ground terminal, and when a negative signal is introduced to the gate electrode, the band-to-band tunneling between the body region and the lightly doped drain region is increased by increasing the voltage of the gate electrode.

2. The ESD protection structure according to claim 1, wherein: The lightly doped drain region has a 5×10 18 cm -2 to 1×10 19 cm -2 doping concentration.

3. The ESD protection structure according to claim 1, wherein: The functional device layer further includes a functional lead-out structure, which passes through the N-type deep well and is electrically connected to the bottom of the body region. A back bias voltage is introduced through the functional lead-out structure to adjust the potential of the body region.

4. The ESD protection structure according to claim 1, wherein: The body region is connected to a common ground terminal through a body contact to form a leakage channel.

5. A method for manufacturing an ESD protection structure with adjustable trigger voltage, characterized in that: The production method comprises the following steps: Providing a P-type substrate, wherein an N-type deep well is formed on the P-type substrate; forming a P-type body region in the N-type deep well; forming a patterned gate structure on the surface of the P-type body region, wherein the gate structure includes a gate electrode and a gate dielectric layer disposed between the gate electrode and the P-type body region interface; forming a lightly doped drain region in a section of the P-type body region adjacent to the gate structure, wherein the lightly doped drain region is N-type and has a higher doping concentration than the P-type body region; A first N-type implant region and a second N-type implant region are formed in the P-type body region, the second N-type implant region being adjacent to the lightly doped drain region and defining an opening together with the gate structure, the second N-type implant region constituting a drain of the ESD protection structure, the first N-type implant region being formed on a side of the gate structure away from the opening to constitute a source of the ESD protection structure, the drain being configured as an electrostatic introduction terminal; Among them, the source, the P-type body region below the channel region and the drain constitute the emitter region, base region and collector region of the parasitic NPN bipolar transistor, and the trigger voltage is modulated by modulating the length of the channel region and changing the width of the base region; the source is connected to the common ground terminal, and when a negative signal is introduced to the gate electrode, the band-to-band tunneling between the body region and the lightly doped drain region is increased by increasing the voltage of the gate electrode.

6. The method for manufacturing an ESD protection structure with adjustable trigger voltage according to claim 5, wherein: The manufacturing method further comprises: forming the lightly doped drain region by an ion implantation process, wherein the lightly doped drain region has a 5×10 18 cm -2 to 1×10 19 cm -2 doping concentration.

7. The method for manufacturing an ESD protection structure with adjustable trigger voltage according to claim 5, wherein: The P-type body region is connected to a common ground terminal through a body contact to form a leakage channel.

8. The method for manufacturing an ESD protection structure with adjustable trigger voltage according to claim 5, wherein: The manufacturing method further includes forming a functional lead-out structure through the N-type deep well, wherein the functional lead-out structure is electrically connected to the bottom of the P-type body region.

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