String driver connection for wafer stack package

Abstract

The present disclosure describes a semiconductor device assembly including a first wafer having complementary metal oxide semiconductor (CMOS) devices including a plurality of string drivers, where each of the plurality of string drivers includes a field effect transistor (FET), a global word line connected to a source of the FET, and a local word line vertically passing through the FET; and a second wafer having a memory array including a plurality of word lines, each of the word lines connected to a corresponding one of the string drivers of the first wafer through a local word line of the corresponding one of the string drivers, wherein the backside surface of the first wafer is bonded to the front side surface of the second wafer to form a wafer stack WOW bond.

Description

Technical Field

[0001] The present disclosure relates generally to string drivers, and more particularly, to string driver direct source and drain connections in a wafer-on-wafer (WOW) package. Background Art

[0002] A microelectronic device generally includes a wafer, such as a complementary metal oxide semiconductor (CMOS) wafer, bonded to a memory array wafer to form a WOW package. The CMOS wafer and memory array wafer may be further mounted on a packaging substrate or carrier wafer and enclosed in a protective cover. The CMOS wafer may include an integrated circuit system with a high density of extremely small components, including processor circuits, imager devices, string drivers, and / or high voltage (HV) circuits. On the other hand, the memory array wafer may include a memory array, including a NAND flash memory array, a dynamic random access memory (DRAM) array, and / or a phase change memory (PCM) array, which is connected to the HV circuits of the CMOS wafer for data and control signal conversion. Conventional processes for bonding a CMOS wafer to a memory array wafer include electrically coupling the CMOS wafer HV circuits to the memory array via string driver circuits and forming a hybrid bond at the interface between the front side surface of the CMOS wafer and the front side surface of the memory array wafer to form a pad-on-array (POA, front-to-front) or pad-on-CMOS (POC, front-to-front) WOW package. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 A schematic diagram depicting WOW bonding of a semiconductor device assembly according to an embodiment of the present technology.

[0004] Figure 2 Schematic diagram depicting a string driver in a conventional WOW package.

[0005] Figure 3A Depicted is a schematic diagram of a string driver having a local word line disposed between adjacent string drivers.

[0006] Figure 3B Depicted is a schematic diagram of a string driver having a local word line passing therethrough in accordance with an embodiment of the present technology.

[0007] Figure 4A Schematic diagram depicting a CMOS wafer introduced into a WOW bonding scheme according to an embodiment of the present technology.

[0008] Figure 4B Schematic diagram depicting a CMOS wafer and a memory array wafer before a WOW bonding process according to an embodiment of the present technology.

[0009] Figure 4CDepicted is a schematic diagram of a WOW package including a CMOS die and a memory array die in accordance with an embodiment of the present technology.

[0010] Figure 5 Depicted are plan views of various string drivers in accordance with embodiments of the present technology.

[0011] Figure 6A Depicted is a cross-sectional view of a string driver including corresponding local word lines, in accordance with an embodiment of the present technology.

[0012] Figure 6B Depicted is a cross-sectional view of a string driver including corresponding global word lines, in accordance with an embodiment of the present technology.

[0013] Figure 7 Depicted is a plan view of a row of string drivers with various shallow trench isolation and partial deep trench isolation configurations in accordance with embodiments of the present technology.

[0014] Figure 8 is a flow chart illustrating a method of processing a WOW bond of a semiconductor device assembly according to an embodiment of the present technology.

[0015] Figure 9 is a schematic diagram of a system including a semiconductor device configured according to an embodiment of the presented technology.

[0016] The drawings illustrate only example embodiments and should not be considered limiting in scope. The elements and features shown in the drawings are not necessarily to scale, with emphasis placed on clearly illustrating the principles of the example embodiments. Furthermore, certain dimensions or placements may be exaggerated to help visually convey such principles. In the drawings, identical reference numerals used across different embodiments designate identical or corresponding, but not necessarily identical, elements. DETAILED DESCRIPTION

[0017] WOW packaging strategies typically separate the production of CMOS devices and memory arrays. For example, the CMOS devices can be processed on a CMOS wafer, and the memory array can be processed on a separate memory array wafer, without any thermal budget constraints between the two. This configuration allows the CMOS devices to be processed at relatively higher temperatures than the memory array wafer, resulting in better device performance. Furthermore, the CMOS wafer and memory array wafer can be bonded at a certain step in the manufacturing flow after each of their front-end-of-line (FEOL) processes is completed.

[0018] Figure 1A schematic diagram depicts a WOW bonding scheme 100 for a semiconductor device assembly according to an embodiment of the present technology. The WOW package includes a CMOS wafer 110, a memory array wafer 120, and a carrier wafer 130. As shown, the CMOS wafer 110 is bonded to the memory array wafer 120, which is further mounted on the carrier wafer 120. In this WOW bonding scheme 100, the backside surface of the CMOS wafer 110 is bonded to the frontside surface of the memory array wafer 120 using a direct bonding technique (e.g., dielectric-to-dielectric fusion bonding with strong covalent bonds). The CMOS wafer may include a substrate 111, a plurality of CMOS devices 112 disposed within or above the substrate 111, a plurality of metal wiring layers 113, and a plurality of bonding pads 115 disposed on the frontside surface of the CMOS wafer 110. On the other hand, the memory array wafer 120 may include a memory array 121, a plurality of bit lines 122 extending vertically through the memory array 121, and a plurality of bonding pads 123, each connected to a corresponding one of the plurality of bit lines 122. It is noteworthy that the CMOS wafer 110 and the memory array wafer 120 include a dielectric layer 116 and a dielectric layer 125 disposed on their backside and frontside surfaces, respectively. Here, the dielectric layers 116 and 125 provide electrical isolation among the components included in each of the CMOS wafer 110 and the memory array wafer 120. In addition, a direct bonding interface with fusion bonding between the CMOS wafer 110 and the memory array wafer 120 can be formed by attaching the dielectric layers 116 and 125 and applying heat or compressive pressure therebetween.

[0019] like Figure 1 As shown in FIG, the WOW bonding scheme 100 further includes electrical contacts 114, each of which connects one metal wiring layer 113 to a corresponding one of a plurality of metal layers 124 for high voltage and control signal conversion from the CMOS wafer 110 to the memory array wafer 120. The electrical contacts 114 can be configured to transmit high voltage or data signals to the bit lines 122 or word lines (not shown) of the memory array for the primary operations of reading and writing flash pages and erasing memory blocks. In this example, the final metal layer (e.g., metal layer 113 of the CMOS wafer having a relatively low processing temperature (e.g., close to 300°C)) can be processed after the WOW direct bonding step. In some embodiments, for cost reduction and packaging process control, the CMOS wafer is preferably no larger than the corresponding memory array wafer.

[0020] The WOW packaging strategy typically utilizes multiple string drivers disposed in a CMOS die to transfer voltages from the HV circuits to corresponding word lines of a memory array of a memory array die. Figure 2A schematic diagram depicts an exemplary string driver 200 positioned near the backside surface of a CMOS wafer 210. In this example, two string drivers 212 are included with a shared drain region. Each of the string drivers is a high-voltage transistor having gate electrodes 218a and 218b, respectively. In this example, the two string drivers 212 have a shared global word line (GWL) 216 connecting the shared drain region to the HV circuit. Additionally, each of the two string drivers 212 has a dedicated local word line (LWL) 214a and 214b, each connecting the source region of the string driver transistor to a corresponding word line of the memory array.

[0021] In conventional single-wafer processes, both GWL and LWL extend vertically from the string driver transistor to the metal layer of the CMOS wafer. The GWL further extends from the metal layer to the HV circuit system for voltage signal conversion. To further provide interconnection and voltage conversion paths between the string driver transistor and the memory array, the LWL is further extended from the CMOS wafer metal layer to the memory array, for example, to the metal pad connected to the word line of the memory array. Figure 2 , LWLs 214a and 214b extend through the dielectric region of the CMOS die and are disposed between adjacent string driver transistors. This CMOS die wiring packing density is limited by inherent string driver requirements such as isolation, voltage handling capability, and device performance.

[0022] Figure 3A A schematic diagram depicting a string driver with LWLs placed between adjacent string drivers in a conventional WOW packaging strategy. For example, Figure 3A The device includes two string driver transistors 312a and 312b that are horizontally aligned and positioned near the backside surface of a CMOS wafer 310. As shown, the backside surface of the CMOS wafer 310 is bonded to the frontside surface of a memory array wafer 320. Furthermore, each of the string drivers 312a and 312b is connected to a GWL and an LWL for memory array control and data signal conversion. In this example, an LWL 316 connects the drain region of the string driver 312a to the pad of the memory array wafer 320. Specifically, the LWL 316 first extends from the top surface of the drain region to the metal layer and then routes through the metal layer to the metal pad 322 for voltage signal conversion. Here, the LWL 316 is positioned between adjacent string driver transistors 312a and 312b by passing through the dielectric material between the adjacent string driver transistors 312a and 312b. The LWL configuration in conventional WOW packaging strategies limits the spacing distance of the string drivers and requires isolation control between the string driver and the adjacent LWL interconnects.

[0023] To address these and other challenges, the present technology includes a novel LWL connection in a WOW packaging solution. Specifically, in the present technology, the LWL is configured to pass through the string driver. Specifically, the LWL can vertically pass through the drain region of the string driver transistor to transfer the voltage from the string driver transistor to the corresponding metal pad of the memory array die. For example, Figure 3B A schematic diagram depicts a string driver with an LWL passing through the drain region according to an embodiment of the present technology. As shown, a CMOS wafer 310' is bonded to a memory array wafer 320'. CMOS wafer 310' includes two string driver transistors 312a' and 312b', each having an LWL 316a' and 316b' passing through its drain region. LWLs 316a' and 316b' transmit the voltage passing through string driver transistors 312a' and 312b' to metal pads 322a' and 322b', respectively. In the present technology, the distance between adjacent string drivers can be further scaled to achieve higher CMOS device density. Furthermore, a string driver device with this configuration can provide better isolation and avoid breakdown during high voltage operation.

[0024] Figure 4A A schematic diagram depicts a CMOS wafer 400 incorporating a WOW bonding scheme according to an embodiment of the present technology. The CMOS wafer 400 includes a plurality of string drivers, each having a gate electrode 408, a source region 404, a drain region 406, and a local deep trench (LDT) region 412. The plurality of string drivers can be disposed at various locations, such as on the front surface of the substrate 402 of the CMOS wafer 400. In addition, the plurality of string drivers can be encapsulated by a dielectric layer 414 for electrical isolation.

[0025] In some embodiments, each of the plurality of string drivers of the introduced CMOS chip 400 may be made of a metal oxide semiconductor field effect transistor (MOSFET). For example, Figure 4AAn n-channel MOSFET is shown, in which a gate electrode 408 including a gate oxide layer 410 is disposed on the front side surface of a substrate 402. A source region 404 and a drain region 406 are disposed at opposite ends of the gate 408. The gate electrode 408 may be composed of polysilicon, a silicide material, and / or a metal composite material such as WN, TiN, or TaN. The gate oxide layer 410 is disposed below the gate electrode 408 and is configured to separate the gate electrode 408 from the underlying source and drain regions 404 and 406. Generally, a thermal oxidation process may be used to form the gate oxide layer 410 having a high dielectric constant (e.g., SiO2, ZrO2, and / or HfO2). In an exemplary embodiment, the substrate 402 may be a p-type substrate (e.g., doped with boron and / or gallium). Additionally, the source region 404 may include an n-doped N+ region 404a and an n-doped N- region 404b. N+ region 404a has a higher n-type (e.g., doped with phosphorus, arsenic, and / or antimony) doping level than N- region 404b and is disposed below the top surface of substrate 402 and embedded in n- region 404b. Furthermore, drain region 406 may include n-doped N+ region 406a and n-doped N- region 406b, both vertically aligned in substrate 402. Specifically, N- region 406b has a lower n-type (e.g., doped with phosphorus, arsenic, and / or antimony) doping level than N+ region 406a and is disposed horizontally between gate electrode 408 and N+ region 406a. In some other embodiments, the string driver may be made of a p-channel MOSFET, for example, including an n-type (e.g., doped with phosphorus, arsenic, and / or antimony) doped substrate and p-type (e.g., doped with boron and / or gallium) doped regions in source 404 and drain 406. A p-channel MOSFET may have P+ and P- regions in its source and drain, similar to the N+ and N- region configuration in the source and drain regions of an n-channel MOSFET.

[0026] Figure 4A The string driver transistor shown in is a voltage controlled device configured to switch or amplify the voltage in the string driver. It has four terminals, including a gate electrode 408, a source region 404, a drain region 406, and a substrate (body) 402. The top surface of the substrate 402 (i.e., the area below the gate oxide layer 410 and between the source region 404 and the drain region 406) can be inverted from p-type to n-type by applying a positive gate voltage. Figure 4AIn the example N-channel MOSFET shown in FIG, when a positive gate voltage is applied, holes beneath the gate oxide layer 410 are pushed downward and a depletion region can be formed from the bound negative atoms associated with the acceptor atoms. A channel is then formed between the source region 404 and the drain region 406. In this case, current flows freely between the source region 404 and the drain region 406, and the gate voltage controls the electrons in the channel. In other embodiments where the string driver includes p-type doped regions in the source and drain, a negative voltage can be applied to the gate to form a hole channel beneath the gate oxide layer 410.

[0027] Each of the plurality of string drivers also includes a global word line (GWL) 414 that connects the string driver to the HV circuitry. The HV circuitry can be disposed in an incoming CMOS chip and connected to the string driver through various levels of metal layer interconnects. Specifically, as Figure 4A As shown in FIG, GWL 414 is connected to N+ region 404a to transmit the voltage signal from the HV circuitry to the source region of the string driver. In the present technology, GWL 414 can be formed by etching isolation material disposed above the MOSFET and filling it with a conductive material including a metal or metal alloy. Using the higher-doped N+ region 404a for the connection effectively reduces the contact resistance between GWL 414 and the source region 404 of the MOSFET. In addition, the lower-doped N- region 404b supports most of the applied source voltage by providing a voltage drop region with increased on-resistance.

[0028] In addition, each of the plurality of string drivers includes a Figure 4A 4. The LDT region 412 of the drain region 406 of the MOSFET shown in FIG. 4 is a local deep trench (LDT) region 412. The LDT region 412 may be filled with a non-conductive material including tetraethyl orthosilicate (TEOS), silicon oxide (SiO), silicon nitride (SiN), silicon boronitride (SiBCN), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon boronitride (SiBN), a low-k dielectric material, or a combination thereof. The LDT region 412 may have a thickness that is close to or less than the n-type doped drain region 406 (e.g., close to 1000 nm). ).like Figure 4A As shown in FIG. 4 , at least the distal surface of the N+ region 406a is surrounded by the LDT region 412. In some embodiments, the LDT region 412 may further extend along the longitudinal direction of the MOSFET to surround the other two sidewall surfaces of the drain region 406. In addition, the introduced CMOS wafer 400 further includes a shallow trench isolation (STI) region (not shown) disposed between adjacent string driver transistors. Specifically, the STI region may be disposed below the front side surface of the substrate 402 and between the parallel gates of the adjacent string driver transistors. The STI region may have a thickness close to or less than thickness to provide electrical isolation between adjacent string driver transistors.

[0029] In some other embodiments, each of the multiple string drivers of the introduced CMOS wafer 400 may be made of other types of transistors, such as FinFETs. For example, substrate 402 may be a p-type doped silicon fin of a FinFET extending horizontally in CMOS wafer 400. Gate electrode 408 may be disposed on the top surface and both sidewall surfaces of fin 402. Source region 404 and drain region 406 of the FinFET, having an n-type N+ region and N- region doping profile similar to that of a MOSFET, may be disposed at both ends of fin 402.

[0030] For the string driver transistor described above, a gate electrode 408 and a gate oxide layer 410 may be formed before implanting the N- regions 404 b and 406 b and the N+ regions 404 a and 406 a to serve as a mask during the implantation, i.e., the source region 404 and the drain region 406 are self-aligned with respect to the gate electrode 408. In addition, the N- regions 404 b and 406 b of the source and drain regions may be laterally diffused into the channel region below the gate electrode 408 during the implantation process or a subsequent thermal annealing process.

[0031] Figure 4B A schematic diagram depicting a CMOS wafer 400 and a memory array wafer 420 prior to a WOW bonding process according to an embodiment of the present technology is shown. Prior to WOW bonding and further metal formation in the CMOS wafer 400, the CMOS wafer 400 is thinned on the back side of the CMOS wafer 400 by a suitable technique, such as wafer back grinding, to remove most of the excess substrate / wafer thickness. The CMOS wafer thinning process can be stopped at the bottom of the LDT region 412 so that the multiple string drivers can be completely isolated by the LDT region 412. As previously described, the STI regions of the multiple string drivers have a thickness smaller than that of the LDT region 412, so that the multiple string drivers of the backside-thinned CMOS wafer 400 still share the silicon bridge below the STI region to prevent transistor floating body problems.

[0032] After the CMOS wafer backside thinning process, a dielectric layer 418 (e.g., an oxide layer) may be deposited on the backside surface of the CMOS wafer. The oxide layer may be silicon oxide processed at a temperature near or below 400° C. by a suitable thin film deposition technique including chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. In this example, the dielectric layer may have a thickness ranging from 50 nm to 200 nm.

[0033] Once the dielectric layer 418 is deposited, the backside surface of the CMOS wafer 400 can be bonded to the frontside surface of the memory array wafer 420 by a WOW bonding process. In some embodiments, the memory array wafer 420 includes one or more memory arrays having multiple word lines, each of which is connected to a metal pad 422. In addition, the memory array (not shown) and the corresponding metal pad 422 are encapsulated by a dielectric layer 424 (e.g., an oxide layer) for electrical isolation.

[0034] In some other embodiments, the CMOS wafer 400 has a silicon-on-insulator (SOI) substrate. The backside thinning process of the CMOS wafer 400 can reduce the thickness of the CMOS wafer 400 until the insulator (e.g., oxide layer) is exposed. The oxide layer of the SOI substrate can be bonded to the dielectric layer 424 of the memory array wafer to perform a WOW bond.

[0035] In the present technology, the CMOS wafer 400 and the memory array wafer 420 can be bonded by forming a dielectric-to-dielectric bond (eg, a strong covalent bond) without any gaps or voids between the dielectric layer 418 and the dielectric layer 424. Figure 4C As shown in , by applying heat and / or compressive force to the WOW bond, the dielectric layers 418 and 424 can be fused together. Figure 4B The WOW bonding shown above also includes aligning the metal pad 422 of each of the memory array word lines to the drain region 406 of the corresponding string driver transistor to accept a local word line (LWL) connection.

[0036] Figure 4C A schematic diagram of a WOW package including a CMOS die 400 and a memory array die 420 is depicted according to an embodiment of the present technology. Specifically, the WOW package includes an LWL 418 that vertically passes through the string drivers of the CMOS die 400 and connects to corresponding metal pads 422 of the memory array die 420.

[0037] In some embodiments, LWL 418 is configured to pass through the drain region 406 of the MOSFET, the dielectric-dielectric interface, and connect to the metal pad 422. In the present technology, LWL 418 can be formed by etching a hole through the encapsulating dielectric layer of the CMOS wafer 400, the drain region 406, and the dielectric layers 418 and 424 disposed between the drain region 406 and the metal pad 422. Figure 4C , for etch uniformity purposes, the hole can be completely located within the interior of the N+ region 406a of the MOSFET drain. In this example, the hole can be etched by an anisotropic etching technique (e.g., a reactive ion etching (RIE) process) that stops at the metal pad 422, for example, by an endpoint detection method.

[0038] In some other embodiments, LWL 418 may partially pass through N+ region 406a and partially pass through adjacent LDT region 412. In this example, the hole may be etched using a single anisotropic etching process or multiple selective etching processes for better etching uniformity control. For example, a silicon etching process selective to dielectric materials may be used to vertically etch a portion of N+ region 406a, and then a directional oxide etching process selective to silicon may be used to vertically etch a portion of LDT region 412.

[0039] Once a hole is etched through the CMOS wafer and to the metal pad 422, a standard silicon contact alloy can be formed on the sidewalls of the hole. A metallization process can be performed to fill the hole with a conductive material, including a metal or metal alloy, to form the LWL 418. In the present technique, the top portion of the LWL 418 will not be connected to any other device on the CMOS wafer 400. For example, the LWL 418 disposed above the MOSFET can be encapsulated with a dielectric material or processed through a dual damascene process to maintain electrical isolation. Additionally, the gate electrode 408 can be connected to the HV circuitry through dedicated switches and passive components.

[0040] In some embodiments, a post-metal process may be used to fabricate an intermediate metal layer in the CMOS wafer 400, and the GWL 414 is connected to the HV circuit system and general circuit wiring through the intermediate metal layer. Figure 4C As shown in FIG, LWL 418 is separated from gate electrode 408 by N-region 406b. Specifically, N-region 406b is disposed vertically in substrate 420 to isolate N+ region 406a, including LWL 418, from gate electrode 406a. Here, N-region 406b may have a width that is close to or greater than the minimum N+ region. Furthermore, N+ region 406a may be configured to prevent shorting from gate electrode 408 through degenerate N-region 406a to LWL 418. Furthermore, by penetrating N+ region 406a, LWL 418 can achieve low contact resistance.

[0041] Now go to Figure 5 , Figure 5 Depicts plan views of string drivers 500 having various configurations according to embodiments of the present technology. Specifically, Figure 5 A 3×3 device segment from a larger string driver array is illustrated. In this example, three columns of string drivers 500a, 500b, and 500c are aligned horizontally and separated by LDT regions 512. Within each of the string driver columns, three pairs of string drivers are aligned in parallel and separated vertically by STI regions 510. Additionally, each of the vertically aligned string drivers shares a gate electrode 504. Figure 5As shown in FIG, each of a pair of string drivers includes two transistors, such as MOSFETs, having a shared source region. In addition, each of the string drivers includes a GWL 506 connected to the source region of the corresponding transistor and an LWL 508 connected to the drain region of the corresponding transistor.

[0042] In some embodiments, the string driver 500 is configured so that the STI portion extends into the LWL region, such as Figure 5 500a on the left column of FIG. In this example, pairs of vertically aligned string driver transistors are separated by STI regions 510. In addition, STI regions 510 partially extend into the LWL 508 region, e.g., LDT regions 512 partially overlap LWL 508 along the longitudinal direction of shared gate electrode 504. Here, the drain region of each of the pairs of string driver transistors is partially surrounded by LTD regions 512.

[0043] In some other embodiments, the string driver is configured so that the STI portion extends into the gate electrode, such as Figure 5 500b on the middle column of FIG. 1 . In this example, pairs of vertically aligned string driver transistors are primarily isolated by LDT regions 512. Specifically, STI regions 510 partially extend into gate electrodes 504, meaning that the lateral outer edges of STI regions 510 overlap gate electrodes 504. In this example, LDT regions 512 surround not only the complete drain region but also a portion of the gate region of the string driver transistors.

[0044] In some other embodiments, the string driver is configured so that the STI terminates in the GWL region, such as Figure 5 500c on the right column of FIG. In this example, the STI region has a limited length (or leaves only a narrow strip) along the longitudinal direction of a pair of string drivers, i.e., close to or less than the diameter of GWL 506. As shown, the vertically aligned pairs of string driver transistors are primarily isolated by LDT regions 512. Here, LDT regions 512 completely surround the drain region, gate region, and a portion of the shared source region of the string driver transistors.

[0045] Figure 6A Describes an embodiment of the present technology along Figure 5 Specifically, Figure 6AAdjacent string driver transistors are illustrated with LWLs passing through corresponding drain regions and isolated by LDT regions 512. In this example, each of the adjacent string driver transistors has a gate electrode 504, a source region (not shown), a substrate 503, and a drain region 406. As depicted, the drain region of each of the string driver transistors includes a lower-level doped N- region 406b and a higher-level doped N+ region 406a, both vertically aligned in substrate 503, with N- region 406b positioned closer to gate electrode 504 to prevent a vertical voltage drop between the gate and N+ drain regions. In the present technique, LWLs 508 are configured to pass vertically through the drain regions of adjacent string driver transistors to transfer control voltages from the HV circuitry to corresponding word lines of the memory array. As shown, LDT regions 512 completely isolate the active regions of the adjacent string driver transistors, such as N+ drain regions 406b, from the LWLs 508 passing therethrough. In addition, the LWL contact is positioned along the sidewall of the LWL 508 through the entire depth of the N+ drain region 406a of the backside thinned CMOS wafer 400 and continues toward the dielectric-dielectric interface of the WOW bond. Compared to conventional string drivers with LWLs that pass through the isolation region between adjacent string driver transistors, the present technology better utilizes the drain region of the string driver transistors to achieve a higher string driver device density on the CMOS wafer for WOW packaging.

[0046] Figure 6B Describes an embodiment of the present technology along Figure 5 A cross-sectional view of the string driver in the BC plane. Specifically, Figure 6B String drivers are illustrated that are aligned in parallel and have GWLs 506 connected to the tops of corresponding N+ source regions 404a. As shown, the parallel-aligned string drivers are partially isolated by STI regions 510. In this example, STI regions 510 have a depth similar to that of N- source regions 404b and do not extend further into the substrate 503 of the string driver transistors. With this configuration, STI regions 510 can isolate adjacent active source regions (e.g., N- regions 404b) to prevent shorting between transistors. Additionally, substrate 503 (e.g., a p-type doped substrate in a MOSFET of CMOS wafer 400) extends between the parallel-aligned string driver transistors and below STI regions 510. Transistor floating body issues can be prevented by grounding or biasing the bridging substrate 503 to a certain voltage.

[0047] Now go to Figure 7 , Figure 7A plan view depicts a column of several pairs of string drivers with various STI and LDT configurations, according to embodiments of the present technology. In this example, multiple parallel-aligned string driver transistor pairs are vertically aligned and isolated by STI and LDTs ​​in different patterns. Specifically, this column of string drivers illustrates three types of isolation 700a, 700b, and 700c.

[0048] String driver isolation 700a has a medium active spacing with STI 710 isolation. As shown, and in some embodiments, isolation 700a includes an STI region 710 that terminates in a GWL region 706. An LDT region 712 completely surrounds a portion of the drain, gate, and source regions of the parallel-aligned string driver transistors. Here, the silicon bridge connection between the parallel-aligned string driver transistors is confined beneath the STI region 710 of isolation 700a. In this example, the isolation between the parallel-aligned string driver transistors is limited by the ability to suppress punch-through beneath the STI region 710 and maintain a high breakdown voltage.

[0049] In some other embodiments, isolation 700b includes a wide active spacing utilizing STI regions 710 and a silicon body connection disposed between the STI regions 710. As shown, isolation 700b has a larger space between the parallel-aligned string driver transistors compared to the medium active spacing 700a. Additionally, isolation 700b includes substrate 702 connected by GWL 706. The substrate 702 of isolation 700b is further isolated from the parallel-aligned upper and lower string driver transistors by STI regions 710 disposed above its top edge and below its bottom edge, respectively. In this example, the STI regions 710 disposed above the top edge and below the bottom edge of substrate 702 have a width approaching the diameter of GWL 706. This isolation 700b may be suitable for applications where the body connection must be isolated from the string driver device, particularly for GWL connections.

[0050] In some other embodiments, isolation 700c includes a narrow active spacing using LDTs ​​712. As shown, the parallel-aligned string drivers are completely isolated by LDTs ​​712 without any silicon body / substrate bridge connections therebetween. In this example, the spacing between the parallel-aligned string driver transistors is limited by dielectric breakdown between adjacent active regions (e.g., adjacent source regions between the parallel-aligned string driver transistors). Another factor that can limit the narrow active spacing in isolation 700c is the capacitive coupling effect that can occur between the parallel-aligned string driver transistors and across isolation region 700c.

[0051] It is noteworthy that the isolations 700a, 700b, and 700c described above can be arranged between parallel-aligned string driver transistors in various patterns. For example, an alternating pattern of "700b-700c-700b-700c" isolations arranged vertically in the string driver device region can be formed to form an H-shaped structure surrounded by the LDT region 712, where the average active spacing of 700b and 700c is acceptable for design rules. This configuration can provide an opportunity for body biasing to improve string driver performance, for example, applying a positive voltage to the bridge body / substrate to reduce the floating body effect in the string driver transistors. In another example, the string driver device region can include periodic body contacts, such as a "700a-700a-700b-700a-700a" pattern arranged between vertically aligned string driver transistors.

[0052] Figure 8 8 is a flow chart illustrating a method 800 for processing a WOW bond of a semiconductor device assembly according to an embodiment of the present technology. For example, the method 800 includes providing a first wafer having a complementary metal oxide semiconductor (CMOS) device at 802, the CMOS device including a plurality of string drivers, wherein each of the plurality of string drivers includes a field effect transistor (FET). For example, the CMOS wafer 400 is provided for WOW bonding, such as Figure 4A 4. CMOS chip 400 includes a plurality of string driver devices, each having a MOSFET transistor. Furthermore, the MOSFET of each of the plurality of string driver devices includes a gate electrode 410, a source region 404, a drain region 406, and a substrate / body 402. In some other examples, the transistors included in the string driver devices may be FinFETs.

[0053] The method 800 also includes forming a plurality of global word lines at 804, each of which is connected to a corresponding FET of one of the plurality of string drivers. For example, Figure 4A Each of the plurality of string driver devices shown in includes a GWL 414 connected to the source region of the MOSFET. Specifically, the GWL 414 can be connected to the highly doped N+ region 404a of the MOSFET to form a low resistance contact therebetween.

[0054] Additionally, method 800 includes thinning the first wafer from its backside surface at 806. For example, CMOS wafer 400 can be thinned from its backside surface by a suitable technique, such as wafer back grinding, to remove a majority of excess substrate / wafer thickness. The wafer backside thinning process can stop at LDT region 412 of CMOS wafer 400. In some other examples, and following the wafer backside thinning process, a dielectric layer, such as dielectric layer 418, can be deposited on the backside surface of CMOS wafer 400.

[0055] Additionally, method 800 includes providing a second wafer having a memory array including a plurality of word lines at 808. For example, memory array wafer 420 may be provided for WOW bonding. Figure 4B As described above, the memory array wafer 420 may include one or more memory arrays, each having a plurality of word lines, each of which is connected to a corresponding metal pad 422 for LWL connection. In addition, the one or more memory arrays are encapsulated by a dielectric layer 424 disposed on the front side surface of the memory array wafer 422.

[0056] Finally, method 800 includes bonding the backside surface of the first wafer to the frontside surface of the second wafer to form a WOW bond at 810. For example, a dielectric-to-dielectric bond (e.g., an oxide-to-oxide diffusion bond) may be formed between dielectric layers 418 and 424. Heat and / or compressive force may be applied to the WOW bond to form a strong covalent bond between CMOS wafer 400 and memory array wafer 420.

[0057] References Figures 1 to 7 Any of the described semiconductor structures may be incorporated into any of a myriad of larger and / or more complex systems, representative examples of which are Figure 9 9. System 900 is schematically shown in FIG. System 900 may include a semiconductor device 910, a power supply 920, a driver 930, a processor 940, and / or other subsystems or components 950. Semiconductor device 910 may include features substantially similar to those of the semiconductor devices described above, and thus may include string driver connections and string driver direct contacts as described in the present technology. The resulting system 900 may perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, representative system 900 may include, but is not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, and appliances. The components of system 900 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). Components of system 900 may also include remote devices and any of a variety of computer-readable media.

[0058] The following describes specific details of several embodiments of semiconductor devices and associated systems and methods. Those skilled in the relevant art will recognize that the appropriate stages of the methods described herein can be performed at the wafer level or at the die level. Therefore, depending on the context in which it is used, the term "substrate" can refer to a wafer-level substrate or to a singulated die-level substrate. In addition, unless the context indicates otherwise, conventional semiconductor manufacturing techniques can be used to form the structures disclosed herein. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0059] According to one aspect of the present disclosure, the semiconductor device described above may be a memory die, such as a dynamic random access memory (DRAM) die, a NAND memory die, a NOR memory die, a magnetic random access memory (MRAM) die, a phase change memory (PCM) die, a ferroelectric random access memory (FeRAM) die, a static random access memory (SRAM) die, or the like. In embodiments where multiple dies are provided in a single assembly, the semiconductor devices may be the same type of memory die (e.g., both NAND, both DRAM, etc.) or different types of memory die (e.g., one DRAM and one NAND, etc.). According to another aspect of the present disclosure, the semiconductor die of the assembly illustrated and described above may be a logic die (e.g., a controller die, a processor die, etc.), or a mix of logic and memory dies (e.g., a memory controller die and the memory dies it controls).

[0060] The devices discussed herein, including memory devices, can be formed on a semiconductor substrate or die (e.g., silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation during the initial formation or growth of the substrate or by any other doping means.

[0061] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the present disclosure and the appended claims. Features that implement the functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0062] As used herein, "or" as used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of..." or "one or more of...") in the claims, including the claims, indicates an inclusive list, so that, for example), a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0063] As used herein, the terms "top," "bottom," "up," "down," "above," and "below" may refer to the relative direction or position of features in a semiconductor device in view of the orientation shown in the figures. However, these terms should be broadly interpreted to include semiconductor devices having other orientations, such as inverted or tilted orientations, where top / bottom, over / under, above / under, up / down, and left / right may be interchanged depending on the orientation.

[0064] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, embodiments from two or more of the methods may be combined.

[0065] It will be appreciated from the foregoing that specific embodiments of the present invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the present invention. Specifically, in the foregoing description, numerous specific details are discussed to provide a thorough and instructive description of embodiments of the present technology. However, those skilled in the relevant art will recognize that the present disclosure may be practiced without the need for one or more of the specific details. In other examples, well-known structures or operations typically associated with memory systems and devices are not shown or described in detail to avoid obscuring other aspects of the present technology. In general, it will be understood that various other devices, systems, and methods other than those specific embodiments disclosed herein may also be within the scope of the present technology.

Claims

1. A semiconductor device assembly comprising: a first chip having a complementary metal oxide semiconductor (CMOS) device including a plurality of string drivers, wherein each of the plurality of string drivers includes a field effect transistor (FET), a global word line connected to a source of the FET, and a local word line vertically passing through the FET; and a second die having a memory array including a plurality of word lines, each of the word lines connected to a corresponding one of the string drivers of the first die through a local word line of the corresponding one of the string drivers; The backside surface of the first wafer is bonded to the frontside surface of the second wafer to form a wafer stack WOW bond. 2 . The semiconductor device assembly of claim 1 , wherein the FET of each of the plurality of string drivers of the first die is a metal oxide semiconductor FET (MOSFET) including a gate, a source, and a drain.

3. The semiconductor device assembly of claim 2 , wherein the global word line of each of the plurality of string drivers is connected to the source of the MOSFET, and wherein the local word line of each of the plurality of string drivers vertically passes through at least a portion of the drain of the MOSFET.

4. The semiconductor device assembly of claim 3 , wherein the drain of the MOSFET of each of the plurality of string drivers comprises a lightly doped drain region and a heavily doped drain region, both extending vertically through a substrate of the MOSFET, wherein the lightly doped drain region is disposed between the gate of the MOSFET and the heavily doped drain region of the MOSFET. 5 . The semiconductor device assembly of claim 4 , wherein the local word line of each of the plurality of string drivers passes vertically through the heavily doped drain region of a corresponding MOSFET. 6 . The semiconductor device assembly of claim 4 , wherein the first wafer includes a plurality of local deep trench (LDT) regions comprising a dielectric material, each of the plurality of LDT regions disposed adjacent to the heavily doped drain region of a corresponding one of the plurality of string drivers. 7 . The semiconductor device assembly of claim 6 , wherein the local word line of each of the plurality of string drivers vertically passes through the heavily doped drain region and adjacent LDT region of a corresponding one of the plurality of string drivers.

8. The semiconductor device assembly of claim 2 , wherein the source of the MOSFET of each of the plurality of string drivers comprises a lightly doped source region and a heavily doped source region, the heavily doped source region being embedded in the lightly doped source region, and wherein the global word line of each of the plurality of string drivers is connected to the heavily doped source region of the corresponding string driver.

9. The semiconductor device assembly of claim 1 , wherein the first wafer includes a dielectric layer disposed at the backside surface of the first wafer and beneath the plurality of string drivers, and wherein the dielectric layer of the first wafer is bonded to a dielectric layer disposed at the frontside surface of the second wafer to form the WOW bond.

10. The semiconductor device assembly of claim 1 , wherein the local word line of each of the plurality of string drivers vertically passes through the first wafer including the corresponding FET of the string driver and the dielectric layer of the first wafer, and wherein the local word line of each of the plurality of string drivers further extends through the WOW bonding interface into the second wafer and is connected to a metal pad connected to a corresponding word line of the memory array of the second wafer.

11. A semiconductor device comprising: a gate disposed on at least the top surface of the substrate; a source disposed at one end of the gate and in the substrate, the source having a lightly doped source region and a heavily doped source region, wherein the heavily doped source region is embedded in the lightly doped source region; a drain disposed at the other end of the gate and in the substrate, the drain having a lightly doped drain region and a heavily doped drain region, both of which extend vertically through the substrate of the semiconductor device; The lightly doped drain region is disposed between the gate and the heavily doped drain region.

12. The semiconductor device according to claim 11, further comprising: a global word line connected to the heavily doped source region of the semiconductor device; and A local word line vertically passes through the drain of the semiconductor device. 13 . The semiconductor device of claim 12 , wherein the local word line vertically passes through the heavily doped drain of the semiconductor device.

14. The semiconductor device of claim 12, further comprising a local deep trench (LDT) region comprising a dielectric material, the LDT region disposed adjacent to the heavily doped drain region of the semiconductor device, wherein the local word line vertically passes through the heavily doped drain region and the adjacent LDT region of the semiconductor device. 15 . The semiconductor device of claim 14 , further comprising a shallow trench isolation (STI) region comprising a dielectric material, the STI region being adjacent to and parallel to the gate of the semiconductor device, wherein the STI region has a depth smaller than that of the LDT region.

16. A method of forming a semiconductor device assembly, comprising: providing a first chip having a complementary metal oxide semiconductor (CMOS) device, the CMOS device including a plurality of string drivers, wherein each of the plurality of string drivers includes a field effect transistor (FET); forming a plurality of global word lines each connected to a corresponding FET of one of the plurality of string drivers; thinning the first wafer from a backside surface of the first wafer; providing a second die having a memory array including a plurality of word lines; and The backside surface of the first wafer is bonded to the frontside surface of the second wafer to form a wafer stack WOW bond.

17. The method of forming a semiconductor device assembly according to claim 16, wherein providing the first wafer comprises: forming a gate on at least a top surface of a substrate of each of the plurality of string drivers; forming a source electrode at one end of the gate and in the substrate, the source electrode having a lightly doped source region and a heavily doped source region, wherein the heavily doped source region is embedded in the lightly doped source region; and forming a drain disposed at the other end of the gate and in the substrate, the drain having a lightly doped drain region and a heavily doped drain region, both extending vertically through the substrate of the semiconductor device, The lightly doped drain region is disposed between the gate and the heavily doped drain region.

18. The method of forming a semiconductor device assembly according to claim 17, wherein providing the first wafer further comprises: forming a local deep trench (LDT) region comprising a dielectric material in the substrate of each of the plurality of string drivers, the LDT region disposed adjacent to the heavily doped drain region of the semiconductor device; and A shallow trench isolation (STI) region including a dielectric material is formed in the substrate of each of the plurality of string drivers, the STI region being adjacent to and parallel to the gate of the semiconductor device, wherein the STI region has a depth smaller than that of the LDT region.

19. The method of forming a semiconductor device assembly according to claim 18, further comprising forming a plurality of local word lines respectively passing through the plurality of string drivers, wherein the plurality of local word lines further pass through the WOW bonding interface and extend into the second wafer, and wherein each of the plurality of local word lines is connected to a corresponding one of a plurality of metal pads in the second wafer, the plurality of metal pads being respectively connected to the plurality of word lines of the memory array in the second wafer.

20. The method of forming a semiconductor device assembly of claim 19, wherein each of the plurality of local word lines passes at least partially through the heavily doped drain region of a corresponding one of the plurality of string drivers.

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