Semiconductor device

Abstract

A semiconductor device is disclosed. The semiconductor device includes a fin-type active region extending along a first direction on a substrate; a gate structure extending across the fin-type active region along a second direction different from the first direction; a source / drain region in the fin-type active region on a side of the gate structure; and a first contact structure and a second contact structure connected to the source / drain region and the gate structure, respectively, wherein at least one of the first contact structure and the second contact structure includes a seed layer on at least one of the gate structure and the source / drain region and comprising a first crystalline metal and a contact plug on the seed layer and comprising a second crystalline metal different from the first crystalline metal, and the second crystalline metal is substantially lattice-matched to the first crystalline metal at an interface between the seed layer and the contact plug.

Description

[0001] Korean Patent Application No. 10-2020-0111054, filed on September 1, 2020 with the Korean Intellectual Property Office and entitled “Semiconductor Device”, is incorporated herein by reference in its entirety. Technical Field

[0002] The embodiments relate to a semiconductor device. Background Technology

[0003] Semiconductor devices can include integrated circuits containing various transistors. With the increasing density of semiconductor components, the scaling down of transistors has accelerated, and therefore, the critical size (CD) of contacts has also decreased. Summary of the Invention

[0004] The embodiment relates to a semiconductor device comprising: a finned active region extending on a substrate along a first direction parallel to an upper surface of the substrate; a gate structure extending across the finned active region along a second direction parallel to the upper surface of the substrate and different from the first direction; a source / drain region located in the finned active region on one side of the gate structure; an insulating portion covering the gate structure and the source / drain region; a first contact structure penetrating the insulating portion and connected to the source / drain region; and a second contact structure penetrating the insulating portion and connected to the gate structure. At least one of the first contact structure and the second contact structure may include a seed layer comprising a first crystalline metal located on at least one of the gate structure and the source / drain region, and a contact plug comprising a second crystalline metal different from the first crystalline metal located on the seed layer. The second crystalline metal may substantially lattice match the first crystalline metal at the interface between the seed layer and the contact plug.

[0005] The embodiments also relate to a semiconductor device comprising: a substrate having a contact region; a first insulating layer located on the substrate and having a first contact hole connected to the contact region; a first seed layer located on the contact region in the first contact hole and comprising a first crystalline metal; and a first contact metal located on the first seed layer, filling the first contact hole, and comprising a second crystalline metal. The second crystalline metal may substantially match the lattice of the first crystalline metal at the interface between the first crystalline metal and the second crystalline metal.

[0006] The embodiments also relate to a semiconductor device comprising: a finned active region extending on a substrate along a first direction parallel to an upper surface of the substrate; a gate structure extending across the finned active region along a second direction parallel to the upper surface of the substrate and different from the first direction; a source / drain region located in the finned active region on one side of the gate structure; a first contact structure connected to the source / drain region; and a second contact structure connected to the gate structure. At least one of the first contact structure and the second contact structure may include a seed layer located on at least one of the gate structure and the source / drain region, and a contact plug located on the seed layer. The seed layer may include a first crystalline conductive material, and the contact plug may include a second crystalline conductive material. The first crystalline conductive material and the second crystalline conductive material may have the same crystal structure, and the difference between the lattice constant of the first crystalline conductive material and the lattice constant of the second crystalline conductive material may be less than 1%. Attached Figure Description

[0007] Features will become apparent to those skilled in the art from a detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1 This is a plan view illustrating a semiconductor device according to an example embodiment;

[0009] Figures 2A to 2C yes Figure 1 The semiconductor device shown in the figure is a cross-sectional view taken along lines I1-I1', I2-I2' and II-II', respectively.

[0010] Figure 3 It is shown Figure 2A An enlarged view of part "A1" of the semiconductor device shown in the image;

[0011] Figure 4 It is shown Figure 3 A schematic diagram of the crystal structure at the interface between the seed layer and the contact plug in the contact structure is shown in the figure.

[0012] Figure 5 It is shown Figure 2B An enlarged view of part "A2" of the semiconductor device shown in the image;

[0013] Figures 6A to 6D This is a cross-sectional view illustrating the main processes of a method for manufacturing a semiconductor package according to an example embodiment;

[0014] Figure 7 and Figure 8 This is a cross-sectional view (formed at the side surface) of the contact structure that a semiconductor device may employ according to various example embodiments (formation of fine structure);

[0015] Figure 9This is a cross-sectional view showing the contact structure that a semiconductor device according to an example embodiment may employ;

[0016] Figure 10 This is a cross-sectional view of a semiconductor device according to an example embodiment;

[0017] Figure 11 It is a cross-sectional view of a semiconductor device according to an example embodiment; and

[0018] Figure 12 This is a cross-sectional view showing a semiconductor device according to an example embodiment. Detailed Implementation

[0019] Figure 1 This is a plan view showing the main components of a semiconductor device according to an example embodiment. Figures 2A to 2C yes Figure 1 The semiconductor device shown in the figure is a cross-sectional view taken along lines I1-I1', I2-I2' and II-II', respectively.

[0020] Reference Figure 1 and Figures 2A to 2C The semiconductor device 100 according to this example embodiment may include a first direction on the substrate 101 parallel to the upper surface of the substrate 101. Figure 1 The fin-shaped active region 105 extends in the X direction and in a second direction different from the first direction (X direction). Figure 1 A gate structure GS extending across the fin-type active region 105 in the Y direction.

[0021] Substrate 101 may include a group IV semiconductor (such as Si or Ge), a group IV-IV compound semiconductor (such as SiGe or SiC), or a group III-V compound semiconductor (such as GaAs, InAs, or InP). Substrate 101 may include an active region AR. The active region AR may be a conductive region (such as a doped well or a doped structure). In an example embodiment, the active region AR may be an N-type well for a P-type metal-oxide-semiconductor (PMOS) transistor or a P-type well for an N-type metal-oxide-semiconductor (NMOS) transistor.

[0022] The fin-shaped active region 105 can be located on the upper surface of the active region AR. The fin-shaped active region 105 can have a third-direction ( Figure 1 The structure protruding from the upper surface of the active region AR in the Z direction (which is perpendicular to the first and second directions). The fin-shaped active region 105 may be referred to herein as the active fin 105.

[0023] In this example embodiment, the number of active fins 105 is three, but it is not limited to this. A single active fin 105 can be formed, or multiple active fins 105 of different numbers can be formed. Figure 1 As shown, three active fins 105 can be arranged parallel to each other on the active region AR in the second direction, and can all extend along the first direction (X direction). The active fins 105 can be configured as the active regions of a transistor.

[0024] Device isolation film 107 may define an active region AR and an active fin 105. In an example embodiment, device isolation film 107 may be formed of an insulating material (such as silicon oxide). Device isolation film 107 may include a first isolation region 107a defining the active region AR and a second isolation region 107b defining the active fin 105. The first isolation region 107a may have a bottom surface deeper than the bottom surface of the second isolation region 107b. The first isolation region 107a may be a deep trench isolation (DTI). The second isolation region 107b may be a shallow trench isolation (STI). The second isolation region 107b may be located on the active region AR. The active fin 105 may penetrate the second isolation region 107b and partially protrude from the upper surface of the second isolation region 107b.

[0025] like Figure 1 As shown, the gate structure GS can have a line structure extending along a second direction (Y direction) intersecting the first direction (X direction). The gate structure GS can be stacked with the region of the active fin 105.

[0026] The gate structure GS may include a gate spacer 141, a gate insulating layer 142 sequentially disposed between the gate spacers 141, a gate electrode 145, and a gate capping layer 147 located on the gate electrode 145.

[0027] The gate electrode 145 may be formed of doped polysilicon, metal, conductive metal nitride, conductive metal carbide, or a combination thereof. For example, the gate electrode 145 may be formed of Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, or a combination thereof, but the material of the gate electrode 145 is not limited thereto. In an example embodiment, the gate electrode 145 may include a layer containing a work function metal and an interstitial metal film. The layer containing the work function metal may contain at least one metal selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The interstitial metal film may be a W film or an Al film. In an example embodiment, the gate electrode 145 may include a stacked structure of TiAlC / TiN / W, a stacked structure of TiN / TaN / TiAlC / TiN / W, or a stacked structure of TiN / TaN / TiN / TiAlC / TiN / W, but is not limited thereto.

[0028] The gate insulating layer 142 can be located on the bottom surface and sidewall of the gate electrode 145, and can extend along the bottom surface of the gate electrode 145 in a second direction. Figure 1 Extending in the Y direction. The gate insulating layer 142 may be disposed between the gate electrode 145 and the active fin 105 and between the gate electrode 145 and the upper surface of the device isolation film 107. Examples of the gate insulating layer 142 may include a silicon oxide film, a silicon oxynitride film, a high-dielectric film with a dielectric constant higher than that of the silicon oxide film, or a combination thereof. The high-dielectric film may be formed of a metal oxide or a metal oxynitride. For example, the high-dielectric film that can be used as the gate insulating layer 142 may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0029] The gate cap layer 147 may be located on the gate electrode 145. The gate cap layer 147 may cover the upper surface of the gate electrode 145 and extend along the second direction ( Figure 1 The gate cap 147 may extend in the Y direction. For example, the gate cap layer 147 may comprise silicon nitride or silicon oxynitride. A gate spacer 141 may be located on opposite sidewalls of the gate electrode 145 and opposite sidewalls of the gate cap layer 147. The gate spacer 141 may extend on opposite sidewalls of the gate electrode 145 along the direction in which the gate electrode 145 extends, and a gate insulating layer 142 may be disposed between the gate electrode 145 and the gate spacer 141. In an example embodiment, the gate spacer 141 may comprise silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon carbonitride (SiC)x N y ), silicon carbide (SiO2) x C y N z (or a combination thereof). In an example embodiment, the gate spacer 141 may include multiple layers, each formed of a different material. Although Figure 2A and Figure 2B The diagram shows a single-layer gate spacer 141, but the gate spacer 141 may comprise multiple spacer layers that are sequentially stacked on the sidewalls of the gate electrode 145 and each has a different dielectric constant.

[0030] The semiconductor device 100 according to this example embodiment may include a source / drain region 110 of an active fin 105 located in a portion of a region on the opposite side of the gate structure GS.

[0031] The source / drain region 110 can be formed by creating a recess in a portion of the active fin 105 and performing selective epitaxial growth (SEG) on the recess. The source / drain region 110 can be formed of, for example, Si, SiGe, or Ge. The source / drain region 110 can have different materials or different shapes depending on whether it is an N-type transistor or a P-type transistor. For example, in the case of a PMOS transistor, the source / drain region 110 can be formed of silicon germanium (SiGe) and can be doped with P-type impurities (e.g., boron (B), indium (In), or gallium (Ga)). A cross-section of the source / drain region 110 (YZ cross-section, see...) Figure 2C The source / drain region 110 can have a pentagonal shape. In the case of an NMOS transistor, the source / drain region 110 can be formed of silicon and can be doped with N-type impurities (e.g., phosphorus (P), nitrogen (N), arsenic (As), or antimony (Sb)). The cross-section (YZ cross-section) of the source / drain region 110 can have a hexagonal shape or a polygonal shape with gentle angles. In this way, the source / drain region 110, the active fin 105, and the gate structure GS can form a three-dimensional semiconductor device, such as a fin field-effect transistor (FinFET).

[0032] The semiconductor device 100 according to this example embodiment may include a first contact structure CS1 that penetrates the insulating portion 160 and is connected to the source / drain region 110, and a second contact structure CS2 that penetrates the insulating portion 160 and is connected to the gate electrode 145 of the gate structure GS.

[0033] The insulating portion 160 may include an inter-gate insulating film 161 and a cap insulating film 162 sequentially stacked on the source / drain region 110. The inter-gate insulating film 161 may be disposed between adjacent gate structures GS and cover the source / drain region 110 and the device isolation film 107. The inter-gate insulating film 161 may have an upper surface substantially coplanar with the upper surface of the gate spacer 141 and the upper surface of the gate cap layer 147. In an example embodiment, at least one of the inter-gate insulating film 161 and the cap insulating film 162 may be formed of silicon nitride, silicon oxide, or silicon oxynitride. In an example embodiment, the inter-gate insulating film 161 may be formed of TEOS, USG, PSG, BSG, BPSG, FSG, SOG, TOSZ, or combinations thereof. The inter-gate insulating film 161 may be formed by, for example, chemical vapor deposition (CVD) or spin coating.

[0034] In this example embodiment, each of the first contact structure CS1 and the second contact structure CS2 may include a seed layer 182 and a contact plug 185 located on the seed layer 182. The seed layer 182 may be located on each of the source / drain region 110 and the gate electrode 145.

[0035] Seed layer 182 can be positioned on the bottom of each of the first contact structure CS1 and the second contact structure CS2 to enhance the bonding strength between the gate electrode 145 and the contact plug 185, and between the source / drain region 110 and the contact plug 185. As a result, seed layer 182 can effectively prevent contact plug 185 from being damaged during processes such as chemical mechanical polishing (CMP) (see...). Figure 6D It falls off during the period.

[0036] According to this example embodiment, seed layer 182 comprises a first crystalline metal, and contact plug 185 comprises a second crystalline metal different from the first crystalline metal. The crystalline metal may comprise a polycrystalline metal or a monocrystalline metal. Seed layer 182 may be formed of a metal having a relatively low resistance similar to that of contact plug 185. Therefore, contact resistance can be reduced. When the first and second crystalline metals are polycrystalline metals, contact plug 185 may have a grain size increased according to the grain size of seed layer 182 (i.e., the first crystalline metal). Mean free path may decrease due to the increase in grain size. Therefore, contact plug 185 may be formed of a material with low resistance.

[0037] Figure 3 yes Figure 2A An enlarged view of part "A1" of the semiconductor device shown in the figure.

[0038] Reference Figure 3The metal silicide film 120 may be located on the source / drain region 110. The metal silicide film 120 may be located on the recessed region 110R of the source / drain region 110. The metal silicide film 120 may be a crystalline silicide film. For example, the metal silicide film 120 may be a silicide film comprising Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, Pd, or combinations thereof. In an example embodiment, the metal silicide film 120 may be formed of CoSi, NiSi, or TiSi.

[0039] The first contact structure CS1 may include a seed layer 182 located on a metal silicide film 120 and a contact plug 185 located on the seed layer 182. In this example embodiment, each of the seed layer 182 and the contact plug 185 may be formed of polycrystalline metal.

[0040] In this example embodiment, the seed layer 182 includes a first crystalline metal comprising a first grain G1, and the contact plug 185 includes a second crystalline metal comprising a second grain G2. In this example embodiment, the first grain G1 and the second grain G2 are defined by grain boundaries GB1 and GB2, respectively, and may both have an in-plane crystalline orientation. To aid understanding, the crystalline orientation of each of the grains G1 and G2... Figure 3 The diagram schematically illustrates the diagonals of each of grains G1 and G2. In this example embodiment, the crystal orientation of the second crystalline metal depends on the crystal orientation of the first crystalline metal, which serves as the seed layer 182, and the second crystalline metal can be deposited on the first crystalline metal in a manner similar to epitaxial growth. This crystal orientation can be confirmed by X-ray diffraction.

[0041] like Figure 4 As shown, the second crystalline metal can substantially match the lattice of the first crystalline metal at the interface between the seed layer 182 and the contact plug 185. That is, the lattice in the first grain G1 and the lattice in the adjacent second grain G2 can substantially match each other, and there can be almost no potential caused by mismatch in the adjacent second grain G2. The conditions for this lattice matching can be determined based on conditions of crystal structure and lattice constants. The first and second crystalline metals can have the same crystal structure (e.g., body-centered cubic (BCC) structure). Furthermore, the lattice constants α1 and α2 of the first and second crystalline metals can be substantially the same, or the difference between them can be significantly small. For example, the difference between the lattice constants α1 and α2 can be less than 1%.

[0042] In an example embodiment, one of the seed layer 182 and the contact plug 185 may include tungsten (W), and the other of the seed layer 182 and the contact plug 185 may include molybdenum (Mo). For example, the seed layer 182 may include tungsten (W), and the contact plug 185 may include molybdenum (Mo). Tungsten (W) and molybdenum (Mo) may have the same properties as... Figure 4 The crystal structures shown are identical body-centered cubic structures BC1 and BC2, and the lattice constants α1 and α2 of tungsten (W) and molybdenum (Mo) can be respectively... and The difference between the lattice constants α1 and α2 can be less than 1%. Similar to epitaxial growth, molybdenum (as the second crystalline metal) can be deposited on tungsten (as the first crystalline metal), and the lattices of adjacent first grains can match those of the second grains. In this lattice matching, the second grain G2 of the contact plug 185 can have a size that increases according to the size of the first grain G1 of the seed layer 182. As the grain size increases, a contact plug 185 with low resistance can be provided. The second grain G2 of the contact plug 185 can have, but is not limited to, a size of 7 nm or larger, or a size of 10 nm or larger. In an example embodiment, where the contact plug 185 includes molybdenum, the resistivity of the contact plug 185 can be 50 μΩ·cm or less, or 10 μΩ·cm or less.

[0043] Seed layer 182 may be located at the bottom of first contact hole CH1 for first contact structure CS1. Contact plug 185 may be disposed in first contact hole CH1 without a blocking film. Sidewall of contact plug 185 may be in direct contact with insulating portion 160. By omitting the blocking film with relatively large resistance, the contact resistance between contact plug 185 and metal silicide film 120 can be reduced, and the size (specifically, width) of first contact structure CS1 can be reduced.

[0044] In the example embodiment, the thickness t of the seed layer 182 can be 5 nm or less, or 3 nm or less, but is not limited thereto. The first crystalline metal for the seed layer 182 can be formed by deposition such as physical vapor deposition (PVD) to ensure the desired crystallinity.

[0045] In this example embodiment, the seed layer 182 is shown to be formed of metal. However, the seed layer 182 may also be formed of another crystalline conductive material (e.g., a crystalline metal compound) that is lattice-matched to the metal of the contact plug 185.

[0046] Reference Figure 5 Similar to the first contact structure CS1, the second contact structure CS2 associated with the gate structure GS can be implemented as a low-resistance contact structure. Figure 5It is shown Figure 2B An enlarged view of part "A2" of the semiconductor device shown in the figure.

[0047] Figure 5 The second contact structure CS2 shown may include a seed layer 182 located on the gate electrode 145 and a contact plug 185 located on the seed layer 182. In this example embodiment, each of the seed layer 182 and the contact plug 185 may be formed of polycrystalline metal. In the example embodiment, when the gate electrode 145 is made of polycrystalline silicon, similar to the first contact structure CS1, a metal silicide film may be formed in the contact region of the gate electrode 145. Additionally, a second contact hole CH2 may define the second contact structure CS2.

[0048] Similar to the first contact structure CS1, the seed layer 182 comprises a first crystalline metal containing first grains G1', and the contact plug 185 comprises a second crystalline metal containing second grains G2'. The first grains G1' and the second grains G2' may be defined by grain boundaries GB1' and GB2', respectively. In the second contact structure CS2, similar to the contact plug 185, the seed layer 182 is also formed of a polycrystalline metal. However, because the seed layer 182 has a small area due to its relatively small thickness, grain boundaries may not be observed in some selected cross-sections.

[0049] The crystal orientation of the second crystalline metal depends on the crystal orientation of the first crystalline metal, which serves as the seed layer 182, and the second crystalline metal can be deposited on the first crystalline metal in a manner similar to epitaxial growth. The second crystalline metal can substantially match the lattice of the first crystalline metal at the interface between the seed layer 182 and the contact plug 185. Similar to the first contact structure CS1, one of the seed layer 182 and the contact plug 185 of the second contact structure CS2 can include tungsten (W), and the other can include molybdenum (Mo). For example, the seed layer 182 can include tungsten (W), and the contact plug 185 can include molybdenum (Mo). The second contact structure CS2 can be formed by a process similar to that used for the first contact structure CS1.

[0050] The semiconductor device 100 may include wiring 190 connected to the first contact structure CS1 and the second contact structure CS2. Wiring 190 may include portions of conductors formed as part of a backend of line (BEOL) process.

[0051] The first interlayer insulating layer 172 and the second interlayer insulating layer 173 may be located on the insulating portion 160. An etch stop film 171 may be disposed between the insulating portion 160 (specifically, the cover insulating film 162) and the first interlayer insulating layer 172. In an example embodiment, the etch stop film 171 may be formed of silicon nitride, silicon carbonitride, aluminum nitride, or aluminum oxide. In an example embodiment, the first interlayer insulating layer 172 and the second interlayer insulating layer 173 may be formed of silicon oxide, silicon nitride, or silicon oxynitride.

[0052] Wiring 190 may include along a first direction ( Figure 1 A metal line ML extending in the X direction and a metal via VM disposed between the first contact structure CS1 and the second contact structure CS2 and the metal line ML.

[0053] Similar to the first contact structure CS1 and the second contact structure CS2, the wiring 190 located on the first and second contact structures can be formed by a combination of a seed layer 182 and a contact plug 185. For example, as Figure 5 As shown, wiring 190 may include a wiring seed layer 192 located in at least a portion of the upper surface of the second contact structure CS2 (specifically, contact plug 185) and a fill metal 195 located on the wiring seed layer 192.

[0054] The wiring seed layer 192 can be formed of a crystalline conductive material. For example... Figure 5 As shown, the wiring seed layer 192 can be formed on the upper surface of the contact plug 185 in the area exposed to the via and on the upper surface of the first interlayer insulating layer 172 (including the surface of the via). In the wiring seed layer 192, as Figure 5 As shown, a crystalline conductive material including a third grain G3 can be deposited in a first region 192a located on the contact plug 185, and an amorphous or quasi-amorphous conductive material can be deposited in a second region 192b located on the surface of a first interlayer insulating layer 172, which may be amorphous. The third grain G3 may be defined by a grain boundary GB3.

[0055] The filler metal 195 may include a crystalline metal. At least in the first region 192a of the wiring seed layer 192, the crystalline orientation of the filler metal 195 affects the crystalline orientation at the boundary between the third grain G3 and the fourth grain G4 in the first region 192a. Furthermore, similar to crystal growth in the first region 192a, crystal growth of the filler metal 195 can also occur in the second region 192b (which is adjacent to the first region 192a). The fourth grain G4, defined by the grain boundary GB4, can have a relatively large size, resulting in the wiring 190 being implemented as a low-resistance structure. In an example embodiment, the wiring seed layer 192 may be formed of a conductive material such as tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tungsten carbonitride (WCN), or tungsten nitride (WN)). Examples of the filler metal 195 may include metals such as molybdenum (Mo), ruthenium (Ru), tungsten (W), cobalt (Co), or copper (Cu)).

[0056] In the example embodiment, similar to the first contact structure CS1 and the second contact structure CS2 described above, the crystal structure and lattice constant of the wiring seed layer 192 and the fill metal 195 can be selected such that the lattice of the third grain G3 of the wiring seed layer 192 and the lattice of the adjacent fourth grain G4 are substantially matched. In the example embodiment, the crystal structures of the two materials can be identical, and the difference between the lattice constants of the two materials can be less than 1%. For example, one of the wiring seed layer 192 and the fill metal 195 may include tungsten (W), and the other of the wiring seed layer 192 and the fill metal 195 may include molybdenum (Mo).

[0057] Figures 6A to 6D This is a cross-sectional view illustrating the main process of a method for manufacturing a semiconductor package according to an example embodiment.

[0058] Reference Figures 6A to 6D The process for forming the first contact structure in the semiconductor device 100 described above is described in detail. For ease of explanation, a cross-sectional view is shown below. Figure 3 The image shows Figure 2A A magnified view of section "A1". Here, although some components of this example embodiment are shown schematically, unless otherwise clearly indicated, reference can be made to... Figures 1 to 5 The descriptions of the same or similar components in the example embodiments shown are used to understand these components.

[0059] Reference Figure 6A A first contact hole CH1 can be formed to connect to the source / drain region 110, and a metal silicide film 120 can be formed on the surface of the source / drain region 110 exposed to the first contact hole CH1.

[0060] A first contact hole CH1 defining a first contact structure can be formed by sequentially etching the inter-gate insulating film 161 and the cap insulating film 162 using an etching mask. A portion of the source / drain region 110 can be exposed to the first contact hole CH1. During the process of forming the first contact hole CH1, the exposed portion of the source / drain region 110 can be recessed to a predetermined depth. In this process, a second contact hole CH2 defining a second contact structure can also be formed.

[0061] A metal silicide film 120 can be formed on the exposed area of ​​the source / drain region 110 by forming a metal layer on the recessed area exposed to the first contact hole CH1 and performing annealing.

[0062] Next, refer to Figure 6B A seed layer 182 can be deposited on the metal silicide film 120.

[0063] Seed layer 182 may comprise a crystalline metal (such as a single-crystal metal or a polycrystalline metal). Seed layer 182 may be formed by linear deposition (such as PVD) to ensure sufficient crystallinity. By such linear deposition, seed layer 182 may be formed not only on the desired portion of the metal silicide film 120 positioned at the bottom of the first contact hole CH1, but also on the upper surface of the insulating portion 160. Seed material layer 182T positioned on insulating portion 160 may be removed in a subsequent process. Seed layer 182 may have a thickness of, but is not limited to, 5 nm or less, or 3 nm or less.

[0064] This can be considered for use with the contact plug 185 that will be formed in subsequent processing. Figure 6D The lattice-matching conditions are used to select the material for forming the seed layer 182. In an example embodiment, the seed layer 182 may include tungsten (W) or molybdenum (Mo). The material used to form the seed layer 182 may include a conductive material, such as a crystalline metal compound suitable for the lattice-matching conditions described above for use with the metal of the contact plug 185. For example, the seed layer 182 may include a conductive material such as tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tungsten carbonitride (WCN), or tungsten nitride (WN).

[0065] Then, refer to Figure 6C A contact plug 185 that fills the first contact hole CH1 can be formed by using a seed layer 182.

[0066] In this process, a metal material layer 185' for the contact plug can be formed to cover the upper surface of the insulating portion 160 while filling the first contact hole CH1. The metal material layer 185' can be formed of a metal (such as molybdenum (Mo), ruthenium (Ru), tungsten (W), cobalt (Co), or copper (Cu)). The metal material layer 185' for the contact plug can be grown to have a specific orientation according to the crystal orientation of the seed layer 182 and can have a relatively large grain size. The metal material layer 185' may include a crystalline metal suitable for lattice matching with the seed layer 182. The crystal structures of the two materials can be identical to each other, and the difference between the lattice constants of the two materials can be less than 1%. For example, the metal material layer 185' may include molybdenum (Mo) or tungsten (W). In an example embodiment, the seed layer 182 may include tungsten (W), and the metal material layer 185' may include molybdenum (Mo).

[0067] In this example embodiment, the metal material layer 185' can be disposed in the first contact hole CH1 without a barrier film. By omitting the barrier film, which has relatively large resistance, the contact resistance between the contact plug 185 and the metal silicide film 120 can be reduced, and the size of the first contact structure CS1 can be reduced. In this example embodiment, the metal material layer 185' for the contact plug can be in direct contact with the insulating portion 160 at the inner sidewall of the first contact hole CH1.

[0068] Next, refer to Figure 6D The contact plug material 185T and seed material layer 182T positioned on the insulating portion 160 can be removed by polishing. For example, a planarization process such as chemical mechanical polishing (CMP) can be performed to expose the upper surface of the cover insulating film 162. The metal material layer 185' can be removed. Figure 6C The portion of the metal material layer 185' positioned on the cover insulating film 162 may be used to fill only the portion of the first contact hole CH1, and this portion may be set as the contact plug 185. The contact plug 185 may have an upper surface substantially coplanar with the upper surface of the insulating portion 160. Then, the BEOL process can be used to form wiring 190 connected to the first contact structure CS1 together with the first interlayer insulating layer 172 and the second interlayer insulating layer 173 in subsequent processes. The second contact structure CS2 may be formed by a process similar to that used for the first contact structure CS1. The contact structure may be modified in various ways. For example, the area where the seed layer is formed may vary depending on the deposition, and the combination of the seed layer and the contact plug may vary in the stack of contact structures.

[0069] Figure 7 and Figure 8 This is a cross-sectional view of the contact structures that can be employed in a semiconductor device according to various example embodiments. The cross-sectional view shows, as... Figure 3 As shown Figure 2A A magnified view of part "A1".

[0070] It is understandable that, apart from the first contact structure CS1' including a seed layer 182' extending to a portion of the inner sidewall of the first contact hole CH1, Figure 7 The first contact structure CS1' shown in the figure is similar to Figure 3 The first contact structure CS1 is shown in the diagram. Furthermore, unless otherwise clearly indicated, reference can be made to... Figures 1 to 4 (Specifically, Figure 3 The components of this example embodiment are understood by referring to the description of the same or similar components shown in the example embodiments.

[0071] In this example embodiment, a seed layer 182' is formed on the bottom of the first contact hole CH1 and also has a portion 182E extending on the inner sidewall of the first contact hole CH1. The extension 182E of the seed layer 182' may include a crystalline portion grown from a metal silicide film 120, which may be crystalline. The contact plug 185 may be grown from the surface of the seed layer 182' and may have a crystalline orientation according to the crystalline orientation of the seed layer 182'. The two materials may be substantially lattice-matched to each other at the interface between the contact plug 185 and the seed layer 182', resulting in the contact plug 185 having a relatively large grain size.

[0072] The case where the first contact structure CS1' has a small size is shown. The first contact structure CS1' with a small size has a relatively small cross-sectional area. Therefore, even when the contact plug 185 comprises polycrystalline metal, it is possible that grain boundaries cannot be observed in some selected cross-sections.

[0073] The dimensions of the first contact structure CS1' can be defined as a bottom width W and a height H. The bottom width W of the first contact structure CS1' can be, but is not limited to, 20 nm or less, or 15 nm or less. In the example embodiment, the aspect ratio of the height H and the bottom width W of the first contact structure CS1' can be 3:1 or greater.

[0074] Reference Figure 8 It is understandable that, apart from the first contact structure CS1” including the seed layer 182” extending to the entire or almost the entire inner wall of the first contact hole CH1, Figure 8 The first contact structure CS1 shown is similar to Figure 3 The first contact structure CS1 is shown, and the second portion 182b of the extension of the seed layer 182” is not formed of crystalline metal. Furthermore, unless otherwise clearly indicated, reference can be made to... Figures 1 to 4 (Specifically, Figure 3The components of this example embodiment are understood by referring to the description of the same or similar components shown in the example embodiments.

[0075] In this example embodiment, the seed layer 182” includes a first portion 182a positioned at the bottom of the first contact hole CH1 and a second portion 182b extending on the inner sidewall of the first contact hole CH1. The second portion 182b of the seed layer 182” may be disposed along almost the entire inner sidewall of the first contact hole CH1. The first portion 182a may include a crystalline (monocrystalline or polycrystalline) portion grown from the metal silicide film 120, and the second portion 182b may be connected to the insulating portion 160 serving as the inner wall surface and may be amorphous or quasi-amorphous. The contact plug 185 may be grown from the surface of the first portion 182a of the seed layer 182” and may have a crystalline orientation according to the crystalline orientation of the first portion 182a. The two materials may be substantially lattice-matched to each other at the interface between the contact plug 185 and the first portion 182a of the seed layer 182”, resulting in the contact plug 185 having a relatively large grain size, thereby providing a low-resistance contact structure.

[0076] Figure 9 This is a cross-sectional view illustrating a contact structure that may be employed in a semiconductor device according to an example embodiment. The cross-sectional view is as follows... Figure 5 The image shows Figure 2B A magnified view of part A2.

[0077] It is understandable that, apart from the locations where seed layer 182' and wiring seed layer 192' are formed, Figure 9 The stack of the second contact structure CS2' shown in the figure and the metal via VM are similar to Figure 5 The stack of the second contact structure CS2 and the metal via VM are shown in the diagram. Furthermore, unless otherwise clearly indicated, reference can be made to... Figure 1 , Figures 2A to 2C and Figure 5 (Specifically, Figure 5 The components of this example embodiment are understood by referring to the description of the same or similar components shown in the example embodiments.

[0078] In this example embodiment, the seed layer 182' includes a first portion 182a' positioned on the bottom of the second contact hole CH2 and a second portion 182b' extending on the inner sidewall of the second contact hole CH2. The second portion 182b' of the seed layer 182' may be disposed along a portion of the sidewall of the second contact hole CH2, and unlike the example embodiment described above, the second portion 182b' may be amorphous or quasi-amorphous. On the other hand, the first portion 182a' may include a crystalline (single-crystal or polycrystalline) portion grown from the metal silicide film 120, and the contact plug 185 may be grown from the surface of the first portion 182a' of the seed layer 182' and have a crystalline orientation according to the crystalline orientation of the first portion 182a'. The lattices of the two materials may substantially match each other at the interface between the contact plug 185 and the first portion 182a' of the seed layer 182'.

[0079] Wiring 190' may include a wiring seed layer 192' located in a portion of the upper surface of the contact plug 185 and a fill metal 195 located on the wiring seed layer 192'. The wiring seed layer 192' may include a crystalline conductive material, and the fill metal 195 may be grown from the surface of the wiring seed layer 192' and have a crystalline orientation according to the crystalline orientation of the seed layer 192'. The two materials may be substantially lattice-matched to each other at the interface between the contact plug 185 and the wiring seed layer 192'.

[0080] Thus, the contact plug 185 and the fill metal 195 can have relatively large grain sizes, thereby providing low-resistance contact structures and wiring structures, respectively.

[0081] The aforementioned wiring 190 and 190' can also be applied to another type of semiconductor device. For example, as shown in... Figures 2A to 2C The fin transistor (FinFET) shown, including the fin channel region, is described as a semiconductor device according to an example embodiment, but the semiconductor device is not limited thereto. A semiconductor device according to some example embodiments may include a tunneling field-effect transistor (FET), a transistor including nanowires, a transistor including nanosheets (i.e., a multi-bridge channel FET (MBCFET) (registered trademark)), or various three-dimensional (3D) transistors.

[0082] Figure 10 This is a cross-sectional view showing a transistor comprising a nanosheet (N-MOSFET) as a semiconductor device according to an example embodiment.

[0083] Reference Figure 10 It is understood that, except that the structure corresponding to the fin-shaped active region 105 in the above example embodiment is a multi-channel structure using nanosheets, the semiconductor device 100A is similar to... Figures 1 to 5The semiconductor device is shown in the figure. Furthermore, unless otherwise clearly indicated, reference may be made to... Figures 1 to 5 The components of this example embodiment are understood by referring to the description of the same or similar components shown in the example embodiments.

[0084] like Figure 10 As shown, the semiconductor device 100A may include a plurality of channel layers CL and a gate electrode 145, the plurality of channel layers CL being located on the active region AR in a third direction perpendicular to the upper surface of the substrate 101. Figure 1 The gate electrodes 145 are spaced apart from each other in the Z direction and each forms a nanosheet structure. The gate electrodes 145 surround multiple channel layers CL and are spaced apart in the Z direction and in the Z direction. Figure 1 The second direction intersecting the Z direction) Figure 1 (Extending in the Y direction). Thus, the gate electrode 145 can be placed between the gate spacers 141 and between the multiple channel layers CL.

[0085] Semiconductor device 100A may include source / drain regions 110 in a portion of an active region AR located on opposite sides of a gate electrode 145, the source / drain regions 110 being connected to a plurality of channel layers CL. In this example embodiment, the source / drain regions 110 may be located in a fin-type active region 105 located on opposite sides of the gate electrode 145, and may be respectively connected to opposite sides of the plurality of channel layers CL in a first direction (e.g., the X direction). In this example embodiment, a case where the number of channel layers CL is three is shown, but the number of channel layers CL is not particularly limited thereto. The channel layers CL may include semiconductor patterns. For example, the semiconductor patterns may be formed of at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge).

[0086] The source / drain region 110 may include a regrown epitaxial region formed by using multiple channel layers CL and active regions AR as seeds. The source / drain region 110 may be formed of silicon (Si) and may be doped with N-type impurities (e.g., phosphorus (P), nitrogen (N), arsenic (As) or antimony (Sb)).

[0087] Semiconductor device 100A according to this example embodiment may include internal spacers IS disposed between respective source / drain regions 110 and gate electrode 145. The internal spacers IS may be disposed on one side of the gate electrode 145. The internal spacers IS and channel layers CL may be arranged alternately along a third direction. Each of the source / drain regions 110 may contact the channel layer CL and may be spaced apart from the gate electrode 145 while the internal spacers are positioned between the source / drain regions 110 and the gate electrode 145. A gate insulating layer 142 may be disposed between the gate electrode 145 and each channel layer CL, and may extend between the gate electrode 145 and each internal spacer IS.

[0088] The source / drain region 110 may include three combined regrown epitaxial regions, and a recessed region 110R may be formed in the upper surface of the source / drain region 110 that connects to the contact hole. A metal silicide film 120 is located on the surface of the recessed region 110R of the source / drain region 110. Similar to the example embodiment described above, the first contact structure CS1 may include a seed layer 182 located on the metal silicide film 120 and a contact plug 185 located on the seed layer 182.

[0089] Each of the seed layer 182 and the contact plug 185 may comprise a polycrystalline metal. The seed layer 182 and the contact plug 185 may each comprise a first crystalline metal and a second crystalline metal. The crystal orientation of the second crystalline metal depends on the crystal orientation of the first crystalline metal serving as the seed layer 182, and the second crystalline metal may be deposited on the first crystalline metal in a manner similar to epitaxial growth. The second crystalline metal may be lattice-matched with the fundamental lattice of the first crystalline metal at the interface between the seed layer 182 and the contact plug 185.

[0090] In an example embodiment, the first crystalline metal and the second crystalline metal may have the same crystal structure (e.g., a body-centered cubic (BCC) structure). Furthermore, the lattice constants of the first crystalline metal and the second crystalline metal may be substantially the same, or the difference between their lattice constants may be significantly small. For example, the difference between the lattice constant α1 of the first crystalline metal and the lattice constant α2 of the second crystalline metal may be less than 1%. In an example embodiment, one of the seed layer 182 and the contact plug 185 may include tungsten (W), and the other may include molybdenum (Mo). Therefore, the grains of the contact plug 185 may have an increased size according to the grain size of the seed layer 182. As the grain size increases, a contact plug 185 with low resistance can be provided. Although not shown, similar to the first contact structure CS1, the second contact structure connected to the gate electrode 145 can be implemented as a low-resistance contact structure.

[0091] The wiring 190 located on the first contact structure CS1 may include a wiring seed layer 192 and a fill metal 195 located on the wiring seed layer 192. Similar to the first contact structure CS1 described above, the lattice of the grains of the wiring seed layer 192 and the lattice of the adjacent grains of the fill metal 195 can be substantially matched with each other, thereby realizing a wiring 190 with low resistance.

[0092] Figure 11 This is a cross-sectional view showing a transistor comprising a nanosheet (P-MOSFET) as a semiconductor device according to an example embodiment.

[0093] Reference Figure 11 The semiconductor device 100B has, for example Figure 10 The example embodiment shown uses a multi-channel structure with nanosheets and is implemented by a P-MOSFET. Similar to the example embodiment described above, it will be understood that the semiconductor device 100B according to this example embodiment is similar to... Figures 1 to 5 and Figure 10 The semiconductor device is shown in the figure. Furthermore, unless otherwise clearly indicated, reference may be made to... Figures 1 to 5 and Figure 10 The components of this example embodiment are understood by referring to the description of the same or similar components shown in the example embodiments.

[0094] Reference Figure 11 Similar to the example embodiments described above ( Figure 10 According to this example embodiment, the semiconductor device 100B may include a plurality of channel layers CL and a gate electrode 145, the plurality of channel layers CL being located on the active region AR in a third direction perpendicular to the upper surface of the substrate 101. Figure 1 The gate electrodes 145 are spaced apart from each other in the Z direction and each forms a nanosheet structure. The gate electrodes 145 surround multiple channel layers CL and are spaced apart in the Z direction and in the Z direction. Figure 1 The second direction intersecting the Z direction) Figure 1 It extends in the Y direction. In addition, the gate electrode 145 can be placed between the gate spacers 141 and between the multiple channel layers CL.

[0095] Semiconductor device 100B may include source / drain regions 110' in a portion of an active region AR located on opposite sides of a gate electrode 145, the source / drain regions 110' being connected to a plurality of channel layers CL. The source / drain regions 110' may be located in fin-type active regions 105 located on opposite sides of the gate electrode 145, and may be respectively connected to opposite sides of the plurality of channel layers CL in a first direction (e.g., the X direction). The source / drain regions 110' may include an epitaxial layer formed using the plurality of channel layers CL and the active region AR as seeds. (This is consistent with the example embodiment described above.) Figure 10 Unlike other regions, the source / drain region 110' can be formed of silicon germanium (SiGe) and can be doped with P-type impurities (e.g., boron (B), indium (In), gallium (Ga), boron trifluoride (BF3)).

[0096] Unlike the example embodiments described above, in the semiconductor device 100B according to this example embodiment, the source / drain region 110' and the gate electrode 145 can be in direct contact with each other without internal spacers IS.

[0097] The source / drain region 110' may include three combined regrown epitaxial regions (the cross-section in the Y direction may have a pentagonal shape), and the metal silicide film 120' may be formed along the staggered (irregular) crystal planes of the source / drain region 110'. The first contact structure CS1' may include a seed layer 182' located on the metal silicide film 120' and a contact plug 185 located on the seed layer 182'.

[0098] Each of the seed layer 182' and the contact plug 185 may comprise a polycrystalline metal. The seed layer 182' and the contact plug 185 may each comprise a first crystalline metal and a second crystalline metal. The crystal orientation of the second crystalline metal depends on the crystal orientation of the first crystalline metal serving as the seed layer 182', and the second crystalline metal may be deposited on the first crystalline metal in a manner similar to epitaxial growth. Specifically, the lattice of the second crystalline metal adjacent to the interface between the seed layer 182' and the contact plug 185 may be matched with the lattice of the first crystalline metal. In such a matching process, the grains of the contact plug 185 may have an increased size according to the grain size of the seed layer 182'. As the grain size increases, a contact plug 185 with low resistance can be provided. Although not shown, a second contact structure connected to the gate electrode 145 can be implemented in a similar manner.

[0099] In an example embodiment, the wiring 190 located on the first contact structure CS1 may include a wiring seed layer 192 and a fill metal 195 located on the wiring seed layer 192. Similar to the first contact structure CS1 described above, the lattice of the grains of the wiring seed layer 192 and the lattice of the grains of the adjacent fill metal 195 can be substantially matched to each other to achieve wiring 190 with low resistance.

[0100] Figure 12 This is a cross-sectional view showing a semiconductor device according to an example embodiment.

[0101] Figure 12 The semiconductor device 200 shown may include a substrate 211 having a contact region, a first interlayer insulating layer 212 located on the substrate 211 and having a first contact hole VH1 connected to the contact region CA, and a contact structure 230 located on the contact region in the first contact hole VH1.

[0102] Contact structure 230 may include a first seed layer 232 formed of a first crystalline metal and a first contact metal 235 formed of a second crystalline metal and filling the first contact hole VH1 on the first seed layer 232. The second crystalline metal may be substantially lattice-matched with the first crystalline metal at the interface between the first and second crystalline metals. In this example embodiment, a portion of the conductor 220 is shown as the contact region CA. However, the contact region CA may be an active region similar to a source / drain region or a metal silicide film similar to the example embodiment described above.

[0103] The semiconductor device 200 according to this example embodiment includes an etch stop film 215 located on a first interlayer insulating layer 212, a second interlayer insulating layer 213 located on the etch stop film 215 and having a second contact hole VH2 connected to a contact structure 230, and wiring 250 located in the second interlayer insulating layer 213 and having a metal via VM connected to the contact structure 230 through the second contact hole VH2.

[0104] The wiring 250 may include a second seed layer 252 formed of a third crystalline metal and a second contact metal 255 formed of a fourth crystalline metal and filling a second contact hole VH2 on the second seed layer 252. The fourth crystalline metal may be lattice-matched with the third crystalline metal at the interface between the third crystalline metal and the fourth crystalline metal.

[0105] Thus, the third and fourth crystalline metals can have the same crystal structure suitable for lattice matching, and the difference between the lattice constants of the third and fourth crystalline metals can be less than 1%. Compared with the grain size of the first and third crystalline metals, the second and fourth crystalline metals can have relatively large grain sizes (e.g., 7 nm or larger), so the resistance of the contact structure 230 and the wiring 250 can be reduced.

[0106] In an example embodiment, the first crystalline metal may be the same as the third crystalline metal, and the second crystalline metal may be the same as the fourth crystalline metal. For example, the first and third crystalline metals may be tungsten (W), and the second and fourth crystalline metals may be molybdenum (Mo).

[0107] By summarizing and reviewing, it can be seen that as the critical dimension (CD) of the contact decreases, the contact resistance increases and can lead to various defects.

[0108] As described above, the embodiments can provide semiconductor devices with excellent reliability. As described above, according to the example embodiment, a seed layer can be formed in each region located on the bottom of the first and second contact structures to improve the bonding strength of the contact plugs. As a result, contact plug detachment during chemical mechanical polishing (CMP) can be effectively prevented. Furthermore, the contact plugs are formed with a lattice matching that of the seed layer, allowing for an increase in the grain size of the contact plugs, thereby significantly reducing contact resistance.

[0109] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used in a general and descriptive sense only and is to be interpreted in a specific way, not for limiting purposes. In some instances, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated at the time of filing of this application. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A semiconductor device, the semiconductor device comprising: The fin-shaped active region extends on the substrate in a first direction parallel to the upper surface of the substrate; A gate structure extends across the fin active region along a second direction parallel to the upper surface of the substrate and different from the first direction; The source / drain region is located in the fin-type active region on one side of the gate structure; An insulating portion covers the gate structure and the source / drain regions; The first contact structure penetrates the insulation portion and connects to the source / drain region; as well as The second contact structure penetrates the insulating portion and connects to the gate structure, wherein: At least one of the first contact structure and the second contact structure includes a seed layer containing a first crystalline metal located on at least one of the gate structure and the source / drain region, and a contact plug located on the seed layer containing a second crystalline metal different from the first crystalline metal. The second crystalline metal has a fundamental lattice match with the first crystalline metal at the interface between the seed layer and the contact plug, wherein the first and second crystalline metals have the same crystal structure, and the difference between the lattice constants of the first and second crystalline metals is less than 1%. The seed layer is located on the bottom of at least one of the first contact structure and the second contact structure, and The contact plug is in direct contact with the insulating portion at the sidewall of at least one of the first contact structure and the second contact structure.

2. The semiconductor device according to claim 1, wherein, One of the first crystalline metal and the second crystalline metal is tungsten, and the other of the first crystalline metal and the second crystalline metal is molybdenum.

3. The semiconductor device according to claim 1, wherein, The bottom width of at least one of the first contact structure and the second contact structure is 20 nm or less.

4. The semiconductor device according to claim 3, wherein, The seed layer has a thickness of 5 nm or less.

5. The semiconductor device according to claim 1, wherein, The seed layer has an extension that extends over the insulating portion at the sidewall of at least one of the first and second contact structures.

6. The semiconductor device according to claim 5, wherein, The portion of the seed layer positioned on the bottom includes a monocrystalline or polycrystalline portion, and the extension of the seed layer includes an amorphous portion.

7. The semiconductor device according to claim 1, wherein, The first contact structure and the second contact structure include at least one of the second contact structure, the gate structure includes a gate electrode, and the seed layer is located on the gate electrode.

8. The semiconductor device according to claim 1, further comprising: An interlayer insulating layer is located on the insulating portion; as well as Metal wires, including metal vias that penetrate the interlayer insulation layer.

9. The semiconductor device according to claim 8, wherein: The metal wire includes: an additional seed layer at at least one of the first and second contact structures and at the metal via, comprising a third crystalline metal; and a fill metal located on the additional seed layer and comprising a fourth crystalline metal different from the third crystalline metal. The fourth crystalline metal is lattice-matched with the third crystalline metal at the interface between the additional seed layer and the filler metal, wherein the third crystalline metal and the fourth crystalline metal have the same crystal structure, and the difference between the lattice constant of the third crystalline metal and the lattice constant of the fourth crystalline metal is less than 1%.

10. The semiconductor device according to claim 1, wherein, The height-to-width ratio of at least one of the first contact structure and the second contact structure is 3:1 or greater.

11. The semiconductor device according to claim 1, wherein, The gate structure includes: The gate electrode extends along the second direction across the fin-shaped active region; and A gate insulating layer is disposed between the gate electrode and the fin-type active region.

12. The semiconductor device of claim 1, further comprising: Multiple channel layers are located on the fin-shaped active region and are spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, and extend in the first direction. The gate structure includes: Gate electrode, surrounding the plurality of channel layers and extending along the second direction; and A gate insulating layer is located between each of the plurality of channel layers and the gate electrode, and between the fin active region and the gate electrode.

13. A semiconductor device, the semiconductor device comprising: The substrate has a contact area; A first insulating layer is located on the substrate and has a first contact hole connected to the contact area; A first seed layer is located on the contact area in the first contact hole and includes a first crystalline metal; as well as A first contact metal, located on the first seed layer, fills the first contact hole and includes a second crystalline metal. Wherein, the second crystalline metal is substantially lattice-matched with the first crystalline metal at the interface between the first and second crystalline metals, wherein the first and second crystalline metals have the same crystal structure, and the difference between the lattice constants of the first and second crystalline metals is less than 1%, and The grain size of the second crystalline metal is 7 nm or larger.

14. The semiconductor device of claim 13, further comprising: A second insulating layer is located on the first insulating layer and has a second contact hole connected to the first contact metal; The second seed layer is located on the first contact metal in the second contact hole and includes a third crystalline metal; as well as The second contact metal, located on the second seed layer, fills the second contact hole and includes a fourth crystalline metal. Wherein, the fourth crystalline metal is lattice-matched with the third crystalline metal at the interface between the third crystalline metal and the fourth crystalline metal, wherein the third crystalline metal and the fourth crystalline metal have the same crystal structure, and the difference between the lattice constant of the third crystalline metal and the lattice constant of the fourth crystalline metal is less than 1%.

15. The semiconductor device according to claim 14, wherein, The first crystalline metal and the third crystalline metal are made of the same material, and the second crystalline metal and the fourth crystalline metal are made of the same material.

16. The semiconductor device according to claim 15, wherein, The first and third crystalline metals are tungsten, and the second and fourth crystalline metals are molybdenum.

17. A semiconductor device, the semiconductor device comprising: The fin-shaped active region extends on the substrate in a first direction parallel to the upper surface of the substrate; A gate structure extends across the fin active region along a second direction parallel to the upper surface of the substrate and different from the first direction; The source / drain region is located in the fin-type active region on one side of the gate structure; An insulating portion covers the gate structure and the source / drain regions; An interlayer insulating layer is located on the insulating portion; Metal wires, including metal vias that penetrate the interlayer insulation layer; The first contact structure is connected to the source / drain region; as well as A second contact structure is connected to the gate structure, wherein: At least one of the first contact structure and the second contact structure includes a seed layer located on at least one of the gate structure and the source / drain region, and a contact plug located on the seed layer. The seed layer comprises a first crystalline conductive material, and the contact plug comprises a second crystalline conductive material. The first crystalline conductive material and the second crystalline conductive material have the same crystal structure, and the difference between the lattice constants of the first crystalline conductive material and the second crystalline conductive material is less than 1%. The metal wire includes: An additional seed layer, located at at least one of the first and second contact structures and at the metal via, and comprising a third crystalline metal; and A filler metal is located on the additional seed layer and includes a fourth crystalline metal different from the third crystalline metal, the fourth crystalline metal having a fundamental lattice match with the third crystalline metal at the interface between the additional seed layer and the filler metal, wherein the third crystalline metal and the fourth crystalline metal have the same crystal structure and the difference between the lattice constant of the third crystalline metal and the lattice constant of the fourth crystalline metal is less than 1%.

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