Channel formation for vertical three-dimensional (3D) memory

Abstract

This application relates to channel formation for vertical three-dimensional (3D) memory. Systems, methods, and devices are provided for depositing alternating layers of a dielectric material and a sacrificial material in repeated iterations to form a vertical stack; forming a plurality of vertical openings through the vertical stack to form elongated vertical columns of a columnar array having sidewalls in the vertical stack; patterning the columns to expose locations to form channel regions; selectively removing a portion of the sacrificial material to form first horizontal openings in the sidewalls of the elongated vertical columns in the first horizontal direction; and depositing a channel material in the first horizontal openings to form the channel regions within the sidewalls for horizontally oriented access devices.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to memory devices, and more particularly, to channel formation for vertical three-dimensional (3D) memory. BACKGROUND

[0002] Memory is often implemented in electronic systems such as computers, cell phones, handheld devices, and the like. There are many different types of memory, including volatile and non-volatile memory. Volatile memory can require power to maintain its data and can include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory can provide persistent data even when power is lost and can include non-volatile memory express (NVMe), or non-Flash, nitride read-only memory (NROM), phase change memory (e.g., phase change random access memory), resistive memory (e.g., resistive random access memory), cross point memory, ferroelectric random access memory (FeRAM), and the like.

[0003] As design rules shrink, less semiconductor space is available for fabricating memory, including DRAM arrays. A corresponding memory cell for a DRAM can include an access device, such as a transistor, having a first source / drain region and a second source / drain region separated by a channel. A gate can be opposite the channel region and separated from the channel by a gate dielectric. An access line, such as a word line, is electrically connected to the gate of the DRAM cell. The DRAM cell can include a storage node, such as a capacitor cell, coupled to a digit line by the access device. By way of example and not limitation, the storage node can include a conductive material, such as a ferroelectric material. The ferroelectric material can include, but is not limited to, zirconium oxide (Zr02), hafnium oxide (Hf02), lanthanum oxide (La02), and aluminum oxide (Al203), or combinations thereof. The access device can be activated (e.g., to select the cell) by an access line coupled to the access transistor. The capacitor can store a charge corresponding to a data value (e.g., a logical “1” or “0”) of the corresponding cell. SUMMARY

[0004] One embodiment of the present disclosure provides a method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines, the method comprising: depositing, in repeated iterations, alternating layers of a dielectric material and a sacrificial material to form a vertical stack; forming a plurality of vertical openings through the vertical stack, the plurality of vertical openings having a first horizontal direction and a second horizontal direction and extending predominantly in the second horizontal direction to form an elongated column of vertical pillars having sidewalls in the vertical stack; patterning the elongated column of vertical pillars to expose locations to form channel regions in the sacrificial material in each of the layers; selectively removing a portion of the sacrificial material to form first horizontal openings in the sidewalls of the elongated column of vertical pillars in the first horizontal direction; and depositing a channel material in the first horizontal openings to form the channel regions within the sidewalls for the horizontally oriented access devices.

[0005] Another embodiment of the present disclosure provides a method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines, the method comprising: depositing, in repeated iterations, alternating layers of a dielectric material and a yttrium oxide (Y203) material to form a vertical stack; forming a plurality of vertical openings through the vertical stack, the plurality of vertical openings having a first horizontal direction and a second horizontal direction and extending predominantly in the second horizontal direction to form an elongated column of vertical pillars having sidewalls in the vertical stack; patterning the elongated column of vertical pillars to expose locations to form channel regions in the layers of the yttrium oxide (Y203) material; selectively etching to remove portions of the yttrium oxide (Y203) material in the first horizontal direction to form first horizontal openings on opposite sides of sidewalls of the elongated column of vertical pillars; and depositing a channel material in the first horizontal openings to form channel regions on the opposite sides of the sidewalls of the elongated column of vertical pillars.

[0006] Yet another embodiment of the present disclosure provides a method for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines, the method comprising: depositing alternating layers of dielectric material and semiconductor material to form a vertical stack; forming a plurality of vertical openings through the vertical stack, the plurality of vertical openings having a first horizontal direction and a second horizontal direction and extending predominantly in the second horizontal direction to form elongated vertical columns of columns having sidewalls in the vertical stack; patterning the elongated vertical columns to expose locations to form channel regions in the semiconductor material; selectively etching to remove portions of the semiconductor material in the first horizontal direction to form first horizontal openings in the semiconductor material on opposing sidewalls of the elongated vertical columns; selectively depositing channel material in the first horizontal openings to form channel regions of the horizontally oriented access devices; conformally depositing conductive material on gate dielectric material in the plurality of vertical openings; and removing portions of the conductive material to form a plurality of separate vertical access lines along the sidewalls of the elongated vertical columns opposite the channel regions.

[0007] Still another embodiment of the present disclosure provides a memory cell array comprising: a plurality of access transistors stacked on one another, each of the access transistors including a first source / drain region, a second source / drain region, and a channel region therebetween, and a body region, the first source / drain region, the second source / drain region, and the channel region being horizontally arranged, wherein the channel region includes a channel material and a passivation material; at least one access line extending vertically and coupled to each of the channel regions of the plurality of access transistors under intervention of a gate dielectric material; a plurality of storage capacitors stacked on one another, each of the plurality of storage capacitors being horizontally disposed and coupled to a corresponding one of the second source / drain regions of the plurality of access transistors; and a plurality of digit lines, each of the plurality of digit lines being coupled to a corresponding one of the first source / drain regions of the plurality of access transistors. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a schematic illustration of a vertical three-dimensional (3D) memory in accordance with a number of embodiments of the present disclosure.

[0009] Figure 2 is a perspective view illustrating a portion of a three-node access device in a vertical three-dimensional (3D) memory array in accordance with a number of embodiments of the present disclosure.

[0010] Figure 3is a perspective view showing a portion of a three-node access device in a vertical three-dimensional (3D) memory array in accordance with a number of embodiments of the present disclosure.

[0011] Figures 4A-4D is a cross-sectional view of forming an array of vertically stacked memory cells for channels of vertical three-dimensional memory at a number of stages of a semiconductor manufacturing process in accordance with a number of embodiments of the present disclosure.

[0012] Figure 5 is a three-dimensional (3D) perspective view of a memory device including a number of channels for vertical 3D memory in accordance with a number of embodiments of the present disclosure.

[0013] Figures 6A-6D shows an example method for forming an array of vertically stacked memory cells having three-node horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor manufacturing process in accordance with a number of embodiments of the present disclosure.

[0014] Figures 7A-7E shows an example method for forming an array of vertically stacked memory cells having three-node horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor manufacturing process in accordance with a number of embodiments of the present disclosure.

[0015] Figures 8A-8E shows an example method for forming an array of vertically stacked memory cells having three-node horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor manufacturing process in accordance with a number of embodiments of the present disclosure.

[0016] Figures 9A-9E shows an example method for forming an array of vertically stacked memory cells having three-node horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor manufacturing process in accordance with a number of embodiments of the present disclosure.

[0017] Figures 10A-10E shows an example method for forming an array of vertically stacked memory cells having three-node horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor manufacturing process in accordance with a number of embodiments of the present disclosure.

[0018] Figure 11 is a block diagram of an apparatus in the form of a computing system including a memory device in accordance with a number of embodiments of the present disclosure. DETAILED DESCRIPTION

[0019] Embodiments of the present disclosure describe tri-node access devices for vertical three-dimensional (3D) memory. As used herein, tri-node is intended to refer to an access device that includes (1) a first source / drain region and (2) a second source / drain region separated by a channel and (3) one or more gates opposite the channel. In a tri-node access device, the channel can be formed from a channel material and a passivation material. Forming the channel from a channel material and a passivation material can increase the stability of the channel compared to a channel that does not include a passivation material. Additional advantages of the structure include reducing the threshold voltage of the channel and reducing the change in the threshold voltage of the channel over time.

[0020] In some embodiments, the channel fabrication step can be performed after the capacitor cell formation process, thus reducing the thermal budget. The channel can be the last element of a vertical stack formed in situ to reduce the amount of time the channel is exposed to heat during the memory device fabrication process.

[0021] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits, if any, correspond to the numbering of the element or component within the figure. Similar elements or components between different figures can be denoted by the use of similar digits. For example, 103 can reference element "03" in Figure 1, and a similar element can be referenced as 203 in Figure 2. Multiple similar elements between different figures can be referenced by the use of a dash and a number or letter, as in 203-1 for element 203-1 in Figure 2, and 203-2 for element 203-2 in Figure 2. Such similar elements can generally be referenced without use of the dash and the extra number or letter, as in 203 for elements 203-1 and 203-2 or other similar elements. Figure 1 Figure 2 Figure 2

[0022] Figure 1 is a block diagram of a device in accordance with many embodiments of the present disclosure. Figure 1 A circuit diagram is shown illustrating a cell array of a three-dimensional (3D) semiconductor memory device in accordance with embodiments of the present disclosure. Figure 1 ​​​The cell array can have a plurality of sub-cell arrays 101-1, 101-2,..., 101-N is shown. The sub-cell arrays 101-1, 101-2,..., 101-N can be arranged along a second direction (D2) 105. Each of the sub-cell arrays, such as sub-cell array 101-2, can include a plurality of access lines 103-1, 103-2,..., 103-Q (which can also be referred to as word lines). Also, each of the sub-cell arrays, such as sub-cell array 101-2, can include a plurality of digit lines 107-1, 107-2,..., 107-P (which can also be referred to as bit lines, data lines, or read lines). In Figure 1 In the figure, the digit lines 107-1, 107-2,..., 107-P are shown as extending in a first direction (D1) 109, and the access lines 103-1, 103-2,..., 103-Q are shown as extending in a third direction (D3) 111. According to embodiments, the first direction (D1) 109 and the second direction (D2) 105 can be considered to be in a horizontal (“X-Y”) plane. The third direction (D3) 111 can be considered to be in a vertical (“Z”) plane. Thus, according to embodiments described herein, the access lines 103-1, 103-2,..., 103-Q extend in a vertical direction, such as the third direction (D3) 111.

[0023] A memory cell, such as 110, can include an access device, such as an access transistor, and a storage node located at the intersection of each access line 103-1, 103-2,..., 103-Q and each digit line 107-1, 107-2,..., 107-P. The memory cells can be written to or read from using the access lines 103-1, 103-2,..., 103-Q and the digit lines 107-1, 107-2,..., 107-P. The digit lines 107-1, 107-2,..., 107-P can conductively interconnect the memory cells along the horizontal columns of each sub-cell array 101-1, 101-2,..., 101-N, and the access lines 103-1, 103-2,..., 103-Q can conductively interconnect the memory cells along the vertical rows of each sub-cell array 101-1, 101-2,..., 101-N. One memory cell, such as 110, can be located between one access line, such as 103-2, and one digit line, such as 107-2. Each memory cell can be uniquely addressed by a combination of the access lines 103-1, 103-2,..., 103-Q and the digit lines 107-1, 107-2,..., 107-P.

[0024] The digit lines 107-1, 107-2, ..., 107-P can be or include conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. The digit lines 107-1, 107-2, ..., 107-P can extend in a first direction (D1) 109. The digit lines 107-1, 107-2, ..., 107-P in a subcell array such as 101-2 can be spaced apart from each other in a vertical direction, for example, in a third direction (D3) 111.

[0025] Access lines 103-1, 103-2, ..., 103-Q may be or include conductive patterns (e.g., metal lines) extending relative to the substrate in a vertical direction, for example, in a third direction (D3) 111. Access lines in a subcell array, such as 101-2, may be spaced apart from each other in a first direction (D1) 109.

[0026] The gate of a memory cell, such as memory cell 110, may be connected to an access line, such as 103-2, and the access means of memory cell 110, such as a first conductive node of a transistor, such as a first source / drain region, may be connected to a digit line, such as 107-2. Each memory cell in the memory cell, such as memory cell 110, may be connected to a storage node, such as a capacitor. The second conductive node of the access means of memory cell 110, such as a second source / drain region of a transistor, may be connected to a storage node, such as a capacitor. Although the references to first source / drain region and second source / drain region are used herein to refer to two separate and distinct source / drain regions, they are not intended to give any particular meaning to the source / drain regions referred to as “first” source / drain region and / or “second” source / drain region. It is only intended that one source / drain region be connected to a digit line, such as 107-2, and the other source / drain region be connected to a storage node.

[0027] Figure 2 This illustrates a three-dimensional (3D) semiconductor memory device, for example, a vertically oriented stack of memory cells in an array, according to some embodiments of the present disclosure. Figure 1 A perspective view of a portion of the subcell array 101-2 shown.

[0028] Figure 3 Showing Figure 2 The unit cell of the 3D semiconductor memory device shown is, for example... Figure 1 A perspective view of the memory cell 110 shown.

[0029] like Figure 2 As shown, a bonding can be formed on the substrate 200. Figure 1One of the plurality of sub-cell arrays, e.g., 101-2, is described. For example, the substrate 200 can be or include a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, embodiments are not limited to these examples.

[0030] As Figure 2 shown in example embodiments, the substrate 200 can have fabricated thereon vertically oriented memory cell stacks extending in a vertical direction, e.g., in a third direction (D3) 111, such as memory cells 110 in Figure 1 According to some embodiments, the vertically oriented memory cell stacks can be fabricated such that each memory cell, e.g., memory cell 110 in Figure 1 is formed on a plurality of vertical levels, e.g., a first level (LI), a second level (L2), and a third level (L3). The repeated vertical levels LI, L2, and L3 can be arranged, e.g.,“stacked,” in the vertical direction, e.g., the third direction (D3) 111 as shown. Each of the repeated vertical levels LI, L2, and L3 can include a plurality of discrete components, e.g., regions, of laterally oriented access devices 230, e.g., transistors, and storage nodes, e.g., capacitors, including access line 203-1, 203-2, …, 203-Q connections and digit line 207-1, 207-2, …, 207-P connections. Figure 1 Figure 1 The plurality of discrete components of the laterally oriented three-node access devices, e.g., transistors 110 in Figures 4A-4D are formed within each level in a plurality of iterations of vertically repeated layers, as described in greater detail below in connection with Figure 1 may extend horizontally in a second direction (D2) 205 similar to the second direction (D2) 105 shown.

[0031] ​The horizontally oriented three-node access device 230, such as a transistor, may include a first source / drain region 221 and a second source / drain region 223 extending laterally in a second direction (D2) 205, separated by a channel 225. In some embodiments, the channel 225 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise an n-type dopant region, such as semiconductor material, formed adjacent to a p-type doped channel, such as semiconductor material, of the access device to form an n-type conductive transistor. In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise a p-type conductive channel, such as doped semiconductor material, formed adjacent to an n-type conductive channel, such as doped semiconductor material, of the access device to form a p-type conductive transistor. By way of example, and not limitation, an n-type dopant may contain phosphorus (P) atoms, and a p-type dopant may contain boron (B) atoms formed in a relatively doped bulk region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0032] Storage node 227, for example, a capacitor, can be connected to a corresponding terminal of the access device. Figure 2 As shown, storage node 227, for example, a capacitor, can be connected to the second source / drain region 223 of the access device. A storage node can be or contains a memory element capable of storing data. Each storage node can be a memory element using one of the following: a capacitor, a magnetic tunnel junction pattern, and / or a variable resistive body containing a phase change material. However, the embodiments are not limited to these examples. In some embodiments, with unit cell, for example... Figure 1 The memory node associated with each access device in the memory cell 110 can be connected to the memory node in the memory cell 110. Figure 1 The second direction (D2)105 shown extends similarly to the second direction (D2)205.

[0033] like Figure 2 As shown, multiple horizontally oriented digit lines 207-1, 207-2, ..., 207-P are in relation to... Figure 1 The first direction (D1) 109 extends similarly to the first direction (D1) 209. The plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P can be connected to... Figure 1The digit lines 107-1, 107-2,..., 107-P shown are similar. The plurality of horizontally oriented digit lines 207-1, 207-2,..., 207-P can be arranged along a third direction (D3) 211, e.g.,“stacked.” The plurality of horizontally oriented digit lines 207-1, 207-2,..., 207-P can include a conductive material. For example, the conductive material can include one or more of: a doped semiconductor, e.g., doped silicon, doped germanium, etc., a conductive metal nitride, e.g., titanium nitride, tantalum nitride, etc., a metal, e.g., tungsten (W), titanium (Ti), tantalum (Ta), etc., and / or a metal-semiconductor compound, e.g., tungsten silicide, cobalt silicide, titanium silicide, etc. Embodiments are not limited, however, to these examples.

[0034] In each of the vertical levels (L1) 213-1, (L2) 213-2, and (L3) 213-M, the horizontally oriented memory cells, e.g., memory cells 110 in Figure 1 may be spaced apart horizontally from one another in the first direction (D1) 209. However, as in conjunction with Figures 4A-4D As described in greater detail below, the plurality of discrete components of the laterally oriented access devices 230, e.g., the first source / drain region 221 and the second source / drain region 223 separated by the trench 225 extending laterally in the second direction (D2) 205 and the plurality of horizontally oriented digit lines 207-1, 207-2,..., 207-P extending laterally in the first direction (D1) 209, can be formed in different vertical layers within each level. For example, the plurality of horizontally oriented digit lines 207-1, 207-2,..., 207-P extending in the first direction (D1) 209 can be disposed on and in electrical contact with a top surface of the first source / drain region 221 and orthogonal to the laterally oriented access devices 230, e.g., transistors, extending laterally in the second direction (D2) 205. In some embodiments, the plurality of horizontally oriented digit lines 207-1, 207-2,..., 207-P extending in the first direction (D1) 209 are formed in a higher vertical layer further from the substrate 200 within a level, e.g., within level (L1), as compared to the layer in which the discrete components of the laterally oriented access devices, e.g., the first source / drain region 221 and the second source / drain region 223 separated by the trench 225, are formed. In some embodiments, the plurality of horizontally oriented digit lines 207-1, 207-2,..., 207-P extending in the first direction (D1) 209 can be connected directly and / or through an additional contact including a metal silicide to the top surface of the first source / drain region 221.

[0035] As Figure 2As shown in the example embodiment of FIG. 2, access lines 203-1, 203-2,..., 203-Q extend in a vertical direction, e.g., in a third direction (D3) 211, with respect to substrate 200. Further, as shown in the example embodiment of FIG. 2, access lines 203-1, 203-2,..., 203-Q in a subcell array, e.g., subcell array 101-2, can be spaced apart from one another in a first direction (D1) 209. Access lines 203-1, 203-2,..., 203-Q can be provided that extend vertically in a third direction (D3) 211 with respect to substrate 200 between a pair of horizontally oriented three-node access devices 230, e.g., transistors, that extend laterally in a second direction (D2) 205, at a level, e.g., a first level (L1), in the first direction (D1) 209 that is adjacent to one another. Each of access lines 203-1, 203-2,..., 203-Q can extend vertically in the third direction (D3) on a sidewall of a respective one of the plurality of horizontally oriented vertically stacked three-node access devices 230, e.g., transistors. Figure 2 Figure 1 As shown in the example embodiment of FIG. 2, access lines 203-1, 203-2,..., 203-Q extend in a vertical direction, e.g., in a third direction (D3) 211, with respect to substrate 200. Further, as shown in the example embodiment of FIG. 2, access lines 203-1, 203-2,..., 203-Q in a subcell array, e.g., subcell array 101-2, can be spaced apart from one another in a first direction (D1) 209. Access lines 203-1, 203-2,..., 203-Q can be provided that extend vertically in a third direction (D3) 211 with respect to substrate 200 between a pair of horizontally oriented three-node access devices 230, e.g., transistors, that extend laterally in a second direction (D2) 205, at a level, e.g., a first level (L1), in the first direction (D1) 209 that is adjacent to one another. Each of access lines 203-1, 203-2,..., 203-Q can extend vertically in the third direction (D3) on a sidewall of a respective one of the plurality of horizontally oriented vertically stacked three-node access devices 230, e.g., transistors.

[0036] As shown in the example embodiment of FIG. 2, access lines 203-1, 203-2,..., 203-Q extend in a vertical direction, e.g., in a third direction (D3) 211, with respect to substrate 200. Further, as shown in the example embodiment of FIG. 2, access lines 203-1, 203-2,..., 203-Q in a subcell array, e.g., subcell array 101-2, can be spaced apart from one another in a first direction (D1) 209. Access lines 203-1, 203-2,..., 203-Q can be provided that extend vertically in a third direction (D3) 211 with respect to substrate 200 between a pair of horizontally oriented three-node access devices 230, e.g., transistors, that extend laterally in a second direction (D2) 205, at a level, e.g., a first level (L1), in the first direction (D1) 209 that is adjacent to one another. Each of access lines 203-1, 203-2,..., 203-Q can extend vertically in the third direction (D3) on a sidewall of a respective one of the plurality of horizontally oriented vertically stacked three-node access devices 230, e.g., transistors. Figure 3

[0037] ​​The vertically extending access lines 203-1, 203-2, ..., 203-Q may contain conductive materials, such as doped semiconductor materials, conductive metal nitrides, metals, and / or metal-semiconductor compounds. Access lines 203-1, 203-2, ..., 203-Q may correspond to... Figure 1 The word line (WL) described.

[0038] like Figure 2 As shown in the example embodiment, an insulating layer dielectric (ILD) 250 can be formed on the end surfaces of horizontally oriented three-node access devices 230, such as transistors, in each layer (L1) 213-1, (L2) 213-2, and (L3) 213-M above the substrate 200, extending in a first direction (D1) 209. The ILD 250 can support vertically stacked memory cell arrays, for example, along a second direction (D2) 205. Figure 1 The 101-1, 101-2, ..., 101-N are isolated and separated. ILD 250 may contain insulating materials, such as dielectric materials, such as oxide materials, silicon oxide (SiO2) materials, silicon nitride (SiN) materials, silicon oxynitride materials and / or combinations thereof.

[0039] although Figure 2 Not shown, but insulating material can fill other spaces in the vertically stacked memory cell array. For example, the insulating material can include one or more of the following: silicon oxide, silicon nitride, and / or silicon oxynitride, etc. However, the embodiments are not limited to these examples.

[0040] Figure 3 A vertically stacked array of memory cells according to some embodiments of the present disclosure is shown in more detail, for example... Figure 1 The unit cell within the sub-cell array 101-2, for example, Figure 1 The memory cell 110 in the example. Figure 3 As shown, the first source / drain region 321 and the second source / drain region 323 can be laterally oriented access devices 330, such as impurity-doped regions of a transistor. The first source / drain region 321 and the second source / drain region 323 can be similar to... Figure 2 The first source / drain region 221 and the second source / drain region 223 are shown. The storage node 327 can be coupled to the second source / drain region 323. The first source / drain region 321 and the second source / drain region 323 can be separated by a channel 325 formed in the body of the semiconductor material of the laterally oriented access device 230, such as a transistor, for example, a body region 326. The first source / drain region 321 and the second source / drain region 323 can be formed by n-type or p-type dopant doped in the body region 326. Embodiments are not limited thereto.

[0041] For example, in an n-type conductive transistor configuration, the laterally oriented access device 230, such as the body region 326 of the transistor, can be formed of a lightly doped (p-)p-type semiconductor material. In one embodiment, the body region 326 and the channel 325 separating the first source / drain region 321 and the second source / drain region 323 can comprise a lightly doped p-type (e.g., low dopant concentration (p-)) polysilicon material composed of boron (B) atoms as an impurity dopant for the polysilicon. In this example, the first source / drain region 321 and the second source / drain region 323 can comprise a highly doped n-type conductive impurity (e.g., a highly doped (n+)) doped in the first source / drain region 321 and the second source / drain region 323. In some embodiments, the highly doped n-type conductive first drain region 321 and the second drain region 323 can comprise a high concentration of phosphorus (P) atoms deposited therein. However, the embodiments are not limited to this example. In other embodiments, the laterally oriented access device 230, such as a transistor, may have a p-type conductivity configuration, in which case the conductivity type of impurities, such as dopants, will be reversed.

[0042] like Figure 3 As shown in the example embodiment, the first source / drain region 321 may occupy the upper portion of the body 326 of a laterally oriented access device 330, such as a transistor. For example, the first source / drain region 321 may have a bottom surface 324 within the body 326 of the laterally oriented access device 330, said bottom surface being vertically positioned higher in a third direction (D3) 311 than the bottom surface of the body 326 of the laterally oriented access device 330. Therefore, the laterally oriented transistor 330 may have a body portion 326 below the first source / drain region 321. Further, as Figure 3 As shown in the example embodiments, with Figure 2 The digit lines 207-1, 207-2, ..., 207-P in the text are... Figure 1 The digital lines 107-1, 107-2, ..., 107-P shown, and similar digital lines such as 307-1, can be disposed on the top surface 322 of the first source / drain region 321 and electrically coupled to the top surface. Digital line 307-1 can extend in the first direction (D1) 309.

[0043] like Figure 3 As shown in the example embodiments, with Figure 2 Access lines 203-1, 203-2, ..., 203-Q and Figure 1An access line 103-1, 103-2,..., 103-Q, similar to the access line 103-1, can extend vertically adjacent to a sidewall of a channel 325 portion of a body 326 of a laterally oriented access device 330, such as a transistor, in a third direction (D3) 311, the access device being horizontally conductive between a first source / drain region 321 and a second source / drain region 323 in a second direction (D2) 305. A gate dielectric material 304 can be interposed between the access line 303-1, a portion of which forms a gate of the laterally oriented access device 330, such as a transistor, and the channel 325. The gate dielectric material 304 can include, for example, a high-k dielectric material, a silicon oxide material, a silicon nitride material, a silicon oxynitride material, or the like, or combinations thereof. Embodiments are not limited in this context. For example, in a high-k dielectric material instance, the gate dielectric material 304 can include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, pyrochlore, or the like.

[0044] Figures 4A-4D is a cross-sectional view of a semiconductor manufacturing process at one stage of forming an array of vertically stacked memory cells to form a channel for a vertical 3D memory in accordance with a number of embodiments of the present disclosure.

[0045] Figure 4A is a cross-sectional view of a semiconductor manufacturing process at one stage of forming an array of vertically stacked memory cells to form a channel for a vertical 3D memory in accordance with a number of embodiments of the present disclosure. Figure 4A In an example embodiment shown in FIG. 4, the method includes depositing alternating layers of a dielectric material 430-1, 430-2, 430-3,..., 430-(N+1) (individually or collectively referred to as dielectric material 430) and a sacrificial material 432-1, 432-2, 432-3,..., 432-N (individually or collectively referred to as sacrificial material 432) in a repeating iteration to form a vertical stack 401 on a working surface of a semiconductor substrate 400. In one embodiment, the dielectric material 430 can be deposited to a thickness, for example, a vertical height in a third direction 411 (D3) in a range of twenty (20) nanometers (nm) to sixty (60) nm. In one embodiment, the sacrificial material 432 can be deposited to a vertical height in the third direction (D3) in a range of approximately twenty (20) nm to one hundred (100) nm. However, embodiments are not limited to these examples.

[0046] In one example, the sacrificial materials 432-1, 432-2, 432-3, ..., 432-N may comprise sacrificial semiconductor materials such as polycrystalline silicon (Si), silicon nitride (SiN), or even oxide-based semiconductor compositions. Although the discussion herein will refer to examples of sacrificial semiconductor materials, the embodiments are not limited to these examples. It is intended that the sacrificial materials 432-1, 432-2, 432-3, ..., 432-N may be selectively etched relative to alternating layers of dielectric materials 430-1, 430-2, 430-3, ..., 430-(N+1).

[0047] like Figure 4A As shown, vertical direction 411 is displayed as... Figures 1-3 The third direction (D3) shown in the first direction, second direction, and third direction is similar to the third direction (D3), for example, the z direction in the xyz coordinate system. In some embodiments, at least two (2) levels are formed by repeated iterations of vertical stack 401. Figure 4A In the example shown, four layers numbered 1, 2, 3, and 4 are depicted as repeated iterations of the vertical stack 401. However, the embodiments are not limited to this example and may include more or fewer repeated iterations. A photolithographic hard mask (HM) layer 435 may be deposited as the top layer on the repeated iterations of the vertical stack 401.

[0048] In some embodiments, dielectric materials 430-1, 430-2, 430-3, ..., 430-(N+1) may be interlayer dielectrics (ILDs). By way of example and not limitation, dielectric materials 430-1, 430-2, 430-3, ..., 430-(N+1) may include silicon dioxide (SiO2) material. In another example, dielectric materials 430-1, 430-2, 430-3, ..., 430-(N+1) may include silicon nitride (Si3N4) material (also referred to herein as “SiN”). In yet another example, dielectric materials 430-1, 430-2, 430-3, ..., 430-(N+1) may include silicon oxycarbide (SiO2). x C y The dielectric materials 430-1, 430-2, 430-3, ..., 430-(N+1) may comprise silicon oxynitride (SiO2). x N y) material (also referred to herein as “SiON”) and / or combinations thereof. Embodiments are not limited to these examples. In some embodiments, the sacrificial semiconductor materials 432-1, 432-2, 432-3,..., 432-N can include silicon (Si) material in a polycrystalline state and / or an amorphous state. In another example, the sacrificial semiconductor materials 432-1, 432-2, 432-3,..., 432-N can include silicon nitride (SiN) material. However, embodiments are not limited to these examples.

[0049] The repeating iterations of alternating dielectric material 430-1, 430-2, 430-3,..., 430-(N+1) layers and sacrificial semiconductor material 432-1, 432-2, 432-3,..., 432-N layers can be deposited in a semiconductor manufacturing apparatus according to a semiconductor manufacturing process such as chemical vapor deposition (CVD). However, embodiments are not limited to this example, and other suitable semiconductor manufacturing techniques can be used to deposit alternating layers of dielectric material 430-1, 430-2, 430-3,..., 430-(N+1) and sacrificial semiconductor material 432-1, 432-2, 432-3,..., 432-N in the repeating iterations to form the vertical stack 401 as shown in FIG. 4.

[0050] Figure 4B is a cross-sectional view at one stage of a semiconductor manufacturing process to form an array of memory cells of a vertical stack at multiple stages of a semiconductor manufacturing process to form a channel for a vertical three-dimensional memory according to many embodiments of the present disclosure.

[0051] According to embodiments, the semiconductor manufacturing processes described in 4B-4D can occur after the formation of the access lines and the elongated pillars extending primarily in the second direction have been performed. Figures 6A-7E According to embodiments, the methods in 4B-4D can form a channel in a semiconductor region. Figures 4A-4D

[0052] As shown in FIG. 4B, the semiconductor manufacturing process can include forming a dielectric material 430-1 in the first direction 402-1 and the second direction 402-2 over the substrate 401-1. According to embodiments, the dielectric material 430-1 can be formed by a semiconductor manufacturing process such as CVD. The dielectric material 430-1 can include a material such as silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and / or combinations thereof. Embodiments are not limited to these examples. Figure 4B ​As shown, the vertical stack 401 can be etched to form a plurality of openings 472-1, 472-2 (individually or collectively referred to as vertical openings 472) in the vertical stack 401. In some embodiments, the etching can be an anisotropic etch. As used herein, the term “anisotropic etch” can refer to an etching that occurs in one direction. The anisotropic etch can occur in a direction perpendicular to the surface of the surface being etched. In this example, the anisotropic etch can be perpendicular to the surface of the vertical stack 401. The openings can be formed through the alternating layers of dielectric material 430 and semiconductor material 432. In some embodiments, the etching can not etch through the bottom dielectric material 430-1. In some embodiments, the dielectric material 430 has been etched to a distance from the vertical openings 472 substantially equivalent to the semiconductor material 432. In some embodiments, each of the vertical openings 472 can have a width in a range of fifty (50) to five hundred (500) nanometers (nm) and a height in a range of 500 to two thousand (2,000) nm. In some embodiments, the vertical openings 472 can form an elongated vertical columnar array in the first direction (D1) with a horizontal width in a range of 50-500 nm. In some embodiments, the alternating layers of dielectric material 430 and semiconductor material 432 deposited in at least two (2) repeat iterations form the vertical stack 401 with a height in a range of two thousand (2000) to ten thousand (10,000) nm.

[0053] Figure 4C is a cross-sectional view at one stage of a semiconductor fabrication process for forming an array of memory cells of a vertical stack at a plurality of stages of a semiconductor fabrication process to form a channel for a vertical 3D memory in accordance with a number of embodiments of the present disclosure.

[0054] As Figure 4CAs shown, a subsequent etch can have been performed to undercut the dielectric material 430. As used herein, the term“undercut” can refer to an etching process that etches the vertical stack 401 from the sides of the opening 472 in the vertical stack 401 and underneath the dielectric material 430. In some embodiments, the etching that undercuts the dielectric material 430 can be an isotropic etch. As used herein, the term“isotropic etch” can refer to an etching that occurs in all directions. In an isotropic etch, the etching material can have equal etch rates for all spatial directions. The subsequent etch can selectively etch the semiconductor material 432 to a horizontal depth farther back from the dielectric material 430 than the opening 472 to form horizontal openings 417-1, 417-2, 417-3, 417-4, 417-5, 417-6, …, 417-N (individually or collectively referred to as horizontal openings 417). In some embodiments, the horizontal depth of the horizontal openings 417 can be in a range of ten (10) nanometers (nm) to forty (40) nm. In some embodiments, the semiconductor material 432 can be a passivation material, such as a yttrium-based dielectric material. For example, the semiconductor material 432 can be yttrium oxide (Y2O3).

[0055] Figure 4D is a cross-sectional view at one stage of a semiconductor fabrication process for forming an array of memory cells of a vertical stack at a plurality of stages of a semiconductor fabrication process to form a channel for a vertical 3D memory in accordance with a number of embodiments of the present disclosure.

[0056] As Figure 4DAs shown, a channel material 418-1, 418-2, 418-3, 418-4 (individually or collectively referred to as channel material 418) can be deposited into the horizontal openings 417. The channel material 418 can be a semiconductor material. For example, the channel material 418 can be an oxide semiconductor, such as zinc oxide (ZnO) and / or indium zinc oxide (InZnO). In some embodiments, the channel material can be a two-dimensional (2D) material, such as tungsten disulfide (WS2) or a metal diselenide material, such as nickel diselenide (NiSe2) or iron diselenide (FeSe2). In some embodiments, the channel material 418 can be formed of an indium gallium zinc oxide (IGZO) material. In some embodiments, the channel material 418 can be selectively deposited in the horizontal openings 417 to have a vertical width (W) in the third direction (D3) that is greater than a horizontal length (L) of the channel region in the second direction (D2). A first portion 418-1 of the channel material can be deposited in a first horizontal opening 417-1, a second portion 418-2 of the channel material can be deposited into a second horizontal opening 417-2, a third portion 418-3 of the channel material can be deposited in a third horizontal opening 417-3, a fourth portion 418-4 of the channel material can be deposited in a fourth horizontal opening 417-4, a fifth portion 418-5 of the channel material can be deposited in a fifth horizontal opening 417-5, a sixth portion 418-6 of the channel material can be deposited in a sixth horizontal opening 417-6, and an Nth channel material 418-N can be deposited in an Nth horizontal opening 417-N. In some embodiments, each portion of the channel material 418 can have a channel length in the second horizontal direction (D2) in a range of approximately twenty (20) to one hundred (100) nm. In some embodiments, the horizontal openings 417 can have a substantially uniform horizontal depth. In some embodiments, the first portion 418-1 of the channel material and the third portion 418-3 of the channel material can be in contact with a first side of the semiconductor material 432. In some embodiments, the second portion 418-2 of the channel material and the fourth portion 418-4 of the channel material can be in contact with a second side of the semiconductor material 432 opposite the first side of the semiconductor material 432. As Figure 5 As shown, subsequent processing steps can be completed to form a gate dielectric and access lines.

[0057] In some embodiments, the channel material 418 can be formed after other elements of the vertical stack 401 have been formed. For example, the channel material 418 can be deposited after capacitor cells associated with horizontal access devices have been formed in an array of memory cells of the vertical stack. In some embodiments, the vertical stack 401 is formed in situ. The channel material 418 can be formed after other elements of the vertical stack 401 to reduce an amount of time the channel material 418 can be exposed to heat in situ. Reducing the amount of time the channel material is exposed to heat in situ can reduce a likelihood of damage to the channel material. For example,Figure 5 The term“channel” as used herein can refer to a combination of the channel material 418 and the semiconductor material 432 in contact with the channel material 418. As shown, different portions of the channel material 418 can be in contact with opposite sides of the semiconductor material 432. The term“thermal budget” as used herein can refer to the total amount of thermal energy transferred to the vertical stack 401 during an elevated thermal process that occurs in situ. A low thermal budget can provide various benefits to the channel, such as reducing any dopant redistribution in the channel. Figure 4D

[0058] As described above, the semiconductor material 432 can be a passivation material. In some embodiments, selectively depositing the channel material 418 with the passivation material 432 can act as a reverse channel passivation material and reduce the threshold voltage (V th ) of the channel 425. The term“threshold voltage” as used herein can refer to the amount of voltage required to create a conductive path between the source / drain regions of a transistor. Reducing the V th The channel 425 can be formed to operate with a threshold voltage of less than 0.4 volts (V). Further, the semiconductor material 432 in the channel can reduce the V th over time.

[0059] Figure 5 is a three-dimensional (3D) perspective view of a memory device 516 including a plurality of channels 525 for vertical 3D memory in accordance with a number of embodiments of the present disclosure. The memory device 516 can include channels 525-1, 525-2, 525-3, …, 525-N (individually or collectively referred to as channels 525). The channels 525 can include channel materials 518-1, 518-2, 518-3, 518-4, 518-5, 518-6, …, 518-N (individually or collectively referred to as channel materials 518) and semiconductor materials 532-1, 532-2, 532-3, …, 532-N (individually or collectively referred to as semiconductor materials 532). Each of the plurality of channels 525 can be stacked on one another in a vertical orientation separated by dielectric materials 530-1, 530-2, 530-3, 530-4, …, 530-N (individually or collectively referred to as dielectric materials 530).

[0060] In some embodiments, the plurality of channels 525 can be formed in a vertical stack 401 (e.g., in conjunction with the vertical stack 401 of FIG. 1). In some embodiments, the plurality of channels 525 can be formed in a vertical stack 401 (e.g., in conjunction with the vertical stack 401 of FIG. 1). Figure 4B ​The gate dielectric material 504 is deposited in the openings 472-1, 472-2 described. In some embodiments, the gate dielectric material 504 can be formed of an oxide material such as one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, pyrochlore, etc. The gate dielectric material 504 can be deposited on the sidewalls of the stack of memory devices 516. Further, the access line material 522 can be deposited on the sidewalls of the gate dielectric material 504.

[0061] Figure 6A An example method for forming an array of vertically stacked memory cells with horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor manufacturing process is shown as Figures 1-3 An example method for forming an array of vertically stacked memory cells with horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor manufacturing process is shown as Figure 6A A top-down view of a semiconductor structure at a particular point in time in a semiconductor manufacturing process is shown according to one or more embodiments. In Figure 6A In the example embodiment shown in the example of FIG. 6, the method includes forming a plurality of first vertical openings 615 with a first horizontal direction (D1) 609 and a second horizontal direction (D2) 605 through the vertical stack to the substrate using an etching process. In one example, as shown in Figure 6A The plurality of first vertical openings 615 can extend primarily in the second horizontal direction (D2) 605 and can form elongated vertical columns 613 with sidewalls 614 in the vertical stack. The plurality of first vertical openings 615 can be formed by patterning a lithography mask 635 using a lithography technique, for example, to form a hard mask (HM) on the vertical stack prior to etching the plurality of first vertical openings 615. In some embodiments, the hard mask can be selective to semiconductor materials (e.g., the semiconductor material 432 described in connection with Figures 4A-4D and dielectric materials (e.g., the dielectric material 430 described in connection with Figures 4A-4D and dielectric materials (e.g., the dielectric material 430 described in connection with

[0062] Figure 6B A top-down view of a semiconductor structure at a particular point in time in a semiconductor manufacturing process is shown according to one or more embodiments. In Figure 6BIn the example embodiment shown in FIG. 6A, the method includes filling the openings 615 with a dielectric material 629. By way of example and not limitation, the dielectric material 629 can be deposited in the plurality of vertical openings 615 using a chemical vapor deposition (CVD) process, a plasma-enhanced CVD (PECVD), an atomic layer deposition (ALD), or other suitable deposition process to fill the plurality of first vertical openings 615. The dielectric material 629 can have a first horizontal direction (D1) 609 and a second horizontal direction (D2) 605 adjacent to the vertical columns of pillars 613 having sidewalls 614 in the vertical stack.

[0063] Figure 6C A top-down view of a semiconductor structure at a particular point in time in a semiconductor manufacturing process is shown in accordance with one or more embodiments. In Figure 6C In the example embodiment shown in FIG. 6A, the method includes filling the openings 615 with a dielectric material 629. By way of example and not limitation, the dielectric material 629 can be deposited in the plurality of vertical openings 615 using a chemical vapor deposition (CVD) process, a plasma-enhanced CVD (PECVD), an atomic layer deposition (ALD), or other suitable deposition process to fill the plurality of first vertical openings 615. The dielectric material 629 can have a first horizontal direction (D1) 609 and a second horizontal direction (D2) 605 adjacent to the vertical columns of pillars 613 having sidewalls 614 in the vertical stack.

[0064] Figure 6D is a cross-sectional view taken along the cut line A-A' in Figure 6C A top-down view of a semiconductor structure at a particular point in time in a semiconductor manufacturing process is shown in accordance with one or more embodiments. In Figure 6D By way of example and not limitation, the gate dielectric material 638 can be conformally deposited in the plurality of vertical openings 672 using a chemical vapor deposition (CVD) process, a plasma-enhanced CVD (PECVD), an atomic layer deposition (ALD), or other suitable deposition process to cover the bottom surfaces and vertical sidewalls of the plurality of vertical openings 672. The gate dielectric material 638 can be deposited to a particular thickness (ti) suitable for a particular design rule, such as a gate dielectric thickness of approximately 10 nanometers (nm). However, embodiments are not limited to this example. The gate dielectric material 638 can separate the conductive material 640 from the repeating iterations of the dielectric material 630-1, 630-2, 630-3,..., 630-N and 630-(N+1) and the semiconductor material 632-1, 632-2, 632-3,..., 632-N in the vertical columns 642. By way of example and not limitation, the gate dielectric material 638 can include a silicon dioxide (Si02) material, an aluminum oxide (AI2O3) material, a high dielectric constant (k), such as a high-k dielectric material, and / or combinations thereof, as also described in FIG. 6B. Figure 3 By way of example and not limitation, the gate dielectric material 638 can include a silicon dioxide (Si02) material, an aluminum oxide (AI2O3) material, a high dielectric constant (k), such as a high-k dielectric material, and / or combinations thereof, as also described in FIG. 6B.

[0065] Furthermore, such as Figure 6D As shown, conductive materials 640-1, 640-2, ..., 640-4 can be conformally deposited on the surface of the gate dielectric material 638 within a plurality of vertical openings 672. By way of example and not limitation, conductive materials 640-1, 640-2, ..., 640-4 can be conformally deposited on the surface of the gate dielectric material 638 within a plurality of vertical openings 672 using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of vertical openings 672 over the gate dielectric material 638. Conductive materials 640-1, 640-2, ..., 640-4 can be conformally deposited to a specific thickness (t2) to form vertically oriented access lines, as shown. Figure 1 And the access lines 103-1, 103-2, ..., 103-Q (which may also be referred to as word lines) shown below, etc., and as appropriate for a particular design rule. For example, conductive materials 640-1, 640-2, ..., 640-4 can be conformally deposited to a thickness of approximately 20 nanometers (nm). However, the embodiments are not limited to this example. By way of example and not limitation, conductive materials 640-1, 640-2, ..., 640-4 may include metals such as tungsten (W), metal compositions, titanium nitride (TiN), doped polycrystalline silicon, and / or similar materials. Figure 3 Some other combination as described in [the text].

[0066] like Figure 6D As shown, conductive materials 640-1, 640-2, ..., 640-4 can be recessed backward to... Figure 6D In the cross-sectional view, the vertical sidewalls are maintained only along the slender, vertical columnar columns now shown as 642-1, 642-2, and 642-3. The conductive material 640-1, 640-2, ..., 640-4 can be recessed rearward by using a suitable selective anisotropic etching process from the vertical opening, for example... Figure 6C Conductive materials 640-1, 640-2, ..., 640-4 are removed from the bottom surface of 672, thereby exposing the gate dielectric material 638 on the bottom surface to form individual conductive materials 640-1, 640-2, ..., 640-4. For example... Figure 6DAs shown, dielectric material 639, such as oxide or other suitable spin-on dielectric (SOD), can then be deposited in the vertical opening 672 using a process such as CVD to fill the vertical opening 672. The dielectric can be planarized to the top surface of a hard mask 635, such as 401 as shown in FIG. 4, using chemical mechanical polishing (CMP) or other suitable semiconductor manufacturing techniques. Subsequently, photolithography material 636, such as the hard mask, can be deposited using CVD and planarized using CMP to cover and close the vertical opening 672 over conductive materials 640-1, 640-2, ..., 640-4. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0067] Figure 7A Demonstrated as Figures 1-3 The example method shown in the document and according to many embodiments of the present disclosure is for forming an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines at another stage of the semiconductor manufacturing process. Figures 6A-6D Compared to the embodiments shown, Figures 7A-7E The embodiments shown illustrate different methods for forming an array of vertically stacked memory cells with horizontally oriented access devices and vertically oriented access lines. Figure 7A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process, according to one or more embodiments, is shown. Figure 7A In an example embodiment, the method includes using a photolithography process to pattern photomasks (hard masks) 735 and 736 and Figure 7B The photolithography mask (hard mask) in the middle is 737. Figure 7A The method further demonstrates the use of selective isotropic etching processes to remove exposed conductive materials 740-1, 740-2, ..., 740-N, 740-(N+1), ..., 740-(Z-1) and 740-Z( Figure 7B In the 740), multiple separate vertical access lines 740-1, 740-2, ..., 740-N, 740-(N+1), ..., 740-(Z-1) and 740-Z are formed independently, for example. Figure 1 And access lines 103-1, 103-2, ..., 103-Q in the following series. Thus, multiple individual vertical access lines 740-1, 740-2, ..., 740-N, 740-(N+1), ..., 740-(Z-1) and 740-Z are shown along the sidewalls of the elongated vertical columns 742-1, 742-2, ..., 742-N.

[0068] like Figure 7Aexposed conductive material 740-1, 740-2,..., 740-N, 740-(N+1),..., 740-(Z-1), and 740-Z can be removed back to the gate dielectric material 738 in 615 in FIG. 4 using a suitable selective isotropic etch process, for example Figure 6A Figure 7A As shown, a subsequent dielectric material 741 such as an oxide or other suitable spin-on dielectric (SOD) can be subsequently deposited to fill the remaining openings from which the exposed conductive material 740-1, 740-2,..., 740-N, 740-(N+1),..., 740-(Z-1), and 740-Z are removed using a process such as CVD or other suitable technique. The dielectric material 741 can be planarized to the top surface of the previous hardmask 635 in 615 as shown in FIG. 4 using a process such as CMP or other suitable technique. In some embodiments, the subsequent photoresist material 737 such as a hardmask can be deposited using CVD and planarized using CMP to cover and enclose the plurality of individual vertical access lines 740-1, 740-2,..., 740-N, 740-(N+1),..., 740-(Z-1), and 740-Z over the working surface of the vertical semiconductor stack 401 in FIG. 4, thereby protecting the plurality of individual vertical access lines 740-1, 740-2,..., 740-N, 740-(N+1),..., 740-(Z-1), and 740-Z along the sidewalls of the elongated vertical columnar columns 742-1, 742-2,..., 742-N. Embodiments are not limited to these process examples, however. Figure 6D

[0069] A cross-sectional view taken along the cut line A-A' in FIG. 4 is shown, which illustrates another view of the semiconductor structure at this particular point in one example semiconductor fabrication process of embodiments of the present disclosure. Figure 7B The cross-sectional view shown is distanced from the plurality of individual vertical access lines 740-1, 740-2,..., 740-N, 740-(N+1),..., 740-(Z-1), and illustrates the repeating iterations of the alternating layers of dielectric material 730-1, 730-2, 730-3,..., 730-(N+1) and sacrificial semiconductor material 732-1, 732-2, 732-3,..., 732-N on the semiconductor substrate 700 to form a vertical stack such as 401 shown in FIG. 4. As shown, the vertical direction 711 is shown as being perpendicular to the horizontal direction 712. Figure 7A Figure 7B Figure 7B Figures 1-3 ​​​​The third direction (D3) 111 shown in the first direction, second direction, and third direction is similar to the third direction (D3), for example, the z direction in the xyz coordinate system. The drawing plane extending to the right and left is on the first direction (D1) 709. Figure 7B In the example embodiment, dielectric material 741 is shown as filling a vertical opening in the deposition of residual gate material dielectric 738. The hard mask 737 described above is deposited on top of hard mask 735 and covers the structure shown.

[0070] Figure 7C Showing along Figure 7A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 7C The cross-sectional view shown is presented as an axis of repeated iterations along alternating layers of dielectric materials 730-1, 730-2, 730-3, ..., 730-(N+1) and sacrificial semiconductor materials 732-1, 732-2, 732-3, ..., 732-N extending in a second direction (D2) 705, along said alternating layers, and within said alternating layers, horizontally oriented access devices and horizontally oriented storage nodes, such as capacitor cells, can be formed within the layers of sacrificial semiconductor materials 732-1, 732-2, 732-3, ..., 732-N. Figure 7C In the drawing, adjacent vertical access lines 740-3 are shown by dashed lines indicating their positions from the plane of the drawing and towards the inward orientation. A hard mask 735 has been deposited on repeated iterations of alternating layers of dielectric materials 730-1, 730-2, 730-3, ..., 730-(N+1) and sacrificial semiconductor materials 732-1, 732-2, 732-3, ..., 732-N.

[0071] Figure 7D Showing along Figure 7A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 7D The cross-sectional view shown is presented as follows: the axis of repeated iterations along alternating layers of dielectric materials 730-1, 730-2, 730-3, ..., 730-(N+1) and sacrificial semiconductor materials 732-1, 732-2, 732-3, ..., 732-N extends in a second direction (D2) 705 outside a certain region, in which horizontally oriented access devices and horizontally oriented memory nodes, such as capacitor cells, will be formed within the layers of sacrificial semiconductor materials 732-1, 732-2, 732-3, ..., 732-N. Figure 7DIn some embodiments, dielectric material 741 is shown filling the space between horizontally oriented access devices and horizontally oriented storage nodes of a vertically oriented array of memory cells, which can be spaced apart along a second direction (D2) 705, extending into and out of the plane of the drawing sheet. A repeating iteration of alternating layers of dielectric material 730-1, 730-2, 730-3,..., 730-(N+1) and sacrificial semiconductor material 732-1, 732-2, 732-3,..., 732-N is shown at the left end of the drawing sheet, at which location horizontally oriented digit lines, such as digit line 107-1, 107-2,..., 107-P, shown in FIG. 1, can be integrated to make electrical contact with second source / drain regions, described in more detail below. Figure 1 and digit line 107-1, 107-2,..., 107-P, shown in FIG. 1, can be integrated to make electrical contact with second source / drain regions, described in more detail below.

[0072] Figure 7E A cross-sectional view taken along cut line D-D' in Figure 7A is shown, which shows another view of the semiconductor structure at this particular point in one example semiconductor fabrication process of embodiments of the present disclosure. A repeating iteration of alternating layers of dielectric material 730-1, 730-2, 730-3,..., 730-(N+1) and sacrificial semiconductor material 732-1, 732-2, 732-3,..., 732-N is shown extending in the plane of the drawing sheet from right to left Figure 7E is shown, which shows another view of the semiconductor structure at this particular point in one example semiconductor fabrication process of embodiments of the present disclosure. A repeating iteration of alternating layers of dielectric material 730-1, 730-2, 730-3,..., 730-(N+1) and sacrificial semiconductor material 732-1, 732-2, 732-3,..., 732-N is shown extending in the plane of the drawing sheet from right to left Figure 7E In some embodiments, first dielectric fill material 739 is shown separating the space between adjacent horizontally oriented access devices and horizontally oriented storage nodes, which can be formed extending into and out of the plane of the drawing sheet, as described in more detail below, and can be spaced apart along a first direction (D1) 709 and vertically stacked into an array extending in a third direction (D3) 711 in three-dimensional (3D) memory.

[0073] Figure 8A is shown, which shows another view of the semiconductor structure at this particular point in one example semiconductor fabrication process of embodiments of the present disclosure. A repeating iteration of alternating layers of dielectric material 730-1, 730-2, 730-3,..., 730-(N+1) and sacrificial semiconductor material 732-1, 732-2, 732-3,..., 732-N is shown extending in the plane of the drawing sheet from right to left Figures 1-3The example method shown in the document and according to many embodiments of the present disclosure is used at another stage of the semiconductor manufacturing process to form an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines. Figure 8A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process, according to one or more embodiments, is shown. Figure 8A In an example embodiment, the method includes using a photolithography process to pattern photomasks 835, 836 and / or 837, as described in Figures 6 and 7. Figure 8A The method further demonstrates the use of one or more etching processes through vertically stacked areas in the access device region, for example... Figure 8C Vertical openings 871-1 and 871-2 are formed in the alternative channel and source / drain transistor regions 843. The vertical openings 871-1 and 871-2 are shown to extend primarily in the first horizontal direction (D1) 809. The one or more etching processes form the vertical openings 871-1 and 871-2 adjacent to the first region of the sacrificial semiconductor material. Figures 8B-8E The vertical stack shown exposes the third sidewall in repeated iterations of alternating layers of dielectric material 830-1, 830-2, 830-3, ..., 830-(N+1) and sacrificial semiconductor material 832-1, 832-2, ..., 832-N. Figure 8A The method further demonstrates the use of selective isotropic etching processes to remove exposed conductive material 840-1, 840-2, ..., 840-N, 840-(N+1), ..., 840-(Z-1) and 840-Z to isolate and independently form multiple individual vertical access lines 840-1, 840-2, ..., 840-N, 840-(N+1), ..., 840-(Z-1) and 840-Z, for example... Figure 1 And access lines 103-1, 103-2, ..., 103-Q, etc. Thus, multiple individual vertical access lines 840-1, 840-2, ..., 840-N, 840-(N+1), ..., 840-(Z-1) and 840-Z are shown along the sidewalls of the elongated vertical column 842. Other numbered components may be similar to those shown and discussed in conjunction with Figures 6 and 7.

[0074] According to an embodiment, in a vertical stack, the access device regions of the sacrificial semiconductor materials 832-1, 832-2, 832-3, ..., 832-N are... Figure 8A and 8CThe transistor regions can be removed from repeating iterations of the dielectric materials 830-1, 830-2, 830-3,..., 830-(N+1) and the sacrificial semiconductor materials 832-1, 832-2, 832-3,..., 832-N to form access devices, e.g., transistors, in the memory node region 850 in which the capacitor cells are formed. In some embodiments, this process is performed prior to selectively removing the semiconductor materials in the memory node region 850 in which the capacitor cells are formed of the sacrificial semiconductor materials. In other embodiments, this process is performed after selectively removing the memory node region 850 in which the capacitor cells are formed of the sacrificial semiconductor materials. According to Figures 8B-8E According to the example embodiments shown in FIG. 8, the method includes selectively etching the access device region 843 of the sacrificial semiconductor materials 832-1, 832-2, 832-3,..., 832-N to form a first horizontal opening at a first horizontal distance rearward from the vertical openings 871-1 and 871-2 in the vertical stack. In some embodiments, the method includes forming a transistor having a first source / drain region, a channel region, and a second source / drain region in the first horizontal opening as the access device. By way of example, and not limitation, forming the first source / drain region, the channel region, and the second source / drain region includes sequentially depositing the first source / drain region, the channel region, and the second source / drain region in the first horizontal opening using an atomic layer deposition (ALD) process. Other suitable semiconductor fabrication techniques and / or memory node structures can be used.

[0075] Figure 8B A cross-sectional view taken along the cut line A-A' in FIG. 8 is shown, which illustrates another view of the semiconductor structure at this particular point in one example semiconductor fabrication process of embodiments of the present disclosure. Figure 8A A cross-sectional view taken along the cut line A-A' in FIG. 8 is shown, which illustrates another view of the semiconductor structure at this particular point in one example semiconductor fabrication process of embodiments of the present disclosure. Figure 8B The cross-sectional view shown is distanced from the plurality of individual vertical access lines 840-1, 840-2,..., 840-N, 840-(N+1),..., 840-(Z-1), and illustrates repeating iterations of alternating layers of the dielectric materials 830-1, 830-2, 830-3,..., 830-(N+1) and the semiconductor materials 832-1, 832-2, 832-3,..., 832-N separated by openings 851 on the semiconductor substrate 800 to form the elongated vertical columns 842-1, 842-2, 842-3 in the vertical stack. The hard mask 835 has been deposited over the elongated vertical columns 843-1, 843-2, 843-3. As shown in FIG. 8, the vertical direction 811 is shown as being perpendicular to the horizontal direction 812. Figure 8B The cross-sectional view shown is distanced from the plurality of individual vertical access lines 840-1, 840-2,..., 840-N, 840-(N+1),..., 840-(Z-1), and illustrates repeating iterations of alternating layers of the dielectric materials 830-1, 830-2, 830-3,..., 830-(N+1) and the semiconductor materials 832-1, 832-2, 832-3,..., 832-N separated by openings 851 on the semiconductor substrate 800 to form the elongated vertical columns 842-1, 842-2, 842-3 in the vertical stack. The hard mask 835 has been deposited over the elongated vertical columns 843-1, 843-2, 843-3. As shown in FIG. 8, the vertical direction 811 is shown as being perpendicular to the horizontal direction 812. Figures 1-3The third direction (D3) 111 shown in the first direction, second direction, and third direction is similar to the third direction (D3), for example, the z direction in the xyz coordinate system. The drawing plane extending to the right and left is on the first direction (D1) 809. Figure 8B In the example embodiment, the materials within the vertical stack—dielectric materials 830-1, 830-2, 830-3, ..., 830-(N+1) and semiconductor materials 832-1, 832-2, 832-3, ..., 832-N—are shown as extending in the second direction (D2) and along the orientation axis of the array of vertically stacked memory cells of the three-dimensional (3D) memory into and out of the plane of the drawing.

[0076] Figure 8C Showing along Figure 8A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 8C The cross-sectional view shown is presented as an axis of repeated iterations along the plane of the drawing from left to right in a second direction (D2) 805, along alternating layers of dielectric materials 830-1, 830-2, 830-3, ..., 830-(N+1) and semiconductor materials 832-1, 832-2, 832-3, ..., 832-N. In these alternating layers, horizontally oriented access devices and horizontally oriented storage nodes, such as capacitor cells, can be formed within the layers of semiconductor materials 832-1, 832-2, 832-3, ..., 832-N. Figure 8C In an example embodiment, an opening 851 is shown, in which horizontally oriented memory nodes, such as capacitor cells, can be formed later in this semiconductor manufacturing process.

[0077] exist Figure 8C In an example embodiment, a combination of Figure 8A The vertical opening 851 and the horizontal opening 879 are formed by the described masking, patterning, and etching processes. (As...) Figure 8C As shown, semiconductor materials 832-1, 832-2, 832-3, ..., 832-N in the second region 844 have been selectively removed to form a horizontal opening 879. In one example, an atomic layer etching (ALE) process is used to selectively etch semiconductor materials 832-1, 832-2, 832-3, ..., 832-N and remove a second distance (D2 opening) backward from the vertical opening 851. Figures 9A-9E As shown, it can be relative to Figures 4A-4D The manufacturing process shown may later or first form horizontally oriented storage nodes, such as capacitor cells, in the horizontal opening 879.

[0078] According to an example embodiment, such as Figure 8C As shown, first source / drain regions 897-1A, 897-1B, 897-1C, ..., 897-1N (each individually or collectively referred to as first source / drain region 897-1) can be formed by allowing source / drain material to flow from the vertical opening 851 into the horizontal opening 879 at its distal end. In some embodiments, the source / drain region material can be an n-type doped semiconductor material or a p-type doped semiconductor material. By way of example, and not limitation, the n-type dopant can contain phosphorus (P) atoms and the p-type dopant can contain boron (B) atoms. In some embodiments, the source / drain material can be a conductive material. By way of example, and not limitation, the conductive material can be a metallic material, such as ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), and tin (Sn). However, the embodiments are not limited thereto, and other suitable semiconductor manufacturing techniques can be utilized.

[0079] like Figure 9C As further shown, the first electrode for the horizontally oriented storage node, such as 961, should be coupled to the first source / drain region 897-1 of the horizontal access device. Figure 9C As shown later, such a horizontally oriented storage node is illustrated in a horizontal opening 879, which, in the plane of the drawing, runs from left to right in a second direction (D2), in contrast to vertically stacked nodes, for example... Figure 4A The vertical opening 851 formed in 401 is spaced at a second distance (D2 opening) and extends along the oriented axis of the horizontal access device and horizontal storage node in the vertically stacked array of memory cells of the three-dimensional (3D) memory. Figure 8C In the drawing, adjacent relative vertical access lines 840-3 are shown by dashed lines indicating the position set inward from the plane of the drawing and towards the center.

[0080] Figure 8D Showing along Figure 8A The cross-sectional view taken by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 8D The cross-sectional view shown is presented as an axis of repeated iterations along alternating layers of dielectric materials 830-1, 830-2, 830-3, ..., 830-(N+1) and semiconductor materials 832-1, 832-2, 832-3, ..., 832-N, extending from left to right in a second direction (D2) 805 outside a certain region in the plane of the drawing. In this region, horizontally oriented access devices and horizontally oriented storage nodes, such as capacitor cells, will be formed within the layers of semiconductor materials 832-1, 832-2, 832-3, ..., 832-N.Figure 8D In the drawing, dielectric material 841 is shown as the space between horizontally oriented access devices and horizontally oriented memory nodes filling a three-dimensional array of vertically oriented memory cells. These horizontally oriented access devices and memory nodes can be separated along a third direction 811 (D3), extending into and out of the plane of the drawing. The left end of the drawing shows a repeated iteration of alternating layers of dielectric materials 830-1, 830-2, 830-3, ..., 830-(N+1) and semiconductor materials 832-1, 832-2, 832-3, ..., 832-N, at which point the horizontally oriented digital lines, for example... Figure 1 The digital lines 107-1, 107-2, ..., 107-P shown below can be integrated to form an electrical contact with the first source / drain region.

[0081] Furthermore, while the references to "first source / drain region" and "second source / drain region" are used herein to refer to two separate and distinct source / drain regions, they are not intended to imbue the source / drain regions referred to as "first" and / or "second" with any particular meaning. The purpose is merely to connect one source / drain region to a bit line such as 107-2, and the other source / drain region to a memory node.

[0082] Figure 8E Showing along Figure 8A The cross-sectional view taken by the cutting line D-D' in the drawing shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. It is shown from right to left in the plane of the drawing. Figure 8E The cross-sectional view shown extends along a repeating axis of alternating layers of dielectric materials 830-1, 830-2, 830-3, ..., 830-(N+1) and semiconductor materials 832-1, 832-2, 832-3, ..., 832-N in a first direction (D1) 809. In these alternating layers, channel regions separated by gate dielectric material 838 and multiple individual vertical access lines 840-1, 840-2, ..., 840-4 are formed in horizontal openings. Figure 8E In the diagram, a first dielectric filler material 839 is shown separating the space between adjacent horizontally oriented access devices and horizontally oriented memory nodes, which may be formed, as described in more detail below, to extend into and out of the plane of the drawing, and may be spaced along a first direction (D1) 809 and vertically stacked to form an array extending in a third direction (D3) 811 in a three-dimensional (3D) memory. A hard mask 836 may cover the structure.

[0083] Figure 9A An example method for forming an array of vertically stacked memory cells with horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor manufacturing process is shown as Figures 1-3 An example method for forming an array of vertically stacked memory cells with horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor manufacturing process is shown as Figure 9A A top-down view of a semiconductor structure at a particular point in time in a semiconductor manufacturing process is shown according to one or more embodiments. In Figure 9A In example embodiments in FIGS. 6-8, the method includes patterning photoresist masks 935, 936, and / or 937, etc. using a lithography process, as described. Figure 9A The method in FIG. 6 further shows forming vertical openings 971-1 and 971-2 through the vertically stacked access device regions, e.g., 843 and 943, using one or more etching processes. Figure 8C The method in FIG. 6 further shows forming vertical openings 971-1 and 971-2 through the vertically stacked access device regions, e.g., 843 and 943, using one or more etching processes. Figure 9C The method in FIG. 6 further shows forming vertical openings 971-1 and 971-2 through the vertically stacked access device regions, e.g., 843 and 943, using one or more etching processes. Figures 9B-9E The method in FIG. 6 further shows forming vertical openings 971-1 and 971-2 through the vertically stacked access device regions, e.g., 843 and 943, using one or more etching processes. Figure 9A As shown, access lines 940-1, 940-2, …, 940-N, 940-(N+1), …, 940-Z and gate dielectric material 938 can be formed. Other numbered components can be similar to those shown and discussed in connection with FIGS. 6-8.

[0084] According to embodiments, in the vertically stacked access device regions (843 and 943), the sacrificial semiconductor material 932-1, 932-2, 932-3, …, 932-N is removed. Figure 9CFor example, transistor regions (943) can be removed through repeated iterations of alternating layers of dielectric materials 930-1, 930-2, 930-3, ..., 930-(N+1) and sacrificial semiconductor materials 932-1, 932-2, 932-3, ..., 932-N to form access devices, such as transistors. In some embodiments, this process is performed before selectively removing the sacrificial material from the storage node regions 950 where capacitor cells are formed of the sacrificial semiconductor materials 932-1, 932-2, 932-3, ..., 932-N. In other embodiments, this process is performed after selectively removing the sacrificial material from the storage node regions where capacitor cells are formed of the sacrificial semiconductor materials 932-1, 932-2, 932-3, ..., 932-N.

[0085] according to Figures 9B-9E The example embodiment shown includes selectively etching access device regions 943 of sacrificial semiconductor materials 932-1, 932-2, 932-3, ..., 932-N to form a first horizontal opening in a vertical stack at a first horizontal distance rearward from vertical openings 971-1 and 971-2. In some embodiments, such as Figures 9B-9E As shown, the method includes forming a transistor having a first source / drain region, a channel region, and a second source / drain region in a first horizontal opening as an access device. By way of example, and not limitation, forming the first source / drain region, the channel region, and the second source / drain region includes sequentially depositing the first source / drain region, the channel region, and the second source / drain region in the first horizontal opening using an atomic layer deposition (ALD) process. Other suitable semiconductor manufacturing techniques and / or memory node structures can be used. In some embodiments, it can be as follows Figures 4A-4D The formation of channel regions as described in the text (e.g., such as...) Figure 5 The channel shown is 525.

[0086] Figure 9B Showing along Figure 9A The cross-sectional view taken by the cutting line A-A' shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 9BThe illustrated cross-sectional view is away from the plurality of individual vertical access lines 940-1, 940-2,..., 940-N, 940-(N+1),..., 940-(Z-1) and shows a repeating iteration of alternating layers of dielectric material 930-1, 930-2, 930-3,..., 930-(N+1) separated on the semiconductor substrate 900 by capacitor cells to form vertical stacks 942-1, 942-2, 942-3 having a first electrode 961, e.g., a bottom cell contact electrode, a cell dielectric 963, and a second electrode 956, e.g., a top common node electrode. A hard mask 935 can be deposited over the vertical stacks 942-1, 942-2, 942-3. As Figure 9B The illustrated third direction 911 (D3) is similar to the third direction (D3) 111 in the first, second, and third directions shown in Figures 1-3 the drawing sheet plane extending to the right and to the left is in the first direction (D1) 909. The drawing sheet plane extending up and down is in the second direction (D2) 905. Figure 9B In example embodiments of the disclosure, the first electrode 961, e.g., a bottom electrode, and the second electrode 956 to be coupled to a source / drain region of a horizontal access device are shown separated by a cell dielectric material 963 extending into and out of the plane of the drawing sheet and along an axis of orientation of the horizontal access device and horizontal storage node in an array of memory cells of a vertical stack of a three-dimensional (3D) memory.

[0087] Figure 9C A cross-sectional view taken along the cut line B-B' in Figure 9A the drawing sheet plane extending to the right and to the left is in the first direction (D1) 909. The drawing sheet plane extending up and down is in the second direction (D2) 905. Figure 9C The illustrated cross-sectional view is shown extending from left to right in the plane of the drawing sheet in the second direction (D2) 905 along an axis of the repeating iteration of alternating layers of dielectric material 930-1, 930-2, 930-3,..., 930-(N+1). However, now shown is that a portion of the sacrificial semiconductor material has been removed in the access device region 943 of the alternating layers of the vertical stack to form horizontal openings 933-1, 933-2, 932-3,..., 933-N in which horizontal oriented access devices having a first source / drain region, e.g., first source / drain regions 997-1A, 997-1B, 997-1C,..., 997-1N (individually or collectively referred to as first source / drain regions 997-1), a channel region, and a second source / drain region can be formed between the vertically alternating layers of dielectric material 930-1, 930-2, 930-3,..., 930-(N+1).Figure 9C In example embodiments of the present disclosure, horizontally oriented storage nodes, such as capacitor cells, are shown as having been formed in the storage node region 944 in this semiconductor fabrication process, and a first electrode 961, such as a bottom electrode, to be coupled to a first source / drain region 997-1 of a horizontal access device, and a second electrode 956, such as a top electrode, to be coupled to a common electrode plane, such as a ground plane, separated by a cell dielectric 963 are shown. However, embodiments are not limited to this example. In other embodiments, the first electrode 961, such as a bottom electrode, to be coupled to a source / drain region of a horizontal access device, and the second electrode 956, such as a top electrode, to be coupled to a common electrode plane, such as a ground plane, separated by a cell dielectric 963 can be formed after the first source / drain region, channel region, and second source / drain region are formed in the regions of the sacrificial semiconductor material 932-1, 932-2, 932-3,..., 932-N.

[0088] In Figure 9C In example embodiments of the present disclosure, the horizontal openings 930-1, 930-2, 930-3,..., 930-N in which the horizontal access devices with first source / drain regions 997-1, channel regions, and second source / drain regions are formed are shown as extending in the second direction 905 (D2) from left to right in the plane of the drawing from a distance from the vertical openings 971-1 and 971-2 formed in the vertical stack and along the axis of orientation of the horizontal access devices and horizontal storage nodes in the array of memory cells of the vertical stack of the three-dimensional (3D) memory in Figure 9C In

[0089] Figure 9D A cross-sectional view taken along the cut line C-C' in Figure 9A is shown, which shows another view of the semiconductor structure at this particular point in one example semiconductor fabrication process of embodiments of the present disclosure. Figure 9D The cross-sectional view shown is shown as extending in the second direction (D2) 905 from left to right in the plane of the drawing along the axis of the repeating iteration of the alternating layers of dielectric material 930-1, 930-2, 930-3,..., 930-N, 930-(N+1) and horizontal openings 933-1, 933-2, 933-3,..., 933-N outside of a region in which the horizontally oriented access devices and horizontally oriented storage nodes, such as capacitor cells, are to be formed. In Figure 9DIn the drawing, dielectric material 941 is shown filling the space between horizontally oriented access devices, which can be spaced along a first direction (D1) to extend into and out of the plane of a three-dimensional array of vertically oriented memory cells. However, in Figure 9D In the cross-sectional view, the second electrode 956 of the capacitor cell structure, such as the top common electrode, is also shown existing in the space between horizontally adjacent devices. The left end of the drawing shows a repeating iteration of alternating layers of dielectric materials 930-1, 930-2, 930-3, ..., 930-(N+1) and horizontal openings 933-1, 933-2, 933-3, ..., 933-N, at which point horizontally oriented digital lines, for example... Figure 1 The digital lines 107-1, 107-2, ..., 107-P shown below can be integrated to form an electrical contact with the second source / drain region of the formed horizontal access device.

[0090] Figure 9E Showing along Figure 9A The cross-sectional view taken by the cutting line D-D' in the drawing shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. It is shown from right to left in the plane of the drawing. Figure 9E The cross-sectional view shown extends along a repeating axis of alternating layers of dielectric materials 930-1, 930-2, 930-3, ..., 930-(N+1) and horizontal openings 933-1, 933-2, 933-3, ..., 933-N in a first direction (D1) 909. In these alternating layers, channel regions separated by gate dielectric material 938 from multiple individual vertical access lines 940-1, 940-2, ..., 940-4 are formed. Figure 9E In the diagram, a first dielectric filler 939 is shown separating the space between adjacent horizontally oriented access devices and horizontally oriented memory nodes, which can be formed to extend into and out of the drawing plane, and can be spaced along a first direction (D1) 909 and vertically stacked into an array extending in a third direction (D3) 911 in a three-dimensional (3D) memory. A hard mask 936 can cover... Figure 9E The structure shown in the figure.

[0091] Figure 10A Demonstrated as Figures 1-3 The example method shown in the document and according to many embodiments of the present disclosure is used at another stage of the semiconductor manufacturing process to form an array of vertically stacked memory cells having horizontally oriented access devices and vertically oriented access lines. Figure 10ATop-down views of a semiconductor structure at a particular point in time in a semiconductor manufacturing process are shown in accordance with one or more embodiments. In Figure 10A In example embodiments, vertical openings 1071-1 and 1071-2 remain from Figures 9A-9E However, in Figures 10A-10E In example embodiments, vertical openings 1071-1 and 1071-2 remain from Figure 9C and 9D Horizontal access devices 1098-1, 1098-2,..., 1098-N of first source / drain regions 1097-1, channel regions 1025-A, 1025-B, 1025-C,..., 1025-N (individually or collectively referred to as channels 1025) and second source / drain regions 1097-2A, 1097-2B, 1097-2C,..., 1097-2N (individually or collectively referred to as second source / drain regions 1097-2) in Figure 10C In example embodiments, vertical openings 1071-1 and 1071-2 remain from Figures 9A-9E However, in Figures 10A-10E In example embodiments, vertical openings 1071-1 and 1071-2 remain from Figure 9C and 9D Horizontal digit lines 1099-1, 1099-2, 1099-N have been formed and integrated to contact, for example, second source / drain regions 1097-2, as shown in Figure 10C and 10D Further, a hard mask 1035 can be deposited over vertical elongated columns 1042. Other numbered components can be similar to those shown and discussed in connection with FIGS. 6, 7, 8, and 9.

[0092] In accordance with embodiments, the sacrificial semiconductor material, for example, 832-1, 832-2, 832-3,..., 832-N, in Figures 8A-8E has been removed to allow the repeated iteration of alternating layers of vertical stack dielectric material, for example, 1030-1, 1030-2, 1030-3,..., 1030-(N+1), and horizontal openings, for example, 933-1, 933-2, 933-3,..., 933-N, to form access devices, for example, transistors, in access device regions 1043, for example, transistor regions. In some embodiments, this process is performed prior to selectively removing the sacrificial material in storage node regions 1050 in which the capacitor cells are formed. In other embodiments, this process is performed after selectively removing the sacrificial material in storage node regions 1050 in which the capacitor cells are formed. In accordance with example embodiments shown in Figures 9A-9E The method includes using an atomic layer deposition (ALD) process or other suitable deposition technique to form a dielectric material, for example, 1030-1, 1030-2, 1030-3,..., 1030-(N+1), in Figures 9A-9EIn the horizontal openings, such as 933-1, 933-2, 933-3, ..., 933-N, a first source / drain region 1097-1, a channel region 1025, and a second source / drain region 1097-2 are selectively deposited. In some embodiments, the first source / drain region 1097-1 can be formed by depositing the first source / drain region material in the memory node regions 1044, 1050. Further, it can be formed by depositing the first source / drain region material in the memory node regions 1044, 1050. Figure 10B The horizontal openings, for example, 933-1, 933-2, 933-3, ..., 933-N, are formed by depositing channel material 1025 and second source / drain region material to form the channel 1025 and the second source / drain region 1097-2. Further, the opening 1051 can be formed by patterning and etching the hard mask 1037.

[0093] Figure 10A Showing along Figure 10B The cross-sectional view taken by the cutting line A-A' shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 10B The cross-sectional view shown is away from multiple individual vertical access lines 1040-1, 1040-2, ..., 1040-N, 1040-(N+1), ..., 1040-(Z-1), and illustrates a repetitive iteration of alternating layers of dielectric materials 1030-1, 1030-2, 1030-3, ..., 1030-(N+1) on a semiconductor substrate 1000, separated by capacitor cells to form vertically elongated columns 1042-1, 1042-2, 1042-3 in a vertical stack. Each capacitor cell has a first electrode 1061, such as a bottom cell contact electrode, a cell dielectric 1063, and a second electrode 1056, such as a top common node electrode. Figures 1-3 As shown, the vertical direction 1011 is displayed as... Figure 10B The third direction (D3) 111 shown in the first direction, second direction, and third direction is similar to the third direction (D3), for example, the z direction in the xyz coordinate system. The drawing plane extending to the right and left is on the first direction (D1) 1009. Figure 10B In an example embodiment, a first electrode 1061, such as a bottom electrode, to be coupled to the source / drain region of a horizontal access device, and a second electrode 1056, are shown separated by a cell dielectric material 1063 that extends into and out of the plane of the drawing along the orientation axis of the horizontal access devices and horizontal memory nodes in an array of vertically stacked memory cells of a three-dimensional (3D) memory. Figure 10CAs shown, a hard mask 1035 has been deposited over the alternating layers of dielectric material 1030-1, 1030-2, 1030-3,..., 1030-(N+1) and capacitor cells having a first electrode 1061, e.g., a bottom cell contact electrode, a cell dielectric 1063, and a second electrode 1056.

[0094] Figure 10A A cross-sectional view taken along the cut line B-B' in Figure 10C A cross-sectional view taken along the cut line B-B' in Figures 9A-9E The cross-sectional view shown is illustrated as extending from left to right in the plane of the drawing sheet in a second direction (D2) 1005 along an axis of repetitive iteration of the alternating layers of dielectric material 1030-1, 1030-2, 1030-3,..., 1030-(N+1). However, now shown is that the first source / drain region material 1097-1, the channel region material 1025, and the second source / drain region material 1097-2 have been deposited in the horizontal openings in Figures 4A-4D The cross-sectional view shown is illustrated as extending from left to right in the plane of the drawing sheet in a second direction (D2) 1005 along an axis of repetitive iteration of the alternating layers of dielectric material 1030-1, 1030-2, 1030-3,..., 1030-(N+1). However, now shown is that the first source / drain region material 1097-1, the channel region material 1025, and the second source / drain region material 1097-2 have been deposited in the horizontal openings in

[0095] Thus, three-node horizontal access devices 1098-1, 1098-2,..., 1098-N have been formed and integrated to the vertical access lines 1040-1, 1040-2,..., 1040-(Z+1) and to the digit lines 1099-1, 1099-2,..., 1099-N without a body contact. Advantages of the structures and processes described herein can include lower off-state current (Ioff) of the access devices compared to silicon-based (Si-based) access devices, lower programming voltages compared to non-3D NAND memory devices, and lower programming voltages compared to 3D NAND memory devices that are not as Figure 10CThe formed channels described in the middle have lower voltage thresholds than the channels 1025 and / or reduced gate-induced drain leakage (GIDL) of the access devices. In some embodiments, the channel and / or source / drain region replacement fabrication steps can be performed after the capacitor cell formation process, thus reducing thermal budget. Since body contacts to the body region of the access devices 1098 are not used, digital line integration can be more easily achieved in the fabrication process. Additionally, since there is less channel length and lower source / drain semiconductor fabrication process formation overhead, the embodiments described herein can achieve better lateral scaling paths compared to paths achieved with doped polysilicon-based channel regions.

[0096] In Figure 10C In the example embodiments, horizontal access devices having first source / drain regions 1097-1, channel regions 1025, and second source / drain regions 1097-2 are shown extending in the second direction 1005 (D2) from left to right in the plane of the drawing sheet, at a distance from the vertically formed openings 1071-1 and 1071-2 in the vertical stack, and along an axis of orientation of horizontal access devices and horizontal storage nodes in an array of memory cells of a vertical stack of a three-dimensional (3D) memory. In Figure 10D In the middle, adjacent opposing vertical access lines 1040-3 are shown by dashed lines indicating a position disposed inward from the plane of the drawing sheet and orientation.

[0097] Figure 10A A cross-sectional view taken along the cut line C-C’ in Figure 10D In the middle, adjacent opposing vertical access lines 1040-3 are shown by dashed lines indicating a position disposed inward from the plane of the drawing sheet and orientation. Figure 10D The shown cross-sectional view is shown extending in the plane of the drawing sheet from left to right in the second direction (D2) 1005 along an axis of repetitive iteration of alternating layers of dielectric material 1030-1, 1030-2, 1030-3, …, 1030-N, 1030-(N+1) and digit lines 1099-1, 1099-2, 1099-3, …, 1099-N (individually or collectively referred to as digit lines 1099) outside of a region in which horizontal oriented access devices and horizontal oriented storage nodes, e.g., capacitor cells, are formed. In Figure 10D In the middle, dielectric material 1041 is shown filling space between horizontal oriented access devices that can be horizontally spaced apart along the first direction (D1) extending into and out of the plane of the drawing sheet of the three-dimensional array of vertically oriented memory cells. In Figure 10EA cross-sectional view in the second electrode 1056, e.g., a top common electrode of a capacitor cell structure, is additionally shown as present in the space between horizontally adjacent devices. A repeating iteration of alternating layers of dielectric material 1030-1, 1030-2, 1030-3,..., 1030-(N+1) and integrally formed horizontally oriented digit lines 1099 extending into and out of the plane of the drawing sheet and connected to source / drain regions of horizontally oriented access devices 1098 is shown at the left end of the drawing sheet.

[0098] Figure 10A A cross-sectional view taken along the cut line D-D' in Figure 10E A cross-sectional view taken along the cut line D-D' in Figure 10C A cross-sectional view taken along the cut line D-D' in Figure 10E A cross-sectional view taken along the cut line D-D' in Figure 11 In

[0099] Figure 11 is a block diagram of a device in the form of a computing system 1170 including a memory device 1173, in accordance with a number of embodiments of the present disclosure. As used herein, a memory device 1173, a memory array 1180, and / or a host 1172 can also each be considered a “device,” for example. In accordance with embodiments, a memory device 1173 can include at least one memory array 1180 having three-node access devices for vertical three-dimensional (3D) memory, as has been described herein.

[0100] In this example, system 1170 includes a host 1172 coupled to a memory device 1173 through an interface 1174. In various other types of systems, computing system 1170 can be a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, a memory card reader, or an Internet of Things (IoT) enabled device. Host 1172 can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry) capable of accessing memory 1173. System 1170 can include separate integrated circuits, or both host 1172 and memory device 1173 can be located on the same integrated circuit. For example, host 1172 can be a system controller of a memory system that includes a number of memory devices 1173, where system controller 1175 provides access to respective memory devices 1173 through another processing resource such as a central processing unit (CPU).

[0101] In Figure 1 In the illustrated example, host 1172 is responsible for executing an operating system (OS) and / or various applications (e.g., processes) that can be loaded to the OS (e.g., by controller 1175 from memory device 1173). The OS and / or various applications can be loaded from memory device 1173 by providing access commands from host 1172 to memory device 1173 to access data including the OS and / or various applications. Host 1172 can also access data utilized by the OS and / or various applications by providing access commands to memory device 1173 to retrieve the data utilized in the execution of the OS and / or various applications.

[0102] For the sake of clarity, system 1170 has been simplified to focus on features relevant to the present disclosure. Memory array 1180 can be a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, a RRAM array, a NAND flash array, and / or a NOR flash array, including at least one three-node access device for three-dimensional (3D) memory. For example, memory array 1180 can be a maskless DL4F2 array such as a 3D-DRAM memory array. Array 1180 can include memory cells arranged in rows coupled by word lines (which can be referred to herein as access lines or select lines) and columns coupled by digit lines (which can be referred to herein as sense lines or data lines). Although a single array 1180 is shown in ​ Embodiments are not limited in this regard, however, as those skilled in the art will appreciate that the functionality of system 1170 can be spread across multiple systems and memory devices 1173.

[0103] Memory device 1173 includes address circuitry 1176 for latching address signals provided by interface 1174. The interface can include, for example, a physical interface (e.g., a data bus, an address bus, and a command bus, or a combined data / address / command bus) employing a suitable protocol. Such a protocol can be custom or proprietary, or the interface 1174 can employ a standardized protocol like Peripheral Component Interconnect Express (PCIe), Gen-Z, CCIX, etc. The address signals are received and decoded by row decoder 1178 and column decoder 1182 to access the memory array 1180. Data can be read from the memory array 1180 by use of read circuitry 1181 which reads a voltage and / or current change on a sense line. Read circuitry 1181 can include, for example, a sense amplifier that can read and latch a page (e.g., a row) of data from the memory array 1180. I / O circuitry 1177 can be used for bidirectional data communication between the host 1172 and the interface 1174. Read / Write circuitry 1183 is used to write data to and read data from the memory array 1180. As an example, circuitry 1183 can include various drivers, latch circuitry, etc.

[0104] Control circuitry 1175 includes registers 1179 and decodes signals provided by the host 1172. The signals can be commands provided by the host 1172. These signals can include a chip enable signal, a write enable signal, and an address latch signal, which are used to control operations performed on the memory array 1180, including data read operations, data write operations, and data erase operations. In various embodiments, the control circuitry 1175 is responsible for executing instructions from the host 1172. The control circuitry 1175 can comprise a state machine, a sequencer, and / or some other type of control circuitry, which can be implemented in hardware, firmware, or software, or any combination of the three. In some examples, the host 1172 can be a controller external to the memory device 1173. For example, the host 1172 can be a memory controller coupled to a processing resource of a computing device.

[0105] The term semiconductor can refer to, for example, a material, a wafer, or a substrate and includes any base semiconductor structure. “Semiconductor” should be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a base semiconductor structure, as well as other semiconductor structures. Furthermore, when reference is made to a semiconductor, this can have been formed in a base semiconductor structure utilizing previous process steps, and the term semiconductor can include the underlying material containing such regions / junctions.

[0106] The figures herein follow a congruent numbering scheme in which one or more first numbers correspond to the figure number and the remaining numbers identify elements or components in the figure. Similar (e.g., identical) elements or components between different figures can be identified by the use of similar numbers. As should be appreciated, elements shown in various embodiments herein can be added, exchanged, and / or eliminated so as to provide a number of further embodiments of the present disclosure. In addition, as should be appreciated, the proportions and / or relative scales of the various elements provided in the figures are intended to illustrate embodiments of the present disclosure and should not be taken in a limiting sense.

[0107] As used herein, “a number of” or “an amount of” something can refer to one or more of such things. For example, a number of or an amount of memory cells can refer to one or more memory cells. A plurality of something means two or more. As used herein, a plurality of actions performed at the same time refers to actions that are at least partially overlapping in a particular time period. As used herein, the term “coupled” can include electrically coupled, directly coupled and / or directly connected (e.g., by direct physical contact), indirectly coupled and / or connected with intervening elements, or coupled in a wireless manner, without intervening elements. The term coupled can further include two or more elements that cooperate or interact with each other (e.g., like in a cause and effect relationship). An element coupled between two elements can be located between and coupled to each of the two elements.

[0108] It should be appreciated that the term vertical accounts for variations in “exact” vertical due to normal manufacturing, measurement, and / or assembly variations, and one of ordinary skill in the art would understand what is meant by the term “vertical.” For example, vertical can correspond to a z-direction. As used herein, when a particular element is “adjacent” to another element, the particular element can cover, can be located above or lateral to, and / or can be in direct physical contact with the other element. For example, “lateral to” can refer to a horizontal direction (e.g., a y-direction or an x-direction) that can be perpendicular to the z-direction.

[0109] While specific embodiments have been shown and described herein, it will be understood by those skilled in the art that computational arrangements to achieve the same results can substitute for the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of various embodiments of the disclosure. It is to be understood that the above description is illustrative only and not in a limiting sense. Having thus described above several aspects of several embodiments of the disclosure, combinations and permutations of these embodiments, as well as other embodiments not specifically described herein, will be apparent to those of ordinary skill in the art to which the disclosure pertains. The scope of the various embodiments of the present disclosure, therefore, includes other applications that are within the scope of the following claims and the equivalents thereof. The scope of the various embodiments of the present disclosure should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. A method for forming an array of vertically stacked memory cells (101, 1180) having horizontally oriented access devices (230, 330) and vertically oriented access lines (103, 203, 303), the method comprising: depositing, in repeated iterations, alternating layers of a dielectric material (430, 530, 630, 730, 830, 930, 1030) and a sacrificial material (432, 532, 632, 732, 832) to form a vertical stack (401); forming a plurality of vertical openings (472, 672) through the vertical stack (401), the plurality of vertical openings having a first horizontal direction (109, 209, 309, 609, 709, 809, 909, 1009) and a second horizontal direction (105, 205, 305, 605, 705, 805, 905, 1005) and extending predominantly in the second horizontal direction (105, 205, 305, 605, 705, 805, 905, 1005) to form an elongated column of vertical columns (613, 642, 742, 842, 942, 1042) having sidewalls in the vertical stack (401); patterning the elongated column of vertical columns (613, 642, 742, 842, 942, 1042) to expose locations to form channel regions (1025) in the sacrificial material (432, 532, 632, 732, 832) in each of the layers; selectively removing a portion of the sacrificial material (432, 532, 632, 732, 832) to form first horizontal openings (417) in the sidewalls (614) of the elongated column of vertical columns (613, 642, 742, 842, 942, 1042) in the first horizontal direction (109, 209, 309, 609, 709, 809, 909, 1009); and depositing a channel material (418, 518) in the first horizontal openings (417) to form the channel regions (1025) within the sidewalls for the horizontally oriented access devices (230, 330).

2. The method of claim 1, wherein depositing the sacrificial material (432, 532, 632, 732, 832) comprises depositing yttrium oxide (Y2O3).

3. The method of any one of claims 1-2, wherein depositing the channel material (418, 518) comprises depositing an indium gallium zinc oxide (IGZO) material as the channel material (418, 518).

4. A method for forming an array of vertically stacked memory cells (101, 1180) having horizontally oriented access devices (230, 330) and vertically oriented access lines (103, 203, 303), the method comprising: depositing (430, 530, 630, 730, 830, 930, 1030) alternating layers of dielectric material (430, 530, 630, 730, 830, 930, 1030) and yttrium oxide (Y2O3) material (432, 532, 632, 732, 832) in repeated iterations to form a vertical stack (401); forming a plurality of vertical openings (472, 672) through the vertical stack (401), the plurality of vertical openings having a first horizontal direction (109, 209, 309, 609, 709, 809, 909, 1009) and a second horizontal direction (105, 205, 305, 605, 705, 805, 905, 1005) and extending predominantly in the second horizontal direction (105, 205, 305, 605, 705, 805, 905, 1005) to form an elongated vertical columnar array (613, 642, 742, 842, 942, 1042) having sidewalls in the vertical stack (401); patterning the elongated vertical columnar array (613, 642, 742, 842, 942, 1042) to expose locations to form channel regions (1025) in the layers of yttrium oxide (Y2O3) material (432, 532, 632, 732, 832); selectively etching to remove portions of the yttrium oxide (Y2O3) material (432, 532, 632, 732, 832) in the first horizontal direction (109, 209, 309, 609, 709, 809, 909, 1009) to form first horizontal openings (417) on opposite sides of sidewalls (614) of the elongated vertical columnar array (613, 642, 742, 842, 942, 1042); and depositing a channel material (418, 518) in the first horizontal openings (417) to form channel regions (1025) on the opposite sides of the sidewalls (614) of the elongated vertical columnar array (613, 642, 742, 842, 942, 1042).

5. The method of claim 4, further comprising selectively depositing the channel material (418, 518) after forming capacitor cells associated with the horizontally oriented access devices (230, 330) in the array of vertical stack memory cells (101, 1180).

6. The method of any one of claims 4-5, further comprising forming a first source / drain region (221, 321, 897-1, 997-1, 1097-1) that couples the channel region (1025) to a digit line (107, 207, 307, 1099) and forming a second source / drain region (223, 323, 1097-2) that couples the channel region (1025) to a horizontally oriented storage node (227, 327) for each of the horizontally oriented access devices (230, 330) in the horizontal orientation.

7. A method for forming an array of vertically stacked memory cells (101, 1180) having horizontally oriented access devices (230, 330) and vertically oriented access lines (103, 203, 303), the method comprising: depositing alternating layers of a dielectric material (430, 530, 630, 730, 830, 930, 1030) and a semiconductor material (432, 532, 632, 732, 832) to form a vertical stack (401); forming a plurality of vertical openings (472, 672) through the vertical stack (401) having a first horizontal direction (109, 209, 309, 609, 709, 809, 909, 1009) and a second horizontal direction (105, 205, 305, 605, 705, 805, 905, 1005) and extending primarily in the second horizontal direction (105, 205, 305, 605, 705, 805, 905, 1005) to form an elongated vertical column of columns (613, 642, 742, 842, 942, 1042) having sidewalls in the vertical stack (401); patterning the elongated vertical column of columns (613, 642, 742, 842, 942, 1042) to expose locations to form channel regions (1025) in the semiconductor material (432, 532, 632, 732, 832); selectively etching to remove portions of the semiconductor material (432, 532, 632, 732, 832) in the first horizontal direction (109, 209, 309, 609, 709, 809, 909, 1009) to form first horizontal openings (417) against the semiconductor material (432, 532, 632, 732, 832) on opposite sidewalls (614) of the elongated vertical column of columns (613, 642, 742, 842, 942, 1042); selectively depositing channel material (418, 518) in the first horizontal openings (417) to form channel regions (1025) of the horizontally oriented access devices (230, 330); conformally depositing an electrically conductive material in the plurality of vertical openings (472, 672) on the gate dielectric material (304, 504, 638, 738, 838, 938, 1038); and removing portions of the electrically conductive material to form a plurality of individual vertical access lines (103, 203, 303) along the sidewalls (614) of the elongated vertical column (613, 642, 742, 842, 942, 1042) opposite the channel region (1025).

8. The method of claim 7, wherein: depositing the semiconductor material (432, 532, 632, 732, 832) comprises depositing a yttrium oxide (Y2O3) composition (432, 532, 632, 732, 832); and Selectively depositing the channel material (418, 518) in the first horizontal opening (417) includes depositing the channel material (418, 518) in combination with the yttrium oxide (Y2O3) composition (432, 532, 632, 732, 832) to act as a reverse channel passivation material and to lower a threshold voltage (V th ) of the channel material (418, 518).

9. The method of claim 7, wherein selectively depositing the channel material (418, 518) in the first horizontal opening (417-1) to form the channel region (1025) of the horizontally oriented access device (230, 330) in combination with a yttrium oxide (Y2O3) composition (432, 532, 632, 732, 832) comprises forming the channel region (1025) to operate at a threshold voltage (V th ) of less than 0.4 volts (V).

10. The method of claim 7, further comprising selectively depositing the channel material (418, 518) in the first horizontal opening (417) to have a vertical width (W) in a third direction (111, 211, 311, 411, 711, 811, 911, 1011) that is greater than a horizontal length (L) of the channel region (1025) in the second direction (105, 205, 305, 605, 705, 805, 905, 1005).

11. An array of memory cells, comprising: a plurality of access transistors stacked on one another, each of the access transistors including a first source / drain region, a second source / drain region, and a channel therebetween, the first source / drain region, the second source / drain region, and the channel being horizontally arranged, wherein the channel includes a first portion of channel material, a second portion of channel material, and a passivation material formed therebetween; a first access line extending vertically and coupled to the first portion of channel material under intervention of a first gate dielectric; a second access line extending vertically and coupled to the second portion of channel material under intervention of a second gate dielectric; a plurality of storage capacitors stacked on one another, each of the plurality of storage capacitors being horizontally disposed and coupled to a corresponding one of the second source / drain regions of the plurality of access transistors; and a plurality of digit lines, each of the plurality of digit lines being coupled to a corresponding one of the first source / drain regions of the plurality of access transistors.

12. The array of memory cells of claim 11, wherein the first portion of channel material is in contact with one side of the passivation material, and the second portion of channel material is in contact with an opposite side of the passivation material.

13. The array of memory cells of any of claims 11-12, wherein a plurality of channels are formed in a vertical pattern, wherein a dielectric material separates each of the plurality of channels.

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