Thin Film Transistor Array Substrate and Its Fabrication Method

Abstract

This invention discloses a thin-film transistor array substrate and its fabrication method. The thin-film transistor array substrate includes a thin-film transistor including a drain, a first passivation layer, and a planarization layer sequentially formed on a substrate. Contact holes are formed in the planarization layer at positions corresponding to the drain, exposing a portion of the surface of the first passivation layer. A common electrode and a protective layer are then formed on the planarization layer at intervals. The protective layer at least covers the sidewalls of the contact holes and exposes a portion of the surface of the first passivation layer at the bottom of the contact holes. In the thin-film transistor array substrate and its fabrication method provided by this invention, because the exposed surface of the planarization layer is covered by the protective layer, the planarization layer portion covered by the protective layer will not be damaged during etching of the second passivation layer, thus avoiding the formation of reactive deposits at the bottom of the contact holes and ensuring good connection between the pixel electrode and the drain.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a thin-film transistor array substrate and its fabrication method. Background Technology

[0002] Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) are capable of displaying high-definition, continuous, and detailed images, and are becoming increasingly popular among consumers.

[0003] Please see Figure 1a The thin-film transistor array substrate includes a substrate 91, thin-film transistors 93 formed on the substrate 91, a common electrode 94, and a pixel electrode 95. A first passivation layer 96 is covered on the thin-film transistor 93, and a planarization layer 97 is covered on the first passivation layer 96. The common electrode 94 is disposed on the planarization layer 97. The thin-film transistor 93 includes a drain 932. A second passivation layer 99 is disposed between the common electrode 94 and the pixel electrode 95. A contact hole 972 is formed on the planarization layer 97 so that the subsequently covered pixel electrode 95 can pass through the contact hole 972 and connect to the drain 932.

[0004] Please refer to the following section on the fabrication process of thin-film transistor array substrates. Figure 1b After forming the planarization layer 97, the planarization layer 97 is first patterned, and contact holes 972 are formed at the positions of the drain 932 on the planarization layer 97. Then, a second passivation layer 99 is covered on the planarization layer 97. Next, please refer to... Figure 1c The first passivation layer 96 and the second passivation layer 99 are drilled in a single process. The first passivation layer 96 is typically made of silicon dioxide, while the second passivation layer 99 is typically made of silicon nitride. The first passivation layer 96 and the second passivation layer 99 are etched using CF4 and O2, respectively. Because the etching gases used for the first passivation layer 96 and the second passivation layer 99 are different, their etching rates are also different, with the etching rate of the second passivation layer 99 being higher than that of the first passivation layer 96. Therefore, when a portion of the first passivation layer 96 is etched, the second passivation layer 99 shows significant lateral etching, thus exposing part of the planarization layer 97 to the etching environment. The exposed planarization layer 97 undergoes fragmentation when bombarded by plasma. The fragmentation products enter the plasma, creating burrs 974 on the exposed surface of the planarization layer 97 and deposits 976 that adhere to the bottom of the contact hole 972. (See also...) Figure 1d Since the etching plasma cannot completely remove the deposit 976, the etch deposit 976 accumulates on the drain 932. The presence of the deposit 976 will affect the connection between the drain 932 and the pixel electrode 95, thereby affecting the signal transmission. Summary of the Invention

[0005] The purpose of this invention is to provide a thin-film transistor array substrate and its fabrication method, which can avoid the planarization layer from being etched and forming burrs, thereby avoiding the generation of reactive deposits at the bottom of the contact holes and ensuring good connection between the pixel electrode and the drain electrode.

[0006] This invention provides a thin-film transistor array substrate, comprising:

[0007] Substrate;

[0008] A thin-film transistor formed on the substrate, the thin-film transistor including a drain electrode;

[0009] A first passivation layer is formed on the thin-film transistor;

[0010] A planarization layer formed on the first passivation layer;

[0011] Contact holes formed on the planarization layer;

[0012] A common electrode and a protective layer are formed on the planarization layer, the common electrode and the protective layer are spaced apart and do not contact each other, the protective layer at least covers the sidewall of the contact hole and exposes a portion of the surface of the first passivation layer at the bottom of the contact hole.

[0013] In one embodiment, the common electrode and the protective layer are made of transparent conductive materials, and the common electrode and the protective layer are disposed in the same layer.

[0014] In one embodiment, the thin-film transistor array substrate further includes:

[0015] A metal wire portion is formed on the common electrode and electrically connected to the common electrode. The protective layer and the metal wire portion are made of metal and are disposed in the same layer at intervals.

[0016] In one embodiment, the protective layer is made of a metallic material.

[0017] The present invention also provides a method for fabricating a thin-film transistor array substrate, comprising:

[0018] Provide substrates;

[0019] A thin-film transistor is formed on the substrate, the thin-film transistor including a drain electrode;

[0020] A first passivation layer is formed on the thin-film transistor;

[0021] A planarization layer is formed on the first passivation layer;

[0022] A contact hole is formed on the planarization layer at the position corresponding to the drain electrode, exposing a portion of the surface of the first passivation layer;

[0023] A common electrode and a protective layer are formed on the planarization layer. The common electrode and the protective layer are spaced apart and do not contact each other. The protective layer at least covers the sidewall of the contact hole and exposes a portion of the surface of the first passivation layer at the bottom of the contact hole.

[0024] In one embodiment, forming the common electrode and the protective layer on the planarization layer specifically includes:

[0025] A first electrode layer is formed on the planarization layer, and the first electrode layer is patterned to form the common electrode and the protective layer, respectively.

[0026] In one embodiment, the common electrode and the protective layer are made of a transparent conductive material.

[0027] In one embodiment, forming the common electrode and the protective layer on the planarization layer specifically includes:

[0028] A first electrode layer is formed on the planarization layer, and the first electrode layer is patterned to form the common electrode;

[0029] A metal layer is formed on the common electrode, the metal layer covering the common electrode and the portion of the planarization layer not covered by the common electrode. The metal layer is patterned to form the protective layer and the metal wire portion electrically connected to the common electrode. The protective layer and the metal wire portion are spaced apart.

[0030] In one embodiment, forming the common electrode and the protective layer on the planarization layer specifically includes:

[0031] A first electrode layer is formed on the planarization layer, and the first electrode layer is patterned to form the common electrode;

[0032] A metal layer is formed on the common electrode, the metal layer covering the portion of the common electrode and the planarization layer not covered by the common electrode, and the metal layer is patterned to form the protective layer.

[0033] In one embodiment, the method for fabricating the thin-film transistor array substrate further includes:

[0034] A second passivation layer is formed, and vias are made in the second passivation layer to expose part of the protective layer and part of the drain electrode;

[0035] A pixel electrode is formed on the second passivation layer and the protective layer, and the pixel electrode is electrically connected to the drain electrode.

[0036] In the thin-film transistor array substrate and its fabrication method of the present invention, a protective layer covers a portion of the exposed surface of the planarization layer. Therefore, when the second passivation layer is etched, the portion of the planarization layer covered by the protective layer will not be damaged, thereby avoiding the generation of reactive deposits at the bottom of the contact hole and ensuring good connection between the pixel electrode and the drain electrode. Attached Figure Description

[0037] To more clearly illustrate the solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1a This is a schematic diagram of the structure of an existing thin-film transistor array substrate.

[0039] Figures 1b-1d for Figure 1a The diagram shows a schematic of the fabrication process of an existing thin-film transistor array substrate.

[0040] Figure 2a This is a schematic diagram of the structure of the thin-film transistor array substrate according to the first embodiment of the present invention.

[0041] Figure 2b-2f This is a schematic diagram of a portion of the fabrication process of a thin-film transistor array substrate according to the first embodiment of the present invention.

[0042] Figure 3a This is a schematic diagram of the structure of the thin-film transistor array substrate according to the second embodiment of the present invention.

[0043] Figures 3b-3f This is a schematic diagram of a portion of the fabrication process of a thin-film transistor array substrate according to a second embodiment of the present invention. Detailed Implementation

[0044] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. Through the description of the specific embodiments, a more in-depth and specific understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the present invention.

[0045] In this article, the terms “first,” “second,” “third,” “fourth,” “fifth,” etc. (if present) are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0046] In this document, the directional terms such as "upper," "lower," "left," "right," "front," "back," "top," and "bottom" (if applicable) are defined according to the position of the structures in the accompanying drawings and the relative positions of the structures, and are only used for clarity and convenience in expressing the technical solution. It should be understood that the use of directional terms should not limit the scope of protection of this application.

[0047] In this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0048] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, describes the specific implementation, structure, features, and effects of the display device and color display method proposed according to the present invention.

[0049] First Embodiment

[0050] This invention provides a thin-film transistor array substrate. Figure 2a This is a schematic diagram of the thin-film transistor array substrate according to the first embodiment of the present invention. Please refer to [link / reference]. Figure 2a The thin-film transistor array substrate of the first embodiment includes:

[0051] Substrate 11. Specifically, substrate 11 may be a transparent glass substrate or a transparent plastic substrate;

[0052] A thin-film transistor is formed on a substrate 11. Specifically, the thin-film transistor includes a gate 12, a gate insulating layer 13, an oxide semiconductor layer 14, an etch barrier layer 15, a source 161, and a drain 162 sequentially formed on the substrate 11. The etch barrier layer 15 has holes that expose part of the oxide semiconductor layer 14. The source 161 and the drain 162 are disposed on the etch barrier layer 15 at intervals, and the source 161 and the drain 162 are respectively in contact with the oxide semiconductor layer 14.

[0053] A first passivation layer 17 is formed on the thin-film transistor, and a via corresponding to the drain 162 is formed on the first passivation layer 17. Specifically, the material of the first passivation layer 17 can be silicon dioxide;

[0054] A planarization layer 18 is formed on the first passivation layer 17, and a contact hole 50 is provided on the planarization layer 18 at the position corresponding to the drain electrode 162.

[0055] A common electrode 191 and a protective layer 192 are formed on the planarization layer 18 and are spaced apart from each other. The protective layer 192 at least covers the sidewall of the contact hole 50.

[0056] A second passivation layer 20 is formed on the common electrode 191, and vias corresponding to the positions of the contact holes 50 are formed on the second passivation layer 20. Specifically, the material of the second passivation layer 20 may be silicon nitride;

[0057] A pixel electrode 30 is formed on the second passivation layer 20 and the protective layer 192. The pixel electrode 30 passes through a via, a contact hole 50 and a through hole in sequence and is electrically connected to the drain electrode 162.

[0058] In this embodiment, the materials of the common electrode 191 and the protective layer 192 can be transparent conductive materials, such as indium tin oxide.

[0059] In this embodiment, the common electrode 191 and the protective layer 192 are disposed in the same layer, so they can be formed simultaneously during manufacturing, which simplifies the manufacturing process and saves costs.

[0060] In the thin-film transistor array substrate of this embodiment, since the exposed part of the planarization layer 18 is covered by the protective layer 192, the part of the planarization layer 18 covered by the protective layer 192 will not be damaged when the second passivation layer 20 is etched, so as to avoid the generation of reactive deposits at the bottom of the contact hole 50, thereby ensuring good connection between the pixel electrode 30 and the drain 162.

[0061] Second Embodiment

[0062] The present invention also provides a method for fabricating a thin-film transistor array substrate. Figures 2b-2f This is a schematic diagram of a portion of the fabrication process of the thin-film transistor array substrate according to the first embodiment of the present invention. Please refer to... Figures 2b-2f The method for fabricating a thin-film transistor array substrate according to the second embodiment includes the following steps:

[0063] S11, a substrate 11 is provided. Specifically, the substrate 11 may be a transparent glass substrate or a transparent plastic substrate.

[0064] S13, a thin-film transistor is formed on the substrate 11, the thin-film transistor including a drain 162. Specifically, step S13 may include:

[0065] S131, a first metal layer is formed on the substrate 11, and the first metal layer is patterned to form the gate 12. Specifically, the first metal layer can be patterned by etching.

[0066] S132, forming a gate insulating layer 13, which covers the gate 12 and the substrate 11 not covered by the gate 12. Specifically, the material of the gate insulating layer 13 may be silicon dioxide.

[0067] S133, an oxide semiconductor layer 14 is formed on the gate insulating layer 13 at the position corresponding to the gate 12. Specifically, the material of the oxide semiconductor layer 14 can be amorphous indium tin oxide.

[0068] S134, an etch barrier layer 15 is formed, which covers the oxide semiconductor layer 14 and the gate insulating layer 13 not covered by the oxide semiconductor layer 14.

[0069] S135, an opening is made in the etch barrier layer 15 to expose a portion of the surface of the oxide semiconductor layer 14.

[0070] S136, a second metal layer is formed on the etch barrier layer 15, and the second metal layer is patterned to form source electrodes 161 and drain electrodes 162 that are spaced apart from each other. The source electrodes 161 and drain electrodes 162 are respectively in contact with the oxide semiconductor layer 14. Specifically, the second metal layer can be patterned by etching.

[0071] S15, a first passivation layer 17 is formed, which covers the source 161, the drain 162, the uncovered oxide semiconductor layer 14, and the uncovered etch barrier layer 15. Specifically, the material of the first passivation layer 17 may be silicon dioxide.

[0072] Please refer to S17 as well. Figure 2a and Figure 2b A planarization layer 18 is formed, which covers the first passivation layer 17. A contact hole 50 is formed on the planarization layer 18 at a position corresponding to the drain electrode 162, exposing a portion of the surface of the first passivation layer 17. Specifically, the contact hole 50 can be formed on the planarization layer 18 by exposure and development.

[0073] Please refer to S19 as well. Figure 2a and Figure 2c A common electrode 191 and a protective layer 192 are formed on the planarization layer 18. Specifically, the common electrode 191 and the protective layer 192 are spaced apart and do not contact each other. The materials of the common electrode 191 and the protective layer 192 can be transparent conductive materials. The protective layer 192 at least covers the sidewall of the contact hole 50 and exposes a portion of the surface of the first passivation layer 17 at the bottom of the contact hole 50. Specifically, the materials of the common electrode 191 and the protective layer 192 can be indium tin oxide. Step S19 may specifically include:

[0074] S191, a first electrode layer is formed on the planarization layer 18.

[0075] S193, the first electrode layer is patterned to form a common electrode 191 and a protective layer 192.

[0076] In this embodiment, processing the first electrode layer can simultaneously form a common electrode 191 and a protective layer 192, which simplifies the manufacturing process and saves costs.

[0077] S21, a second passivation layer 20 is formed, and vias are formed in the second passivation layer 20. Through-holes are formed in the first passivation layer 17 to expose a portion of the protective layer 192 and a portion of the drain electrode 162. Specifically, vias and through-holes can be formed by etching. Specifically, the material of the second passivation layer 20 can be silicon nitride. Step S21 may specifically include:

[0078] Please refer to S211 as well. Figure 2a and Figure 2d A second passivation layer 20 is formed, and photoresist 21 is disposed on the second passivation layer 20. The second passivation layer 20 covers the common electrode 191, the protective layer 192 and the partial planarization layer 18.

[0079] Please refer to S213 as well. Figure 2a and Figure 2e The second passivation layer 20 and the first passivation layer 17 are etched sequentially to form vias and through holes in the second passivation layer 20 and the first passivation layer 17, respectively, to expose part of the protective layer 192 and part of the drain electrode 162.

[0080] Please refer to S23 as well. Figure 2a and Figure 2f A pixel electrode 30 is formed, which is located on the second passivation layer 20 and the protective layer 192. Specifically, the pixel electrode 30 is electrically connected to the drain electrode 162 through a via, a contact hole 50, and a through-hole.

[0081] In the thin-film transistor array substrate of this embodiment, since the exposed part of the planarization layer 18 is covered by the protective layer 192, the part of the planarization layer 18 covered by the protective layer 192 will not be damaged when the second passivation layer 20 is etched, so as to avoid the generation of reactive deposits at the bottom of the contact hole 50, thereby ensuring good connection between the pixel electrode 30 and the drain 162.

[0082] Third Embodiment

[0083] This invention provides a thin-film transistor array substrate. Figure 3a This is a schematic diagram of the thin-film transistor array substrate according to the first embodiment of the present invention. Please refer to [link / reference]. Figure 3aThe thin-film transistor array substrate of the third embodiment is basically the same in structure as that of the thin-film transistor array substrate of the first embodiment. The difference is that, in this embodiment, the thin-film transistor array substrate further includes a metal wire portion 194, which is located above the common electrode 191 and is electrically connected to the common electrode 191. Furthermore, the protective layer 192 and the metal wire portion 194 are disposed in the same layer, and the material of the protective layer 192 is metal.

[0084] In this embodiment, by providing a metal wire portion 194 in contact with the common electrode 191, the impedance of the common electrode 191 can be reduced, thereby reducing signal delay. The protective layer 192 and the metal wire portion 194 are disposed in the same layer and can be formed simultaneously. It can be understood that in another embodiment, the metal wire portion 194 can be formed between the planarization layer 18 and the common electrode 191. In yet another embodiment, the metal wire portion 194 can be omitted, the protective layer 192 is made of a metallic material, and the protective layer 192 and the common electrode 191 are formed separately.

[0085] In the thin-film transistor array substrate of this embodiment, since the exposed part of the planarization layer 18 is covered by the protective layer 192, the part of the planarization layer 18 covered by the protective layer 192 will not be damaged when the second passivation layer 20 is etched, so as to avoid the generation of reactive deposits at the bottom of the contact hole 50, thereby ensuring good connection between the pixel electrode 30 and the drain 162.

[0086] Fourth embodiment

[0087] The present invention also provides a method for fabricating a thin-film transistor array substrate. Figures 3b-3f This is a partial fabrication process diagram of the thin-film transistor array substrate according to the third embodiment of the present invention. Please refer to [link / reference]. Figures 3b-3f The method for fabricating a thin-film transistor array substrate according to the fourth embodiment includes the following steps:

[0088] S31, a substrate 11 is provided. Specifically, the substrate 11 may be a transparent glass substrate or a transparent plastic substrate.

[0089] S33, a thin-film transistor is formed on the substrate 11, the thin-film transistor including a drain 162. Specifically, step S33 may include:

[0090] S331, a first metal layer is formed on the substrate 11, and the first metal layer is patterned to form the gate 12. Specifically, the first metal layer can be patterned by etching.

[0091] S332, a gate insulating layer 13 is formed, which covers the gate 12 and the substrate 11 not covered by the gate 12. Specifically, the material of the gate insulating layer 13 may be silicon dioxide.

[0092] S333, an oxide semiconductor layer 14 is formed on the gate insulating layer 13 at the position corresponding to the gate 12. Specifically, the material of the oxide semiconductor layer 14 can be amorphous indium tin oxide.

[0093] S334, an etch barrier layer 15 is formed, which covers the oxide semiconductor layer 14 and the gate insulating layer 13 not covered by the oxide semiconductor layer 14.

[0094] S335, an opening is made in the etch barrier layer 15 to expose a portion of the surface of the oxide semiconductor layer 14.

[0095] S336, a second metal layer is formed on the etch barrier layer 15, and the second metal layer is patterned to form source electrodes 161 and drain electrodes 162 that are spaced apart from each other. The source electrodes 161 and drain electrodes 162 are respectively in contact with the oxide semiconductor layer 14. Specifically, the second metal layer can be patterned by etching.

[0096] S35, a first passivation layer 17 is formed, which covers the source 161, the drain 162, the uncovered oxide semiconductor layer 14, and the uncovered etch barrier layer 15. Specifically, the material of the first passivation layer 17 may be silicon dioxide.

[0097] Please refer to S37 as well. Figure 3a and Figure 3b A planarization layer 18 is formed, which covers the first passivation layer 17. A contact hole 50 is formed on the planarization layer 18 at a position corresponding to the drain electrode 162, exposing a portion of the surface of the first passivation layer 17. Specifically, the contact hole 50 can be formed on the planarization layer 18 by exposure and development.

[0098] S39, a common electrode 191 is formed on the planarization layer 18. The material of the common electrode 191 can be a transparent conductive material. Specifically, the material of the common electrode 191 can be indium tin oxide. Step S39 may specifically include:

[0099] S391, a first electrode layer is formed on the planarization layer 18.

[0100] S393, the first electrode layer is patterned to form a common electrode 191.

[0101] Please refer to S41 as well. Figure 3a and Figure 3cA protective layer 192 and a metal wire portion 194 are formed on the common electrode 191 and the planarization layer 18. Specifically, the protective layer 192 and the metal wire portion 194 are spaced apart and do not contact each other. The protective layer 192 at least covers the sidewall of the contact hole 50 and exposes a portion of the surface of the first passivation layer 17 at the bottom of the contact hole 50. The metal wire portion 194 is formed on the common electrode 191 and is electrically connected to the common electrode 191. Step S41 may specifically include:

[0102] S411, a metal layer is formed on the portion of the common electrode 191 and the planarization layer 18 not covered by the common electrode 191.

[0103] S413, the metal layer is patterned to form a protective layer 192 and a metal conductive portion 194. Specifically, the metal layer can be patterned by etching.

[0104] In this embodiment, processing the metal layer can simultaneously form a protective layer 192 and a metal wire portion 194, making the manufacturing process relatively simple.

[0105] S43, a second passivation layer 20 is formed, and vias are formed in the second passivation layer 20. Through-holes are formed in the first passivation layer 17 to expose a portion of the protective layer 192 and a portion of the drain electrode 162. Specifically, vias and through-holes can be formed by etching. Specifically, the material of the second passivation layer 20 can be silicon nitride. Step S43 may specifically include:

[0106] Please refer to S431 as well. Figure 3a and 3d A second passivation layer 20 is formed, and photoresist 21 is disposed on the second passivation layer 20. The second passivation layer 20 covers the metal wire portion 194, the protective layer 192, and a partial planarization layer 18.

[0107] Please refer to S433 as well. Figure 3a and 3e The second passivation layer 20 and the first passivation layer 17 are etched sequentially to form vias and through holes in the second passivation layer 20 and the first passivation layer 17, respectively, to expose part of the protective layer 192 and part of the drain electrode 162.

[0108] Please refer to S435 as well. Figure 3a and 3f A pixel electrode 30 is formed, which is located on the second passivation layer 20 and the protective layer 192. Specifically, the pixel electrode 30 is electrically connected to the drain electrode 162 through a via, a contact hole 50, and a through-hole.

[0109] In this embodiment, by providing a metal wire portion 194 that contacts the common electrode 191, the impedance of the common electrode 191 can be reduced, thereby reducing signal delay. It is understood that in another embodiment, the metal wire portion 194 can be formed between the planarization layer 18 and the common electrode 191; in yet another embodiment, the metal wire portion 194 can be omitted, and in step S41 above, only the protective layer 192 is formed by patterning the metal layer.

[0110] In the thin-film transistor array substrate of this embodiment, since the exposed part of the planarization layer 18 is covered by the protective layer 192, the part of the planarization layer 18 covered by the protective layer 192 will not be damaged when the second passivation layer 20 is etched, so as to avoid the generation of reactive deposits at the bottom of the contact hole 50, thereby ensuring good connection between the pixel electrode 30 and the drain 162.

[0111] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0112] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A thin-film transistor array substrate, characterized in that, include: Substrate (11); A thin-film transistor is formed on the substrate (11), the thin-film transistor including a drain (162). A first passivation layer (17) is formed on the thin-film transistor. A planarization layer (18) is formed on the first passivation layer (17). Contact holes (50) are formed on the planarization layer (18); A common electrode (191) and a protective layer (192) are formed on the planarization layer (18), the common electrode (191) and the protective layer (192) are spaced apart and do not contact each other, the protective layer (192) at least covers the sidewall of the contact hole (50) and exposes a portion of the surface of the first passivation layer (17) at the bottom of the contact hole (50).

2. The thin-film transistor array substrate according to claim 1, characterized in that, The common electrode (191) and the protective layer (192) are made of transparent conductive materials, and the common electrode (191) and the protective layer (192) are disposed in the same layer.

3. The thin-film transistor array substrate according to claim 1, characterized in that, The thin-film transistor array substrate further includes: A metal wire portion (194) is formed on the common electrode (191), the metal wire portion (194) is electrically connected to the common electrode (191), the protective layer (192) and the metal wire portion (194) are made of metal material, and the protective layer (192) and the metal wire portion (194) are arranged in the same layer at intervals.

4. The thin-film transistor array substrate according to claim 1, characterized in that, The protective layer (192) is made of a metallic material.

5. A method for fabricating a thin-film transistor array substrate, characterized in that, include: Provide a substrate (11); A thin-film transistor is formed on the substrate, the thin-film transistor including a drain (162). A first passivation layer (17) is formed on the thin-film transistor. A planarization layer (18) is formed on the first passivation layer (17); A contact hole (50) is made on the planarization layer (18) at the position corresponding to the drain (162) to expose part of the surface of the first passivation layer (17); A common electrode (191) and a protective layer (192) are formed on the planarization layer (18). The common electrode (191) and the protective layer (192) are spaced apart and do not contact each other. The protective layer (192) at least covers the sidewall of the contact hole (50) and exposes a portion of the surface of the first passivation layer (17) at the bottom of the contact hole (50).

6. The method for fabricating a thin-film transistor array substrate according to claim 5, characterized in that, Forming the common electrode (191) and the protective layer (192) on the planarization layer (18) specifically includes: A first electrode layer is formed on the planarization layer (18), and the first electrode layer is patterned to form the common electrode (191) and the protective layer (192).

7. The method for fabricating a thin-film transistor array substrate according to claim 6, characterized in that, The common electrode (191) and the protective layer (192) are made of transparent conductive materials.

8. The method for fabricating a thin-film transistor array substrate according to claim 5, characterized in that, Forming the common electrode (191) and the protective layer (192) on the planarization layer (18) specifically includes: A first electrode layer (19) is formed on the planarization layer (18), and the first electrode layer (19) is patterned to form the common electrode (191). A metal layer is formed on the common electrode (191), the metal layer covering the portion of the common electrode (191) and the planarization layer (18) not covered by the common electrode (191), the metal layer is patterned to form the protective layer (192) and the metal wire portion (194) electrically connected to the common electrode (191), the protective layer (192) and the metal wire portion (194) are spaced apart.

9. The method for fabricating a thin-film transistor array substrate according to claim 5, characterized in that, Forming the common electrode (191) and the protective layer (192) on the planarization layer (18) specifically includes: A first electrode layer is formed on the planarization layer (18), and the first electrode layer is patterned to form the common electrode (191). A metal layer is formed on the common electrode (191), the metal layer covering the portion of the common electrode (191) and the planarization layer (18) not covered by the common electrode (191), and the metal layer is patterned to form the protective layer (192).

10. The method for fabricating a thin-film transistor array substrate according to claim 5, characterized in that, The method for fabricating the thin-film transistor array substrate further includes: A second passivation layer (20) is formed, and a via is formed in the second passivation layer (20). A through hole is formed in the first passivation layer (17) to expose part of the protective layer (192) and part of the drain (162). A pixel electrode (30) is formed on the second passivation layer (20) and the protective layer (192), and the pixel electrode (30) is electrically connected to the drain (162).

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