Array module and display panel

Abstract

This invention provides an array module and a display panel, comprising: an array substrate and a light-emitting layer disposed on the array substrate. The array substrate has a metal layer, and the light-emitting layer includes multiple pixel regions, with pixel-defining regions formed between adjacent pixel regions. The metal layer includes at least two parallel sub-metal lines, which are stacked along the thickness direction of the array substrate. At least one sub-metal line's orthographic projection onto the light-emitting layer lies within the pixel-defining region, and the orthographic projections of the remaining sub-metal lines onto the light-emitting layer are at least partially located within the pixel regions. This avoids the influence of sub-metal lines whose orthographic projections onto the light-emitting layer lie within the pixel-defining regions on the flatness of the light-emitting layer. The array module and display panel provided by this invention can improve the flatness of the pixel regions, reduce the possibility of the anode being scratched by the mask, and ensure the display effect of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display device technology, and more particularly to an array module and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) display panels are increasingly widely used due to their advantages such as light weight, self-illumination, wide viewing angle, low driving signal, high luminous efficiency, low power consumption, and fast response speed.

[0003] In related technologies, an array module may include a substrate and a first power line, a first insulating layer, a second power line, a second insulating layer and a pixel defining layer sequentially stacked on the substrate. The first power line and the second power line are disposed opposite to each other and are located below the pixel openings of each pixel defining layer.

[0004] However, the aforementioned power lines have thickness, resulting in poor flatness at the pixel opening. This makes the anode in the pixel opening easily scratched by the mask in subsequent processes, affecting the display effect of the display panel. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention provide an array module and a display panel that can improve the flatness at the pixel opening, reduce the possibility of the anode being scratched by the mask plate, and ensure the display effect of the display panel.

[0006] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0007] A first aspect of the present invention provides an array module, comprising: an array substrate and a light-emitting layer stacked on the array substrate, wherein the array substrate has a metal layer, and the light-emitting layer includes a plurality of pixel regions, wherein a pixel-defining region is formed between adjacent pixel regions.

[0008] The metal layer includes at least two parallel sub-metal lines, which are stacked along the thickness direction of the array substrate; wherein, the orthogonal projection of at least one sub-metal line on the light-emitting layer is located within the pixel region, and the orthogonal projection of the remaining sub-metal lines on the light-emitting layer is at least partially located within the pixel region.

[0009] The array module provided in this embodiment provides an external power signal to the light-emitting layer by setting a metal layer on the array module. The metal layer is configured as at least two parallel sub-metal lines, thereby reducing the total resistance of the metal layer and mitigating the voltage difference effect caused by the metal layer, thus avoiding uneven brightness of the display panel. Specifically, at least one sub-metal line is placed in the pixel definition area to avoid affecting the flatness of the light-emitting layer in the pixel area, reducing the possibility of the anode being scratched by the mask, and thus ensuring the display effect of the display panel.

[0010] In one possible implementation, the metal layer comprises two parallel first sub-metal lines and a second sub-metal line.

[0011] In one possible implementation, a plurality of first sub-metal lines are spaced apart along a first direction of the array substrate, and the first sub-metal lines extend along a second direction of the array substrate, with the first and second directions being perpendicular to each other.

[0012] The orthographic projection of the first sub-metal line onto the light-emitting layer at least partially overlaps with a plurality of pixel regions spaced apart along the second direction in the light-emitting layer;

[0013] Preferably, the array substrate includes a plurality of driving circuit groups spaced apart along a first direction, each driving circuit group including a plurality of driving circuits spaced apart along a second direction, one driving circuit being disposed corresponding to one pixel region, and one driving circuit group being electrically connected to a first sub-metal line.

[0014] In this way, the path in the thickness direction between the driving circuit and the first sub-metal line is relatively short, and they can be directly electrically connected through vias. The process is relatively simple, so that the external power signal can be written into the driving circuit through the first sub-metal line, and then the external power signal can be input to the light-emitting layer through the driving circuit to control the light-emitting process of the light-emitting layer.

[0015] In one possible implementation, the orthographic projection of the second sub-metal line onto the light-emitting layer at least partially overlaps with the orthographic projection of the first sub-metal line onto the light-emitting layer, and the overlapping portions are all located within the pixel-defined area.

[0016] Preferably, the second sub-metal line has a gap between its orthogonal projection onto the light-emitting layer and the pixel area.

[0017] This reduces the impact of overlapping portions on the pixel area, thereby reducing the impact on the flatness of the light-emitting layer in the pixel area, thus ensuring the display effect of the display panel.

[0018] In one possible implementation, the orthogonal projection of the second sub-metal line onto the light-emitting layer comprises multiple interconnected line segments;

[0019] Multiple line segments form a mesh structure, which includes multiple mesh openings, with one pixel area located in one mesh opening;

[0020] or,

[0021] Multiple line segments include multiple first line segments and multiple second line segments, which are connected end to end in a staggered manner along a first direction, and adjacent first line segments and second line segments have an included angle;

[0022] The connection between the first line segment and the second line segment overlaps with the orthographic projection of the first sub-metal line onto the light-emitting layer.

[0023] Preferably, each pixel region has a first line segment and a second line segment distributed on its outer periphery; the multiple line segments include multiple third line segments, which are arranged one-to-one on the outer periphery of the multiple pixel regions and connected to the first line segment or the second line segment on the outer periphery of the pixel region;

[0024] The connection point of the first line segment, the second line segment and the third line segment overlaps with the orthographic projection of the first sub-metal line on the light-emitting layer;

[0025] Preferably, the orthographic projection of the second sub-metal line on the light-emitting layer includes a plurality of auxiliary line segments, which are located one-to-one between each two adjacent pixel regions distributed along the second direction, and connect the line segments between two adjacent pixel regions.

[0026] Each auxiliary line segment extends along the second direction, and multiple auxiliary line segments are arranged at intervals along the second direction to form multiple auxiliary line segment groups, and multiple auxiliary line segment groups are arranged at intervals along the first direction.

[0027] Each auxiliary line segment overlaps with a different portion of the orthographic projection of the first sub-metal line onto the light-emitting layer.

[0028] In this way, there are many ways to set the second sub-metal line, which can be applied to different arrangements of the pixel area. The orthographic projection of the first sub-metal line on the light-emitting layer and the orthographic projection of the second sub-metal line on the light-emitting layer have an overlapping part, so that the first sub-metal line and the second sub-metal line can be electrically connected through the via corresponding to the overlapping part.

[0029] In one possible implementation, the orthographic projection of the second sub-metal line onto the light-emitting layer is a plurality of unconnected line segments, each line segment extending along the second direction, and the plurality of line segments are distributed one-to-one between each two adjacent pixel regions distributed along the second direction.

[0030] Multiple line segments are arranged at intervals along the second direction to form multiple line segment groups, and multiple line segment groups are arranged at intervals along the first direction;

[0031] Each line segment overlaps with a different portion of the orthographic projection of the first sub-metal line onto the light-emitting layer.

[0032] In this way, the orthographic projection of the first sub-metal line on the light-emitting layer and the orthographic projection of the second sub-metal line on the light-emitting layer have an overlapping portion, so that the first sub-metal line and the second sub-metal line can be electrically connected through the vias corresponding to the overlapping portion, and the structure of the second sub-metal line is relatively simple and the manufacturing cost is low.

[0033] In one possible implementation, the orthographic projection of the second sub-metal line onto the light-emitting layer does not overlap with the orthographic projection of the first sub-metal line onto the light-emitting layer.

[0034] The orthographic projection of the second sub-metal line on the light-emitting layer extends along the second direction and is located between the orthographic projections of two adjacent first sub-metal lines on the light-emitting layer.

[0035] In this way, the first and second sub-metal lines do not overlap in the thickness direction, which can greatly reduce the impact of the first and second sub-metal lines on the overall flatness of the light-emitting layer.

[0036] In one possible implementation, the orthographic projection of the first sub-metal line on the light-emitting layer overlaps with the orthographic projection of the second sub-metal line on the light-emitting layer. A first via is provided on the insulating layer between the first and second sub-metal lines. The orthographic projection of the first via on the light-emitting layer is located in the overlapping portion. The first sub-metal line and the second sub-metal line are electrically connected through the first via.

[0037] In this way, the orthographic projection of the first sub-metal line on the light-emitting layer overlaps with the orthographic projection of the second sub-metal line on the light-emitting layer, so that the first sub-metal line and the second sub-metal line can be electrically connected through the first via corresponding to the overlapping part, reducing the difficulty of connecting the first sub-metal line and the second sub-metal line.

[0038] In one possible implementation, a display area and a non-display area are also included, with the non-display area located outside the display area and multiple pixel areas located inside the display area;

[0039] The non-display area includes a first bus and a second bus. The first bus is electrically connected to a plurality of first sub-metal lines, and the second bus is electrically connected to a plurality of second sub-metal lines.

[0040] A second via is provided on the insulating layer between the first sub-metal line and the second sub-metal line. The second via is located in the non-display area, and the first bus and the second bus are electrically connected through the second via.

[0041] The first bus and / or the second bus are used to connect to an external power supply.

[0042] In this way, by setting the first bus and the second bus to electrically connect the first sub-metal line and the second sub-metal line, it is not necessary to set vias in the display area to connect the first sub-metal line and the second sub-metal line, thereby reducing the number of vias in the display area and reducing the impact on the screen transmittance of the display area.

[0043] A second aspect of the present invention provides a display panel including the array module provided in the first aspect.

[0044] The display panel provided in this embodiment includes an array module. An external power signal is provided to the light-emitting layer by setting a metal layer on the array module. The metal layer is configured as at least two parallel sub-metal lines, thereby reducing the total resistance of the metal layer and mitigating the voltage difference effect caused by the metal layer, thus avoiding uneven brightness in the display panel. At least one sub-metal line is positioned within a pixel definition area to avoid affecting the flatness of the light-emitting layer in the pixel area, reducing the possibility of the anode being scratched by the mask, and thus ensuring the display effect of the display panel.

[0045] The structure of the present invention, as well as its other inventive objects and beneficial effects, will become more apparent from the description of preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 A top view of the bus of the array module provided in an embodiment of the present invention;

[0048] Figure 2 A top view of the first sub-metal line and the second sub-metal line in the display area provided in an embodiment of the present invention;

[0049] Figure 3 A cross-sectional view of the array module provided in an embodiment of the present invention;

[0050] Figure 4 for Figure 2 Cross-sectional view along the EE direction;

[0051] Figure 5 for Figure 2 Cross-sectional view along the FF direction;

[0052] Figure 6 for Figure 2 Cross-sectional view along the GG direction;

[0053] Figure 7 A top view of a second sub-metal wire provided in an embodiment of the present invention;

[0054] Figure 8 A top view of another second sub-metal wire provided in an embodiment of the present invention;

[0055] Figure 9 A top view of another second sub-metal wire provided in an embodiment of the present invention;

[0056] Figure 10 A top view of another second sub-metal wire provided in an embodiment of the present invention;

[0057] Figure 11 This is a top view of another second sub-metal wire provided in an embodiment of the present invention.

[0058] Explanation of reference numerals in the attached figures:

[0059] 100 - Array module; 100a - Display area; 100b - Non-display area;

[0060] 10 - Substrate; 20 - Metal layer; 21 - First sub-metal line;

[0061] 22-Second sub-metal wire; 221-First segment; 222-Second segment;

[0062] 223 - Third line segment; 224 - Auxiliary line segment; 30 - Light-emitting layer;

[0063] 30a - Pixel area; 30b - Pixel-defined area; 31 - Anode layer;

[0064] 32 - Pixel limiting layer; 321 - Opening; 33 - Emissive material layer;

[0065] 40 - Insulating layer; 41 - First insulating layer; 42 - Second insulating layer;

[0066] 51 - First bus; 52 - Second bus; 60 - Touch layer;

[0067] 61-Touch metal layer; 62-Inorganic isolation layer; 63-Protective layer;

[0068] 70 - Encapsulation layer; 71 - First inorganic encapsulation layer; 72 - Organic encapsulation layer;

[0069] 73 - Second inorganic encapsulation layer. Detailed Implementation

[0070] The array module may include an array substrate and a light-emitting layer disposed on the array substrate. The array substrate has a metal layer, and the light-emitting layer includes a pixel region and a pixel-defined region. An anode layer is located in the pixel region and disposed in the light-emitting layer on the side closest to the array substrate. The anode layer is electrically connected to a thin-film transistor (TFT) structure in the array substrate through vias. The metal layer can serve as an ELVDD power trace, which can be electrically connected to a driver chip, forming the external power supply for the array module. Thus, an ELVDD power signal is provided to the TFTs in the array module through the metal layer, and the TFTs input this ELVDD power signal to the light-emitting layer to control the light-emitting process of the light-emitting layer.

[0071] In related technologies, the metal layer may include a first power line and a second power line connected in parallel. The first power line is located on the side of the second power line away from the light-emitting layer. An insulating layer is provided between the first power line and the second power line, and between the second power line and the light-emitting layer, for electrically isolating the first power line and the second power line, as well as between the second power line and the light-emitting layer. The orthographic projection of the first power line on the light-emitting layer and the orthographic projection of the second power line on the light-emitting layer are both at least partially located in the pixel area.

[0072] However, to reduce the resistance of the first and second power lines, the power lines are relatively thick. Although an insulating layer is provided on the side of both the first and second power lines away from the array substrate, this insulating layer can reduce the impact of the two power lines on the flatness of the film layers above the insulating layer. However, because the insulating layer is made of organic material, it has a certain degree of deformability. Both power lines cause the insulating layer to bulge towards the side away from the array substrate. For example, the first and second power lines located below the light-emitting layer in the pixel area will form a protruding structure in the pixel area. This protruding structure causes part of the anode layer in the pixel area to bulge, resulting in poor flatness of the anode layer. The reduced flatness of the anode layer will affect the flatness of the light-emitting layer located in the pixel area, thereby affecting the display effect of the display panel. In addition, the protruding anode layer is prone to contact with the mask in subsequent processes, and being scratched by the mask will also affect the display effect of the display panel.

[0073] To address the aforementioned technical problems, embodiments of the present invention provide an array module and a display panel. By providing an external power signal to the light-emitting layer through a metal layer on the array module, and by configuring the metal layer as at least two parallel sub-metal lines, the total resistance of the metal layer is reduced, thereby mitigating the voltage difference effect caused by the metal layer and preventing uneven brightness of the display panel. Specifically, at least one sub-metal line is positioned within a pixel definition area to avoid affecting the flatness of the light-emitting layer in the pixel area, reducing the possibility of the anode layer being scratched by the mask during subsequent processes, thus ensuring the display effect of the display panel.

[0074] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions of the present invention will be described in more detail below with reference to the accompanying drawings of the preferred embodiments. In the drawings, the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of the present invention. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0075] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0076] This invention provides an array module 100, such as... Figure 1 and Figure 2 As shown, the array module 100 includes a display area 100a and a non-display area 100b, with the non-display area 100b surrounding the display area 100a.

[0077] like Figure 3 As shown, the array module 100 includes an array substrate and a light-emitting layer 30 disposed on the array substrate. A metal layer 20 is disposed in the array substrate. The metal layer 20 is used to input the ELVDD power signal to the light-emitting layer 30. An insulating layer 40 is disposed on the side of the metal layer 20 near the light-emitting layer 30 so that the metal layer 20 and the light-emitting layer 30 are electrically insulated from each other through the insulating layer 40.

[0078] The array substrate may include a substrate 10 and TFTs (not shown) located on the substrate 10. The TFTs are located on the side of the metal layer 20 facing the substrate 10, and the light-emitting layer 30 is located on the side of the metal layer 20 away from the substrate 10. That is, the TFTs, the metal layer 20, and the light-emitting layer 30 are sequentially stacked on the substrate 10. The substrate 10 may be made of rigid transparent glass or a light-transmitting material such as polyimide (PI) or ethylene terephthalate (PET). The substrate 10 provides support for the remaining structural layers that are subsequently disposed. The substrate 10 and the structural layers between the substrate 10 and the light-emitting layer 30 can together form the array substrate.

[0079] Metal layer 20 can be a metal trace that provides the ELVDD power signal, and metal layer 20 can be electrically connected to an external power chip. The power chip provides the ELVDD power signal to the TFT in the array module 100 through metal layer 20. The TFT inputs the ELVDD power signal to the light-emitting layer 30 to control the light-emitting process of the light-emitting layer.

[0080] The metal layer 20 includes at least two parallel sub-metal lines. An insulating layer 40 is provided between each sub-metal line and between the metal layer 20 and the light-emitting layer 30 to electrically insulate the sub-metal lines and between the metal layer 20 and the light-emitting layer 30. The parallel sub-metal lines have lower resistance than any single sub-metal line, thus reducing the total resistance of the metal layer 20. At least two sub-metal lines are stacked along the thickness direction of the array substrate. Since the light-emitting layer 30 requires high flatness, otherwise its light-emitting effect will be affected, impacting the display panel's performance. Therefore, the insulating layer 40 between the metal layer 20 and the light-emitting layer 30 can be an insulating layer with a flattening effect to reduce the impact of each sub-metal line on the flatness of the light-emitting layer 30 and ensure the display panel's performance.

[0081] like Figure 2 As shown, the light-emitting layer 30 may include multiple pixel areas 30a, and a pixel defining area 30b is formed between adjacent pixel areas 30a. Each pixel area 30a is located within the display area 100a. The light-emitting layer 30 in the pixel area 30a is the light-emitting unit of the array module 100. Therefore, when the flatness of the light-emitting layer 30 in the pixel area 30a is poor, it will affect the display effect of the display panel.

[0082] The number of sub-metal lines can be two, three, four, or five, etc., and this application does not limit the number of sub-metal lines. The number of sub-metal lines whose orthogonal projection on the light-emitting layer 30 is located within the pixel-defined region 30b can be one, two, three, or four, etc., and this application does not limit this number.

[0083] In a specific implementation, at least one sub-metal line has its orthogonal projection on the light-emitting layer 30 located within the pixel-defined region 30b. In this way, the sub-metal line whose orthogonal projection on the light-emitting layer 30 is located within the pixel-defined region 30b will not affect the flatness of the light-emitting layer 30 in the pixel region 30a, thereby improving the flatness of the light-emitting layer 30 and reducing the possibility of the anode layer being scratched by the mask in subsequent processes, so as to ensure the display effect of the display panel.

[0084] For example, the sub-metal line closest to the light-emitting layer 30 does not overlap with the light-emitting layer 30 in the thickness direction in the pixel region 30a. Since the insulating layer between each sub-metal line also has a certain planarization effect, the sub-metal line closest to the light-emitting layer 30 has a greater impact on the planarity of the light-emitting layer 30, while the sub-metal lines in the other layers have a relatively smaller impact on the planarity of the light-emitting layer 30. This configuration can effectively improve the planarity of the light-emitting layer 30. Of course, other sub-metal lines can also be configured to not overlap with the light-emitting layer 30 in the thickness direction, thereby improving the planarity of the light-emitting layer 30 and providing more options for the configuration of the metal layer 20.

[0085] In some embodiments, the orthogonal projection of at least one sub-metal line onto the light-emitting layer 30 is at least partially located within the pixel region 30a (excluding sub-metal layers whose orthogonal projection onto the light-emitting layer 30 is located within the pixel-defined region 30b). Since the TFT can be disposed opposite to the pixel region 30a, the sub-metal line whose orthogonal projection onto the light-emitting layer 30 is at least partially located in the pixel region 30a can be electrically connected to the TFT via a via.

[0086] For example, the sub-metal line closest to the TFT is partially overlapped with the pixel region 30a in the thickness direction. This facilitates the electrical connection between the metal layer 20 and the TFT through vias and reduces the impact on the layout of other sub-metal lines. Alternatively, the orthogonal projections of other sub-metal lines can be at least partially located within the pixel region 30a, thus providing more options for the arrangement of the metal layer 20.

[0087] It is understandable that the TFT can also have a portion of its structure overlapping the pixel-defined region 30b along the thickness direction of the array module 100, and the sub-metal lines can also be electrically connected through this portion of the TFT's structure. In this case, the orthogonal projection of all the sub-metal lines in the metal layer 20 onto the light-emitting layer 30 can be placed in the pixel-defined region 30b, which can effectively reduce the impact of the metal layer 20 on the flatness of the light-emitting layer 30 in the pixel region 30a.

[0088] This application describes in detail the metal layer 20, which includes two sub-metal lines.

[0089] like Figures 4-6 As shown, the metal layer 20 may include a first sub-metal line 21 and a second sub-metal line 22 connected in parallel. The first sub-metal line 21 is the sub-metal line away from the light-emitting layer 30, and the second sub-metal line 22 is the sub-metal line close to the light-emitting layer 30. Because the two sub-metal lines are connected in parallel, the resistance of the metal layer 20 is relatively low.

[0090] In this configuration, the orthographic projection of the first sub-metal line 21 onto the light-emitting layer 30 lies within the pixel-defined region 30b, thus avoiding any impact of the first sub-metal line 21 on the flatness of the light-emitting layer 30 in the pixel region 30a. Alternatively, the orthographic projection of the second sub-metal line 22 onto the light-emitting layer 30 lies within the pixel-defined region 30b, thereby avoiding any impact of the second sub-metal line 22 on the flatness of the light-emitting layer 30 in the pixel region 30a. Alternatively, the orthographic projections of both the first sub-metal line 21 and the second sub-metal line 22 onto the light-emitting layer 30 lie within the pixel-defined region 30b, thereby further improving the flatness of the light-emitting layer 30 in the pixel region 30a.

[0091] This application provides a detailed description of the second sub-metal line 22, whose orthogonal projection on the light-emitting layer 30 is located within the pixel region 30b, and the first sub-metal line 21, whose orthogonal projection on the light-emitting layer 30 is at least partially located in the pixel region 30a.

[0092] A first insulating layer 41 is disposed between the first sub-metal line 21 and the second sub-metal line 22, and a second insulating layer 42 is disposed between the second sub-metal line 22 and the light-emitting layer 30. The first insulating layer 41 and the second insulating layer 42 can be insulating layers with a planarization effect. The insulating layer 40 can form a planar structure below the pixel region 30a and the pixel-defined region 30b for both to be disposed. This reduces the influence of the structure below the pixel region 30a and the pixel-defined region 30b on the planarity of the light-emitting layer 30 therein.

[0093] like Figure 5As shown, a pixel defining layer 32 is provided in the light-emitting layer 30, and the opening 321 on the pixel defining layer 32 can form a pixel region 30a. The pixel defining layer 32 surrounding the opening 321 can form a pixel defining region 30b. The opening 321 may include an anode layer 31, a light-emitting material layer 33, and a cathode layer (not shown), as well as an electron blocking layer and a hole transport layer (not shown) located between the anode layer 31 and the light-emitting material layer 33, and a hole blocking layer and an electron transport layer (not shown) located between the cathode layer and the light-emitting material layer 33. This embodiment does not limit the specific structure of the light-emitting layer. The anode layer 31 is located on the side of the light-emitting material layer 33 closer to the second insulating layer 42, and the cathode layer is located on the side of the light-emitting material layer 33 away from the second insulating layer 42. The anode layer 31 and the cathode layer can provide electrical signals to the light-emitting material layer 33 to ensure the normal light emission of the light-emitting material layer 33.

[0094] The anode layer 31 in pixel region 30a can be connected to the TFT structure in the array substrate. The input of electrical signals in the anode layer 31 can be controlled by the TFT structure, thereby controlling the light emission process of the light-emitting material layer 33.

[0095] In this embodiment, as Figure 2 As shown, the section line EE in the figure represents the overlapping portion of the orthographic projection of the first sub-metal line 21 onto the light-emitting layer 30 and the orthographic projection of the second sub-metal line 22 onto the light-emitting layer 30 (e.g., Figure 4 As shown). In the figure, the FF cross-section line represents the orthogonal projection of the first sub-metal line 21 onto the light-emitting layer 30, located within the pixel region 30a, and offset from the second sub-metal line 22 in the thickness direction of the array module 100 (e.g.). Figure 5 (As shown). In the figure, the GG cross-section line represents the portion where the orthogonal projection of the second sub-metal line 22 onto the light-emitting layer 30 is located within the pixel-defined region 30b, and is offset from the first sub-metal line 21 in the thickness direction of the array module 100 (e.g., Figure 6 (As shown). At least a portion of the orthographic projection of the first sub-metal line 21 onto the light-emitting layer 30 lies within the pixel region 30a, so that the first sub-metal line 21 can be electrically connected to the driving circuit (i.e., TFT) in the array substrate through vias. The orthographic projections of the second sub-metal lines 22 onto the light-emitting layer 30 are all located within the pixel defining region 30b. The second sub-metal lines 22 and the pixel region 30a do not overlap in the thickness direction of the array module 100, reducing the impact of the second sub-metal lines 22 on the flatness of the light-emitting layer 30 in the pixel region 30a, thereby ensuring the display effect of the display panel.

[0096] In addition, such as Figure 5As shown, if the height difference between the anode layer 31 and the pixel limiting layer 32 in the pixel limiting region 30b in the thickness direction of the array substrate is small, during the formation of structural layers such as the light-emitting material layer 33 on the anode layer 31, the metal mask strip in the mask plate is prone to rigid contact with the anode layer 31, thereby scratching the anode layer 31, causing dark spot defects, affecting product yield, and even affecting the reliability of the display panel. In this embodiment, the orthogonal projection of the second sub-metal line 22 on the light-emitting layer 30 is all located within the pixel limiting region 30b, the anode layer 31 in the pixel region 30a is relatively flat, and the height difference between the anode layer 31 and the pixel limiting layer 32 in the pixel limiting region 30b is large, reducing the possibility of the anode layer 31 being scratched.

[0097] It should be noted that, as Figure 2 As shown in the figure, the X direction is the first direction of the array module 100, and the Y direction is the second direction of the array module 100. The first direction X can be perpendicular to the second direction Y.

[0098] In this embodiment, as Figure 2 As shown, there can be multiple first sub-metal lines 21, which are arranged at intervals along the first direction X of the array substrate. Each first sub-metal line 21 extends along the second direction Y of the array substrate, that is, the length extension direction of the first sub-metal line 21 is the second direction Y. In this way, the structure of the first sub-metal line 21 is relatively simple and the manufacturing cost is low. The first sub-metal line 21 can extend from the display area 100a to the non-display area 100b, which facilitates the connection with the external ELVDD power signal.

[0099] like Figure 7 As shown, the dashed box A in the figure includes multiple pixel areas 30a, which form a pixel group. These pixel areas 30a are arranged at intervals along the second direction Y. The light-emitting layer 30 may include multiple pixel groups, which are arranged at intervals along the first direction X. One of the first sub-metal lines 21 is positioned opposite to one of the pixel groups; that is, the orthographic projection of one of the first sub-metal lines 21 onto the light-emitting layer 30 lies within one of the pixel groups.

[0100] It should be noted that in this embodiment, "spaced arrangement," for example, multiple pixel areas 30a in a pixel group arranged spaced apart along the second direction Y, refers to a configuration where there is a gap between each pair of adjacent pixel areas 30a, and they do not touch each other. Adjacent pixel areas 30a can be separated by a pixel limiting layer 32. In other words, "spaced arrangement" means that there is a gap between each pair of adjacent structures, and they do not touch each other.

[0101] In one optional embodiment, the array substrate includes multiple driving circuits (TFTs), each corresponding to a plurality of pixel regions 30a. A pixel region group can correspond to multiple driving circuits spaced apart along a second direction Y, forming a driving circuit group along the second direction Y. One driving circuit group is positioned opposite to one of the first sub-metal lines 21, and each driving circuit in the driving circuit group is electrically connected to the oppositely positioned first sub-metal line 21. This results in a shorter thickness path between the driving circuit in the driving circuit group and the first sub-metal line 21, allowing for direct connection vias between layers. This simplifies the process and facilitates the input of the ELVDD power signal to the driving circuit through the first sub-metal line 21.

[0102] In some embodiments, the orthographic projection of the second sub-metal line 22 onto the light-emitting layer 30 at least partially overlaps with the orthographic projection of the first sub-metal line 21 onto the light-emitting layer 30, so that the first sub-metal line 21 and the second sub-metal line 22 are connected through vias in the overlapping portion. Furthermore, the overlapping portions are both located within the pixel definition area 30b, avoiding the overlapping portion being located in the pixel area 30a, which would result in poor flatness of the light-emitting layer 30 in the pixel area 30a, thus reducing the impact of the overlapping portion on the display effect of the display panel.

[0103] In this design, a first via is provided in the insulating layer 40 between the first sub-metal line 21 and the second sub-metal line 22, through which the first sub-metal line 21 and the second sub-metal line 22 are electrically connected. A metal connector can be deposited in the first via to electrically connect the first sub-metal line 21 and the second sub-metal line 22 together. This results in a shorter path in the thickness direction of the overlapping portion of the first sub-metal line 21 and the second sub-metal line 22, allowing for direct connection via the first via, simplifying the process. Furthermore, since the first via is located within the pixel definition area 30b, it avoids affecting the light-emitting layer 30 in the pixel area 30a, ensuring the display quality of the display panel.

[0104] In one alternative implementation, such as Figure 7 As shown, there is a gap between the orthogonal projection of the second sub-metal line 22 on the light-emitting layer 30 and the pixel region 30a. Since the second sub-metal line 22 causes the second insulating layer 42 to bulge in the direction away from the substrate 10, when there is a gap between the orthogonal projection of the second sub-metal line 22 on the light-emitting layer 30 and the pixel region 30a, the bulge is a certain distance away from the pixel region 30a, and has a small impact on the flatness of the pixel region 30a.

[0105] By placing the second sub-metal line 22 in the region opposite to the pixel definition region 30b, the influence of the second sub-metal line 22 on the flatness of the light-emitting layer 30 in the pixel region 30a can be avoided. The placement method of the second sub-metal line 22 can include the following implementation methods:

[0106] As a first achievable implementation of the second sub-metal line 22, such as Figure 7 As shown, the orthographic projection of the second sub-metal line 22 onto the light-emitting layer 30 includes multiple interconnected line segments, which form a mesh structure. In other words, the orthographic projection of the second sub-metal line 22 onto the light-emitting layer 30 is a mesh structure, which includes multiple mesh openings, with each pixel region 30a correspondingly located within one of these openings. This results in a larger area for the mesh structure of the second sub-metal line 22, providing more options for via connections between the second sub-metal line 22 and other structural layers, allowing for more flexible connection schemes. Furthermore, the second sub-metal line 22 has a lower resistance, reducing the voltage drop effect it introduces.

[0107] As a second achievable implementation of the second sub-metal line 22, such as Figure 8 As shown, there can be multiple second sub-metal lines 22, which extend along the first direction X. In this way, the second sub-metal lines 22 can extend from the display area 100a to the non-display area 100b, facilitating connection to an external ELVDD power signal.

[0108] The orthographic projection of a second sub-metal line 22 onto the light-emitting layer 30 comprises multiple interconnected line segments. These segments include multiple first line segments 221 and multiple second line segments 222, which are sequentially staggered along a first direction X, with adjacent first and second line segments 221 and 222 forming an angle. This avoids overlap between the first and second line segments 221 and 222 and the pixel area 30a, reducing their impact on the flatness of the pixel area 30a. The connection point between the first and second line segments 221 and 222 overlaps with the first sub-metal line 21. The first and second sub-metal lines 21 and 222 can be connected via vias at the overlapping portion, making the connection relatively convenient.

[0109] It should be noted that the included angle between adjacent first line segment 221 and multiple second line segments 222 can be adjusted according to the shape of the pixel-defined area 30b to ensure that the first line segment 221 and the second line segment 222 can adapt to the shape of the pixel-defined area 30b and be better distributed in the pixel-defined area 30b.

[0110] like Figure 8As shown, the extension direction of each first sub-metal line 21 is the second direction Y, and the extension direction of each second sub-metal line 22 is the first direction X. The length extension directions of the first sub-metal line 21 and the second sub-metal line 22 are completely different, which better reduces the influence of the two on the flatness of the light-emitting layer 30 and is beneficial to the uniformity of the display panel.

[0111] As a third possible implementation of the second sub-metal line 22, such as Figure 9 As shown, in Figure 8 Based on this, each pixel region 30a has a first line segment 221 and a second line segment 222 distributed around its outer periphery. In addition, multiple line segments include multiple third line segments 223, which are correspondingly disposed around the outer periphery of the pixel regions 30a and connected to the first line segment 221 or the second line segment 222 around the outer periphery of that pixel region 30a. In this embodiment, the third line segment 223 increases the area of ​​the first line segment 221 and the second line segment 222, thereby increasing the area of ​​the second sub-metal line 22. When the second sub-metal line 22 is connected to other structural layers vias, there are more available locations, and the connection scheme is more flexible.

[0112] It should be noted that the third line segment 223 can be... Figure 9 The line segment 221 shown in the figure can also be connected to the second line segment 222. The angle between the third line segment 223 and the first line segment 221, as well as the angle between the third line segment 223 and the second line segment 222, can also be adjusted according to the shape of the pixel-defined area 30b to ensure that the first line segment 221, the second line segment 222, and the third line segment 223 can adapt to the shape of the pixel-defined area 30b and be better distributed in the pixel-defined area 30b.

[0113] The connection point of the first line segment 221, the second line segment 222, and the third line segment 223 overlaps with the orthographic projection of the first sub-metal line 21 on the light-emitting layer 30. The first sub-metal line 21 and the second sub-metal line 22 can be connected through vias at the overlapping portion, which is relatively convenient.

[0114] Furthermore, when the first line segment 221 and the second line segment 222 form a shape like... Figure 8 When the second sub-metal line 22 is shown, multiple third segments 223 are provided between two adjacent second sub-metal lines 22 (e.g., Figure 9 (in the middle), so that two adjacent second sub-metal wires 22 can be connected. This is equivalent to, the third segment 223 can... Figure 8 By connecting the various second sub-metal lines 22 in parallel, the total resistance of the second sub-metal lines 22 can be reduced, thereby reducing the voltage difference effect caused by the second sub-metal lines 22.

[0115] In some implementations, such as Figure 2 As shown, the orthographic projection of the second sub-metal line 22 onto the light-emitting layer 30 may further include multiple auxiliary line segments 224. These auxiliary line segments 224 are located one-to-one between each pair of adjacent pixel regions 30a distributed along the second direction Y, and connect the adjacent pixel regions 30a. Each auxiliary line segment 224 extends along the second direction Y. This further increases the area of ​​the line segments, resulting in a larger area for the second sub-metal line 22. When the second sub-metal line 22 is connected to other structural layers vias, there are more available locations, and the connection scheme is more flexible.

[0116] like Figure 2 The dashed box C includes multiple auxiliary line segments 224, which form an auxiliary line segment group. These auxiliary line segments 224 are spaced apart along the second direction Y to form an auxiliary line segment group. The second sub-metal line 22 has multiple auxiliary line segment groups, which are spaced apart along the first direction X. Each auxiliary line segment 224 overlaps with a different portion of the orthographic projection of the first sub-metal line 21 onto the light-emitting layer 30. In this way, the auxiliary line segments 224 increase the overlap area of ​​the first sub-metal line 21 and the second sub-metal line 22 in the thickness direction, allowing for greater flexibility in the placement of the first via between the first sub-metal line 21 and the second sub-metal line 22.

[0117] It should be noted that the auxiliary line segment 224 can be applied to the various embodiments of the second sub-metal line 22 described above, but the auxiliary line segment 224 is not a necessary structure for the second sub-metal line 22. In practical applications, it is possible to select whether to provide the auxiliary line segment 224 and in which embodiment it is provided, as needed.

[0118] As another possible implementation of the second sub-metal line 22, such as Figure 10 As shown, the orthographic projection of the second sub-metal line 22 onto the light-emitting layer 30 consists of multiple unconnected line segments. These line segments are located one-to-one between every two adjacent pixel regions 30a distributed along the second direction Y, and each line segment extends along the second direction Y. This results in a relatively simple structure for the second sub-metal line 22 and lower manufacturing costs.

[0119] like Figure 10 The dashed box D in the diagram includes multiple line segments, which are arranged at intervals along the second direction Y to form a line segment group. The second sub-metal line 22 includes multiple line segment groups, which are arranged at intervals along the first direction X. Each line segment overlaps with a different portion of the orthographic projection of the first sub-metal line 21 onto the light-emitting layer 30. The first sub-metal line 21 and the second sub-metal line 22 can be connected through vias at the overlapping portion, making the connection relatively convenient.

[0120] As another possible implementation of the second sub-metal line 22, such as Figure 11 As shown, the orthographic projection of the second sub-metal line 22 onto the light-emitting layer 30 does not overlap with the orthographic projection of the first sub-metal line 21 onto the light-emitting layer 30. The orthographic projection of the second sub-metal line 22 onto the light-emitting layer 30 extends along the second direction Y and is located between the orthographic projections of two adjacent first sub-metal lines 21 onto the light-emitting layer 30. Since the overlap of the first sub-metal lines 21 and 22 in the thickness direction has a significant impact on the flatness of the light-emitting layer 30, ensuring that the first sub-metal lines 21 and 22 do not overlap in the thickness direction can greatly reduce the impact of the first sub-metal lines 21 and 22 on the overall flatness of the light-emitting layer 30.

[0121] It should be noted that the first sub-metal line 21 and the second sub-metal line 22 do not overlap in the thickness direction, and their paths in the thickness direction of the array substrate are relatively long. Other structural layers are required in conjunction with the first via to connect the first sub-metal line 21 and the second sub-metal line 22, making the process complex and affecting the thickness of the array module 100. To connect the first sub-metal line 21 and the second sub-metal line 22 in parallel, a bus can be set in the non-display area 100b for connection.

[0122] like Figure 1 As shown, the bus may include a first bus 51, which is electrically connected to all the first sub-metal lines 21.

[0123] Additionally, the bus can also include a second bus 52, which is electrically connected to all the second sub-metal lines 22. A second via is provided in the insulating layer 40 between the first sub-metal line 21 and the second sub-metal line 22. The second via is located in the non-display area 100b, and the first bus 51 and the second bus 52 are electrically connected through the second via. This allows the first sub-metal line 21 and the second metal line 22 to be connected in parallel via the first bus 51 and the second bus 52.

[0124] If a first via is provided in the display area 100a to connect the first sub-metal line 21 and the second sub-metal line 22, the metal connector at the line switching point would need to cover the via, resulting in a larger area for the metal connector at the first via. This would affect the screen transmittance of the display area 100a, which is detrimental to the design of under-display fingerprint recognition products. Using a bus to connect the first sub-metal line 21 and the second sub-metal line 22 in parallel avoids the need for a first via in the display area 100a, reducing the impact on the screen transmittance of the display area 100a.

[0125] It should be noted that in embodiments where the orthographic projection of the second sub-metal line 22 on the light-emitting layer 30 consists of multiple unconnected line segments, it is impossible to electrically connect all the second sub-metal lines 22 together via the second bus 52. Therefore, the second bus 52 cannot be configured, and the first sub-metal line 21 and the second sub-metal line 22 cannot be connected in parallel via the first bus 51 and the second bus 52. The first sub-metal line 21 and the second sub-metal line 22 need to be connected in parallel through the first via. In other embodiments, the second sub-metal line 22 can extend to the non-display area 100b to connect with the second bus 52. Therefore, the second sub-metal line 22 in other embodiments can be electrically connected to the second bus 52.

[0126] In all the above embodiments, the first sub-metal line 21 can extend to the non-display area 100b, thereby achieving an electrical connection with the first bus 51.

[0127] When the first sub-metal line 21 and the second sub-metal line 22 are connected in parallel via the first bus 51 and the second bus 52, a first via may not be provided between the first sub-metal line 21 and the second sub-metal line 22. This avoids the impact of the first via on the transmittance of the display area 100a. In other examples, when the first sub-metal line 21 and the second sub-metal line 22 are connected in parallel via the first bus 51 and the second bus 52, a first via may also be provided between the first sub-metal line 21 and the second sub-metal line 22. In this way, there are more vias between the first sub-metal line 21 and the second sub-metal line 22, and the parallel structure has better stability.

[0128] At least one of the first bus 51 and the second bus 52 must be configured to input the ELVDD power signal into the TFT. When only one bus is configured, the first sub-metal line 21 and the second sub-metal line 22 need to be electrically connected through a first via. This embodiment does not limit the configuration of the bus or the first via. When only one of the first bus 51 and the second bus 52 is configured, that bus needs to be connected to an external power chip to input the ELVDD power signal into the TFT. When both the first bus 51 and the second bus 52 are configured, one bus can be connected to the external power chip, or both buses can be connected to the external power chip to input the ELVDD power signal into the TFT. This embodiment does not limit this.

[0129] Specifically, the sub-metal line can extend from the display area 100a to the non-display area 100b. For example, the first sub-metal line 21 can extend along the second direction Y into the non-display area 100b, and the first bus 51 can be disposed at one end of the array module 100 in the second direction Y. Figure 1In this configuration, the first bus 51 is positioned at the upper or lower end of the array module 100. Alternatively, the first bus 51 can be positioned at both ends of the array module 100. In other examples, the first bus 51 can also be arranged around the periphery of the display area 100a, forming a ring-shaped structure. This allows for various connection schemes between the first bus 51 and the first sub-metal line 21. The second bus 52 is configured similarly to the first bus 51 and will not be described further.

[0130] The configuration of the first bus 51 and the second bus 52 can be the same or different.

[0131] In some embodiments, such as Figure 6 As shown, a touch layer 60 is disposed on the side of the light-emitting layer 30 away from the array substrate. The touch layer 60 includes a touch metal layer 61. The orthographic projection of the touch metal layer 61 onto the light-emitting layer 30 can be located within the pixel-defined region 30b to avoid the influence of the touch metal layer 61 on the pixel aperture ratio. Specifically, within the pixel-defined region 30b, the orthographic projection of the touch metal layer 61 onto the light-emitting layer 30 at least partially overlaps with the orthographic projection of the sub-metal line onto the light-emitting layer 30. With this arrangement, the overall area of ​​the orthographic projections of the touch metal layer 61 and the sub-metal line within the pixel-defined region 30b is smaller, thereby reducing the area of ​​the pixel-defined region 30b and improving the pixel aperture ratio.

[0132] The touch layer 60 may also include an inorganic isolation layer 62, which is located on the side of the touch metal layer 61 close to the array substrate. The touch metal layer 61 is electrically insulated from other structural layers in the touch layer 60 through the inorganic isolation layer 62.

[0133] A protective layer 63 may be provided on the side of the touch metal layer 61 facing away from the array substrate. The protective layer 63 may be an OC adhesive, which protects the touch metal layer 61. An encapsulation layer 70 may be provided between the touch layer 60 and the light-emitting layer 30. The encapsulation layer 70 may include a first inorganic encapsulation layer 71, an organic encapsulation layer 72, and a second inorganic encapsulation layer 73 stacked sequentially.

[0134] In addition, this application also provides a display panel, which may include the array module 100 in the above embodiments. The display panel may also include a cover plate, which is located on the side of the touch layer 60 away from the array substrate, and the cover plate protects the array module 100.

[0135] In the description of the embodiments of the present invention, it should be understood that the terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In the description of the present invention, "a plurality of" means two or more, unless otherwise precisely specified.

[0136] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0137] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An array module, characterized in that, include: An array substrate and a light-emitting layer disposed on the array substrate, the array substrate having a metal layer, the light-emitting layer including a plurality of pixel regions, and a pixel-defining region formed between adjacent pixel regions; the light-emitting layer having a pixel-defining layer, and the pixel region being formed by an opening on the pixel-defining layer; The metal layer includes at least two parallel sub-metal lines, and the at least two sub-metal lines are stacked along the thickness direction of the array substrate; wherein, the orthographic projection of at least one sub-metal line on the light-emitting layer is located within the pixel definition area, and the orthographic projections of the remaining sub-metal lines on the light-emitting layer are at least partially located within the pixel area; The metal layer includes two parallel-connected first sub-metal lines and second sub-metal lines; Multiple first sub-metal wires are arranged at intervals along a first direction, and the first sub-metal wires extend along a second direction, with the first direction and the second direction being perpendicular to each other; The orthographic projection of the second sub-metal line on the light-emitting layer at least partially overlaps with the orthographic projection of the first sub-metal line on the light-emitting layer, and the overlapping portions are both located within the pixel definition area; Along the second direction, a pixel region is provided between two adjacent overlapping portions.

2. The array module according to claim 1, characterized in that, The orthographic projection of the first sub-metal line onto the light-emitting layer at least partially overlaps with the plurality of pixel regions spaced apart along the second direction in the light-emitting layer.

3. The array module according to claim 2, characterized in that, The array substrate includes a plurality of driving circuit groups spaced apart along the first direction. Each driving circuit group includes a plurality of driving circuits spaced apart along the second direction. One driving circuit is correspondingly disposed to one pixel region. One driving circuit group is electrically connected to one of the first sub-metal lines.

4. The array module according to claim 3, characterized in that, The second sub-metal line has a gap between its orthogonal projection onto the light-emitting layer and the pixel area.

5. The array module according to claim 4, characterized in that, The orthographic projection of the second sub-metal line onto the light-emitting layer includes multiple interconnected line segments; The multiple line segments form a mesh structure, the mesh structure including multiple mesh openings, and a pixel region is located in one of the mesh openings; or, The plurality of line segments include a plurality of first line segments and a plurality of second line segments, which are connected end to end in a staggered manner along the first direction, and adjacent first line segments and second line segments have an included angle; the connection point of the first line segment and the second line segment overlaps with the orthographic projection of the first sub-metal wire on the light-emitting layer.

6. The array module according to claim 5, characterized in that, Each pixel region has a first line segment and a second line segment distributed on its outer periphery; the multiple line segments include multiple third line segments, which are disposed one-to-one on the outer periphery of the multiple pixel regions and connected to the first line segment or the second line segment on the outer periphery of the pixel region; the connection point of the first line segment, the second line segment and the third line segment overlaps with the orthographic projection of the first sub-metal line on the light-emitting layer.

7. The array module according to claim 5, characterized in that, The orthographic projection of the second sub-metal line onto the light-emitting layer includes a plurality of auxiliary line segments, one of which is located between two adjacent pixel regions distributed along the second direction and connects the line segments between the two adjacent pixel regions. Each of the auxiliary line segments extends along the second direction, and the multiple auxiliary line segments are arranged at intervals along the second direction to form multiple auxiliary line segment groups, and the multiple auxiliary line segment groups are arranged at intervals along the first direction; Each of the auxiliary line segments overlaps with a different portion of the orthographic projection of the first sub-metal line onto the light-emitting layer.

8. The array module according to claim 4, characterized in that, The orthographic projection of the second sub-metal line onto the light-emitting layer is a plurality of unconnected line segments, each of which extends along the second direction, and the plurality of line segments are distributed one-to-one between each two adjacent pixel regions distributed along the second direction. Multiple line segments are arranged at intervals along the second direction to form multiple line segment groups, and multiple line segment groups are arranged at intervals along the first direction; Each of the line segments overlaps with a different portion of the orthographic projection of the first sub-metal line onto the light-emitting layer.

9. The array module according to any one of claims 4-8, characterized in that, A first via is provided on the insulating layer between the first sub-metal line and the second sub-metal line. The orthographic projection of the first via on the light-emitting layer is located in the overlapping portion. The first sub-metal line and the second sub-metal line are electrically connected through the first via.

10. The array module according to any one of claims 2-7, characterized in that, It also includes a display area and a non-display area, wherein the non-display area is located around the display area and the plurality of pixel areas are located within the display area; The non-display area includes a first bus and a second bus, wherein the first bus is electrically connected to a plurality of first sub-metal lines and the second bus is electrically connected to a plurality of second sub-metal lines; A second via is provided on the insulating layer between the first sub-metal line and the second sub-metal line. The second via is located in the non-display area, and the first bus and the second bus are electrically connected through the second via. The first bus and / or the second bus are used for electrical connection to an external power source.

11. A display panel, characterized in that, It includes at least the array module according to any one of claims 1-10.

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