A multi-parallel IPM fault protection device, system and method

Abstract

The present invention discloses a multi-parallel IPM fault protection device, system and method, the device comprises a main control module and a fault identification and positioning module connected to each other, the fault identification and positioning module comprises a first level conversion unit and a latch unit connected to each other, the input end of the latch unit is connected to the fault signal of multiple parallel connected IPMs for latching, the latch signal is level converted by the first level conversion unit, and then output to the main control module, and the main control module performs fault identification and positioning. The present invention can realize the fault protection of multiple parallel IPMs at the same time, and has the advantages of simple structure, low cost, high fault protection efficiency and accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of IPM (Intelligent Power Module) fault protection, and in particular to a multi-parallel IPM fault protection device, system and method. Background Art

[0002] IPM (Intelligent Power Module) integrates power switch devices and drive circuits, and also integrates short circuit protection, undervoltage protection and other fault output circuits and device temperature output functions. It not only has the advantages of high current density, low saturation voltage and high voltage resistance of GTR (high power transistor), but also has the advantages of high input impedance, high switching frequency and low drive power of MOSFET (field effect transistor). IPM also has fault self-diagnosis and protection functions. When a fault occurs, it can output a fault signal to ensure that it is not damaged.

[0003] In the case of special loads, multiple IPMs are usually required to be used in parallel to drive the load together. Since IPMs integrate many components internally, the components are interrelated and affect each other, and various types of failures may occur during use. The anti-interference ability of parallel IPMs will become worse. Once an IPM fails, it may affect the stability and reliability of the entire system, which is not conducive to the stable operation of the entire system. Therefore, it is very necessary to provide accurate and effective fault protection for parallel IPMs.

[0004] As for the fault protection of IPM, currently, the fault protection method is usually for a single IPM, that is, the fault signal output by each single IPM is monitored and identified. However, when this method is applied to multiple IPMs in parallel, since each IPM will continue to output signals, the output signal may be a normal signal output by the IPM, or it may be a fault feedback signal. The fault feedback signal sent by the IPM is usually maintained for a short time, which is in the microsecond level (≥20us). It takes a certain amount of time for the fault feedback signal to be sent and transmitted to the processor detection and identification end. In addition, since the processor program running cycle has a certain time, it is easy for the detection and identification end to fail to detect the fault feedback signal with a short maintenance time, resulting in missed detection, thereby failing to achieve the purpose of timely protection of the IPM.

[0005] For example, Chinese patent application CN201210298006.2 discloses a DSP-based induction motor variable frequency speed regulation system. This solution uses DSP to send drive signals to IPM and uses DSP to receive and process IPM error signals. When IPM fails or other abnormalities occur, DSP can shut down the sending of IPM drive signals to protect IPM. The above solution is only for fault protection of a single IPM. When applied to multiple IPMs in parallel, since each parallel IPM will continuously output signals at the same time, the fault feedback signal is very easy to cause missed detection due to its short duration. Therefore, the above solution is not actually applicable to the fault protection identification of multiple parallel IPMs.

[0006] The fault protection of multiple parallel IPMs also needs to be low-cost, simple and reliable, so as to achieve low-cost and reliable engineering applications. For example, Chinese patent application CN201010204616.2 discloses an IPM drive and protection method in a motor control system. This solution uses FPGA to send drive signals to IPM, and uses FPGA to receive and process IPM error signals. When IPM errors or other abnormalities occur, FPGA can shut down the sending of IPM drive signals to protect IPM. In the above solution, the computing power of FPGA is limited, and complex motor control algorithms cannot be run in engineering, resulting in the need to add other control chips in the control system for auxiliary processing, which not only increases the complexity of the system, but also increases the cost. Summary of the invention

[0007] The technical problem to be solved by the present invention is: in response to the technical problems existing in the prior art, the present invention provides a multi-parallel IPM fault protection device, system and method with simple structure, low cost, high fault protection efficiency and accuracy, which can realize fault protection of multiple parallel IPMs at the same time.

[0008] In order to solve the above technical problems, the technical solution proposed by the present invention is:

[0009] A multi-parallel IPM fault protection device includes a main control module and a fault identification and positioning module connected to each other. The fault identification and positioning module includes a first level conversion unit and a latch unit connected to each other. The input end of the latch unit is connected to the fault signal of multiple parallel-connected IPMs for latching. After the latch signal is level-converted by the first level conversion unit, it is output to the main control module, and the main control module performs fault identification and positioning.

[0010] Furthermore, the fault identification and positioning module also includes a latch reset control unit connected to the latch unit, and the latch reset control unit accesses the fault signal of each IPM for logic processing, and outputs the logic processing result to the latch reset control end of the latch unit after a delay to control the latch unit to perform latch reset.

[0011] Furthermore, the latch reset control unit includes a logic processing subunit for performing logic processing and a delay subunit for delaying, the input end of the logic processing subunit is connected to the fault signal of each IPM, and the output end is connected to the latch reset control end of the latch unit through the delay subunit.

[0012] Furthermore, the logic processing subunit includes multiple AND gates and a NAND gate, each of the AND gates is connected to the NAND gate respectively, each of the AND gates is connected to the fault signals of two IPMs for AND operation, and the NAND gate performs NAND operation on the results output by each of the AND gates, and the output result is provided to the delay subunit.

[0013] Furthermore, the delay subunit is any one of a capacitor-based delay circuit, an RC-based delay circuit, an operational amplifier-based delay circuit, and a transistor-based delay circuit.

[0014] Furthermore, it also includes a fault detection module connected to the main control module, the fault detection module includes a second level conversion unit and a fault signal logic processing unit connected to each other, the fault signal logic processing unit is used to access the fault signal of each IPM for logic processing, and the logic processing result is output to the detection end of the main control module after level conversion by the second level conversion unit to realize fault detection.

[0015] Furthermore, when the detection end of the main control module receives a signal, it determines that an IPM failure occurs, and controls to block the PWM pulses sent to each IPM.

[0016] Furthermore, the fault detection module includes a plurality of AND gates, each of which is connected to the fault signals of two IPMs and performs AND operation to output the fault signals.

[0017] Furthermore, the main control module adopts DSP.

[0018] Furthermore, the latch unit is a trigger or a latch.

[0019] Furthermore, it also includes an isolation protection circuit arranged between the IPM and the main control module to achieve isolation protection of data interaction between the IPM and the main control module.

[0020] Furthermore, the isolation protection circuit includes an isolation optocoupler and / or an isolation operational amplifier, and the signal output by the main control module and / or the fault signal output by the IPM is transmitted through the isolation optocoupler, and the temperature signal output by the IPM is transmitted to the main control module through the isolation operational amplifier.

[0021] Furthermore, a multi-parallel IPM system includes a plurality of IPMs for driving a load, wherein each two IPMs constitute a group of IPMs, and each of the IPMs is connected in parallel, and further includes a fault protection device as described above connected to each of the IPMs.

[0022] Furthermore, every two IPMs share a driving isolation power supply.

[0023] A multi-parallel IPM fault protection method, characterized in that the steps include:

[0024] S01 receives a fault signal from multiple IPMs connected in parallel;

[0025] S02. The fault signal received by each IPM is latched and output by the latch unit;

[0026] S03. After the latched output fault signal is level-converted, the fault is identified and located.

[0027] Furthermore, the step S03 also includes a latch reset control step, including: accessing the fault signal of each IPM for logic processing, and outputting the logic processing result to the reset control terminal of the latch unit after a delay, so as to control the latch unit to perform latch reset.

[0028] Furthermore, in the step S02, the fault signals of every two IPMs are ANDed and all the ANDed results are then ANDed to obtain the logic processing result.

[0029] Furthermore, it also includes a fault detection step, including: accessing the fault signal of each IPM for logic processing, and outputting the logic processing result to the detection end after level conversion; when the detection end detects the signal, it is determined that there is an IPM fault.

[0030] Furthermore, in the fault detection step, an AND operation is performed on every two fault signals of each IPM to obtain the logic processing result.

[0031] Compared with the prior art, the advantages of the present invention are:

[0032] 1. The present invention receives the fault signals of each IPM connected in parallel by a latch unit, latches and outputs them to the main control module after level conversion, and the main control module 1 performs fault identification, and at the same time connects the fault signals of each IPM connected in parallel to the latch reset control unit, performs logic processing, and outputs the logic processing result to the reset control end of the latch unit after delay. When an IPM feeds back a fault signal, it generates an effective control signal to the latch reset control unit after a certain delay after logic processing. Since the fault signal has been latched, it can effectively ensure accurate identification of the faults of each IPM. At the same time, through the delayed latch reset control, the continuous execution of fault identification and positioning can also be achieved, thereby effectively solving the problem of accurate positioning and identification of multiple IPM fault signals.

[0033] 2. The present invention realizes fault identification and positioning through hardware circuits such as latch units and latch reset control units. Not only is the circuit structure simple, which can reduce the complexity and cost of implementation, but also the reliability and efficiency of identification and positioning can be improved by using hardware to realize fault identification and positioning.

[0034] 3. The present invention further implements a fast fault detection function based on a hardware detection method. When an IPM fault occurs, the fault signals of each IPM are logically processed and then directly sent to the detection end of the main control module after level conversion through a second level conversion unit. As a result, as long as the detection end of the main control module receives a valid signal, it can quickly determine that a fault signal exists. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of the structural principle of a multi-parallel IPM fault protection device according to embodiment 1 of the present invention.

[0036] Figure 2 It is a schematic diagram of the principle of the isolation protection circuit arrangement in Example 1 of the present invention.

[0037] Figure 3 It is a schematic diagram of the structure of two groups of IPMs in the multi-parallel IPM system of Example 1 of the present invention.

[0038] Figure 4 It is a schematic diagram of the structure of a multi-parallel IPM fault protection device in Example 2 of the present invention.

[0039] Legend: 1. Main control module; 2. Fault identification and positioning module; 201. First level conversion unit; 202. Latch unit; 203. Latch reset control unit; 231. Logic processing subunit; 232. Delay subunit; 3. Fault detection module; 301. Second level conversion unit; 302. Fault signal logic processing unit. DETAILED DESCRIPTION

[0040] The present invention is further described below in conjunction with the accompanying drawings and specific preferred embodiments, but the protection scope of the present invention is not limited thereby.

[0041] Embodiment 1:

[0042] like Figure 1 As shown, the multi-parallel IPM fault protection device of this embodiment includes a main control module 1 and a fault identification and positioning module 2 which are interconnected. The fault identification and positioning module 2 includes a first level conversion unit 201 and a latch unit 202 which are interconnected. The input end of the latch unit 202 is connected to the fault signals of multiple parallel-connected IPMs for latching. After the latch signal is level-converted by the first level conversion unit 201, it is output to the main control module 1, and the main control module 1 performs fault identification and positioning.

[0043] In this embodiment, the latch unit 202 receives the fault signal of each IPM connected in parallel (if a fault occurs, the fault signal corresponds to a valid signal state, if no fault occurs, the fault signal corresponds to an invalid signal state), and after latching, the level is converted by the level conversion module 2 and output to the main control module 1, and the main control module 1 performs fault identification. Since the fault signal has been latched, it can effectively ensure accurate identification of the fault of each IPM, avoid missed detection due to the fault signal lasting too short, and thus effectively solve the problem of accurate positioning and identification of multiple IPM fault signals.

[0044] In this embodiment, the fault identification and positioning module 2 also includes a latch reset control unit 203 connected to the latch unit 202. The latch reset control unit 203 accesses the fault signal of each IPM for logic processing, and outputs the logic processing result to the latch reset control end of the latch unit 202 after delay, so as to control the latch unit 202 to perform latch reset. The above logic processing is to perform logic operations on each fault signal to obtain the result of whether there is a fault signal (if there is an IPM fault signal, a valid signal is obtained after logic processing, otherwise an invalid signal is obtained). When an IPM feedbacks a fault signal, a valid control signal is generated after logic processing to the latch reset control unit 203. Since the logic processing result received by the latch reset control unit 203 has been delayed, the fault signal will be latched by the latch unit 202 first, and the main control module 1 will perform fault identification. After a period of time, the latch unit 202 will be controlled to perform latch reset, so as to wait for the main control module 1 to reset after identification is completed, and wait for the next fault. This embodiment can realize the continuous execution of fault identification and positioning through delayed latch reset control, and combined with the above-mentioned fault signal latch, it can effectively solve the problem of accurate positioning and identification of multiple IPM fault signals. In this embodiment, the latch reset control unit 203 includes a logic processing subunit 231 for performing logic processing and a delay subunit 232 for delaying. The input end of the logic processing subunit 231 is connected to the fault signal of each IPM, and the output end is connected to the latch reset control end of the latch unit 202 through the delay subunit 232. The above-mentioned logic processing subunit 231 specifically performs logic operations on each fault signal through logic processing to obtain the result of whether there is a fault signal, that is, if there is an IPM fault signal, a valid signal is obtained after logic processing, otherwise an invalid signal is obtained. The above-mentioned valid signal and invalid signal correspond to the valid and invalid states of the latch reset control terminal of the latch reset control unit 203, that is, when the logic processing sub-unit 231 outputs a valid signal, indicating that there is an IPM fault signal, then a valid signal is sent to the latch reset control terminal after a delay to control the latch reset; otherwise, if the logic processing sub-unit 231 outputs an invalid signal, indicating that there is no IPM fault signal, there is no need to send a signal to the latch reset control terminal.

[0045] In this embodiment, the logic processing subunit 231 specifically includes a plurality of AND gates and a NAND gate, each AND gate is connected to the NAND gate, each AND gate is connected to the fault signals of two IPMs for AND operation, so as to perform AND operation on the fault signals of every two IPMs, and the NAND gate performs NAND operation on the results output by each AND gate, and the output result is provided to the delay subunit 232. When an IPM sends a fault signal, at least one signal of the fault signal after being processed by the AND gate will become a low level (a high level corresponds to no fault, and a low level corresponds to a fault), and a rising edge can be generated after being processed by the NAND gate, and the signal is output to the latch reset control unit 203 after passing through the delay subunit 232, so as to realize latch control.

[0046] It can be understood that if the latch reset control terminal of the latch reset control unit 203 is valid at the falling edge, the structure of the logic processing sub-unit 231 can be adjusted accordingly, such as replacing the NAND gate with an AND gate, so that when there is a fault signal, a falling edge is generated to drive the latch unit 202 to reset. The specific details can be determined according to actual needs.

[0047] In this embodiment, the delay subunit 232 can adopt a capacitor-based delay circuit, an RC-based delay circuit, an op amp-based delay circuit, and a transistor-based delay circuit, etc., which can be determined according to actual needs. The delay time of the delay subunit 232 can be determined according to the time required for the main control module 1 to realize fault identification, so that when the main control module 1 completes the fault identification, the latch unit 202 is controlled to perform latch reset, and the specific delay time setting can be set according to actual needs.

[0048] In this embodiment, the latch unit 202 can be implemented by a trigger or a latch, etc. The trigger can be a D trigger, etc., and the latch can be an SR latch, etc. The signal output end of the trigger or latch is connected to the fault signal output end of each IPM, the output end of the trigger or latch is connected to the input end of the first level conversion unit 201, and the reset control end of the trigger or latch is connected to the output end of the latch reset control unit 203. Of course, the latch unit 202 can also be implemented by other circuits and devices that can realize the latching function except for the trigger and latch.

[0049] In this embodiment, a fault detection module 3 connected to the main control module 1 is also included. The fault detection module 5 includes a second level conversion unit 301 and a fault signal logic processing unit 302 connected to each other. The fault signal logic processing unit 302 is used to access the fault signal of each IPM for logic processing. The result of the logic processing is output to the detection end of the main control module 1 after level conversion by the second level conversion unit 301 to achieve fault detection. The above logic processing is to perform logic operations on each fault signal to obtain the result of whether there is a fault signal. If there is an IPM fault signal, a valid signal is obtained after logic processing. Otherwise, an invalid signal is obtained. After the fault signal of each IPM is logically processed, it is directly sent to the detection end of the main control module 1 after level conversion by the second level conversion unit 301. When there is an IPM sending a fault signal, a valid signal will be generated after logic processing and output to the detection end of the main control module 1. As long as the detection end of the main control module 1 receives the valid signal, it can be determined that there is a fault signal, and rapid fault detection of the fault can be achieved. This fault detection is faster than the above-mentioned fault identification and positioning, because by combining this fault detection and the above-mentioned fault identification and positioning, when there is an IPM fault, the occurrence of the fault can be quickly detected first, so that the fault status can be obtained in time, and then accurate fault identification and positioning can be achieved through fault identification and positioning, and the location of the fault can be determined, realizing the dual functions of rapid fault detection and accurate fault identification and positioning.

[0050] In this embodiment, when the detection end of the main control module 1 receives a signal, it determines that an IPM fault occurs and controls pulse blocking, so that the pulse output can be quickly blocked according to the fault signal, thereby achieving the effect of effectively protecting the IPM and peripheral circuits.

[0051] In this embodiment, the fault signal logic processing unit 302 specifically includes a plurality of AND gates, each of which receives the fault signals of two IPMs and performs an AND operation on the fault signals, and then outputs the result. In this way, the fault signals of every two IPMs are ANDed together. Then, when an IPM sends a fault signal, at least one of the fault signals after being processed by the AND gate will become a low level (a high level corresponds to no fault, and a low level corresponds to a fault), and will be output to the main control module 1 through the second level conversion unit 301.

[0052] In this embodiment, the first level conversion unit 201 and the second level conversion unit 301 are used to convert the received level signal so as to match the detection of the main control module 1. After the signal is processed by logic, if there is a fault signal, a valid level will be generated after conversion by the first level conversion unit 201 and the second level conversion unit 301, and provided to the signal input end or the detection end of the main control module 1, so that the fault identification and location can be performed after the signal input end of the main control module 1 receives the valid level, and after the detection end detects the valid level, it can be determined that there is an IPM fault signal. The above-mentioned first level conversion unit 201 and the second level conversion unit 301 can be implemented by two separate conversion circuits, and of course, can also be implemented by an integrated conversion circuit.

[0053] In this embodiment, an isolation protection circuit is also provided between the IPM and the main control module 1 to implement isolation protection of data interaction between the IPM and the main control module 1 , thereby further improving the reliability of data interaction between the IPM and the main control module 1 .

[0054] like Figure 2 As shown, the isolation protection circuit in this embodiment includes an isolation optocoupler and an isolation operational amplifier. The signal output by the main control module 1 and the fault signal output by the IPM are transmitted through the isolation optocoupler, and the temperature signal output by the IPM is transmitted to the main control module 1 through the isolation operational amplifier. In this embodiment, a first optocoupler is specifically set to transmit the signal (PWM pulse signal) output by the main control module 1 to the IPM after passing through the first optocoupler, and a second optocoupler is set to transmit the fault signal output by the IPM to the main control module 1 through the second optocoupler. The above-mentioned isolation optocoupler can specifically adopt a high-speed optocoupler with a high common mode rejection ratio, and other types of optocouplers can also be used according to actual needs. By adopting the above-mentioned full isolation method, the IPM and the DSP control signal side are completely isolated and controlled by using isolation optocouplers and isolation operational amplifiers, which can greatly enhance the anti-interference ability of the circuit.

[0055] like Figure 3 As shown, this embodiment also includes a multi-parallel IPM system, which includes multiple IPMs for driving loads, each two IPMs constitute a group of IPMs, and each IPM is connected in parallel, and also includes a fault protection device as described above connected to each IPM, which can accurately identify the fault and the fault location when the IPM fails, ensuring the stability and reliability of each parallel IPM. When designing the PCB of the circuit, the current return path can be reduced, that is, Figure 1 The path length of the circuit (1) in the circuit is increased to meet the requirement of improving the anti-interference performance of the circuit.

[0056] In this embodiment, every two IPMs share a driving isolation power supply (such as Figure 3+15V isolated power module), that is, using two IPMs to share one driving power supply, the PCB can be finely designed to reduce the current return path, thereby enhancing the anti-interference of the circuit, while reducing the number of isolated power supplies used and reducing the cost of the equipment. Of course, other driving power supply methods can also be used according to actual needs, such as one driving power supply to power one IPM separately, and then multiple IPMs are processed in parallel.

[0057] The steps of the multi-parallel IPM fault protection method of this embodiment include:

[0058] S01 receives a fault signal from multiple IPMs connected in parallel;

[0059] S02. The fault signal received by each IPM is latched and output by the latch unit 202;

[0060] S03. After the latched output fault signal is level-converted, the fault is identified and located.

[0061] In this embodiment, step S03 also includes a latch reset control step, including: accessing the fault signal of each IPM for logic processing, and outputting the logic processing result to the reset control terminal of the latch unit 202 after a delay to control the latch unit 202 to perform latch reset.

[0062] In step S02 of this embodiment, an AND operation is performed on the fault signals of every two IPMs, and all the AND operation results are then subjected to a NOT operation to obtain a logical processing result.

[0063] This embodiment also includes a fault detection step, including: accessing the fault signal of each IPM for logic processing, converting the level of the logic processing result and outputting it to the detection end; when the detection end detects the signal, it is determined that there is an IPM fault.

[0064] In the fault detection step of this embodiment, an AND operation is performed on every two fault signals of each IPM to obtain a logic processing result.

[0065] The multi-parallel IPM fault protection method of this embodiment is consistent with the principle of the multi-parallel IPM fault protection device described above, and will not be described in detail here.

[0066] Embodiment 2:

[0067] The multi-parallel IPM system of this embodiment specifically includes 6 IPMs, 2 IPMs form a group of IPMs, and 6 IPMs are connected in parallel to drive the load. The 6 IPMs use the same DC high-voltage power supply to drive different coils of the magnetic levitation motor in parallel to reduce the length of the current return path and improve the anti-interference performance of the circuit. At the same time, the design cost is taken into account. On the IPM drive power supply side, 2 IPMs share a drive isolation power supply, that is, every 2 IPMs use the same IPM drive power supply, and the control side power supply is isolated and separated from the drive power supply.

[0068] The multi-parallel IPM fault protection device of this embodiment includes a main control module 1 and a fault identification and positioning module 2 connected to each other. The fault identification and positioning module 2 includes a first level conversion unit 201, a latch unit 202 and a latch reset control unit 203 connected in sequence. The input end of the latch unit 202 is connected to the fault signals of multiple parallel connected IPMs for latching. After the latch signal is converted by the first level conversion unit 201, it is output to the main control module 1, and the main control module 1 performs fault identification and positioning. The latch reset control unit 203 is connected to the fault signal of each IPM for logic processing, and the result of the logic processing is output to the latch reset control end of the latch unit 202 after a delay, so as to control the latch unit 202 to perform latch reset. In addition, the main control module 1 is implemented by DSP, and the DSP performs switch control on the IPM. The latch unit 202 is implemented by a D flip-flop. By making full use of the powerful computing performance of the DSP, combined with flip-flops, etc., efficient driving and fault protection of multiple parallel IPMs can be effectively achieved.

[0069] In this embodiment, the latch reset control unit 203 includes a logic processing subunit 231 for performing logic processing and a delay subunit 232 for delaying. The input end of the logic processing subunit 231 is connected to the fault signal of each IPM, and the output end is connected to the latch reset control end of the latch unit 202 through the delay subunit 232. The logic processing subunit 231 specifically includes three AND gates and one NAND gate, each AND gate is connected to the NAND gate, each AND gate is connected to the fault signal of two IPMs for AND operation, and the NAND gate performs NAND operation on the output result of each AND gate, and the output result is provided to the delay subunit 232. The delay subunit 232 specifically adopts a capacitor.

[0070] In this embodiment, an isolation protection circuit is also included between the IPM and the main control module 1 to achieve isolation protection of data interaction between the IPM and the main control module 1, further improving the reliability of data interaction between the IPM and the main control module 1. The isolation protection circuit includes an isolation optical coupler and an isolation operational amplifier, see Figure 2As shown, the signal output by the main control module 1 and the fault signal output by the IPM are transmitted through the isolation optocoupler, and the temperature signal output by the IPM is transmitted to the main control module 1 through the isolation op amp. In order to enhance the anti-interference ability of the circuit, in this embodiment, the PWM signal is generated by the DSP and sent to the IPM through optocoupler isolation. The fault feedback signal of the IPM is also sent back to the DSP after being isolated by the optocoupler. The above-mentioned optocoupler uses a high-speed optocoupler with a high common-mode rejection ratio to improve the anti-interference performance of the circuit. The temperature feedback signal of the IPM is isolated by an isolation op amp and then sent to the on-chip AD module of the DSP. The above-mentioned isolation op amp is an isolation op amp with a unilateral voltage input and a differential voltage output, and has the performance of isolating 3KV voltage. Every two IPMs use the same isolation power supply to power the isolation device (optocoupler, isolation op amp), as shown in the +5V isolation power module 1 in the figure below. On the path of fault feedback and temperature feedback, capacitors are placed close to the device pins for filtering.

[0071] In this embodiment, a fault detection module 3 connected to the DSP is also included. The fault detection module 5 includes a second level conversion unit 301 and a fault signal logic processing unit 302 connected to each other. The fault signal logic processing unit 302 is used to access the fault signal of each IPM for logic processing. The logic processing result is output to the detection end (TZ detection tube) of the DSP after level conversion by the second level conversion unit 301 to realize fault detection, that is, the fault feedback detection is also completed by the DSP. The TZ pin on the DSP can quickly detect the fault and realize the DSP pulse blocking, thereby protecting the IPM module. In this embodiment, the second level conversion unit 301 is specifically implemented with the first level conversion unit 201 using an integrated level conversion chip.

[0072] Since there are 6 IPM fault feedback signals, such as Figure 4 As shown, in this embodiment, the fault feedback signals of the six IPMs are divided into two parts for detection and processing, including:

[0073] One part is the fast detection and processing of fault signals, which is used to quickly block the PWM output pulse of DSP after detecting the IPM fault signal. This part uses a 2-input AND gate to process the fault feedback signals of 6 IPMs in pairs, and sends the 3 processed signals directly to the TZ detection pin of DSP through a level converter. The TZ pin of DSP is a hardware detection pin. When a signal is detected, the hardware directly blocks the PWM pulse output, reducing the running time of the program blocking pulse. Because this part has a fast detection circuit, it cannot accurately determine which IPM reported the fault signal, and another part of the IPM fault feedback detection circuit completes this function.

[0074] The other part is the identification, location, detection and processing of fault signals. Since the IPM fault feedback signal is maintained for a short time, in order to identify and locate the faulty IPM, the IPM fault signal is sent to the D flip-flop. The signal from the D flip-flop is sent to the GPIO port of the DSP through the level converter for program judgment and identification; the three-way fault feedback signal processed by the AND gate and the reset signal of the DSP pass through the NAND gate together, and then after capacitor delay processing, it is sent to the control pin of the D flip-flop. When a fault occurs, at least one of the three fault signals processed by the AND gate will become a low level, and after NAND gate processing and capacitor delay, a rising edge will appear to the control pin of the D flip-flop. At this time, the input port signal of the D flip-flop comes earlier than the control pin signal of the D flip-flop, so that the signal at the input end of the D flip-flop is latched and output to the DSP until the DSP accurately identifies and locates the IPM fault. Then the DSP outputs the reset signal to latch and reset the D flip-flop, waiting for the next fault to occur.

[0075] Through the above-mentioned device of this embodiment, it is possible to quickly block the pulse output according to the fault signal to protect the IPM and peripheral circuits, and also to accurately locate and identify multiple IPM fault signals to solve the problem of accurately locating and identifying multiple IPM fault signals.

[0076] The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A multi-parallel IPM fault protection device, characterized in that: The invention comprises a main control module (1) and a fault identification and positioning module (2) which are connected to each other, wherein the fault identification and positioning module (2) comprises a first level conversion unit (201) and a latch unit (202) which are connected to each other, wherein the input end of the latch unit (202) is connected to a plurality of fault signals of IPMs connected in parallel for latching, and the latch signal is level-converted by the first level conversion unit (201) and then output to the main control module (1), and the main control module (1) performs fault identification and positioning; The fault identification and positioning module (2) further comprises a latch reset control unit (203) connected to the latch unit (202), wherein the latch reset control unit (203) receives the fault signal of each IPM for logic processing, and outputs the logic processing result to the latch reset control terminal of the latch unit (202) after a delay, so as to control the latch unit (202) to perform latch reset; The latch reset control unit (203) comprises a logic processing subunit (231) for performing logic processing and a delay subunit (232) for performing delay, wherein the input end of the logic processing subunit (231) is connected to the fault signal of each IPM, and the output end is connected to the latch reset control end of the latch unit (202) through the delay subunit (232).

2. The multi-parallel IPM fault protection device according to claim 1, characterized in that: The logic processing subunit (231) comprises a plurality of AND gates and a NAND gate, each of the AND gates being connected to the NAND gate respectively, each of the AND gates receiving the fault signals of two IPMs to perform an AND operation, the NAND gate performing a NAND operation on the output results of each of the AND gates, and providing the output result to the delay subunit (232).

3. The multi-parallel IPM fault protection device according to claim 2, characterized in that: The delay subunit (232) is any one of a capacitor-based delay circuit, an RC-based delay circuit, an operational amplifier-based delay circuit, and a transistor-based delay circuit.

4. The multi-parallel IPM fault protection device according to claim 1, characterized in that: The invention also comprises a fault detection module (3) connected to the main control module (1), wherein the fault detection module (3) comprises a second level conversion unit (301) and a fault signal logic processing unit (302) which are connected to each other, wherein the fault signal logic processing unit (302) is used to access the fault signal of each IPM for logic processing, and the logic processing result is output to the detection end of the main control module (1) after level conversion by the second level conversion unit (301) to realize fault detection.

5. The multi-parallel IPM fault protection device according to claim 4, characterized in that: When the detection end of the main control module (1) receives a signal, it determines that an IPM failure has occurred and controls the blocking of the PWM pulses sent to each IPM.

6. The multi-parallel IPM fault protection device according to claim 5, characterized in that: The fault detection module (3) comprises a plurality of AND gates, each of which receives the fault signals of two IPMs and performs an AND operation on the fault signals before outputting the result.

7. The multi-parallel IPM fault protection device according to any one of claims 1 to 6, characterized in that: The main control module (1) adopts DSP.

8. The multi-parallel IPM fault protection device according to any one of claims 1 to 6, characterized in that: The latch unit (202) is a trigger or a latch.

9. The multi-parallel IPM fault protection device according to any one of claims 1 to 6, characterized in that: It also comprises an isolation protection circuit arranged between the IPM and the main control module (1) to realize isolation protection of data interaction between the IPM and the main control module (1).

10. The multi-parallel IPM fault protection device according to claim 9, characterized in that: The isolation protection circuit comprises an isolation optical coupler and an isolation operational amplifier. The signal output by the main control module (1) and / or the fault signal output by the IPM is transmitted via the isolation optical coupler, and the temperature signal output by the IPM is transmitted to the main control module (1) via the isolation operational amplifier.

11. A multi-parallel IPM system, comprising a plurality of IPMs for driving a load, wherein each two IPMs constitute a group of IPMs, and each of the IPMs is connected in parallel, characterized in that: It also includes a fault protection device as described in any one of claims 1 to 10 connected to each of the IPMs.

12. The multi-parallel IPM system according to claim 11, characterized in that: Every two of the IPMs share a driving isolation power supply.

13. A multi-parallel IPM fault protection method, characterized in that the steps include: S01 receives a fault signal from multiple IPMs connected in parallel; S02. The received fault signals of each IPM are latched and outputted by the latch unit (202); S03. After the latched output fault signal is level-converted, fault identification and positioning are performed; The step S03 also includes a latch reset control step, comprising: accessing the fault signal of each IPM for logic processing, and outputting the logic processing result to the reset control terminal of the latch unit (202) after a delay, so as to control the latch unit (202) to perform latch reset.

14. The multi-parallel IPM fault protection method according to claim 13, characterized in that: In the step S02, the fault signals of every two IPMs are ANDed and all the ANDed results are then ANDed to obtain the logic processing result.

15. The multi-parallel IPM fault protection method according to claim 13 or 14, characterized in that: It also includes a fault detection step, including: accessing the fault signal of each IPM for logic processing, converting the level of the logic processing result and outputting it to the detection end; when the detection end detects the signal, it is determined that there is an IPM fault.

16. The multi-parallel IPM fault protection method according to claim 15, characterized in that: In the fault detection step, specifically, an AND operation is performed on every two fault signals of the fault signals of each IPM to obtain the logic processing result.

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