Amplification device

Abstract

The present invention provides an amplification device capable of suppressing instability caused by changes in characteristics relative to temperature variations. The amplification device (1) includes: an amplifier (10) comprising a multi-stage power amplifier (PA1 to PA3) connected in cascade; and a bias circuit (20) supplying a bias current to the amplifier (10). The bias current (Ib1) supplied to the primary power amplifier (PA1) in the multi-stage power amplifier (PA1 to PA3) has a positive temperature characteristic, and the bias current (Ib3) supplied to the final stage power amplifier (PA3) has a negative temperature characteristic.

Description

Technical Field

[0001] This invention relates to an amplification device having an amplifier and a bias circuit. Background Technology

[0002] Conventionally, amplification devices are known that include: an amplifier, specifically a power amplifier; and a bias circuit that supplies bias current to the power amplifier. As an example of the bias circuit in such an amplification device, Patent Document 1 discloses a bias circuit that includes: a current mirror circuit; and a current supply circuit that supplies current to the current mirror circuit. The current supply circuit has a temperature compensation circuit. In this bias circuit, for example, when the temperature rises, the bias current is increased using the temperature compensation circuit, suppressing an extreme drop in the gain of the bias circuit.

[0003] Prior art literature

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2013-98904

[0006] For example, in the case of an amplifier containing multiple cascaded power amplifiers, bias current is supplied to each of the power amplifiers from a bias circuit as described above. However, there are many cases where the specifications of the multiple power amplifiers are different. If bias currents with the same temperature characteristics are supplied to each power amplifier, the characteristics of the amplifier with multiple power amplifiers may sometimes become unstable in relation to temperature changes. Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] Therefore, the object of the present invention is to provide an amplification device capable of suppressing the instability of characteristics relative to temperature changes.

[0009] Methods for solving problems

[0010] To achieve the above objectives, one aspect of the present invention relates to an amplification device comprising: an amplifier including a multi-stage power amplifier connected in cascade; and a bias circuit supplying a bias current to the amplifier, wherein the bias current supplied to the primary power amplifier in the multi-stage power amplifier has a positive temperature characteristic, and the bias current supplied to the final stage power amplifier has a negative temperature characteristic.

[0011] Invention Effects

[0012] In amplification devices, the ability to suppress changes in properties relative to temperature becomes unstable. Attached Figure Description

[0013] Figure 1 This is the circuit diagram of the amplifier in the comparative example.

[0014] Figure 2 This is a schematic structural block diagram of the amplification device involved in the implementation method.

[0015] Figure 3 This is a diagram illustrating an example of the bias current supplied to the amplifier of the amplification device involved in the embodiment.

[0016] Figure 4 This is a diagram illustrating an example of the collector current supplied to the amplifier of the amplification device involved in the embodiment.

[0017] Figure 5 This is a diagram showing the EVM (Error Vector Magnitude) of the amplifier in the amplification device of the embodiment.

[0018] Figure 6 This is a structural block diagram illustrating the functional structure of the bias circuit of the amplification device according to the embodiment.

[0019] Figure 7 This is a circuit diagram of the bias circuit of the amplification device involved in the implementation method.

[0020] Symbol Explanation

[0021] 1. Amplification device

[0022] 10 Amplifier

[0023] 20 Bias Circuit

[0024] 30 Common constant current source

[0025] 31. First Current Mirror Circuit

[0026] 31a and 31b transistors

[0027] 32. Second Current Mirror Circuit

[0028] 32a and 32b transistors

[0029] 33 Resistor element

[0030] 34. Startup transistors

[0031] 40 First Bias Power Supply Section

[0032] 41. First Current Amplifier Circuit

[0033] 41a Current Amplification Component

[0034] 45. First constant current source

[0035] 46 Operational Amplifier No. 1

[0036] 47. Introduction of the first transistor

[0037] 48 First variable resistor

[0038] 50 Adder-side current amplification section

[0039] Node on one side of 50a

[0040] Node on the other side of 50b

[0041] 51 First detection resistor

[0042] 52 Second detection resistor

[0043] 55 Adder-side operational amplifier

[0044] 56 biased output transistors

[0045] 60 Second Bias Power Supply Section

[0046] 61. Second Current Amplifier Circuit

[0047] 61a Current Amplifier

[0048] 65. Second constant current source

[0049] 66. Operational Amplifier No. 2

[0050] 67. The second introduction of transistors

[0051] 68 Second Variable Resistor

[0052] 70 Subtraction-side current amplification section

[0053] Node on one side of 70a

[0054] 70b The node on the other side

[0055] 73 Third detection resistor

[0056] 74 Fourth detection resistor

[0057] 75 Subtraction-side operational amplifier

[0058] 76 Biased Output Transistors

[0059] BB bias branch

[0060] ia1 First Amplification Current

[0061] ia2 Second Amplified Current

[0062] Ib1, Ib2, Ib3 bias currents

[0063] Collector currents Ic1, Ic2, and Ic3

[0064] id1 First introduced current

[0065] id2 The second introduced current

[0066] is1 First supply current

[0067] is2 Second Supply Current

[0068] it1 First total current

[0069] it2 Second Total Current

[0070] Matching circuits for MN1, MN2, MN3, and MN4

[0071] Nodes n1, n2, n3, n4, n5

[0072] PA1, PA2, PA3, PAn power amplifiers

[0073] Pin RF input terminal

[0074] Pout RF output terminal

[0075] RT remote temperature compensator

[0076] TD temperature sensing element

[0077] VBG reference voltage

[0078] Vcc high-potential side power line

[0079] Vss Low-potential side power line. Detailed Implementation

[0080] (The process of completing this invention)

[0081] First, the process of completing the present invention will be described using the amplification device 101 as an example of a comparative example.

[0082] Figure 1 This is a circuit diagram of the amplification device 101 in the comparative example.

[0083] The comparative example amplification device 101 includes an amplifier 110 and a bias circuit 120 that supplies bias current to the amplifier 110.

[0084] Amplifier 110 is a circuit that amplifies a high-frequency signal input from the RF input terminal Pin and outputs it from the RF output terminal Pout. Amplifier 110 includes an amplification transistor 111, and DC cutoff capacitors 112 and 113. The base of the amplification transistor 111 is connected to the RF input terminal Pin via the DC cutoff capacitor 112, the collector is connected to the RF output terminal Pout via the DC cutoff capacitor 113, and the emitter is connected to ground. At node n102 between the collector and the DC cutoff capacitor 113, a high-potential power supply line is connected via an inductor.

[0085] The bias circuit 120 is connected via a resistor to node n101 between the base of the amplifying transistor 111 and the DC cutoff capacitor 112. The bias circuit 120 has a temperature compensation circuit 121. The bias circuit 120 supplies a bias current with desired temperature characteristics to the amplifying transistor 111 via the resistor and node n101.

[0086] The comparative amplifier 110 includes one amplifying transistor 111. However, in the case where the amplifier includes multiple amplifying transistors 111 connected in cascade, bias currents are supplied to each of the multiple amplifying transistors 111 from the bias circuit 120 described above. However, it is common for the multiple amplifying transistors 111 to have different specifications. If bias currents with the same temperature characteristics are supplied to each amplifying transistor 111, the characteristics of the transistors may sometimes become unstable in an amplifier with multiple amplifying transistors 111.

[0087] To address this, the amplification device of the present invention does not supply bias currents with the same temperature characteristics to all of the multiple amplification transistors, but instead supplies bias currents with temperature characteristics different from the aforementioned identical temperature characteristics to at least a portion of the amplification transistors. Therefore, in the amplification device, it is possible to suppress the instability of characteristics that change with temperature.

[0088] Hereinafter, embodiments of the present invention will be described in detail using the accompanying drawings. Furthermore, the embodiments described below are either general or specific examples. The numerical values, constituent elements, arrangements of constituent elements, and connection methods shown in the following embodiments are examples only and are not intended to limit the present invention. Constituent elements in the following embodiments not described in the independent claims are described as optional constituent elements.

[0089] (Implementation Method)

[0090] [1. Simplified Structure of the Amplification Device]

[0091] Reference Figures 2-5The general structure of the amplification device involved in the implementation method will be described.

[0092] Figure 2 This is a schematic structural block diagram of the amplification device 1 according to the embodiment.

[0093] The amplification device 1 includes an amplifier 10 for amplifying high-frequency signals and a bias circuit 20 for supplying bias current to the amplifier 10. The amplifier 10 is composed of a first IC chip, and the bias circuit 20 is composed of a second IC chip, which is different from the first IC chip. In addition, a bias branch BB, which will be described later, is provided on the first IC chip.

[0094] Amplifier 1 is, for example, built into a communication device that transmits and receives high-frequency signals. Examples of high-frequency signals input to amplifier 1 include those in the 2.4 GHz or 5 GHz bands under the IEEE 802.11 standard. Amplifier 1 has an RF input terminal Pin for inputting the high-frequency signal to amplifier 10 and an RF output terminal Pout for outputting the high-frequency signal amplified by amplifier 10.

[0095] Amplifier 10 is disposed on the path connecting the RF input terminal Pin and the RF output terminal Pout. Amplifier 10 has cascaded multi-stage power amplifiers. The amplifier 10 in this embodiment has a primary power amplifier PA1, a second-stage power amplifier PA2, and a third-stage power amplifier PA3, with the third-stage power amplifier PA3 becoming the final-stage power amplifier PAn. Each power amplifier PA1 to PA3 has an amplification transistor. The amplification transistor is, for example, a GaAs bipolar transistor or a SiGe bipolar transistor.

[0096] The input terminal of power amplifier PA1 is connected to the RF input terminal Pin via matching circuit MN1. The output terminal of power amplifier PA1 is connected to the input terminal of power amplifier PA2 via matching circuit MN2. The output terminal of power amplifier PA2 is connected to the input terminal of power amplifier PA3 via matching circuit MN3. The output terminal of power amplifier PA3 is connected to the RF output terminal Pout via matching circuit MN4. Each matching circuit MN1 to MN4 is used to match the impedance between the RF input terminal and the power amplifier, between the power amplifiers themselves, and between the power amplifier and the RF output terminal. These circuits include passive components such as inductors and capacitors.

[0097] Furthermore, in power amplifier PA1, a collector current Ic1 is supplied from the high-potential side power line Vcc; in power amplifier PA2, a collector current Ic2 is supplied from the high-potential side power line Vcc; and in power amplifier PA3, a collector current Ic3 is supplied from the high-potential side power line Vcc. In amplifier 10, the primary power amplifier PA1 has the highest gain and the lowest output power, while the final, third-stage power amplifier PA3 has the lowest gain and the highest output power.

[0098] In this embodiment, amplifier 10 includes three stages of power amplifiers PA1 to PA3, but the number of stages of the power amplifier is not limited to this. For example, amplifier 10 may also include n stages (n is an integer greater than or equal to 2) of power amplifiers, with the nth stage power amplifier becoming the final stage power amplifier PAn.

[0099] The bias circuit 20 is a circuit that supplies bias current to the amplifier 10. The bias circuit 20 has a temperature compensation function and controls the voltage so that it can supply a given bias current according to the ambient temperature or the temperature of a specific part.

[0100] The bias circuit 20 includes a first bias power supply section 40, a second bias power supply section 60, and a common constant current source 30.

[0101] The common constant current source 30 is a common current source that supplies current to the first bias power supply section 40 and the second bias power supply section 60 respectively.

[0102] The first bias power supply unit 40 is connected to node n1 between the matching circuit MN1 and the input terminal of the power amplifier PA1. The first bias power supply unit 40 supplies the primary bias current Ib1 to the primary power amplifier PA1 via node n1.

[0103] The second bias power supply unit 60 is connected via a bias branch BB to node n2 between the matching circuit MN2 and the input terminal of the power amplifier PA2, and to node n3 between the matching circuit MN3 and the input terminal of the power amplifier PA3. The second bias power supply unit 60 supplies a second-stage bias current Ib2 to the second-stage power amplifier PA2 via the bias branch BB and node n2. Furthermore, the second bias power supply unit 60 supplies a third-stage bias current Ib3 to the third-stage power amplifier PA3 via the bias branch BB and node n3. In this embodiment, the third-stage bias current Ib3 becomes the final-stage bias current Ibn supplied to the final-stage power amplifier Pan.

[0104] The bias branch BB, for example, has a resistor and a current mirror circuit. After appropriately shunting and amplifying the output current of the second bias power supply section 60, the bias branch BB outputs a bias current Ib2 to the power amplifier PA2, and further outputs a bias current Ib3 to the power amplifier PA3.

[0105] The first bias power supply section 40 and the second bias power supply section 60 are power supply sections with different temperature characteristics. The first bias power supply section 40 has a PTAT (Proportional To Absolute Temperature) characteristic that increases with increasing temperature. The second bias power supply section 60 has a CTAT (Complementary Proportional To Absolute Temperature) characteristic that decreases with increasing temperature. That is, the first bias power supply section 40 increases the bias current Ib1 supplied to the primary power amplifier PA1 as the temperature rises, while the second bias power supply section 60 decreases the bias currents Ib2 and Ib3 supplied to the second and third stage power amplifiers PA2 and PA3 as the temperature rises.

[0106] Figure 3 This is a diagram showing an example of the bias currents Ib1, Ib2, and Ib3 supplied to the amplifier 10 of the amplification device 1. Figure 4 This is a diagram showing an example of the collector currents Ic1, Ic2, and Ic3 supplied to the amplifier 10 of the amplification device 1.

[0107] exist Figure 3 The diagram shows that the bias current Ib1 supplied from the first bias power supply section 40 to power amplifier PA1 has PTAT characteristics, and the bias currents Ib2 and Ib3 supplied from the second bias power supply section 60 to power amplifiers PA2 and PA3 have CTAT characteristics. If bias currents Ib1 to Ib3 are supplied to each power amplifier PA1 to PA3, then collector currents Ic1 to Ic3 are consumed in each power amplifier PA1 to PA3. Figure 4 The diagram shows that the collector current IcI consumed by power amplifier PA1 has PTAT characteristics, while the collector currents Ic2 and Ic3 consumed by power amplifiers PA2 and PA3 have CTAT characteristics, respectively.

[0108] Thus, in the amplification device 1, the bias current Ib1 supplied to the primary power amplifier PA1 among the multi-stage power amplifiers PA1 to PA3 has a positive temperature characteristic, and the bias current Ib3 supplied to the third stage power amplifier PA3, which is the final stage power amplifier, has a negative temperature characteristic.

[0109] Furthermore, in the amplification device 1, the bias current supplied to a given stage of the multi-stage power amplifiers PA1 to PA3 exhibits a temperature characteristic showing a negative tendency compared to the bias current supplied to a stage further upstream than the given stage. Specifically, the bias current supplied to the second-stage power amplifier PA2 exhibits a temperature characteristic showing a negative tendency compared to the bias current supplied to the primary power amplifier PA1. Furthermore, the bias current supplied to the third-stage power amplifier PA3 exhibits a temperature characteristic showing a negative tendency compared to the bias current supplied to the second-stage power amplifier PA2. Additionally, "showing a negative tendency" means that the tangent of the slope of the temperature characteristic is close to tan(-90°).

[0110] In this way, by setting the bias current Ib1 supplied to the primary power amplifier PA1 to have a positive temperature characteristic, and setting the bias current Ib3 supplied to the third stage power amplifier PA3 (which is the final stage power amplifier) ​​to have a negative temperature characteristic, the EVM (Error Vector Magnitude) can be reduced, and the instability of the characteristic relative to temperature changes can be suppressed. The EVM of the amplifier 10 of the amplification device 1 will be explained below.

[0111] Figure 5 This is a graph showing the EVM of amplifier 10 in amplification device 1. EVM is a metric used to evaluate the linearity of a device. Figure 5 The image shows the EVM at 25°C and 85°C.

[0112] Figure 5 The dashed line represents the EVM of the amplifier in the comparative example amplifier. In the comparative example amplifier, the temperature characteristics of the bias current supplied to all stages of the power amplifier are the same.

[0113] Figure 5 The solid line represents the EVM of amplifier 10 in the amplification device 1 of the embodiment. In the amplification device 1 of the embodiment, the temperature characteristics of the bias current supplied to each stage of the power amplifier are different for each stage. Figure 5 As shown, in the range where the output power P is 14dBm or more and 20dBm or less, the EVM value of the embodiment becomes smaller compared to the comparative example. That is, in the amplification device 1 of the embodiment, the temperature characteristics of the bias current are optimized for each stage of the power amplifier, resulting in a smaller EVM value.

[0114] As an example of optimization, for instance, for the primary power amplifier PA1, a bias current Ib1 with PTAT characteristics is supplied to compensate for the gain decrease of power amplifier PA1 when the temperature rises. Furthermore, for the third-stage power amplifier PA3, a bias current Ib3 with CTAT characteristics is supplied within the power range that can be handled while keeping distortion below a certain level, reducing the current consumption of power amplifier PA3 when the temperature rises. For the second-stage power amplifier PA2, if the gain of power amplifier PA2 and the power that can be handled are sufficient when the temperature rises, a bias current Ib2 with CTAT characteristics is supplied. On the other hand, if the overall gain of amplifier 10 is insufficient, a bias current with PTAT characteristics is supplied. Additionally, in... Figure 5 In the example, a bias current Ib2 with CTAT characteristics is supplied in the power amplifier PA2 of the second stage.

[0115] In this way, by optimizing the temperature characteristics of each stage of the power amplifier, the value of EVM is reduced, thereby suppressing the instability of the characteristics relative to temperature changes in the amplification device 1.

[0116] Furthermore, in amplification device 1, a bias current Ib2 with a positive or negative temperature characteristic is supplied to the second-stage power amplifier PA2. However, a fixed bias current without a temperature characteristic can also be supplied to the second-stage power amplifier PA2. That is, in an amplification device such as amplification device 1 that includes three stages of power amplifiers, it is sufficient to supply a bias current with a positive temperature characteristic to the primary power amplifier and a bias current with a negative temperature characteristic to the final-stage power amplifier. The temperature characteristic of the bias current supplied to the intermediate-stage power amplifier (the second-stage power amplifier) ​​located between the primary and final-stage power amplifiers can be any temperature characteristic.

[0117] Furthermore, for example, when a bias current with a positive temperature characteristic is supplied to both the primary power amplifier and the second-stage power amplifier, the temperature characteristic of the bias current supplied to the second-stage power amplifier may exhibit the same tendency as the temperature characteristic of the bias current supplied to the primary power amplifier, or it may exhibit a more negative or more positive tendency. Conversely, for example, when a bias current with a negative temperature characteristic is supplied to both the second-stage power amplifier and the final-stage power amplifier, the temperature characteristic of the bias current supplied to the second-stage power amplifier may exhibit the same tendency as the temperature characteristic of the bias current supplied to the final-stage power amplifier, or it may exhibit a more negative or more positive tendency.

[0118] Furthermore, in an amplification device that includes two or more power amplifiers between the primary power amplifier and the final power amplifier, i.e., an amplification device containing four or more power amplifiers, it is preferable that the power amplifier supplied with a bias current having positive temperature characteristics or a bias current without temperature characteristics is not located in a stage close to the final power amplifier, compared to the power amplifier supplied with a bias current having negative temperature characteristics.

[0119] For example, in an amplification device containing a four-stage power amplifier, compared to a structure in which bias currents with positive temperature characteristics are supplied to the primary and third-stage power amplifiers and bias currents with negative temperature characteristics are supplied to the second and final-stage power amplifiers, the following structures can more reliably suppress the instability of characteristics relative to temperature changes: 1) a structure in which bias currents with positive temperature characteristics are supplied to the primary, second, and third-stage power amplifiers and bias currents with negative temperature characteristics are supplied to the final-stage power amplifier; 2) a structure in which bias currents with positive temperature characteristics are supplied to the primary and second-stage power amplifiers, bias currents without temperature characteristics are supplied to the third-stage power amplifier and bias currents with negative temperature characteristics are supplied to the final-stage power amplifier; or 3) a structure in which bias currents with positive temperature characteristics are supplied to the primary stage and bias currents with negative temperature characteristics are supplied to the second, third, and final-stage power amplifiers, etc. Furthermore, in this case, as with the bias currents supplied to the primary, second, and third stages of the power amplifier in 1), for bias currents with the same temperature characteristics, the bias current supplied to the power amplifier closer to the final stage than to the given stage may exhibit a more positive or a more negative tendency compared to the bias current supplied to the power amplifier of a given stage. Alternatively, it may exhibit the exact same tendency.

[0120] [2. Functional Structure of Bias Circuit]

[0121] Next, the functional structure of the bias circuit 20 will be explained.

[0122] Figure 6 This is a block diagram showing the functional structure of the bias circuit 20 of the amplification device 1.

[0123] As previously described, the bias circuit 20 includes a first bias power supply section 40, a second bias power supply section 60, and a common constant current source 30.

[0124] The common constant current source 30 is a current source with positive temperature characteristics. The common constant current source 30 supplies current to the first bias power supply section 40 and the second bias power supply section 60, respectively. In addition, a startup transistor 34 for starting the bias circuit 20 is provided in the common constant current source 30.

[0125] The first bias power supply unit 40 includes a first current amplifier circuit 41, a first constant current source 45, and an addition-side current amplifier unit 50.

[0126] In the current amplification section 50 on the addition side, node 50a on one side is connected to the first current amplification circuit 41 and the first constant current source 45 via node n4, and node 50b on the other side is connected to the amplifier 10. In addition, node n4 is a common node located between the first current amplification circuit 41, the first constant current source 45 and the current amplification section 50 on the addition side.

[0127] The first current amplifier circuit 41 is connected to the common constant current source 30. The first current amplifier circuit 41 amplifies the first supply current is1 supplied from the common constant current source 30 and generates the first amplified current ia1.

[0128] The first constant current source 45 is a constant current source without temperature compensation or with low temperature dependence. The first constant current source 45 is introduced as the first introduced current id1 from node 50a on one side of the current amplification section 50 on the addition side.

[0129] At node n4 of the first bias power supply section 40, a first amplified current ia1 is added to the first input current id1 introduced by the first constant current source 45. As a result, at node 50a on one side of the current amplification section 50, a first total current it1 (it1 = id1 + ia1) flows after the sum of the first input current id1 and the first amplified current ia1. Furthermore, a first voltage required for the first total current it1 to flow is formed on one side.

[0130] If a first voltage is generated on one side of the current amplification section 50 on the addition side, the same first voltage is generated on the other side, and then an amplified current based on the first voltage is output from node 50b on the other side. The amplified current output from the current amplification section 50 on the addition side has a positive temperature characteristic and is supplied to the power amplifier PA1 as a bias current Ib1.

[0131] The second bias power supply unit 60 includes a second current amplifier circuit 61, a second constant current source 65, and a subtraction-side current amplifier unit 70.

[0132] In the subtraction-side current amplification section 70, node 70a on one side is connected to the second current amplification circuit 61 and the second constant current source 65 via node n5, and node 70b on the other side is connected to the amplifier 10. In addition, node n5 is a common node located between the second current amplification circuit 61, the second constant current source 65, and the subtraction-side current amplification section 70.

[0133] The second current amplifier circuit 61 is connected to the common constant current source 30. The second current amplifier circuit 61 amplifies the second supply current is2 supplied from the common constant current source 30 and generates a second amplified current ia2.

[0134] The second constant current source 65 is a constant current source without temperature compensation or with low temperature dependence. The second constant current source 65 is introduced as a second introduced current id2 from node 70a on one side of the subtraction side current amplification section 70.

[0135] At node n5 of the second bias power supply section 60, the second input current id2 introduced by the second constant current source 65 is subtracted from the second amplified current ia2. As a result, at node 70a on the subtraction side current amplification section 70, a second total current it2 (it2 = id2 - ia2) flows after subtracting the second amplified current ia2 from the second input current id2. Furthermore, a second voltage required for the second total current it2 to flow is formed on one side.

[0136] If a second voltage is formed on one side of the subtraction-side current amplification section 70, a second voltage is also formed on the other side, and then an amplified current based on the second voltage is output from the node 70b on the other side. The amplified current output from the subtraction-side current amplification section 70 has a negative temperature characteristic and is supplied to the power amplifier PA2 as a bias current Ib2, and is also supplied to the power amplifier PA3 as a bias current Ib3.

[0137] [3. Circuit structure of the bias circuit]

[0138] Next, the circuit structure used to implement the above-mentioned functions of the bias circuit 20 will be described.

[0139] Figure 7 This is a circuit diagram of the bias circuit 20 of the amplification device 1 according to the embodiment.

[0140] As previously described, the bias circuit 20 includes a first bias power supply section 40, a second bias power supply section 60, and a common constant current source 30.

[0141] The common constant current source 30 has a first current mirror circuit 31 connected to the high-potential power supply line Vcc, a second current mirror circuit 32 cascaded with the first current mirror circuit 31, and a resistor element 33 connected in series between the second current mirror circuit 32 and the low-potential power supply line Vss. The first current mirror circuit 31 includes a pair of pMOS transistor elements (transistors 31a and 31b), and the second current mirror circuit 32 includes a pair of nMOS transistor elements (transistors 32a and 32b) (MOS: Metal-oxide-semiconductor field-effect transistor). The resistor element 33 in the common constant current source 30 is a single element shared by the first current mirror circuit 31 and the second current mirror circuit 32. The resistor element 33 has a negative temperature characteristic. Therefore, the current output from the common constant current source 30 has a positive temperature characteristic.

[0142] The output side of the second current mirror circuit 32 is connected to the first current amplifier circuit 41, and outputs a first supply current is1 to the first current amplifier circuit 41. The output side of the first current mirror circuit 31 is connected to the second current amplifier circuit 61, and outputs a second supply current is2 to the second current amplifier circuit 61.

[0143] As previously described, the first bias power supply unit 40 includes a first current amplifier circuit 41, a first constant current source 45, and an adder-side current amplifier unit 50.

[0144] The first current amplifier circuit 41 has a current amplification element 41a, which is an nMOS transistor element. The gate of the current amplification element 41a is connected to the output side of the second current mirror circuit 32, the source is connected to the low-potential power supply line Vss, and the drain is connected to node n4. The first current amplifier circuit 41 amplifies the first supply current is1 output from the second current mirror circuit 32 and generates a first amplified current ia1.

[0145] The first constant current source 45 has a first operational amplifier 46, a first input transistor 47, and a first variable resistor 48.

[0146] The first input transistor 47 is, for example, an nMOS transistor. The control terminal (gate) of the first input transistor 47 is connected to the output side of the first operational amplifier 46. One end of the input / output terminal (source) is connected to the low-potential power supply line Vss via a first variable resistor 48, and the other end (drain) is connected to node n4. The first variable resistor 48 is connected in series between one end of the input / output terminal of the first input transistor 47 and the low-potential power supply line Vss. One input terminal of the first operational amplifier 46 is connected to the reference voltage VBG, and the other input terminal is connected to one end of the input / output terminal of the first input transistor 47.

[0147] Furthermore, in the amplification device 1, a temperature sensing element TD for detecting the temperature of the amplifier 10 is built into the first IC chip of the amplifier 10. Additionally, a remote temperature compensator RT connected to the temperature sensing element TD is provided in the first bias power supply section 40. The remote temperature compensator RT can remotely operate active and variable components based on the detection results of the temperature sensing element TD.

[0148] The adder-side current amplification section 50 includes an adder-side operational amplifier 55 serving as a comparator, a first detection resistor 51 and a second detection resistor 52 for comparison, and a bias output transistor 56. The resistance values ​​of the first detection resistor 51 and the second detection resistor 52 for comparison are different from each other. The bias output transistor 56 is, for example, a pMOS transistor element.

[0149] A first sense resistor 51 is connected to the first input terminal of the adder-side operational amplifier 55, and a second sense resistor 52 is connected to the second input terminal. A bias output transistor 56 is connected to the output side of the adder-side operational amplifier 55.

[0150] The first sensing resistor 51 is connected in series between node 50a on one side of the adder-side current amplifier 50 and the high-potential power supply line Vcc. Furthermore, the first sensing resistor 51 is connected to node n4 via node 50a on one side. The second sensing resistor 52 is connected in series between node 50b on the other side of the adder-side current amplifier 50 and the high-potential power supply line Vcc. Furthermore, the second sensing resistor 52 is connected to the drain of the bias output transistor 56 via node 50b on the other side.

[0151] The gate of the bias output transistor 56 is connected to the output side of the adder-side operational amplifier 55, the drain is connected to the second sense resistor 52 via node 50b on the other side, and the source is connected to the power amplifier PA1 of the amplifier 10.

[0152] At node n4 of the first bias power supply section 40, a first amplified current ia1 is added to the first input current id1 introduced by the first constant current source 45. As a result, at node 50a on one side of the current amplification section 50, a first total current it1, which is the sum of the first input current id1 and the first amplified current ia1, flows through. Furthermore, a first voltage required for the first total current it1 to flow through is formed on one side.

[0153] If a first voltage is generated on one side of the adder-side current amplification section 50, the same first voltage is generated on the other side via the adder-side operational amplifier 55 and the bias output transistor 56. Then, an amplified current based on the first voltage is output from node 50b on the other side. The amplification rate of the amplified current is determined by the resistance values ​​of the first detection resistor 51 and the second detection resistor 52. For example, the resistance value of the second detection resistor 52 is smaller than the resistance value of the first detection resistor 51. The amplified current output from the adder-side current amplification section 50 has a positive temperature characteristic and is supplied to the power amplifier PA1 as a bias current Ib1.

[0154] On the other hand, the second bias power supply unit 60 includes a second current amplification circuit 61, a second constant current source 65, and a subtraction-side current amplification unit 70.

[0155] The second current amplifier circuit 61 has a current amplification element 61a, which is a pMOS transistor element. The gate of the current amplification element 61a is connected to the output side of the first current mirror circuit 31, the source is connected to node n5, and the drain is connected to the high-potential power supply line Vcc. The second current amplifier circuit 61 amplifies the second supply current is2 output from the first current mirror circuit 31 and generates a second amplified current ia2.

[0156] The second constant current source 65 has a second operational amplifier 66, a second introduced transistor 67, and a second variable resistor 68.

[0157] The second introduced transistor 67 is, for example, an nMOS transistor. The control terminal (gate) of the second introduced transistor 67 is connected to the output side of the second operational amplifier 66. One end of the input / output terminal (source) is connected to the low-potential power supply line Vss via the second variable resistor 68, and the other end (drain) is connected to node n5. The second variable resistor 68 is connected in series between one end of the input / output terminal of the second introduced transistor 67 and the low-potential power supply line Vss. One input terminal of the second operational amplifier 66 is connected to the reference voltage VBG, and the other input terminal is connected to one end of the input / output terminal of the second introduced transistor 67.

[0158] The subtraction-side current amplification section 70 includes a subtraction-side operational amplifier 75 serving as a comparator, a third detection resistor 73 and a fourth detection resistor 74 for comparison, and a bias output transistor 76. The resistance values ​​of the third detection resistor 73 and the fourth detection resistor 74 for comparison are different from each other. The bias output transistor 76 is, for example, a pMOS transistor element.

[0159] A third sense resistor 73 is connected to the first input terminal of the subtraction-side operational amplifier 75, and a fourth sense resistor 74 is connected to the second input terminal. A bias output transistor 76 is connected to the output side of the subtraction-side operational amplifier 75.

[0160] The third sensing resistor 73 is connected in series between node 70a on one side of the subtraction-side current amplification section 70 and the high-potential power supply line Vcc. Furthermore, the third sensing resistor 73 is connected to node n5 via node 70a on one side. The fourth sensing resistor 74 is connected in series between node 70b on the other side of the subtraction-side current amplification section 70 and the high-potential power supply line Vcc. Furthermore, the fourth sensing resistor 74 is connected to the drain of the bias output transistor 76 via node 70b on the other side.

[0161] The gate of the bias output transistor 76 is connected to the output side of the subtraction-side operational amplifier 75, the drain is connected to the fourth detection resistor 74 via the node 70b on the other side, and the source is connected to the power amplifiers PA2 and PA3 of the amplifier 10 via the bias branch BB.

[0162] At node n5 of the second bias power supply section 60, the second input current id2 introduced by the second constant current source 65 is subtracted from the second amplified current ia2. As a result, at node 70a on the subtraction side current amplification section 70, a second total current it2, which is the result of subtracting the second amplified current ia2 from the second input current id2, flows through it. Furthermore, a second voltage required for the second total current it2 to flow through is formed on one side.

[0163] If a second voltage is formed on one side of the subtraction-side current amplification section 70, a second voltage is also formed on the other side via the subtraction-side operational amplifier 75 and the bias output transistor 76. Furthermore, an amplified current based on the second voltage is output from node 70b on the other side. The amplification rate of the amplified current is determined by the resistance values ​​of the third detection resistor 73 and the fourth detection resistor 74. For example, the resistance value of the fourth detection resistor 74 is smaller than the resistance value of the third detection resistor 73. The amplified current output from the subtraction-side current amplification section 70 has a negative temperature characteristic and is supplied to power amplifier PA2 as bias current Ib2. Additionally, it is supplied to power amplifier PA3 as bias current Ib3.

[0164] [4. Effects, etc.]

[0165] The amplification device 1 according to this embodiment includes: an amplifier 10 comprising a series of cascaded power amplifiers PA1, PA2, and PA3; and a bias circuit 20 that supplies bias current to the amplifier 10. The bias current Ib1 supplied to the primary power amplifier PA1 among the multi-stage power amplifiers PA1 to PA3 has a positive temperature characteristic, and the bias current Ib3 supplied to the final stage power amplifier PA3 has a negative temperature characteristic.

[0166] In this way, by setting the bias current Ib1 supplied to the primary power amplifier PA1 to a positive temperature characteristic and setting the bias current Ib3 supplied to the final stage power amplifier PA3 to a negative temperature characteristic, the EVM value of amplifier 10 can be reduced. Therefore, in amplification device 1, the instability of characteristics relative to temperature changes can be suppressed.

[0167] Alternatively, the bias current supplied to a given stage of the multi-stage power amplifiers PA1 to PA3 may have a temperature characteristic that shows a negative tendency compared to the bias current supplied to a power amplifier stage further ahead of the given stage.

[0168] Therefore, in the amplification device 1, the ability to suppress changes in characteristics relative to temperature changes becomes unstable.

[0169] In addition, the bias circuit 20 includes: a first bias power supply section 40, which outputs a bias current Ib1 to the primary power amplifier PA1; a second bias power supply section 60, which outputs a bias current Ib3 to the final stage power amplifier PA3; and a common constant current source 30, which supplies current to the first bias power supply section 40 and the second bias power supply section 60 respectively.

[0170] In this way, by using the common constant current source 30, which serves as a common current source, to supply current to the first bias power supply unit 40 and the second bias power supply unit 60, the amplifier device 1 with bias circuit 20 can be miniaturized.

[0171] Alternatively, the first bias power supply unit 40 may have a first current amplification circuit 41 and a first constant current source 45 that amplifies the first supply current is1 supplied from the common constant current source 30 and generates a first amplified current ia1, and the second bias power supply unit 60 may have a second current amplification circuit 61 and a second constant current source 65 that amplifies the second supply current is2 supplied from the common constant current source 30 and generates a second amplified current ia2, in which the first bias power supply unit 40 adds the first amplified current ia1 to the first input current id1 introduced by the first constant current source 45, and the second bias power supply unit 60 subtracts the second amplified current ia2 from the second input current id2 introduced by the second constant current source 65.

[0172] Therefore, the first bias power supply unit 40 can be set to a positive temperature characteristic by the above addition, and the second bias power supply unit 60 can be set to a negative temperature characteristic by the above subtraction. Thus, for example, a bias current Ib1 can be supplied based on the current of the first bias power supply unit 40 with a positive temperature characteristic, and a bias current Ib3 can be supplied based on the current of the second bias power supply unit 60 with a negative temperature characteristic, thereby reducing the EVM value of the amplifier 10. Therefore, in the amplification device 1, the instability of the characteristics relative to temperature changes can be suppressed.

[0173] Alternatively, the common constant current source 30 may have: a first current mirror circuit 31 connected to the high-potential side power supply line Vcc; a second current mirror circuit 32 cascaded with the first current mirror circuit 31; and a resistive element 33 connected in series between the second current mirror circuit 32 and the low-potential side power supply line Vss, having a positive temperature coefficient.

[0174] Therefore, the circuit structure of the common constant current source 30 can be simplified, and the amplifier device 1 with the common constant current source 30 can be miniaturized.

[0175] Alternatively, the first current amplifier circuit 41 may have an nMOS transistor element, the second current amplifier circuit 61 may have a pMOS transistor element, the first current mirror circuit 31 may have a pMOS transistor element, the second current mirror circuit 32 may have an nMOS transistor element, the output side of the second current mirror circuit 32 may be connected to the first current amplifier circuit 41, and the output side of the first current mirror circuit 31 may be connected to the second current amplifier circuit 61.

[0176] Therefore, the current output from the second current mirror circuit 32 (first supply current is1) can be amplified by the first current amplification circuit 41 to generate a first amplified current ia1, and the current output from the first current mirror circuit 32 (second supply current is2) can be amplified by the second current amplification circuit 61 to generate a second amplified current ia2. Thus, the first amplified current ia1 can be used for current addition to generate a current with positive temperature characteristics, and a bias current Ib1 can be supplied based on this positive temperature characteristics. Furthermore, the second amplified current ia2 can be used for current subtraction to generate a current with negative temperature characteristics, and a bias current Ib3 can be supplied based on this negative temperature characteristics. Therefore, the EVM value of the amplifier 10 can be reduced, and in the amplification device 1, the instability of characteristics relative to temperature changes can be suppressed.

[0177] Alternatively, the first constant current source 45 may have: a first operational amplifier 46; a first input transistor 47, with a control terminal connected to the output side of the first operational amplifier 46; and a first variable resistor 48, connected in series between one end of the input / output terminal of the first input transistor 47 and the low-potential power supply line Vss.

[0178] Therefore, by changing the resistance value of the first variable resistor 48, for example, the value of the first introduced current id1 can be changed, and the positive temperature characteristic of the bias current Ib1 output from the first bias power supply unit 40 can be altered. This allows for adjustment to reduce the EVM value of the amplifier 10, suppressing instability in the characteristics relative to temperature changes within the amplification device 1. Furthermore, by generating the first introduced current id1 using the first operational amplifier 46 and the first introduced transistor 47, a stable first introduced current id1 can be output for a short time.

[0179] Alternatively, the second constant current source 65 may have: a second operational amplifier 66; a second input transistor 67, with a control terminal connected to the output side of the second operational amplifier 66; and a second variable resistor 68, connected in series between one end of the input / output terminal of the second input transistor 67 and the low-potential power line Vss.

[0180] Therefore, by changing the resistance value of the second variable resistor 68, for example, the value of the second introduced current id2 can be changed, thereby altering the negative temperature characteristic of the bias current Ib3 output from the second bias power supply unit 60. This allows for adjustment to reduce the EVM value of the amplifier 10, suppressing instability in the characteristics relative to temperature changes within the amplification device 1. Furthermore, by generating the second introduced current id2 using the second operational amplifier 66 and the second introduced transistor 67, a stable second introduced current id2 can be output for a short time. This further suppresses characteristic instability within the amplification device 1.

[0181] Alternatively, the first introduced transistor 47 and the second introduced transistor 67 may be nMOS transistor elements.

[0182] Therefore, compared to the case where components other than MOS transistors are used for introduction, a stable first introduction current id1 and a stable second introduction current id2 can be output in a short time.

[0183] Alternatively, the first bias power supply unit 40 may have an adder-side current amplification unit 50, which generates a bias current Ib1 supplied to the primary power amplifier PA1 based on a first total current it1 obtained by adding the first input current id1 and the first amplification current ia1, and the second bias power supply unit 60 may have a subtractor-side current amplification unit 70, which generates a bias current Ib3 supplied to the final stage power amplifier PA3 based on a second total current it2 obtained by subtracting the second amplification current ia2 from the second input current id2.

[0184] By having such an addition-side current amplification section 50 and a subtraction-side current amplification section 70, it is possible to set the bias current Ib1 supplied to the primary power amplifier PA1 to a positive temperature characteristic and the bias current Ib3 supplied to the final stage power amplifier PA3 to a negative temperature characteristic. This reduces the EVM value of the amplifier 10, and in the amplification device 1, it is possible to suppress the instability of characteristics relative to temperature changes.

[0185] Alternatively, the adder-side current amplification unit 50 may have an adder-side operational amplifier 55, a first detection resistor 51 connected in series between the first input terminal of the adder-side operational amplifier 55 and the high-potential power supply line Vcc, and a second detection resistor 52 connected in series between the second input terminal of the adder-side operational amplifier 55 and the high-potential power supply line Vcc, wherein the resistance values ​​of the first detection resistor 51 and the second detection resistor 52 are different from each other.

[0186] In this way, by setting the first detection resistor 51 and the second detection resistor 52 to different resistance values, the current amplification rate of the current amplification unit 50 on the addition side can be easily changed. As a result, in the amplification device 1, it is possible to easily suppress the instability of characteristics that change with temperature.

[0187] Alternatively, the subtraction-side current amplification unit 70 may include a subtraction-side operational amplifier 75, a third detection resistor 73 connected in series between the first input terminal of the subtraction-side operational amplifier 75 and the high-potential power supply line Vcc, and a fourth detection resistor 74 connected in series between the second input terminal of the subtraction-side operational amplifier 75 and the high-potential power supply line Vcc, wherein the resistance values ​​of the third detection resistor 73 and the fourth detection resistor 74 are different from each other.

[0188] In this way, by setting the third detection resistor 73 and the fourth detection resistor 74 to different resistance values, the current amplification rate of the subtraction-side current amplification unit 70 can be easily changed. As a result, in the amplification device 1, it is possible to easily suppress the instability of characteristics relative to temperature changes.

[0189] (Other methods, etc.)

[0190] The amplification device according to the embodiments of the present invention has been described above, but the present invention is not limited to the above embodiments. For example, modifications to the above embodiments as follows can also be included in the present invention.

[0191] For example, in one embodiment, an example is shown where the bias circuit 20 has two bias power supply sections: a first bias power supply section 40 and a second bias power supply section 60, but this is not a limitation. For example, the bias circuit 20 may also have multiple bias power supply sections corresponding to the number of power amplifiers. However, as in the embodiment, by using a single power supply section to supply bias current to multiple power amplifiers PA2 and PA3, circuits such as current sources and voltage sources that can be shared can be common, and the bias circuit can be miniaturized.

[0192] For example, the amplification device can also be configured to amplify high-frequency signals from standards other than IEEE 802.11 (e.g., LTE or W-CDMA).

[0193] Industrial availability

[0194] As an amplification device with stable characteristics relative to temperature changes, this invention can be widely used in communication equipment.

Claims

1. An amplification device comprising: Amplifiers, including cascaded multi-stage power amplifiers; and The bias circuit supplies bias current to the amplifier. in, The bias current supplied to the primary power amplifier in the multi-stage power amplifier has a positive temperature characteristic, while the bias current supplied to the final stage power amplifier has a negative temperature characteristic. The bias circuit includes: a first bias power supply section that outputs a bias current supplied to the primary power amplifier; and a second bias power supply section that outputs a bias current supplied to the final stage power amplifier. A common constant current source supplies current to the first bias power supply section and the second bias power supply section, respectively. The first bias power supply section includes a first current amplifier circuit and a first constant current source. The first current amplifier circuit amplifies the first supply current supplied from the common constant current source and generates a first amplified current. The second bias power supply section includes a second current amplifier circuit and a second constant current source. The second current amplifier circuit amplifies the second supply current supplied from the common constant current source and generates a second amplified current. In the first bias power supply section, the first amplified current is added to the first introduced current introduced by the first constant current source. In the second bias power supply section, the second introduced current is subtracted from the second amplified current introduced by the second constant current source.

2. An amplification device, comprising: Amplifiers, including cascaded multi-stage power amplifiers; and The bias circuit supplies bias current to the amplifier. in, The bias current supplied to the primary power amplifier in the multi-stage power amplifier has a positive temperature characteristic, while the bias current supplied to the final stage power amplifier has a negative temperature characteristic. The bias current supplied to a given stage of the multi-stage power amplifier exhibits a negative temperature characteristic compared to the bias current supplied to a stage preceding the given stage. The bias circuit includes: a first bias power supply section that outputs a bias current supplied to the primary power amplifier; and a second bias power supply section that outputs a bias current supplied to the final stage power amplifier. A common constant current source supplies current to the first bias power supply section and the second bias power supply section, respectively. The first bias power supply section includes a first current amplifier circuit and a first constant current source. The first current amplifier circuit amplifies the first supply current supplied from the common constant current source and generates a first amplified current. The second bias power supply section includes a second current amplifier circuit and a second constant current source. The second current amplifier circuit amplifies the second supply current supplied from the common constant current source and generates a second amplified current. In the first bias power supply section, the first amplified current is added to the first introduced current introduced by the first constant current source. In the second bias power supply section, the second introduced current is subtracted from the second amplified current introduced by the second constant current source.

3. The amplification device according to claim 1 or 2, wherein, The common constant current source has: a first current mirror circuit connected to the high-potential side power line; a second current mirror circuit cascaded with the first current mirror circuit; and a resistive element connected in series between the second current mirror circuit and the low-potential side power line, having a positive temperature coefficient.

4. The amplification device according to claim 3, wherein, The first current amplifier circuit has nMOS transistor elements. The second current amplifier circuit has pMOS transistor elements. The first current mirror circuit has pMOS transistor elements. The second current mirror circuit has nMOS transistor elements. The output side of the second current mirror circuit is connected to the first current amplifier circuit. The output side of the first current mirror circuit is connected to the second current amplifier circuit.

5. The amplification device according to claim 1 or 2, wherein, The first constant current source includes: a first operational amplifier; a first input transistor, with a control terminal connected to the output side of the first operational amplifier; and a first variable resistor, connected in series between one end of the input / output terminal of the first input transistor and the low-potential power supply line.

6. The amplification device according to claim 5, wherein, The second constant current source includes: a second operational amplifier; a second input transistor, with a control terminal connected to the output side of the second operational amplifier; and a second variable resistor, connected in series between one end of the input / output terminal of the second input transistor and the low-potential power supply line.

7. The amplification device according to claim 6, wherein, The first introduced transistor and the second introduced transistor are both nMOS transistor elements.

8. The amplification device according to claim 1 or 2, wherein, The first bias power supply section includes an additive current amplification section that generates a bias current supplied to the primary power amplifier based on a first total current obtained by adding the first input current and the first amplified current. The second bias power supply section includes a subtraction-side current amplification section, which generates a bias current supplied to the power amplifier of the final stage based on a second total current obtained by subtracting the second amplified current from the second introduced current.

9. The amplification device according to claim 8, wherein, The adder-side current amplification section includes: an adder-side operational amplifier; a first detection resistor connected in series between the first input terminal of the adder-side operational amplifier and the high-potential power supply line; and a second detection resistor connected in series between the second input terminal of the adder-side operational amplifier and the high-potential power supply line. The resistance values ​​of the first detection resistor and the second detection resistor are different from each other.

10. The amplification device according to claim 8, wherein, The subtraction-side current amplification section includes: a subtraction-side operational amplifier; a third detection resistor connected in series between the first input terminal of the subtraction-side operational amplifier and the high-potential power supply line; and a fourth detection resistor connected in series between the second input terminal of the subtraction-side operational amplifier and the high-potential power supply line. The resistance values ​​of the third and fourth detection resistors are different from each other.

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